4035B ETC1 | Alldatasheet

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DESCRIPTION — The 40368 is a fully synchronous edge-triggered 4-Bit Shift Repister with a Clock Toad SYMBOL Input (CP), four synchronous Parallel Data Inputs (Po-P3), two synchronous Serial Data Inputs (J, Rk), a synchronous Parallel Enable input (PE), Buffered Parallel Outputs from all 4-bit positions (Ag-A3), rvone ‘a True/Complement Input (T/C) and an overriding asynchronous Master Reset Input (MR), Operation is synchronous (except for Master Reset) and is edge-triggered on the LOW-t0-HIGH n yeh transition of the Clock Input (CP). When the Parallel Enable Input (PE) is HIGH, data is loaded into ode the register from Parallel Inputs (Pq-Pg) on the LOW-to-HIGH transition of the Clock Input (CP). LS wss8 ‘When the Paralle! Enable Input (PE) is LOW, data is shifted into the first register position from the az Serial Data Inputs (J, K) and all the data in the register is shifted one position to the right on the wre 9) Os Se, LOW-t0-HIGH transition of the Clock Input (CP). D-type entry is obtained by tying the two Serial Data Inputs (J, K) together. stews The Outputs (Qp-0g) ar witer inverting or nonintng, depending onthe Teue/Compares Inox Vpp «Fin 16 (T/G). With the T/@ Input HIGH, the Outputs (Q-Og) are non-inverting (Active HIGH), With the Veg "Pins. TIE Input LOW, the Outputs (Q9-O3) are inverting (Active LOW). AHIGH on the Master Reset Input (MR) resets all four bit positions (Qg-Q3 = LOW if T/E = HIGH, CONNECTION DIAGRAM {09-03 = HIGH if T/€ = LOW) independent of all other input conditions. Dir (ror view) «TYPICAL SHIFT FREQUENCY OF 17 MHz AT Vpp = 10V Geb. J, INPUTS TO THE FIRST STAGE se oa * T/E INPUT FOR TRUE OR COMPLEMENTARY OUTPUTS a SYNCHRONOUS PARALLEL ENABLE oF ope CLOCK EDGE-TRIGGERED ON LOW-TO-HIGH TRANSITION “Ge of }o ASYNCHRONOUS MASTER RESET sq one PIN NAMES de nie PE Parallel Enable Input id. “A Po-P3 Parallel Data Inputs = “}? a First Stage J Input (Active HIGH) K First Stage K Input (Active LOW) NOTE: 7 cP Clock Input (L+H Edge-Triggered) ‘The Flatpak version has the same TIC True/Complement Input pinouts (Connection Diagram) as the |" MR Morter Feset Input Dual Ivline Packego. 9-03 Buffered Parallel Outputs LOGIC DIAGRAM i ol HU AU U UO U o=pe a ‘SED —=D DD DD’ DD dh ob i So < 0 Cy © ee | @ pe! a has U Vop =Pin 16 U y ly y Veg = Pin © @ ® ic) ® © = Pin Number Pa fs o 7-73

FAIRCHILD CMOS * 40358 DC CHARACTERISTICS: Vpp as shown, Vgg = 0 V (See Note 1) _ LIMITS: SYMBOL | PARAMETER Vpo=5V Vpp =10V Vop-18V. UNITS | TEMP | TEST CONDITIONS iwi | Typ [max [Min | TP [MAX | win | T¥P[ MAX | ues Je Lf | ao PT | ao TTT co [vaste ‘oo (| Romer [Tf so [300 600 Al inputs at Supply bo FE et pt ee ES 4 OVorVpp Corcent [| [0 [TT [0 | e00 | [max | AC CHARACTERISTICS AND SET-UP REQUIREMENTS: Vpp as shown, Vsg = 0 V, Ta = 25°C (See Note 2) SYMBOL PARAMETER: Vpp =5V Vpp = 10V. Vop = 15V UNITS | TEST CONDITIONS [win [TvP [MAX MIN [TYP [MAX] MIN | TYP [MAX | LH 200 | 400 90 | 180 60 Propagation Delay, CP 500 75 | 1 ‘PLH Propagation Delay, MR to Qn ‘80 {PHL 500 | 75 | 180 'PLH | propagation Delay, T/C to Qn 96 {PHL 95 85 75 ‘TLH Output Transition Time trae 85 7s CL=50 pF, igCP | CP Minimum Putee With [ras [sof e820 ae [a fe] my = 200K ‘Mth | MA Minimum Pulse Width 150 [60 || 70 [a6 [| 86 [20 [as | input Transition eee [MR Recovery Time [120 | 60 [sa | 30 [| a3 [22 [| as | times < 20 ts Set-Up Time, Pa to OP 7900 38 th Hold Time, Py to CP -90 o ts ‘Set-Up Time, PE to CP 100 46 88 | 32 th Hold Time, PE to CP -90 -32 |_o | -22 ts Set-Up Time, J, R to CP ry th Hold Time, J, K to CP -37 Maximum Input Clock Frequency [_| [| [| om | z 2] 17 20 NoTes 1 itional OC Characteristics ore listed inthis section under 40008 Series CMOS Family Characteristics 2. Propagation Delays and Output Transition Times are graphically deserved m tie section under 40008 Series CMOS Family Characteristics 3. For fave, input rte and fall times are greater than oF aqua! 128 ne and lest than or eave! to 20 ne 4 [rs tecothmended thet input rise and fall times 10 the Clock Input be les than YS us at Voy = 8 V, 448 at Voo = 10V, and 3s st Voo 18 774

Anniswubt cP PULSE MOTH AND SETUP AND HOLD Timea Fe-7O Gr. FOP AND JOR R70 CP tee] on im Noun MR RECOVERY TIME AND MINIMUM MR PULSE WIDTH NOTE: seca and Mok! Tena are shown a postve values but maybe peti et naprive value 7-75