4029B

CD4029BC FAIRCHILD | Alldatasheet

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Features

■ Wide supply voltage range: 3V to 15V ■ High noise immunity: 0.45 VDD (typ.) ■ Low power TTL compatibility: fan out of 2 driving 74L or 1 driving 74LS ■ Parallel jam inputs ■ Binary or BCD decade up/down counting Ordering Code: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Pin Assignments for DIP, SOIC and SOP Top View Order Number Package Number Package Description CD4029BCWM M16B 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide body CD4029BCSJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide CD4029BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

www.fairchildsemi.com 2 CD4029BC Logic Diagram

3 www.fairchildsemi.com CD4029BC Absolute Maximum Ratings(Note 1) (Note 2) Recommended Operating Conditions (Note 2) Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. Except for “Operating Tempera- ture Range” they are not meant to imply that the devices should be oper- ated at these limits. The table of “Electrical Characteristics” provides conditions for actual device operation. Note 2: V SS = 0V unless otherwise specified. Note 3: IOH and IOL are tested one output at a time. DC Supply Voltage (VDD ) −0.5V to +18 VDC Input Voltage (VIN) −0.5V to VDD + 0.5 VDC Storage Temperature Range (TS) −65°C to +150°C Power Dissipation (PD ) Dual-In-Line 700 mW Small Outline 500 mW Lead Temperature (TL) (Soldering, 10 seconds) 260 °C DC Supply Voltage (VDD ) 3V to 15 V DC Input Voltage (VIN) 0V to V DD VDC Operating Temperature Range (TA) −40°C to +85°C Symbol Parameter Conditions −40°C +25°C +85°C Units Min Max Min Typ Max Min Max IDD Quiescent Device Current V DD = 5V 20 20 150 µA VDD = 10V 40 40 300 µA VDD = 15V 80 80 600 µA VOL LOW Level |I O | < 1 µA Output Voltage V DD = 5V 0.05 0 0.05 0.05 V VDD = 10V 0.05 0 0.05 0.05 V VDD = 15V 0.05 0 0.05 0.05 V VOH HIGH Level |I O | < 1 µA Output Voltage V DD = 5V 4.95 4.95 5 4.95 V VDD = 10V 9.95 9.95 10 9.95 V VDD = 15V 14.95 14.95 15 14.95 V Input Voltage V DD = 10V, VO = 1V or 9V 3.0 3.0 3.0 V Input Voltage V DD = 10V, VO = 1V or 9V 7.0 7.0 7.0 V IIN Input Current V DD = 15V, VIN = 0V −0.3 −10−5 −0.3 −1.0 µA VDD = 15V, VIN = 15V 0.3 10 −5 0.3 1.0 µA

www.fairchildsemi.com 4 CD4029BC TA = 25°C, CL = 50 pF , RL = 200k, Input trCL = tfCL = 20 ns, unless otherwise specified Note 4: *AC Parameters are guaranteed by DC correlated testing. Note 5: C PD determines the no load AC power consumption of any CMOS device. For complete explanation, see 74C Family Characteristics application note, AN-90. Symbol Parameter Conditions Min Typ Max Units CLOCKED OPERATION tPHL or tPLH Propagation Delay Time V DD = 5V 200 400 ns to Q Outputs V DD = 10V 85 170 ns VDD = 15V 70 140 ns tPHL or tPLH Propagation Delay Time V DD = 5V 320 640 ns to Carry Output V DD = 10V 135 270 ns VDD = 15V 110 220 ns tPHL or tPLH Propagation Delay Time C L = 15 pF to Carry Output V DD = 5V 285 570 ns VDD = 10V 120 240 ns VDD = 15V 95 190 ns tTHL or tTLH T ransition Time/Q V DD = 5V 100 200 ns or Carry Output V DD = 10V 50 100 ns VDD = 15V 40 80 ns tWH or tWL Minimum Clock V DD = 5V 160 320 ns Pulse Width V DD = 10V 70 135 ns VDD = 15V 55 110 ns trCL or tfCL Maximum Clock Rise V DD = 5V 15 µs and Fall Time V DD = 10V 10 µs VDD = 15V 5 µs tSU Minimum Set-Up Time V DD = 5V 180 360 ns VDD = 10V 70 140 ns VDD = 15V 55 110 ns fCL Maximum Clock Frequency V DD = 5V 1.5 3.1 MHz VDD = 10V 3.7 7.4 MHz VDD = 15V 4.5 9 MHz C IN Average Input Capacitance Any Input 5 7.5 pF C PD Power Dissipation Capacitance Per Package (Note 5) 65 pF PRESET ENABLE OPERATION tPHL or tPLH Propagation Delay Time V DD = 5V 285 570 ns to Q output V DD = 10V 115 230 ns VDD = 15V 95 195 ns tPHL or tPLH Propagation Delay Time V DD = 5V 400 800 ns to Carry Output V DD = 10V 165 330 ns VDD = 15V 135 260 ns tWH Minimum Preset Enable V DD = 5V 80 160 ns Pulse Width V DD = 10V 30 60 ns VDD = 15V 25 50 ns tREM Minimum Preset Enable V DD = 5V 150 300 ns Removal Time V DD = 10V 60 120 ns VDD = 15V 50 100 ns CARRY INPUT OPERATION t PHL or tPLH Propagation Delay Time V DD = 5V 265 530 ns to Carry Output V DD = 10V 110 220 ns VDD = 15V 90 180 ns tPHL , tPLH Propagation Delay Time C L = 15 pF to Carry Output V DD = 5V 200 400 ns VDD = 10V 85 170 ns VDD = 15V 70 140 ns

5 www.fairchildsemi.com CD4029BC Logic Waveforms Decade Mode Binary Mode

www.fairchildsemi.com 6 CD4029BC Switching Time Waveforms Cascading Packages Parallel Clocking Ripple Clocking Carry out lines at the 2nd or later stages may have a negative-going spike due to differential internal delays. These spikes do not affect counter operation, but if the carry out is used to trigger external circuitry the carry out should be gated with the clock.

7 www.fairchildsemi.com CD4029BC Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body Package Number M16B 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. CD4029BC Presettable Binary/Decade Up/Down Counter LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Package Number N16E