4027

HEF4027B PHILIPS | Alldatasheet

Document overview

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Technical content

Product specification File under Integrated Circuits, IC04 January 1995 INTEGRATED CIRCUITS HEF4027B flip-flops Dual JK flip-flop For a complete data sheet, please also download:

• The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC
• The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC

Philips Semiconductors Product specification Dual JK flip-flop HEF4027B flip-flops

DESCRIPTION

The HEF4027B is a dual JK flip-flop which is edge-triggered and features independent set direct D ), clear direct (CD ), clock (CP) inputs and outputs (O,O). Data is accepted when CP is LOW, and transferred to the output on the positive-going edge of the clock. The active HIGH asynchronous clear-direct (C D ) and set-direct (SD ) are independent and override the J, K, and CP inputs. The outputs are buffered for best system performance. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. Fig.1 Functional diagram. Fig.2 Pinning diagram. FUNCTION TABLES Notes 1. H = HIGH state (the more positive voltage) L = LOW state (the less positive voltage) X = state is immaterial = positive-going transition O n + 1 = state after clock positive transition PINNING FAMILY DATA, IDD LIMITS category FLIP-FLOPS See Family Specifications INPUTS OUTPUTS SD C D CP J K O O HL X X X H L LH X X X L H HH XXX H H INPUTS OUTPUTS SD C D CP J K O n + 1 O n + 1 L L L L no change LL HL H L LL LH L H LL H H O n O n J,K synchronous inputs CP clock input (L to H edge-triggered) S D asynchronous set-direct input (active HIGH) C D asynchronous clear-direct input (active HIGH) O true output O complement output HEF4027BP(N): 16-lead DIL; plastic (SOT38-1) HEF4027BD(F): 16-lead DIL; ceramic (cerdip) (SOT74) HEF4027BT(D): 16-lead SO; plastic (SOT109-1) ( ): Package Designator North America

Philips Semiconductors Product specification Dual JK flip-flop HEF4027B flip-flops AC CHARACTERISTICS VSS = 0 V; Tamb =2 5°C; CL = 50 pF; input transition times≤ 20 ns VDD V SYMBOL MIN. TYP. MAX. TYPICAL EXTRAPOLATION FORMULA Propagation delays CP → O, O 5 105 210 ns 78 ns + (0,55 ns/pF) CL HIGH to LOW 10 t PHL 40 80 ns 29 ns + (0,23 ns/pF) CL 15 30 60 ns 22 ns + (0,16 ns/pF) CL 5 85 170 ns 58 ns + (0,55 ns/pF) CL LOW to HIGH 10 t PLH 35 70 ns 27 ns + (0,23 ns/pF) CL 15 30 60 ns 22 ns + (0,16 ns/pF) CL SD → O 5 70 140 ns 43 ns + (0,55 ns/pF) CL LOW to HIGH 10 t PLH 30 60 ns 19 ns + (0,23 ns/pF) CL 15 25 50 ns 17 ns + (0,16 ns/pF) CL C D → O 5 120 240 ns 93 ns + (0,55 ns/pF) CL HIGH to LOW 10 t PHL 45 90 ns 33 ns + (0,23 ns/pF) CL 15 35 70 ns 27 ns + (0,16 ns/pF) CL SD → O 5 140 280 ns 113 ns + (0,55 ns/pF) CL HIGH to LOW 10 t PHL 55 110 ns 44 ns + (0,23 ns/pF) CL 15 40 80 ns 32 ns + (0,16 ns/pF) CL Fig.3 Logic diagram (one flip-flop).

Philips Semiconductors Product specification Dual JK flip-flop HEF4027B flip-flops C D → O 5 75 150 ns 48 ns + (0,55 ns/pF) CL LOW to HIGH 10 t PLH 35 70 ns 24 ns + (0,23 ns/pF) CL 15 25 50 ns 17 ns + (0,16 ns/pF) CL Output transition times 5 60 120 ns 10 ns + (1,0 ns/pF) CL HIGH to LOW 10 t THL 30 60 ns 9 ns + (0,42 ns/pF) CL 15 20 40 ns 6 ns + (0,28 ns/pF) CL 5 60 120 ns 10 ns + (1,0 ns/pF) CL LOW to HIGH 10 t TLH 30 60 ns 9 ns + (0,42 ns/pF) CL 15 20 40 ns 6 ns + (0,28 ns/pF) CL Set-up time 5 50 25 ns see also waveforms Figs 4 and 5 J,K→ CP 10 t su 30 10 ns 15 20 5 ns Hold time 5 25 0 ns J,K→ CP 10 t hold 20 0 ns 15 15 5 ns Minimum clock 5 80 40 ns pulse width; LOW 10 t WCPL 30 15 ns 15 24 12 ns Minimum SD ,C D 5 tWSDH, tWCDH 90 45 ns pulse width; HIGH 10 40 20 ns 15 30 15 ns Recovery time 5 tRSD, tRCD 20 −15 ns for SD ,C D 10 15 −10 ns 15 10 −5n s Maximum clock 5 4 8 MHz see also waveforms Fig.4pulse frequency 10 f max 12 25 MHz J = K = HIGH 15 15 30 MHz VDD V TYPICAL FORMULA FOR P ( µW) Dynamic power 5 900 f i+∑ (foC L)× VDD 2 where dissipation per 10 4 500 f i+∑ (foC L)× VDD 2 fi= input freq. (MHz) package (P) 15 13 200 f i+∑ (foC L)× VDD 2 fo = output freq. (MHz) C L = load capacitance (pF) ∑ (foC L) = sum of outputs VDD = supply voltage (V) VDD V SYMBOL MIN. TYP. MAX. TYPICAL EXTRAPOLATION FORMULA

Philips Semiconductors Product specification Dual JK flip-flop HEF4027B flip-flops

APPLICATION INFORMATION

Some examples of applications for the HEF4027B are:

• Registers
• Counters
• Control circuits Fig.4 Waveforms showing set-up times, hold times and minimum clock pulse width. Set-up and hold times are shown as positive values but may be specified as negative values. Fig.5 Waveforms showing recovery times for SD and CD ; minimum SD and CD pulse widths.