CD4016BC FAIRCHILD | Alldatasheet

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Technical content

Features

■ Wide supply voltage range: 3V to 15V ■ Wide range of digital and analog switching: ±7.5 VPEAK ■ “ON” resistance for 15V operation: 400Ω (typ.) ■ Matched “ON” resistance over 15V signal input: ΔR ON = 10Ω (typ.) ■ High degree of linearity: 0.4% distortion (typ.) @ fIS = 1 kHz, VIS = 5 Vp-p, VDD −VSS = 10V, RL = 10 kΩ ■ Extremely low “OFF” switch leakage: 0.1 nA (typ.) @ V DD − VSS = 10V TA = 25°C ■ Extremely high control input impedance: 1012Ω (typ.) ■ Low crosstalk between switches: −50 dB (typ.) @ fIS = 0.9 MHz, RL = 1 kΩ ■ Frequency response, switch “ON”: 40 MHz (typ.)

Applications

  • Analog signal switching/multiplexing Signal gating Squelch control Chopper Modulator/Demodulator Commutating switch
  • Digital signal switching/multiplexing
  • CMOS logic implementation
  • Analog-to-digital/digital-to-analog conversion
  • Digital control of frequency, impedance, phase, and ana- log-signal gain Ordering Code: Devices also available in Tape and Reel. Specify by appending the letter suffix “X” to the ordering code. Connection Diagram Pin Assignments for DIP and SOIC Schematic Diagram Order Number Package Number Package Description CD4016BCM M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow CD4016BCN N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

www.fairchildsemi.com 2 CD4016BC Absolute Maximum Ratings(Note 1) (Note 2) Recommended Operating Conditions (Note 2) Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The tables of “Recom- mended Operating Conditions” and “Electrical Characteristics” provide con- ditions for actual device operation. Note 2: V SS = 0V unless otherwise specified. Note 3: If the switch input is held at VDD , VIHC is the control input level that will cause the switch output to meet the standard “B” series VOH and IOH output levels. If the analog switch input is connected to VSS , VIHC is the control input level — which allows the switch to sink standard “B” series |IOH |, high level cur- rent, and still maintain a VOL ≤ “B” series. These currents are shown in Figure 8. VDD Supply Voltage −0.5V to +18V VIN Input Voltage −0.5V to VDD + 0.5V TS Storage Temperature Range −65°C to + 150°C Power Dissipation (PD ) Dual-In-Line 700 mW Small Outline 500 mW Lead Temperature (Soldering, 10 seconds) 260 °C VDD Supply Voltage 3V to 15V VIN Input Voltage 0V to V DD TA Operating Temperature Range −40°C to +85°C Symbol Parameter Conditions −40°C2 5 °C +85°C Units Min Max Min Typ Max Min Max IDD Quiescent Device V DD = 5V, VIN = VDD or VSS 1.0 0.01 1.0 7.5 µA Current V DD = 10V, VIN = VDD or VSS 2.0 0.01 2.0 15 µA VDD = 15V, VIN = VDD or VSS 4.0 0.01 4.0 30 µA Signal Inputs and Outputs R ON “ON” Resistance R L = 10kΩ to (VDD − VSS )/2 VC = VDD , VIS = VSS or VDD VDD = 10V 610 275 660 840 Ω VDD = 15V 370 200 400 520 Ω R L = 10kΩ to (VDD − VSS )/2 VC = VDD VDD = 10V, VIS = 4.75 to 5.25V 1900 850 2000 2380 Ω VDD = 15V, VIS = 7.25 to 7.75V 790 400 850 1080 Ω ΔR ON Δ“ON” Resistance R L = 10kΩ to (VDD − VSS )/2 Between any 2 of V C = VDD , VIS = VSS to VDD

4 Switches V DD = 10V 15 Ω

(In Same Package) V DD = 15V 10 Ω IIS Input or Output V C = 0, VDD = 15V ±50 ±0.1 ±50 ±200 nA Leakage V IS = 0V or 15V, Switch “OFF” V OS = 15V or 0V Control Inputs VILC LOW Level Input V IS = VSS and VDD Voltage V OS = VDD and VSS IIS = ±10 µA VDD = 5V 0.9 0.7 0.4 V VDD = 10V 0.9 0.7 0.4 V VDD = 15V 0.9 0.7 0.4 V VIHC HIGH Level Input V DD = 5V 3.5 3.5 3.5 V Voltage V DD = 10V 7.0 7.0 7.0 V VDD = 15V 11.0 11.0 11.0 V (Note 3) and Figure 8 IIN Input Current V CC − VSS = 15V ±0.3 ±10−5 ±0.3 ±1.0 µA VDD ≥ VIS ≥ VSS VDD ≥ VC ≥ VSS

3 www.fairchildsemi.com CD4016BC TA = 25°C, tr = tf = 20 ns and VSS = 0V unless otherwise specified Note 4: AC Parameters are guaranteed by DC correlated testing. Note 5: These devices should not be connected to circuits with the power “ON”. Note 6: In all cases, there is approximately 5 pF of probe and jig capacitance on the output; however, this capacitance is included in C L wherever it is speci- fied. Note 7: VIS is the voltage at the in/out pin and VOS is the voltage at the out/in pin. VC is the voltage at the control input. Symbol Parameter Conditions Min Typ Max Units tPHL , tPLH Propagation Delay Time V C = VDD , CL = 50 pF , (Figure 1) Signal Input to Signal Output R L = 200k VDD = 5V 58 100 ns VDD = 10V 27 50 ns VDD = 15V 20 40 ns tPZH , tPZL Propagation Delay Time R L = 1.0 kΩ , CL = 50 pF , (Figure 2, Figure 3) Control Input to Signal V DD = 5V 20 50 ns Output HIGH Impedance to V DD = 10V 18 40 ns Logical Level V DD = 15V 17 35 ns tPHZ , tPLZ Propagation Delay Time R L = 1.0 kΩ , CL = 50 pF , (Figure 2, Figure 3) Control Input to Signal V DD = 5V 15 40 ns Output Logical Level to V DD = 10V 11 25 ns HIGH Impedance V DD = 15V 10 22 ns Sine Wave Distortion V C = VDD = 5V, VSS = −50 . 4 % R L = 10 kΩ , VIS = 5 VP-P, f = 1 kHz, (Figure 4) Frequency Response — Switch V C = VDD = 5V, VSS = −5V, 40 MHz “ON” (Frequency at −3 dB) R L = 1 kΩ , VIS = 5 VP-P,

20 Log10 VOS /VOS (1 kHz) −dB,

(Figure 4) Feedthrough — Switch “OFF” V DD = 5V, VC = VSS = −5V, 1.25 MHz (Frequency at −50 dB) R L = 1 kΩ , VIS = 5 VP-P,

20 Log10 (VOS /VIS) = −50 dB,

(Figure 4) Crosstalk Between Any Two V DD = VC(A) = 5V; VSS = VC(B) = −5V , 0.9 MHz Switches (Frequency at −50 dB) R L = 1 kΩ VIS(A) = 5 VP-P,

20 Log10 (VOS(B)/VOS(A)) = −50 dB,

(Figure 5) Crosstalk; Control Input to V DD = 10V, RL = 10 kΩ 150 mV P-P Signal Output R IN = 1 kΩ , VCC = 10V Square Wave, C L = 50 pF (Figure 6) Maximum Control Input R L = 1 kΩ , CL = 50 pF , (Figure 7) VOS(f) = ½ VOS (1 kHz) VDD = 5V 6.5 MHz VDD = 10V 8.0 MHz VDD = 15V 9.0 MHz C IS Signal Input Capacitance 4p F C OS Signal Output Capacitance V DD = 10V 4 pF C IOS Feedthrough Capacitance V C = 0V 0.2 pF C IN Control Input Capacitance 57 . 5 p F

FIGURE 8. CD4016B Switch Test Conditions for VIHC

7 www.fairchildsemi.com CD4016BC Typical Applications

4 Input Multiplexer

The CD4016B is composed of 4, two-transistor analog switches. These switches do not have any linearization or compensation circuitry for “RON ” as do the CD4066B's. Because of this, the special operating considerations for the CD4066B do not apply to the CD4016B, but at low sup- ply voltages, ≤5V, the CD4016B's on resistance becomes non-linear. It is recommended that at 5V, voltages on the in/ out pins be maintained within about 1V of either V DD or VSS ; and that at 3V the voltages on the in/out pins should be at VDD or VSS for reliable operation.

www.fairchildsemi.com 8 CD4016BC Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Package Number M14A

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. CD4016BC Quad Bilateral Switch LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Package Number N14A