CD4015BMS INTERSIL | Alldatasheet

Document overview

  • Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
  • PDF pages: 8

Technical content

Features

  • High-Voltage Type (20V Rating)
  • Medium Speed Operation 12MHz (typ.) Clock Rate at VDD - VSS = 10V
  • Fully Static Operation
  • 8 Master-Slave Flip-Flops Plus Input and Output Buffering
  • 100% Tested For Quiescent Current at 20V
  • 5V, 10V and 15V Parametric Ratings
  • Standardized Symmetrical Output Characteristics
  • Maximum Input Current of 1µA at 18V Over Full Pack- age-Temperature Range; 100nA at 18V and 25 oC
  • Noise Margin (Full Package-Temperature Range) = - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V
  • Meets All Requirements of JEDEC Tentative Standard No. 13B, “Standard Specifications for Description of ‘B’ Series CMOS Devices”

Applications

  • Serial-Input/Parallel-Output Data Queueing
  • Serial to Parallel Data Conversion
  • General-Purpose Register

Description

CD4015BMS consists of two identical, independent, 4-stage serial-input/parallel output registers. Each register has inde- pendent CLOCK and RESET inputs as well as a single serial DATA input. “Q” outputs are available from each of the four stages on both registers. All register stages are D type, mas- ter-slave flip-flops. The logic level present at the DATA input is transferred into the first register stage and shifted over one stage at each positive-going clock transition. Resetting of all stages is accomplished by a high level on the reset line. Register expansion to 8 stages using one CD4015BMS package, or to more than 8 stages using additional CD4015BMS’s is possible. The CD4015BMS is supplied in these 16 lead outline pack- ages: Braze Seal DIP H4X Frit Seal DIP H1F Ceramic Flatpack H6W December 1992 File Number 3295

TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS

  1. Go/No Go test with limits applied to inputs
  2. For accuracy, voltage is measured differentially to VDD. Limit

TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS oC and +125oC limits guaranteed, 100% testing being implemented. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS

  1. All voltages referenced to device GND.
  2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized

on initial design release and upon design changes which would affect these characteristics. TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS NOTES: 1. All voltages referenced to device GND.

  1. See Table 2 for +25oC limit.

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)

TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25 O C TABLE 6. APPLICABLE SUBGROUPS NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2. TABLE 7. TOTAL DOSE IRRADIATION TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS

  1. Each pin except VDD and GND will have a series resistor of 10K± 5%, VDD = 18V± 0.5V
  2. Each pin except VDD and GND will have a series resistor of 47K± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures,

All Intersil semiconductor products are manufactured, assembled and tested underISO9000 quality systems certification. may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

1130 Brussels, Belgium

FIGURE 1. CD4015BMS LOGIC DIAGRAM

FIGURE 8. TYPICAL POWER DISSIPATION AS METALLIZATION: Thickness: 11kÅ − 14kÅ, AL.