NCP12400_V01 ONSEMI | Alldatasheet
Document overview
- Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
- PDF pages: 47
Technical content
Features
- Fixed−Frequency Current−Mode Operation 65 kHz or 100 kHz Frequency Options
- Frequency Foldback then Skip Mode for Maximized Performance in Light Load and Standby Conditions
- Timer−Based Overload Protection with Latched (Option A) or Autorecovery (Option B) Operation
- High−V oltage Current Source with Brown−Out Detection and Dynamic Self−Supply, Simplifying the Design of the VCC Circuitry
- Frequency Modulation for Softened EMI Signature
- Adjustable Overpower Protection Dependant on the Mains V oltage
- Fault Input for Overvoltage and Over Temperature Protection
- VCC Operation up to 28 V , with Overvoltage Detection
- 300/500 mA Source/Sink Drive Peak Current Capability
- 4/10 ms Soft−Start
- Internal Thermal Shutdown
- No−Load Standby Power < 30 mW
- X2 Capacitor in EMI Filter Discharging Feature
- These are Pb−Free Devices Typical Applications
- Offline Adapters for Notebooks, LCD, and Printers
- Offline Battery Chargers
- Consumer Electronic Power Supplies
- Auxiliary/Housekeeping Power Supplies
- Offline Adapters for Notebooks SOIC−7 CASE 751U MARKING DIAGRAM (Note: Microdot may be in either location) PIN CONNECTIONS 400VWXYZf FAULT FB CS GND DRV HV (Top View) = Specific Device Code (see page 2) A = Assembly Location L = Wafer Lot Y = Year W = Work Week /C0071 = Pb−Free Package XXXXX ALYW/C0071 /C0071 VCC See detailed ordering and shipping information on page 44 of this data sheet.
ORDERING INFORMATION
Figure 1. Flyback Converter Application using the NCP12400 Table 1. OPTIONS
800 Hz burst
Table 2. SPECIFIC DEVICE CODE KEY
400 V W X Y Z f
Table 3. PIN FUNCTION DESCRIPTION autorecovery mode or can be latched depending on the option.
2 FB Feedback + Shutdown
the low consumption Off mode if the FB input pin is pulled to GND.
3 CS Current Sense This input senses the primary current for current−mode operation, and offers an
4 GND The controller ground. 5 DRV Drive Output Drives external MOSFET. connected to an external auxiliary voltage. sensing for the overpower protection purposes. It is not allowed to connect this pin to a dc voltage.
Figure 2. Simplified Internal Block Schematic
11 V regulator
Table 4. MAXIMUM RATINGS should not be assumed, damage may occur and reliability may be affected.
- This device series contains ESD protection and exceeds the following tests:
- This device contains latch-up protection and exceeds 100 mA per JEDEC Standard JESD78.
- As mounted on a 80 x 100 x 1.5 mm FR4 substrate with a single layer of 50 mm
for a JEDEC 51-1 conductivity test PCB. Test conditions were under natural convection or zero air flow.
- As mounted on a 80 x 100 x 1.5 mm FR4 substrate with a single layer of 100 mm2 of 2 oz copper traces and heat spreading area. As specified
for a JEDEC 51-2 conductivity test PCB. Test conditions were under natural convection or zero air flow.
- As mounted on a 80 x 100 x 1.5 mm FR4 substrate with a single layer of 650 mm2 of 2 oz copper traces and heat spreading area. As specified
for a JEDEC 51-3 conductivity test PCB. Test conditions were under natural convection or zero air flow. Table 5. ELECTRICAL CHARACTERISTICS
- CS pin source current is a sum of I bias and IOPC, thus at VHV = 125 V is observed the Ibias only, because IOPC is switched off.
- CS pin source current is a sum of I bias and IOPC, thus at VHV = 125 V is observed the Ibias only, because IOPC is switched off.
- CS pin source current is a sum of I bias and IOPC, thus at VHV = 125 V is observed the Ibias only, because IOPC is switched off.
- CS pin source current is a sum of I bias and IOPC, thus at VHV = 125 V is observed the Ibias only, because IOPC is switched off.
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
www.onsemi.com
APPLICATION INFORMATION
The NCP12400 includes all necessary features to build a safe and efficient power supply based on a fixed−frequency flyback converter. The NCP12400 is a multimode controller as illustrated in Figure 43. The mode of operation depends upon line and load condition. Under all modes of operation, the NCP12400 terminates the DRV signal based on the switch current. Thus, the NCP12400 always operates in current mode control so that the power MOSFET current is always limited. Under normal operating conditions, the FB pin commands the operating mode of the NCP12400 at the voltage thresholds shown in Figure 43. At normal rated operating loads (from 100% to approximately 33% full rated power) the NCP12400 controls the converter in a fixed−frequency PWM mode. It can operate in the continuous conduction mode (CCM) or discontinuous conduction mode (DCM) depending upon the input voltage and loading conditions. If the controller is used in CCM with a wide input voltage range, the duty−ratio may increase up to 50%. The build−in slope compensation prevents the appearance of sub−harmonic oscillations in this operating area. For loads that are between approximately 32% and 10% of full rated power, the converter operates in frequency foldback mode (FFM). If the feedback pin voltage is lower than 1.4 V the peak switch current is kept constant and the output voltage is regulated by modulating the switching frequency for a given and fixed input voltage V HV. Effectively, operation in FFM results in the application of constant volt −seconds to the flyback transformer each switching cycle. V oltage regulation in FFM is achieved by varying the switching frequency in the range from 65 kHz to 28 kHz. For extremely light loads (below approximately 6% full rated power), the converter is controlled using bursts of 28 kHz pulses. This mode is known as skip mode. The FFM, keeping constant peak current and skip mode allows design of the power supplies with increased efficiency under the light loading conditions. Keep in mind that the aforementioned boundaries of steady −state operation are approximate because they are subject to converter design parameters. Figure 43. Mode Control with FB Pin Voltage voltage increases above the 2.2 V level. latched A and the autorecovery B on the following figures. mode if the thermal shutdown protection is activated.
Figure 44. Operating Status Diagram of the Device
Figure 45. VCC Management Timing Diagram device by the remote control being in off mode.
controller actually starts the next time VCC reaches VCC(on). increases before the current−mode control takes over. source is needed to supply VCC during normal operation. stopping during load transients when the V CC might drop. Figure 46. VCC Start−up Timing Diagram voltage on HV pin is too low (below VHV(min)).
Figure 47. Latch After the Preshort standard ac−dc conversion applications. brown−out condition is detected, and the controller stops.
Figure 48. Ac Line Drop−out Timing Diagram doesn’t stop in case of line cycle drop−out. restart is allowed only after the 1st watch dog signal event. device restart is shown at Figure 50.
Figure 49. Ac Line Drop−out Timing Diagram with the Parasitic Spike
Figure 50. Detailed Timing Diagram of the Device Restart after the Short ac Line Drop−out
www.onsemi.com X2 Cap Discharge Feature The X2 capacitor discharging feature is offered by usage of the NCP12400. This feature save approx. 16 mW – 25 mW input power depending on the EMI filter X2 capacitors volume and it saves the external components count as well. The discharge feature is ensured via the start−up current source with a dedicated control circuitry for this function. The X2 capacitors are being discharged by current defined as I start2 when this need is detected. There is used a dedicated structure called ac line unplug detector inside the X2 capacitor discharge control circuitry. See the Figure 51 for the block diagram for this structure and Figures 52, 53, 54 and 55 for the timing diagrams. The basic idea of ac line unplug detector lies in comparison of the direct sample of the high voltage obtained via the high voltage sensing structure with the delayed sample of the high voltage. The delayed signal is created by the sample & hold structure. The comparator used for the comparison of these signals is without hysteresis inside. The resolution between the slopes of the ac signal and dc signal is defined by the sampling time T SAMPLE and additional internal offset NOS. These parameters ensure the noise immunity as well. The additional offset is added to the picture of the sampled HV signal and its analog sum is stored in the C 1 storage capacitor. If the voltage level of the HV sensing structure output crosses this level the comparator CMP output signal resets the detection timer and no dc signal is detected. The additional offset N OS can be measured as the V HV(hyst) on the HV pin. If the comparator output produces pulses it means that the slope of input signal is higher than set resolution level and the slope is positive. If the comparator output produces the low level it means that the slope of input signal is lower than set resolution level or the slope is negative. There is used the detection timer which is reset by any edge of the comparator output. It means if no edge comes before the timer elapses there is present only dc signal or signal with the small ac ripple at the HV pin. This type of the ac detector detects only the positive slope, which fulfils the requirements for the ac line presence detection. In case of the dc signal presence on the high voltage input, the direct sample of the high voltage obtained via the high voltage sensing structure and the delayed sample of the high voltage are equivalent and the comparator produces the low level signal during the presence of this signal. No edges are present at the output of the comparator, that’s why the detection timer is not reset and dc detect signal appears. The minimum detectable slope by this ac detector is given by the ration between the maximum hysteresis observed at HV pin V HV(hyst),max and the sampling time: Smin /C0043 VHV(hyst),max Tsample (eq. 1) Than it can be derived the relationship between the minimum detectable slope and the amplitude and frequency of the sinusoidal input voltage: Vmax /C0043 VHV(hyst),max 2 /C0064/C0112/C0064f /C0064Tsample /C0043 5 2 /C0064/C0112/C006435 /C00641 /C006410−3 /C0043 The minimum detectable AC RMS voltage is 16 V at frequency 35 Hz, if the maximum hysteresis is 5 V and sampling time is 1 ms. The X2 capacitor discharge feature is available in any controller operation mode to ensure this safety feature. The detection timer is reused for the time limiting of the discharge phase, to protect the device against overheating. The discharging process is cyclic and continues until the ac line is detected again or the voltage across the X2 capacitor is lower than V HV(min). This feature ensures to discharge quite big X2 capacitors used in the input line filter to the safe level. It is important to note that it is not allowed to connect HV pin to any dc voltage due this feature. e.g. directly to bulk capacitor. During the HV sensing or X2 cap discharging the VCC net is kept above the VCC(off) voltage by the Self−Supply in any mode of device operation to supply the control circuitry. During the discharge sequence is not allowed to start−up the device.
Figure 53. The ac Line Unplug Detector Timing Diagram Detail with Noise Effects
Figure 54. HV Pin ac Input Timing Diagram with X2 Capacitor Discharge Sequence when the Application is
Figure 55. HV Pin ac Input Timing Diagram with X2 Capacitor Discharge Sequence When the Application is decreases below the 0.6 V the controller enters the off mode. capacitor is maintained by the Dynamic Self−Supply circuit. features are disabled in this mode.
www.onsemi.com Quiet−Skip To further avoid acoustic noise, the circuit prevents the burst frequency during skip mode from entering the audible range by limiting it to a maximum of 800 Hz. This is achieved via a timer t quiet that is activated during Quiet−Skip. The start of the next burst cycle is prevented until this timer has expired. As the output power decreases, the switching frequency decreases. Once it hits minimum switching frequency f OSC(min), the skip −in threshold is reached and burst mode is entered − switching stops as soon as the current drive pulses ends – it does not stop immediately. Once switching stops, FB will rise. As soon as FB crosses the skip−exit threshold, drive pulses will resume, but the controller remains in burst mode. At this point, a 1250 /C0109s (typ) timer t quiet is started together with a count to n P,sk ip pulses counter. This n P,sk ip pulses counter ensures the minimum number of DRV signal pulses in burst. The next time the FB voltage drops below the skip−in threshold, DRV pulses stop at the end of the current pulse as long as n P,sk ip drive pulses have been counted (if not, they do not stop until the end of the n P,sk ip −th pulse). They are not allowed to start again until the timer expires, even if the skip−exit threshold is reached first. It is important to note that the timer will not force the next cycle to begin – i.e. if the natural skip frequency is such that skip −exit is reached after the timer expires, the drive pulses will wait for the skip −exit threshold. This means that during no−load, there will be a minimum of n P,sk ip drive pulses, and the burst−cycle period will likely be much longer than 1250 /C0109s. This operation helps to improve efficiency at no−load conditions. In order to exit burst mode, the FB voltage must rise higher than Vskip(tran) level. If this occurs before tquiet expires, the drive pulses will resume immediately – i.e. the controller won’t wait for the timer to expire. Figure 63 provides an example of how Quiet−Skip works, while Figure 62 shows the immediate leaving the quiet skip mode by crossing the transient enhancement level V skip(tran).
36 V, but most of the MOSFETs that will be connected to the
and 800 mA for sink current. soft−start (the 2 comparators outputs are OR’ed). Figure 64. Soft−Start Feature
Figure 67. Needs for Line Compensation For True Overpower Protection by changing the value of the resistor. Figure 68. Overpower Protection Current Relation to Feedback Voltage Figure 69. Overpower Protection Current Relation to Peak of Rectified Input Line AC voltage
365 V125 V
Figure 70. Block Schematic of Overpower Protection Circuit even with very poor coupling or high leakage inductance. supply. See Figure 71 for the timing diagram.
Figure 71. Overpower Compensation Timing Diagram
Table 6. PROTECTION MODES AND THE LATCH MODE RELEASES
Figure 72. Latched Timer−Based Overcurrent Protection
Figure 73. Timer−based Protection Mode with Autorecovery Release from Latch−off
Figure 74. OVP/OTP Detection Schematic
Figure 75. Latch Timing Diagram status diagrams at the Figure 44.
www.onsemi.com Ordering Part No. Overload Protection Switching Frequency Package Shipping† NCP12400BAHAB0DR2G Latched 65 kHz SOIC−7 (Pb−Free) 2500 / Tape & Reel NCP12400BAHBB0DR2G Latched 65 kHz NCP12400BBBBB2DR2G Autorecovery 65 → 100 kHz NCP12400BBHAA1DR2G Autorecovery 100 kHz NCP12400CAHAB0DR2G Latched 65 kHz NCP12400CBAAB0DR2G Autorecovery 65 kHz NCP12400CBBAB0DR2G Autorecovery 65 kHz NCP12400CBHAA0DR2G Autorecovery 65 kHz NCP12400EAHBB0DR2G Latched 65 kHz NCP12400BBBBA0DR2G Autorecovery 65 kHz NCP12400BBHAB0DR2G Autorecovery 65 kHz NCP12400BBEBA0DR2G Autorecovery 65 kHz NCP12400BBAAA0DR2G Autorecovery 65 kHz †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
SOIC−7 CASE 751U−01 ISSUE E DATE 20 OCT 2009 SEATING PLANE R J X 45/C0095 K NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B ARE DATUMS AND T IS A DATUM SURFACE. 4. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 5. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. S DH C SCALE 1:1 DIM A MIN MAX MIN MAX INCHES 4.80 5.00 0.189 0.197 MILLIMETERS B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.053 0.069 D 0.33 0.51 0.013 0.020 G 1.27 BSC 0.050 BSC H 0.10 0.25 0.004 0.010 J 0.19 0.25 0.007 0.010 K 0.40 1.27 0.016 0.050 M 0 8 0 8 N 0.25 0.50 0.010 0.020 S 5.80 6.20 0.228 0.244 −A− −B− G MBM0.25 (0.010) −T− BM0.25 (0.010) T S A S M XXX = Specific Device Code A = Assembly Location L = Wafer Lot Y = Year W = Work Week /C0071= Pb−Free Package GENERIC MARKING DIAGRAM 7 PL /C0095/C0095/C0095/C0095 *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ /C0071”, may or may not be present. XXXXX ALYWX /C0071 STYLES ON PAGE 2 1.52 0.060 7.0 0.275 0.6 0.024 1.270 0.050 4.0 0.155 /C0466mm inches/C0467SCALE 6:1 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. SOLDERING FOOTPRINT* MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. 98AON12199DDOCUMENT NUMBER: DESCRIPTION: Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 27−LEAD SOIC © Semiconductor Components Industries, LLC, 2019 www.onsemi.com
SOIC−7 CASE 751U−01 ISSUE E DATE 20 OCT 2009 STYLE 4: PIN 1. ANODE 2. ANODE 3. ANODE 4. ANODE 5. ANODE 6. ANODE 7. NOT USED 8. COMMON CATHODE STYLE 1: PIN 1. EMITTER 2. COLLECTOR 3. COLLECTOR 4. EMITTER 5. EMITTER 7. NOT USED 8. EMITTER STYLE 2: PIN 1. COLLECTOR, DIE, #1 2. COLLECTOR, #1 3. COLLECTOR, #2 4. COLLECTOR, #2 5. BASE, #2 6. EMITTER, #2 7. NOT USED 8. EMITTER, #1 STYLE 3: PIN 1. DRAIN, DIE #1 2. DRAIN, #1 3. DRAIN, #2 4. DRAIN, #2 5. GATE, #2 6. SOURCE, #2 7. NOT USED 8. SOURCE, #1 STYLE 6: PIN 1. SOURCE 2. DRAIN 3. DRAIN 4. SOURCE 5. SOURCE 7. NOT USED 8. SOURCE STYLE 5: PIN 1. DRAIN 2. DRAIN 3. DRAIN 4. DRAIN 7. NOT USED 8. SOURCE STYLE 7: PIN 1. INPUT 2. EXTERNAL BYPASS 3. THIRD STAGE SOURCE 4. GROUND 5. DRAIN 6. GATE 3 7. NOT USED 8. FIRST STAGE Vd STYLE 8: PIN 1. COLLECTOR (DIE 1) 2. BASE (DIE 1) 3. BASE (DIE 2) 4. COLLECTOR (DIE 2) 5. COLLECTOR (DIE 2) 6. EMITTER (DIE 2) 7. NOT USED 8. COLLECTOR (DIE 1) STYLE 9: PIN 1. EMITTER (COMMON) 2. COLLECTOR (DIE 1) 3. COLLECTOR (DIE 2) 4. EMITTER (COMMON) 5. EMITTER (COMMON) 6. BASE (DIE 2) 7. NOT USED 8. EMITTER (COMMON) STYLE 10: PIN 1. GROUND 2. BIAS 1 3. OUTPUT 4. GROUND 5. GROUND 6. BIAS 2 7. NOT USED 8. GROUND STYLE 11: PIN 1. SOURCE (DIE 1) 2. GATE (DIE 1) 3. SOURCE (DIE 2) 4. GATE (DIE 2) 5. DRAIN (DIE 2) 6. DRAIN (DIE 2) 7. NOT USED 8. DRAIN (DIE 1) ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. 98AON12199DDOCUMENT NUMBER: DESCRIPTION: Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 2 OF 27−LEAD SOIC © Semiconductor Components Industries, LLC, 2019 www.onsemi.com
onsemi, , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION TECHNICAL SUPPORT North American Technical Support: Voice Mail: 1 800−282−9855 Toll Free USA/Canada Phone: 011 421 33 790 2910 LITERATURE FULFILLMENT: Email Requests to: orderlit@onsemi.com onsemi Website: www.onsemi.com Europe, Middle East and Africa Technical Support: Phone: 00421 33 790 2910 For additional information, please contact your local Sales Representative