CD4001BC FAIRCHILD | Alldatasheet

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I Low power TTL: Fan out of 2 driving 74L compatibility: or 1 driving 74LS I 5V–10V–15V parametric ratings I Symmetrical output characteristics I Maximum input leakage 1 µA at 15V over full temperature range Ordering Code: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagrams Pin Assignments for DIP , SOIC and SOP CD4001BC Top View Pin Assignments for DIP and SOIC CD4011BC Top View Order Number Package Number Package Description CD4001BCM M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow CD4001BCSJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide CD4001BCN N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide CD4011BCM M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow CD4011BCN N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

www.fairchildsemi.com 2 CD4001BC/CD4011BC Schematic Diagrams CD4001BC 1/4 of device shown J = A + B Logical “1” = HIGH Logical “0” = LOW All inputs protected by standard CMOS protection circuit. CD4011BC 1/4 of device shown J = A  B Logical “1” = HIGH Logical “0” = LOW All inputs protected by standard CMOS protection circuit.

3 www.fairchildsemi.com CD4001BC/CD4011BC Absolute Maximum Ratings(Note 1) (Note 2) Recommended Operating Conditions Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. Except for “Operating Tempera- ture Range” they are not meant to imply that the devices should be oper- ated at these limits. The Electrical Characteristics tables provide conditions for actual device operation. Note 2: All voltages measured with respect to V SS unless otherwise speci- fied. Note 3: IOL and IOH are tested one output at a time. CD4001BC: TA = 25°C, Input tr; tf = 20 ns. CL = 50 pF, RL = 200k. Typical temperature coefficient is 0.3%/°C. Note 4: AC Parameters are guaranteed by DC correlated testing. Voltage at any Pin −0.5V to VDD +0.5V Power Dissipation (PD ) Dual-In-Line 700 mW Small Outline 500 mW V DD Range −0.5 VDC to +18 VDC Storage Temperature (TS) −65°C to +150°C Lead Temperature (TL) (Soldering, 10 seconds) 260 °C Operating Range (VDD )3 V DC to 15 VDC Operating Temperature Range CD4001BC, CD4011BC −55°C to +125°C Symbol Parameter Conditions −55°C +25°C +125°C Units Min Max Min Typ Max Min Max IDD Quiescent Device V DD = 5V, VIN = VDD or VSS 0.25 0.004 0.25 7.5 µACurrent V DD = 10V, VIN = VDD or VSS 0.5 0.005 0.50 15 VDD = 15V, VIN = VDD or VSS 1.0 0.006 1.0 30 VOL LOW Level V DD = 5V 0.05 0 0.05 0.05 VOutput Voltage V DD = 10V |I O | < 1 µA 0.05 0 0.05 0.05 VDD = 15V 0.05 0 0.05 0.05 VOH HIGH Level V DD = 5V 4.95 4.95 5 4.95 VOutput Voltage V DD = 10V |I O | < 1 µA 9.95 9.95 10 9.95 VDD = 15V 14.95 14.95 15 14.95 VIL LOW Level V DD = 5V, VO = 4.5V 1.5 2 1.5 1.5 VInput Voltage V DD = 10V, VO = 9.0V 3.0 4 3.0 3.0 VDD = 15V, VO = 13.5V 4.0 6 4.0 4.0 VIH HIGH Level V DD = 5V, VO = 0.5V 3.5 3.5 3 3.5 VInput Voltage V DD = 10V, VO = 1.0V 7.0 7.0 6 7.0 VDD = 15V, VO = 1.5V 11.0 11.0 9 11.0 IIN Input Current V DD = 15V, VIN = 0V −0.10 −10−5 −0.10 −1.0 µA VDD = 15V, VIN = 15V 0.1 10 −5 0.10 1.0 Symbol Parameter Conditions Typ Max Units tPHL Propagation Delay Time, V DD = 5V 120 250 nsHIGH-to-LOW Level V DD = 10V 50 100 VDD = 15V 35 70 tPLH Propagation Delay Time, V DD = 5V 110 250 nsLOW-to-HIGH Level V DD = 10V 50 100 VDD = 15V 35 70 tTHL , tTLH Transition Time V DD = 5V 90 200 nsVDD = 10V 50 100 VDD = 15V 40 80 C IN Average Input Capacitance Any Input 5 7.5 pF C PD Power Dissipation Capacity Any Gate 14 pF

www.fairchildsemi.com 4 CD4001BC/CD4011BC CD4011BC: TA= 25°C, Input tr; tf = 20 ns. CL = 50 pF, RL = 200k. Typical Temperature Coefficient is 0.3%/°C. Note 5: AC Parameters are guaranteed by DC correlated testing. Typical Performance Characteristics Typical Transfer Characteristics Typical Transfer Characteristics Typical Transfer Characteristics Symbol Parameter Conditions Typ Max Units tPHL Propagation Delay, V DD = 5V 120 250 nsHIGH-to-LOW Level V DD = 10V 50 100 VDD = 15V 35 70 tPLH Propagation Delay, V DD = 5V 85 250 nsLOW-to-HIGH Level V DD = 10V 40 100 VDD = 15V 30 70 tTHL , tTLH Transition Time V DD = 5V 90 200 nsVDD = 10V 50 100 VDD = 15V 40 80 C IN Average Input Capacitance Any Input 5 7.5 pF C PD Power Dissipation Capacity Any Gate 14 pF

5 www.fairchildsemi.com CD4001BC/CD4011BC Typical Performance Characteristics (Continued) Typical Transfer Characteristics

www.fairchildsemi.com 6 CD4001BC/CD4011BC Typical Performance Characteristics (Continued)

7 www.fairchildsemi.com CD4001BC/CD4011BC Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M14A

www.fairchildsemi.com 8 CD4001BC/CD4011BC Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D

9 www.fairchildsemi.com CD4001BC/CD4011BC Quad 2-Input NOR Buffered B Series Gate  Quad 2-Input NAND Buffered B Series Gate Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N14A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD ’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com