3826A

3826A RENESAS | Alldatasheet

Document overview

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Technical content

DESCRIPTION

The 3826 group (A version) is the 8-bit microcomputer based on the 740 family core technology. The 3826 group (A version) has the LCD drive control circuit, an 8- channel A/D converter, D/A converter, serial interface and PWM as additional functions. The various microcomputers in the 3826 group (A version) include variations of internal memory size and packaging. For details, re- fer to the section on part numbering. For details on availability of microcomputers in the 3826 group (A version), refer the section on group expansion.

FEATURES

(at 10 MHz oscillation frequency)

• Memory size
• Serial interface (used as DTMF and CTCSS function)
• LCD drive control circuit
• 2 Clock generating circuits (connect to external ceramic resonator or quartz-crystal oscillator)
• Power source voltage
• Power dissipation (f(XIN) = 10 MHz, VCC = 5 V, Ta = 25 °C) (f(XIN) = stop, f(XCIN) = 32 kHz, VCC = 3 V, Ta = 25 °C)

APPLICATIONS

Camera, household appliances, consumer electronics, etc.

3826 Group (A version)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER REJ03B0029-0200 Rev.2.00 2006.05.24 Rev.2.00 May. 24, 2006 page 1 of 90 REJ03B0028-0200

Rev.2.00 May. 24, 2006 page 2 of 90 REJ03B0028-0200 PIN CONFIGURATION (TOP VIEW) Fig. 2 Pin configuration (Package type: PLQP0100KB-A) 1 2 3 4 5 6 7 8 9 1 01 11 21 31 41 51 61 71 81 92 02 12 22 32 42 5 51525354555657585960616263646566676869707172737475

001 M3826XMXA-XXXGP

3/φ/T OUT 3/RTP 2/RTP 1/PWM 0/PWM 2/INT P72 P73 P71 P70/INT0 XCIN XCOUT XIN XOU T VSS P27 P26 P25 P24 P23 P21 P16 P22 P20 P17 RESET P76 P75 P74 P15/SEG 39 P14/SEG 38 1/SEG 0/SEG 2/SEG 3/SEG 4/SEG SEG SEG SEG 5/SEG 6/SEG 7/SEG 0/SEG 1/SEG 2/SEG 3/SEG 4/SEG 5/SEG 6/SEG 7/SEG 0/SEG 1/SEG 2/SEG 3/SEG SEG SEG P62/S CLK21 /AN 1/S OUT2 /AN 0/S IN2 /AN P63/S CLK22 /AN 6/S CLK1 5/T XD 4/R XD 7/S RDY1 Fig. 1 Pin configuration (Package type: PRQP0100JB-A) 1 2 3 4 5 6 7 8 9 1 01 11 21 31 41 51 61 71 81 92 02 12 22 32 42 52 62 72 82 93 0 515253545556575859606162636465666768697071727374757677787980 100 M3826XMXA-XXXFP SEG 9 1/SEG 0/SEG 2/SEG 3/SEG 4/SEG SEG SEG SEG SEG SEG SEG 5/SEG 6/SEG 7/SEG 0/SEG 1/SEG 2/SEG 3/SEG 4/SEG 5/SEG 6/SEG 7/SEG 0/SEG 1/SEG 2/SEG 3/SEG 4/SEG 5/SEG C V 7/AN 6/AN 5/AN 4/AN 2/S CLK21 /AN 1/S OUT2 /AN 0/S IN2 /AN 7/ADT/DA 6/DA 5/CNTR 4/CNTR 3/RTP 2/RTP 1/PWM 0/PWM 6/S CLK1 5/T XD 4/R XD 3/φ/T OUT 2/INT 1/INT C 2 VL2 VL3 COM 0 COM 1 COM 2 VREF AV SS VCC SEG 8 SEG 0 SEG 1 SEG 2 SEG 4 SEG 5 SEG 6 SEG 7 SEG 3 P72 P73 P71 P70/INT0 XCIN XCOUT XIN XOUT VSS P27 P26 P25 P24 P23 P21 P16 P22 P20 P17 RESET SEG SEG COM 3 7/S RDY1 3/S CLK22 /AN

Rev.2.00 May. 24, 2006 page 3 of 90 REJ03B0028-0200 FUNCTIONAL BLOCK DIAGRAM (Package type: PRQP0100JB-A) Fig. 3 Functional block diagram INT1,INT2 CNTR 0,CNTR DA ADTC P U A X Y S PC H PC L PS RESET V CC V SS ( 5 V ) ( 0 V ) R O M R A M 91 40 P4(8) P2(8) P0(8) P1(8) P6(8) P7(8) P3(8) P5(8) 12 10099 98 97 96 95 94 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 57 58 59 60 61 62 63 64 49 50 51 52 53 54 55 56 41 42 43 44 45 46 47 48 65 66 67 68 69 70 71 72 19 20 21 22 23 24 25 26 36 37 27 28 29 30 31 32 33 34 34567 89 1 0 9 3 11 12 13 14 15 16 17 18 X CIN X COUT X IN OUT X COUT X X CIN SI/O1 (8) V REF AV SS V C C V V COM COM COM COM SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG φ X CIN COUT X 38 39 SI/O2(8) PWM(8) φ INT0 DA2/CTCSS DA1/DTMF DA T OUT LCD drive control circuit LCD display RAM (20 bytes) Timer X (16)Timer Y (16) Timer 1 (8) Timer 2 (8)Timer 3 (8) Data bus Clock generating circuit Main clock input Main clock output Sub-clockoutput Sub-clock input Reset Key input (Key-on wake up) interrupt Real time port function A/D converter (8) I/O port P0 I/O port P1 I/O port P2 I/O port P4 I/O port P5 I/O port P6 Output port P3 I/O port P7 Reset input Sub-clock output Sub-clock inputWatchdog timer

Rev.2.00 May. 24, 2006 page 4 of 90 REJ03B0028-0200 Table 1 Pin description (1) VCC VSS FunctionPin Name Function except a port function

• LCD segment output pins Power source • Apply voltage of power source to VCC , and 0 V to VSS . (For the limits of VCC , refer to “Recom- mended operating conditions”. VREF AV SS RESET XIN XOUT VL1–VL3 C 1, C2 COM 0–COM 3 SEG 0–SEG 17 P00/SEG 26– P07/SEG 33 P10/SEG 34– P15/SEG 39 P16, P17 P20 – P27 P3 0/SEG 18 – P3 7/SEG 25 Analog refer- ence voltage Analog power source Reset input Clock input Clock output LCD power source Charge-pump capacitor pin Common output Segment output I/O port P0 I/O port P1 I/O port P2 Output port P3
• Reference voltage input pin for A/D converter and D/A converter.
• GND input pin for A/D converter and D/A converter.
• Connect to V SS .
• Reset input pin for active “L”.
• Input and output pins for the main clock generating circuit.
• Connect a ceramic resonator or a quartz-crystal oscillator between the X IN and XOUT pins to set the oscillation frequency.
• If an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open. A feedback resistor is built-in.
• Input 0 ≤ VL1 ≤ VL2 ≤ VL3 voltage.
• Input 0 – VL3 voltage to LCD. (0 ≤ VL1 ≤ VL2 ≤ VL3 when a voltage is multiplied.)
• External capacitor pins for a voltage multiplier (3 times) of LCD control.
• LCD common output pins.
• COM 2 and COM 3 are not used at 1/2 duty ratio.
• COM 3 is not used at 1/3 duty ratio.
• LCD segment output pins.
• 8-bit I/O port.
• CMOS compatible input level.
• CMOS 3-state output structure.
• Pull-up control is enabled.
• I/O direction register allows each 8-bit pin to be pro- grammed as either input or output.
• 6-bit I/O port.
• CMOS compatible input level.
• CMOS 3-state output structure.
• Pull-up control is enabled.
• I/O direction register allows each 6-bit pin to be pro- grammed as either input or output.
• 2-bit I/O port.
• CMOS compatible input level.
• CMOS 3-state output structure.
• I/O direction register allows each pin to be individually programmed as either input or output.
• Pull-up control is enabled.
• 8-bit I/O port.
• CMOS compatible input level.
• CMOS 3-state output structure.
• I/O direction register allows each pin to be individually programmed as either input or output.
• Pull-up control is enabled.
• 8-bit output.
• CMOS 3-state output structure.
• Port output control is enabled.
• Key input (key-on wake-up) interrupt input pins
• LCD segment output pins

Rev.2.00 May. 24, 2006 page 5 of 90 REJ03B0028-0200 Table 2 Pin description (2) FunctionPin Name Function except a port function P40 P41/INT1, P42/INT2 P43/φ/TOUT P44/RXD, P45/TXD, P46/SCLK1 , P47/SRDY1 P50/PWM 0, P51/PWM 1 P52/RTP0, P53/RTP1 P54/CNTR 0, P55/CNTR 1 P56/DA1 P57/ADT/DA2 P60/SIN2/AN0, P61/SOUT2 /AN1, P62/SCLK21 /AN2, P63/SCLK22 /AN3 P64/AN4– P67/AN7 P70/INT0 P71–P7 7 I/O port P4 I/O port P5 I/O port P6 Input port P7 I/O port P7 Sub-clock output Sub-clock input

• 1-bit I/O port.
• CMOS compatible input level.
• N-channel open-drain output structure.
• I/O direction register allows this pin to be individually programmed as either input or output.
• 7-bit I/O port.
• CMOS compatible input level.
• CMOS 3-state output structure.
• I/O direction register allows each pin to be individually programmed as either input or output.
• Pull-up control is enabled.
• 8-bit I/O port.
• CMOS compatible input level.
• CMOS 3-state output structure.
• I/O direction register allows each pin to be individually programmed as either input or output.
• Pull-up control is enabled.
• 8-bit I/O port.
• CMOS compatible input level.
• CMOS 3-state output structure.
• I/O direction register allows each pin to be individually programmed as either input or output.
• Pull-up control is enabled.
• 1-bit input port.
• INT i interrupt input pins
• System clock φ output pin
• Timer 2 output pin
• Serial I/O1 I/O pins
• PWM output pins
• Real time port output pins
• Timer X, Y I/O pins
• D/A converter output pin
• D/A converter output pin
• A/D external trigger input pin
• A/D converter input pins
• Serial I/O2 I/O pins
• A/D converter input pins XCOUT XCIN
• INT0 interrupt input pin
• 7-bit I/O port.
• CMOS compatible input level.
• N-channel open-drain output structure.
• I/O direction register allows each pin to be individually programmed as either input or output.
• Sub-clock generating circuit I/O pins. (Connect a oscillator. External clock cannot be used.)

Rev.2.00 May. 24, 2006 page 6 of 90 REJ03B0028-0200 Fig. 4 Part numbering M3826 A M F A – XXX FPProduct ROM size A B C D E F : 4096 bytes : 8192 bytes : 12288 bytes : 16384 bytes : 20480 bytes : 24576 bytes : 28672 bytes : 32768 bytes : 36864 bytes : 40960 bytes : 45056 bytes : 49152 bytes : 53248 bytes : 57344 bytes : 61440 bytes The first 128 bytes and the last 2 bytes of ROM are reserved areas ; they cannot be used. Memory type M: Mask ROM version ROM number Package type FP GP : PRQP0100JB-A : PLQP0100KB-A Characteristics A : A version : 192 bytes : 256 bytes : 384 bytes : 512 bytes : 640 bytes : 768 bytes : 896 bytes : 1024 bytes : 1536 bytes : 2048 bytes : 2560 bytes RAM size A

Rev.2.00 May. 24, 2006 page 7 of 90 REJ03B0028-0200 Renesas expands the 3826 group (A version) as follows. Memory Type Support for mask ROM version. Memory Size Packages Memory Expansion Plan Fig. 5 Memory expansion plan R OM size (bytes) RAM size (bytes) 256 512 768 1024 1280 1536 1792192 2048 2304 2560 32K 28K 24K 20K 16K 12K 52K 48K 44K 40K 36K 56K 60K M38268MCA M3826AMFA Mass production Mass production Currently planning products are listed below. Table 3 Support products As of Apr. 2006 Remarks Mask ROM version Mask ROM version Mask ROM version Mask ROM version Package PRQP0100JB-A PLQP0100KB-A PRQP0100JB-A PLQP0100KB-A Part number M38268MCA-XXXFP M38268MCA-XXXGP M3826AMFA-XXXFP M3826AMFA-XXXGP RAM size (bytes) 153649152 (49022) 61440 (61310) ROM size (bytes) ROM size for User in ( ) 2560

Rev.2.00 May. 24, 2006 page 8 of 90 REJ03B0028-0200 CENTRAL PROCESSING UNIT (CPU) The 3826 group uses the standard 740 family instruction set. Re- fer to the table of 740 family addressing modes and machine instructions or the 740 Family Software Manual for details on the instruction set. Machine-resident 740 family instructions are as follows: The FST and SLW instruction cannot be used. The STP, WIT, MUL, and DIV instruction can be used. The central processing unit (CPU) has six registers. Figure 6 shows the 740 Family CPU register structure. [Accumulator (A)] The accumulator is an 8-bit register. Data operations such as arithmetic data transfer, etc., are executed mainly through the ac- cumulator. [Index Register X (X)] The index register X is an 8-bit register. In the index addressing modes, the value of the OPERAND is added to the contents of register X and specifies the real address. [Index Register Y (Y)] The index register Y is an 8-bit register. In partial instruction, the value of the OPERAND is added to the contents of register Y and specifies the real address. [Stack Pointer (S)] The stack pointer is an 8-bit register used during subroutine calls and interrupts. This register indicates start address of stored area (stack) for storing registers during subroutine calls and interrupts. The low-order 8 bits of the stack address are determined by the contents of the stack pointer. The high-order 8 bits of the stack address are determined by the stack page selection bit. If the stack page selection bit is “0” , the high-order 8 bits becomes “00 16”. If the stack page selection bit is “1”, the high-order 8 bits becomes “0116”. Figure 9 shows the operations of pushing register contents onto the stack and popping them from the stack. Table 6 shows the push and pop instructions of accumulator or processor status reg- ister. Store registers other than those described in Figure 9 with pro- gram when the user needs them during interrupts or subroutine calls. [Program Counter (PC)] The program counter is a 16-bit counter consisting of two 8-bit registers PCH and PCL. It is used to indicate the address of the next instruction to be executed. Fig. 6 740 Family CPU register structure A Accumulator b7 b0 b15 b0 b7 b0 X Index register X Y Index register Y S Stack pointer PC L Program counterPC H N V T B D I Z C Processor status register (PS) Carry flag Zero flag Interrupt disable flag Decimal mode flag Break flag Index X mode flag Overflow flag Negative flag

Rev.2.00 May. 24, 2006 page 9 of 90 REJ03B0028-0200 Table 4 Push and pop instructions of accumulator or processor status register Accumulator Processor status register Push instruction to stack PHA PHP Pop instruction from stack PLA PLP Fig. 7 Register push and pop at interrupt generation and subroutine call N o t e: C o n d i t i o n f o r a c c e p t a n c e o f a n i n t e r r u p t r e q u e s t h e r e E x e c u t e J S R O n g o i n g R o u t i n e M S P C H ) S S M S P C L) E x e c u t e R T S P C L)M S S S S S S S P C H )M S S u b r o u t i n e P O P re t u r n a d d r e s s f r o m s t a c k P u s h r e t u r n a d d r e s s o n s t a c k M S P S E x e c u t e R T I P S S S S S S I n t e r r u p t S e r v i c e R o u t i n e P O P c o n t e n t s o f p r o c e s s o r s t a t u s r e g i s t e r f r o m s t a c k M S P C H ) S S M S P C L) S S P C L)M S S S S S P C H )M S P O P r e t u r n a d d r e s s f r o m s t a c k I F l a g i s s e t f r o m t o F e t c h t h e j u m p v e c t o r P u s h r e t u r n a d d r e s s o n s t a c k P u s h c o n t e n t s o f p r o c e s s o r s t a t u s r e g i s t e r o n s t a c k I n t e r r u p t r e q u e s t N o t e I n t e r r u p t e n a b l e b i t c o r r e s p o n d i n g t o e a c h i n t e r r u p t s o u r c e i s “ 1 ” I n t e r r u p t d i s a b l e f l a g i s

Rev.2.00 May. 24, 2006 page 10 of 90 REJ03B0028-0200 [Processor status register (PS)] The processor status register is an 8-bit register consisting of 5 flags which indicate the status of the processor after an arithmetic operation and 3 flags which decide MCU operation. Branch opera- tions can be performed by testing the Carry (C) flag , Zero (Z) flag, Overflow (V) flag, or the Negative (N) flag. In decimal mode, the Z, V, N flags are not valid.

• Bit 0: Carry flag (C) The C flag contains a carry or borrow generated by the arith- metic logic unit (ALU) immediately after an arithmetic operation. It can also be changed by a shift or rotate instruction.
• Bit 1: Zero flag (Z) The Z flag is set to “1” if the result of an immediate arithmetic op- eration or a data transfer is “0”, and set to “0” if the result is anything other than “0”.
• Bit 2: Interrupt disable flag (I) The I flag disables all interrupts except for the interrupt gener- ated by the BRK instruction. Interrupts are disabled when the I flag is “1”.
• Bit 3: Decimal mode flag (D) The D flag determines whether additions and subtractions are executed in binary or decimal. Binary arithmetic is executed when this flag is “0”; decimal arithmetic is executed when it is “1”. Decimal correction is automatic in decimal mode. Only the ADC and SBC instructions can be used for decimal arithmetic.
• Bit 4: Break flag (B) The B flag is used to indicate that the current interrupt was gen- erated by the BRK instruction. When the BRK instruction is generated, the B flag is set to “1” automatically. When the other interrupts are generated, the B flag is set to “0”, and the proces- sor status register is pushed onto the stack.
• Bit 5: Index X mode flag (T) When the T flag is “0”, arithmetic operations are performed be- tween accumulator and memory. When the T flag is “1”, direct arithmetic operations and direct data transfers are enabled be- tween memory locations.
• Bit 6: Overflow flag (V) The V flag is used during the addition or subtraction of one byte of signed data. It is set to “1” if the result exceeds +127 to -128. When the BIT instruction is executed, bit 6 of the memory loca- tion operated on by the BIT instruction is stored in the V flag.
• Bit 7: Negative flag (N) The N flag is set to “1” if the result of an arithmetic operation or data transfer is negative. When the BIT instruction is executed, bit 7 of the memory location operated on by the BIT instruction is stored in the negative flag. Table 5 Instructions to set each bit of processor status register to “0” or “1” Instruction setting to “1” Instruction setting to “0” C flag SEC CLC Z flag I flag SEI CLI D flag SED CLD B flag T flag SET CLT V flag CLV N flag

Rev.2.00 May. 24, 2006 page 11 of 90 REJ03B0028-0200 [CPU Mode Register (CPUM)] 003B16 The CPU mode register contains the stack page selection bit and the system clock control bits, etc. The CPU mode register is allocated at address 003B16. Fig. 8 Structure of CPU mode register P r o c e s s o r m o d e b i t s b b S i n g l e c h i p m o d e S t a c k p a g e s e l e c t i o n b i t p a g e p a g e N o t u s e d a t r e a d i n g W r i t e t o t h i s b i t a t w r i t i n g XC s w i t c h b i t O s c i l l a t i o n s t o p XC I N – XC O U T o s c i l l a t i n g f u n c t i o n M a i n c l o c k XI N –XO U s t o p b i t O s c i l l a t i n g S t o p p e d M a i n c l o c k d i v i s i o n r a t i o s e l e c t i o n b i t f XI N ) h i g h s p e e d m o d e f XI N ) m i d d l e s p e e d m o d e Sy s t e m c l o c k s e l e c t i o n b i t XI N – XO U T s e l e c t e d m i d d l e h i g h s p e e d m o d e XC I N – XC O U T s e l e c t e d l o w s p e e d m o d e D o n o t s e l e c t C P U m o d e r e g i s t e r ( C P U M ( C M ) : a d d r e s s 0 0 3 B1 b 7 b 0

Rev.2.00 May. 24, 2006 page 12 of 90 REJ03B0028-0200 Special Function Register (SFR) Area The Special Function Register area in the zero page contains con- trol registers such as I/O ports and timers. RAM RAM is used for data storage and for stack area of subroutine calls and interrupts. ROM The first 128 bytes and the last 2 bytes of ROM are reserved for device testing and the rest is user area for storing programs. Interrupt Vector Area The interrupt vector area contains reset and interrupt vectors. Zero Page The 256 bytes from addresses 000016 to 00FF16 are called the zero page area. The internal RAM and the special function regis- ters (SFR) are allocated to this area. The zero page addressing mode can be used to specify memory and register addresses in the zero page area. Access to this area with only 2 bytes is possible in the zero page addressing mode. Special Page The 256 bytes from addresses FF0016 to FFFF16 are called the special page area. The special page addressing mode can be used to specify memory addresses in the special page area. Ac- cess to this area with only 2 bytes is possible in the special page addressing mode. Fig. 9 Memory map diagram 1 9 2 0 0 F F1 B B B A R A M a r e a R A M s i z e b y t e s A d d r e s s X X X 4 0 9 6 F 0 0 01 E D C B A F 0 8 01 E D C B A R O M a r e a R O M s i z e b y t e s A d d r e s s Y Y Y A d d r e s s Z Z Z 0 1 0 01 0 0 0 01 0 0 4 01 F F 0 01 F F D C 1 F F F E1 F F F F1 X X X X1 Y Y Y Y1 Z Z Z Z1 R A M R O M 0 0 5 41 S F R a r e a N o t u s e d I n t e r r u p t v e c t o r a r e a R e s e r v e d R O M a r e a b y t e s Z e r o p a g e S p e c i a l p a g e L C D d i s p l a y R A M a r e a R e s e r v e d R O M a r e a

Rev.2.00 May. 24, 2006 page 13 of 90 REJ03B0028-0200 Fig. 10 Memory map of special function register (SFR) 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C 16 002D 16 002E16 002F16 003016 003116 003216 003316 003416 003516 003616 003716 003816 003916 003A16 003B16 003C 16 003D 16 003E16 003F16 000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C 16 000D 16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C 16 001D 16 001E16 001F16 Port P0 register (P0) Port P1 register (P1) Port P1 direction register (P1D) Port P2 register (P2) Port P2 direction register (P2D) Port P3 register (P3) Port P4 register (P4) Port P4 direction register (P4D) Port P5 register (P5) Port P5 direction register (P5D) Port P6 register (P6) Port P6 direction register (P6D) Port P7 register (P7) Port P7 direction register (P7D) Serial I/O1 status register (SIO1STS) Serial I/O1 control register (SIO1CON) UART control register (UARTCON) Baud rate generator (BRG) Interrupt control register 2(ICON2) Timer 3 register (T3) Timer X mode register (TXM) Interrupt edge selection register (INTEDGE) CPU mode register (CPUM) Interrupt request register 1(IREQ1) Interrupt request register 2(IREQ2) Interrupt control register 1(ICON1) Timer X low-order register (TXL) Timer Y low-order register (TYL) Timer 1 register (T1) Timer 2 register (T2) Timer X high-order register (TXH) Timer Y high-order register (TYH) PULL register A (PULLA) PULL register B (PULLB) Timer Y mode register (TYM) Timer 123 mode register (T123M) TOUT /φ output control register (CKOUT) Segment output enable register (SEG) LCD mode register (LM) AD control register (ADCON) AD conversion high-order register (ADH) Transmit/Receive buffer register(TB/RB) Key input control register (KIC) Port P0 direction register (P0D) Port P3 output control register (P3C) Reserved area (Note) Serial I/O2 control register (SIO2CON) Serial I/O2 register (SIO2) PWM control register (PWMCON) PWM prescaler (PREPWM) PWM register (PWM) DA1 conversion register (DA1) DA2 conversion register (DA2) DA control register (DACON) Watchdog timer control register (WDTCON) Note: Do not write to the addresses of reserved area. AD conversion low-order register (ADL) CTSCSS timer (low) (CTCSSL) CTSCSS timer (high) (CTCSSH) DTMF high group timer (DTMFH) DTMF low group timer (DTMFL)

Rev.2.00 May. 24, 2006 page 14 of 90 REJ03B0028-0200 The I/O ports (ports P0, P1, P2, P4, P5, P6, P71–P7 7) have direc- tion registers. Ports P16, P17, P4, P5, P6, and P71–P77 can be set to input mode or output mode by each pin individually. P00–P0 7 and P10-P15 are respectively set to input mode or output mode in a lump by bit 0 of the direction registers of ports P0 and P1 (see Figure 11). When “0” is set to the bit corresponding to a pin, that pin becomes an input mode. When “1” is set to that bit, that pin becomes an output mode. If data is read from a port set to output mode, the value of the port latch is read, not the value of the pin itself. A port set to input mode is floating. If data is read from a port set to input mode, the value of the pin itself is read. If a pin set to input mode is written to, only the port latch is written to and the pin remains floating. Port P3 Output Control Register Bit 0 of the port P3 output control register (address 000716) en- ables control of the output of ports P30–P3 7. When the bit is set to “1”, the port output function is valid. When resetting, bit 0 of the port P3 output control register is set to “0” (the port output function is invalid) and pulled up. Fig. 11 Structure of port P0 direction register, port P1 direc- tion register Fig. 12 Structure of port P3 output control register Po r t s P 00 t o P 07 d i r e c t i o n r e g i s t e r I n p u t m o d e O u t p u t m o d e N o t u s e d U n d e f i n e d a t r e a d i n g I f w r i t i n g t o t h e s e b i t s w r i t e P o r t P 0 d i r e c t i o n r e g i s t e r P D a d d r e s s b 7 b 0 N o t e : I n p o r t s s e t t o o u t p u t m o d e , t h e p u l l - u p c o n t r o l b i t b e c o m e s i n v a l i d a n d p u l l u p r e s i s t o r i s n o t c o n n e c t e d P o r t s P 10 t o P 15 d i r e c t i o n r e g i s t e r I n p u t m o d e O u t p u t m o d e N o t u s e d U n d e f i n e d a t r e a d i n g I f w r i t i n g t o t h e s e b i t s w r i t e P o r t P d i r e c t i o n r e g i s t e r P o r t P d i r e c t i o n r e g i s t e r I n p u t m o d e O u t p u t m o d e P o r t P 1 d i r e c t i o n r e g i s t e r P D a d d r e s s b 7 b 0 P o r t s P 30 t o P 37 o u t p u t c o n t r o l b i t O u t p u t f u n c t i o n i s i n v a l i d P u l l e d u p O u t p u t f u n c t i o n i s v a l i d N o p u l l u p N o t u s e d U n d e f i n e d a t r e a d i n g I f w r i t i n g t o t h e s e b i t s w r i t e P o r t P 3 o u t p u t c o n t r o l r e g i s t e r P C a d d r e s s b 7 b 0 N o t e : I n p i n s s e t t o s e g m e n t o u t p u t b y s e g m e n t o u t p u t e n a b l e b i t s b i t s o f s e g m e n t o u t p u t e n a b l e r e g i s t e r a d d r e s s t h i s b i t b e c o m e s i n v a l i d a n d p u l l u p r e s i s t o r i s n o t c o n n e c t e d

Rev.2.00 May. 24, 2006 page 15 of 90 REJ03B0028-0200 Fig. 13 Structure of PULL register A and PULL register B Pull-up Control By setting the PULL register A (address 001616) or the PULL reg- ister B (address 001716), ports P0 to P2, P4 to P6 can control pull-up with a program. However, the contents of PULL register A and PULL register B do not affect ports set to output mode and the ports are no pulled up. The PULL register A setting is invalid for pins selecting segment output with the segment output enable register and the pins are not pulled up. P 00, P 01 p u l l - u p c o n t r o l b i t P 02, P p u l l u p c o n t r o l b i t P 04– P p u l l u p c o n t r o l b i t P 10–P p u l l u p c o n t r o l b i t P 14, P p u l l u p c o n t r o l b i t P 16, P p u l l u p c o n t r o l b i t P 20–P p u l l u p c o n t r o l b i t P 24– P p u l l u p c o n t r o l b i t P U L L r e g i s t e r A P U L L A a d d r e s s b 7 b 0 P 41– P 43 p u l l - u p c o n t r o l b i t P 44– P p u l l u p c o n t r o l b i t P 50– P p u l l u p c o n t r o l b i t P 54– P p u l l u p c o n t r o l b i t P 60– P p u l l u p c o n t r o l b i t P 64– P p u l l u p c o n t r o l b i t N o t u s e d a t r e a d i n g 0 : D i s a b l e E n a b l e P U L L r e g i s t e r B P U L L B a d d r e s s b 7 b 0 N o t e : T h e c o n t e n t s o f P U L L r e g i s t e r A a n d P U L L r e g i s t e r B d o n o t a f f e c t p o r t s s e t t o o u t p u t m o d e

Rev.2.00 May. 24, 2006 page 16 of 90 REJ03B0028-0200 A/D external trigger input DA 1 output DTMF input Diagram No.Related SFRsInput/OutputNamePin Non-Port FunctionI/O Format Table 6 List of I/O port function (1) P00/SEG 26– P07/SEG 33 P10/SEG 34– P15/SEG 39 P16 , P17 P20–P2 7 P30/SEG 18– P37/SEG 25 P40 P41/INT1, P42/INT2 P43/φ/TOUT P44/RXD, P45/TXD, P46/SCLK1 , P47/SRDY1 P50/PWM 0, P51/PWM 1 P52/RTP0, P53/RTP1 P54/CNTR 0 P55/CNTR 1 P56/DA1 P57/ADT/ DA 2 Port P0 Port P1 Port P2 Port P3 Port P4 Port P5 Input/output, byte unit Input/output, 6-bit unit Input/output, individual bits Input/output, individual bits Output Input/output, individual bits Input/output, individual bits CMOS compatible input level CMOS 3-state output CMOS compatible input level CMOS 3-state output CMOS compatible input level CMOS 3-state output CMOS compatible input level CMOS 3-state output CMOS 3-state output CMOS compatible input level N-channel open-drain output CMOS compatible input level CMOS 3-state output CMOS compatible input level CMOS 3-state output LCD segment output LCD segment output Key input (key-on wake-up) interrupt input LCD segment output INT i interrupt input Timer 2 output System clock φ output Serial I/O1 I/O Real time port output Timer X I/O Timer Y input PULL register A Segment output enable register PULL register A Segment output enable register PULL register A PULL register A Interrupt control register 2 Key input control register Segment output enable register Interrupt edge selection register PULL register B Timer 123 mode register TOUT /φ output control register PULL register B Serial I/O1 control register Serial I/O1 status register UART control register PULL register B PWM control register PULL register B Timer X mode register PULL register B Timer X mode register PULL register B Timer Y mode register PULL register B DA control register PULL register B DA control register AD control register (1) (2) (1) (2) (4) (3) (13) (4) (12) (5) (6) (7) (8) (10) (9) (11) (14) (15) (15) Port P3 output control register

Rev.2.00 May. 24, 2006 page 17 of 90 REJ03B0028-0200 Pin Name I/O Format Non-Port Function Related SFR S Diagram No.Input/Output Notes 1: How to use double-function ports as function I/O pins, refer to the applicable sections. 2: Make sure that the input level at each pin is either 0 V or VCC before execution of the STP instruction. When an electric potential is at an intermediate potential, a current will flow from VCC to VSS through the input-stage gate and power source current may increase. Table 7 List of I/O port function (2) P60/SIN2/AN0 P61/SOUT2 / AN 1 P62/SCLK21 / AN 2 P63/SCLK22 / AN 3 P64/AN4– P67/AN7 P70/INT0 P71–P7 7 COM 0–COM 3 SEG 0–SEG 17 Port P6 Port P7 Common Segment Input/ output, individual bits Input Input/ output, individual bits Output Output CMOS compatible input level CMOS 3-state output CMOS compatible input level CMOS compatible input level N-channel open-drain output LCD common output LCD segment output A/D converter input Serial I/O2 I/O A/D converter input INT 0 interrupt input PULL register B AD control register Serial I/O2 control register AD control register PULL register B Interrupt edge selection register (17) (18) (19) (20) (16) (23) (13) (21) (22) LCD mode register

Rev.2.00 May. 24, 2006 page 18 of 90 REJ03B0028-0200 Fig. 14 Port block diagram (1) (5) Port P44(4) Ports P16, P17, P2, P41, P42 Pull-up control VL1/VSS VL2/VL3/VCC VL1/VSS VL2/VL3/VCC VL1/VSS VL2/VL3/VCC (1) Ports P01–P07, P11–P15 Data bus Port latch Interface logic level shift circuit Pull-up Port Segment Segment/PortLCD drive timing Segment output enable bit Segment data Port direction register Port direction register (2) Ports P00, P10 Data bus Port latch Interface logic level shift circuit Port Segment Segment/PortLCD drive timing Segment data Port direction register Direction register Pull-up Data bus Port latch Interface logic level shift circuit Port Segment Segment/PortLCD drive timing Segment data Port P3 output control bit Pull-up(3) Port P3 Data bus Port latch Direction register Key input interrupt input INT1, INT2 interrupt input Except P16, P17 Pull-up control Data bus Port latch Direction register Serial I/O1 enable bit Serial I/O1 input Receive enable bit Segment output enable bit Segment output enable bit Port P3 output control bit

Rev.2.00 May. 24, 2006 page 19 of 90 REJ03B0028-0200 Fig. 15 Port block diagram (2) (6) Port P45 (7) Port P46 (8) Port P47 (9) Ports P52,P53 (10) Ports P50,P51 PWM function enable bit PWM output (11) Port P54 Pulse output mode Timer output CNTR 0 interrupt input Pull-up control Direction register Data bus Port latch Serial I/O1 output P45/TxD P-channel output disable bit Serial I/O1 enable bit Transmit enable bit Serial I/O1 clock output Direction register Data bus Port latch Pull-up controlSerial I/O1 enable bit Serial I/O1 clock input Serial I/O1 synchronous clock selection bit Serial I/O1 mode selection bit Serial I/O1 enable bit Pull-up control Serial I/O1 mode selection bit Serial I/O1 enable bit SRDY1 output enable bit Direction register Data bus Port latch Serial I/O1 ready output Direction register Data bus Port latch Pull-up control Real time port control bit Real time port data Pull-up control Direction register Data bus Port latch Pull-up control Direction register Data bus Port latch

Rev.2.00 May. 24, 2006 page 20 of 90 REJ03B0028-0200 Fig. 16 Port block diagram (3) (12) Port P43 TOUT /φ output enable bit Timer 2 TOUT output System clock φ output TOUT /φ output selection bit (13) Ports P40,P71–P77 (14) Port P55 CNTR 1 interrupt input (15) Ports P56,P57 A/D external trigger input D/A converter output Except P56 (16) Ports P64–P67 (17) Port P60 Analog input pin selection bit A/D converter input Serial I/O2 input DA 1, DA2 output enable bits Direction register Port latchData bus Pull-up control Direction register Port latchData bus Direction register Port latchData bus Pull-up control Direction register Port latchData bus Pull-up control Direction register Port latchData bus Pull-up control Analog input pin selection bit A/D converter input Direction register Port latchData bus Pull-up control

Rev.2.00 May. 24, 2006 page 21 of 90 REJ03B0028-0200 Fig. 17 Port block diagram (4) (18) Port P61 (19) Port P62 (20) Port P63 Serial I/O2 output Serial I/O2 transmit end signal Serial I/O2 synchronous clock selection bit Serial I/O2 port selection bit Pull-up control Analog input pin selection bit A/D converter input P61/SOUT2 P-channel output disable bit (21) COM0–COM 3 (22) SEG0–SEG 17 VL3 VL2 VL1 VSS VL2/VL3 VL1/VSS (23) Port P70 INT0 input Serial I/O2 synchronous clock selection bit Serial I/O2 clock output Serial I/O2 clock input Serial I/O2 port selection bit Synchronous clock output pin selection bit A/D converter input Serial I/O2 clock output A/D converter input Direction register Port latchData bus Pull-up control Direction register Port latchData bus Analog input pin selection bit Pull-up control Direction register Port latchData bus Analog input pin selection bit Serial I/O2 synchronous clock selection bit Serial I/O2 port selection bit Data bus The gate input signal of each transistor is controlled by the LCD duty ratio and the bias value. The voltage applied to the sources of P- channel and N-channel transistors is the controlled voltage by the bias value. Synchronous clock output pin selection bit

Rev.2.00 May. 24, 2006 page 22 of 90 REJ03B0028-0200 Interrupts occur by seventeen sources: seven external, nine inter- nal, and one software. When an interrupt request is accepted, the program branches to the interrupt jump destination address set in the vector address (see Table 8). Interrupt Control Each interrupt is controlled by an interrupt request bit, an interrupt enable bit, and the interrupt disable flag except for the software in- terrupt set by the BRK instruction. An interrupt is accepted if the corresponding interrupt request and enable bits are “1” and the in- terrupt disable flag is “0”. Interrupt enable bits can be set to “0” or “1” by program. Interrupt request bits can be set to “0” by program, but cannot be set to “1” by program. The BRK instruction interrupt and reset cannot be disabled with any flag or bit. When the interrupt disable (I) flag is set to “1”, all interrupt requests except the BRK instruction interrupt and reset are not accepted. When several interrupt requests occur at the same time, the inter- rupts are received according to priority. Interrupt Operation By acceptance of an interrupt, the following operations are auto- matically performed: 1. The contents of the program counter and the processor status register are automatically pushed onto the stack. 2. The interrupt jump destination address is read from the vector table into the program counter. 3. The interrupt disable flag is set to “1” and the corresponding in- terrupt request bit is set to “0”. Notes1: Vector addresses contain interrupt jump destination addresses. 2: Reset is not an interrupt. Reset has the higher priority than all interrupts. Table 8 Interrupt vector addresses and priority RemarksInterrupt Request Generating Conditions At reset At detection of either rising or falling edge of INT0 input At detection of either rising or falling edge of INT1 input At completion of serial I/O1 data reception At completion of serial I/O1 transmit shift or when transmis- sion buffer is empty Interrupt Source LowHigh Priority Vector Addresses (Note 1) Reset (Note 2) INT0 INT1 Serial I/O1 reception Serial I/O1 transmission Timer X Timer Y Timer 2 Timer 3 CNTR 0 CNTR 1 Timer 1 INT2 Serial I/O2 Key input (Key-on wake-up) ADT A/D conversion BRK instruction FFFD FFFB 16 FFF9 16 FFF7 16 FFF5 16 FFF3 16 FFF1 16 FFEF 16 FFED 16 FFEB 16 FFE9 16 FFE7 16 FFE5 16 FFE3 16 FFE1 16 FFDF 16 FFDD 16 FFFC 16 FFFA 16 FFF8 16 FFF6 16 FFF4 16 FFF2 16 FFF0 16 FFEE 16 FFEC 16 FFEA 16 FFE8 16 FFE6 16 FFE4 16 FFE2 16 FFE0 16 FFDE 16 FFDC 16 At timer X underflow At timer Y underflow At timer 2 underflow At timer 3 underflow At detection of either rising or falling edge of CNTR 0 input At detection of either rising or falling edge of CNTR1 input At timer 1 underflow At detection of either rising or falling edge of INT 2 input At completion of serial I/O2 data transmission or reception At falling of conjunction of input level for port P2 (at input mode) At falling edge of ADT input At completion of A/D conversion At BRK instruction execution Non-maskable External interrupt (active edge selectable) External interrupt (active edge selectable) Valid when serial I/O1 is selected Valid when serial I/O1 is selected External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) Valid when serial I/O2 is selected External interrupt (valid at falling) Valid when ADT interrupt is selected External interrupt (valid at falling) Valid when A/D interrupt is selected Non-maskable software interrupt

Rev.2.00 May. 24, 2006 page 23 of 90 REJ03B0028-0200 Fig. 18 Interrupt control Fig. 19 Structure of interrupt-related registers ■ Notes on interrupts When setting the followings, the interrupt request bit may be set to “1”.

• When switching external interrupt active edge Related register: Interrupt edge selection register (address 3A 16) Timer X mode register (address 2716) Timer Y mode register (address 2816)
• When switching interrupt sources of an interrupt vector address where two or more interrupt sources are allocated Related register: Interrupt source selection bit of AD control reg- ister (bit 6 of address 3416) When not requiring for the interrupt occurrence synchronous with these setting, take the following sequence. ➀ Set the corresponding interrupt enable bit to “0” (disabled). ➁ Set the interrupt edge select bit (polarity switch bit) or the inter- rupt source selection bit. ➂ Set the corresponding interrupt request bit to “0” after 1 or more instructions have been executed. ➃ Set the corresponding interrupt enable bit to “1” (enabled). I n t e r r u p t r e q u e s t b i t I n t e r r u p t e n a b l e b i t I n t e r r u p t d i s a b l e f l a g ( I ) B R K i n s t r u c t i o n R e s e t I n t e r r u p t r e q u e s t a c c e p t a n c e b7 b0 Interrupt edge selection register INT0 interrupt edge selection bit INT1 interrupt edge selection bit INT2 interrupt edge selection bit Not used (“0” at reading) (INTEDGE : address 003A16) Interrupt request register 1 INT0 interrupt request bit INT1 interrupt request bit Serial I/O1 receive interrupt request bit Serial I/O1 transmit interrupt request bit Timer X interrupt request bit Timer Y interrupt request bit Timer 2 interrupt request bit Timer 3 interrupt request bit Interrupt control register 1 INT0 interrupt enable bit INT1 interrupt enable bit Serial I/O1 receive interrupt enable bit Serial I/O1 transmit interrupt enable bit Timer X interrupt enable bit Timer Y interrupt enable bit Timer 2 interrupt enable bit Timer 3 interrupt enable bit 0 : No interrupt request issued 1 : Interrupt request issued (IREQ1 : address 003C16) (ICON1 : address 003E16) Interrupt request register 2 CNTR 0 interrupt request bit CNTR 1 interrupt request bit Timer 1 interrupt request bit INT 2 interrupt request bit Serial I/O2 interrupt request bit Key input interrupt request bit ADT/A/D conversion interrupt request bi t Not used (“0” at reading) (IREQ2 : address 003D16) Interrupt control register 2 CNTR 0 interrupt enable bit CNTR 1 interrupt enable bit Timer 1 interrupt enable bit INT 2 interrupt enable bit Serial I/O2 interrupt enable bit Key input interrupt enable bit ADT/A/D conversion interrupt enable bit Not used (“0” at reading) (Write “0” to this bit) 0 : Interrupts disabled 1 : Interrupts enabled (ICON2 : address 003F16) 0 : Falling edge active 1 : Rising edge active b7 b0 b7 b0 b7 b0 b7 b0

Rev.2.00 May. 24, 2006 page 24 of 90 REJ03B0028-0200 Key Input Interrupt (Key-on Wake Up) The key input interrupt is enabled when any of port P2 is set to in- put mode and the bit corresponding to key input control register is set to “1”. A Key input interrupt request is generated by applying “L” level voltage to any pin of port P2 of which key input interrupt is en- abled. In other words, it is generated when AND of input level goes from “1” to “0”. A connection example of using a key input in- terrupt is shown in Figure 22, where an interrupt request is gener- ated by pressing one of the keys consisted as an active-low key matrix which inputs to ports P2 0–P2 3. Fig. 20 Connection example when using key input interrupt and port P2 block diagram P o r t P 20 l a t c h P o r t P 20 d i r e c t i o n r e g i s t e r P o r t P 21 l a t c h P o r t P 21 d i r e c t i o n r e g i s t e r P o r t P 22 l a t c h P o r t P 22 d i r e c t i o n r e g i s t e r P o r t P 23 l a t c h P o r t P 23 d i r e c t i o n r e g i s t e r P o r t P 24 l a t c h P o r t P 24 d i r e c t i o n r e g i s t e r P o r t P 25 l a t c h P o r t P 25 d i r e c t i o n r e g i s t e r P o r t P 26 l a t c h P o r t P 26 d i r e c t i o n r e g i s t e r P o r t P 27 l a t c h P o r t P 27 d i r e c t i o n r e g i s t e r P 20 i n p u t P 21 i n p u t P 22 i n p u t P 23 i n p u t P 24 o u t p u t P 25 o u t p u t P 26 o u t p u t P 27 o u t p u t P U L L r e g i s t e r A B i t P o r t P 2 I n p u t r e a d i n g c i r c u i t P o r t P X x L l e v e l o u t p u t ✽ P c h a n n e l t r a n s i s t o r f o r p u l l u p C M O S o u t p u t b u f f e r K e y i n p u t i n t e r r u p t r e q u e s t P 27 ke y i n p u t c o n t r o l b i t P 26 k e y i n p u t c o n t r o l b i t ✽✽ ✽ ✽✽ ✽ ✽✽ ✽ P 25 k e y i n p u t c o n t r o l b i t P 24 k e y i n p u t c o n t r o l b i t P 23 k e y i n p u t c o n t r o l b i t = “ 1 ” P U L L r e g i s t e r A B i t P 22 k e y i n p u t c o n t r o l b i t = “ 1 ” P 21 k e y i n p u t c o n t r o l b i t = “ 1 ” P 20 k e y i n p u t c o n t r o l b i t = “ 1 ”

Rev.2.00 May. 24, 2006 page 25 of 90 REJ03B0028-0200 The key input interrupt is controlled by the key input control regis- ter and the port direction register. When enabling the key input interrupt, set “1” to the key input control bit. A key input can be ac- cepted from pins set as the input mode in ports P20–P2 7. Fig. 21 Structure of key input control register P 20 k e y i n p u t c o n t r o l b i t P k e y i n p u t c o n t r o l b i t P k e y i n p u t c o n t r o l b i t P k e y i n p u t c o n t r o l b i t P k e y i n p u t c o n t r o l b i t P k e y i n p u t c o n t r o l b i t P k e y i n p u t c o n t r o l b i t P k e y i n p u t c o n t r o l b i t 0 : K e y i n p u t i n t e r r u p t d i s a b l e d K e y i n p u t i n t e r r u p t e n a b l e d K e y i n p u t c o n t r o l r e g i s t e r K I C a d d r e s s b 7 b 0

Rev.2.00 May. 24, 2006 page 26 of 90 REJ03B0028-0200 The 3826 group has five timers: timer X, timer Y, timer 1, timer 2, and timer 3. Timer X and timer Y are 16-bit timers, and timer 1, timer 2, and timer 3 are 8-bit timers. All timers are down count timers. When the timer reaches “0”, an underflow occurs at the next count pulse and the corresponding timer latch is reloaded into the timer and the count is continued. When a timer underflows, the interrupt request bit corresponding to that timer is set to “1”. Fig. 22 Timer block diagram P 55/ C N T R 1 P 54/ C N T R 0 Q Q T S Q D Q D Q T S P 43/φ/ TO U T XC I N C N T R 0 a c t i v e e d g e s w i t c h b i t T i m e r 1 c o u n t s o u r c e s e l e c t i o n b i t R e a l t i m e p o r t c o n t r o l b i t f ( XI N ) / 1 6 f XC I N ) w h e n φ XC I N / C N T R 1 a c t i v e e d g e s w i t c h b i t T i m e r Y s t o p c o n t r o l b i t F a l l i n g e d g e d e t e c t i o n P e r i o d m e a s u r e m e n t m o d e T i m e r Y i n t e r r u p t r e q u e s t P u l s e w i d t h H L c o n t i n u o u s l y m e a s u r e m e n t m o d e R i s i n g e d g e d e t e c t i o n T i m e r Y o p e r a t i n g m o d e b i t s T i m e r X i n t e r r u p t r e q u e s t T i m e r X m o d e r e g i s t e r w r i t e s i g n a l P 43 d i r e c t i o n r e g i s t e r P u l s e o u t p u t m o d e P 54 l a t c h T i m e r X s t o p c o n t r o l b i t T i m e r X w r i t e c o n t r o l b i t L a t c h T i m e r X o p e r a t - i n g m o d e b i t s P u l s e w i d t h m e a s u r e m e n t m o d e C N T R 0 a c t i v e e d g e s w i t c h b i t P u l s e o u t p u t m o d e P 54 d i r e c t i o n r e g i s t e r TO U T o u t p u t a c t i v e e d g e s w i t c h b i t T i m e r 2 w r i t e c o n t r o l b i t T i m e r 3 c o u n t s o u r c e s e l e c t i o n b i t T i m e r 2 i n t e r r u p t r e q u e s t T i m e r 3 i n t e r r u p t r e q u e s t T i m e r 2 c o u n t s o u r c e s e l e c t i o n b i t T i m e r 1 i n t e r r u p t r e q u e s t D a t a b u sR e a l t i m e p o r t c o n t r o l b i t R e a l t i m e p o r t c o n t r o l b i t T i m e r 3 l a t c h ( 8 ) T i m e r 3 r e g i s t e r ( 8 ) T i m e r 1 l a t c h ( 8 ) T i m e r 1 r e g i s t e r ( 8 ) T i m e r 2 l a t c h ( 8 ) T i m e r 2 r e g i s t e r ( 8 ) T i m e r X l o w - o r d e r r e g i s t e r ( 8 ) T i m e r X ( l o w ) l a t c h ( 8 ) T i m e r X ( h i g h ) l a t c h ( 8 ) T i m e r Y ( l o w ) l a t c h ( 8 ) T i m e r Y ( h i g h ) l a t c h ( 8 ) L a t c h P 43 l a t c h f ( XI N ) / 1 6 f XC I N ) w h e n φ XC I N / f ( XI N ) / 1 6 f XC I N ) w h e n φ XC I N / f ( XI N ) / 1 6 f XC I N ) w h e n φ XC I N / f ( XI N ) / 1 6 f XC I N ) w h e n φ XC I N / P 52/ R T P0 P 53/ R T P1 R T P0 d a t a f o r r e a l t i m e p o r t R T P1 d a t a f o r r e a l t i m e p o r t P 52 d i r e c t i o n r e g i s t e r P 52 l a t c h P 53 d i r e c t i o n r e g i s t e r P 53 l a t c h φ T i m e r X h i g h - o r d e r r e g i s t e r ( 8 ) T i m e r Y l o w - o r d e r r e g i s t e r ( 8 ) T i m e r Y h i g h - o r d e r r e g i s t e r ( 8 ) Q TO U T/φ o u t p u t s e l e c t i o n b i t TO U T/φ o u t p u t e n a b l e b i t TO U T/φ o u t p u t e n a b l e b i t

Rev.2.00 May. 24, 2006 page 27 of 90 REJ03B0028-0200 Timer X is a 16-bit timer and is equipped with the timer latch. The division ratio of timer X is given by 1/(n+1), where n is the value in the timer latch. Timer X is a down-counter. When the contents of timer X reach “000016”, an underflow occurs at the next count pulse and the contents of the timer latch are reloaded into the timer and the count is continued. When the timer underflows, the timer X interrupt request bit is set to “1”. Timer X can be selected in one of four modes by the timer X mode register and can be controlled the timer X write and the real time port. (1) Timer mode The timer counts f(XIN)/16 (or f(XCIN)/16 in low-speed mode). (2) Pulse output mode Each time the timer underflows, a signal output from the CNTR0 pin is inverted. Except for this, the operation in pulse output mode is the same as in timer mode. When using a timer in this mode, set the P54/CNTR 0 pin to output mode (set “1” to bit 4 of port P5 direction register). (3) Event counter mode The timer counts signals input through the CNTR0 pin. Except for this, the operation in event counter mode is the same as in timer mode. When using a timer in this mode, set the P54/ CNTR 0 pin to input mode (set “0” to bit 4 of port P5 direction reg- ister). (4) Pulse width measurement mode The count source is f(XIN)/16 (or f(XCIN)/16 in low-speed mode). If CNTR 0 active edge switch bit is “0”, the timer counts while the input signal of CNTR0 pin is at “H”. If it is “1”, the timer counts while the input signal of CNTR0 pin is at “L”. When using a timer in this mode, set the P54/CNTR 0 pin to input mode (set “0” to bit 4 of port P5 direction register).

• Read and write to timer X high-order, low-order registers When reading and writing to the timer X high-order and low-order registers, be sure to read/write both the timer X high- and low-or- der registers. When reading the timer X high-order and low-order registers, read the high-order register first. When writing to the timer X high-order and low-order registers, write the low-order register first. The timer X cannot perform the correct operation if the next operation is per- formed.
• Write operation to the high- or low-order register before reading the timer X low-order register
• Read operation from the high- or low-order register before writing to the timer X high-order register Fig. 23 Structure of timer X mode register T i m e r X m o d e r e g i s t e r T X M a d d r e s s T i m e r X w r i t e c o n t r o l b i t W r i t e v a l u e i n l a t c h a n d t i m e r W r i t e v a l u e i n l a t c h o n l y R e a l t i m e p o r t c o n t r o l b i t R e a l t i m e p o r t f u n c t i o n i n v a l i d R e a l t i m e p o r t f u n c t i o n v a l i d R T d a t a f o r r e a l t i m e p o r t R T d a t a f o r r e a l t i m e p o r t T i m e r X o p e r a t i n g m o d e b i t s b b T i m e r m o d e P u l s e o u t p u t m o d e E v e n t c o u n t e r m o d e P u l s e w i d t h m e a s u r e m e n t m o d e C N T R 0 a c t i v e e d g e s w i t c h b i t C o u n t a t r i s i n g e d g e i n e v e n t c o u n t e r m o d e S t a r t f r o m H o u t p u t i n p u l s e o u t p u t m o d e M e a s u r e H p u l s e w i d t h i n p u l s e w i d t h m e a s u r e m e n t m o d e F a l l i n g e d g e a c t i v e f o r C N T R 0 i n t e r r u p t C o u n t a t f a l l i n g e d g e i n e v e n t c o u n t e r m o d e S t a r t f r o m L o u t p u t i n p u l s e o u t p u t m o d e M e a s u r e L p u l s e w i d t h i n p u l s e w i d t h m e a s u r e m e n t m o d e R i s i n g e d g e a c t i v e f o r C N T R 0 i n t e r r u p t T i m e r X s t o p c o n t r o l b i t C o u n t s t a r t C o u n t s t o p b 7 b 0
• Timer X Write Control Which write control can be selected by the timer X write control bit (bit 0) of the timer X mode register (address 002716), writing data to both the latch and the timer at the same time or writing data only to the latch. When the operation “writing data only to the latch” is selected, the value is set to the timer latch by writing data to the timer X register and the timer is updated at next underflow. After reset, the operation “writing data to both the latch and the timer at the same time” is selected, and the value is set to both the latch and the timer at the same time by writing data to the timer X register. The write operation is independent of timer X count operation, operating or stopping. When the value is written in latch only, a value is simultaneously set to the timer X and the timer X latch if the writing in the high- order register and the underflow of timer X are performed at the same timing. Unexpected value may be set in the high-order timer on this occasion.
• Real Time Port Control While the real time port function is valid, data for the real time port are output from ports P5 2 and P5 3 each time the timer X underflows. (However, if the real time port control bit is changed from “0” to “1” after set of the real time port data, data are output independent of the timer X operation.) If the data for the real time port is changed while the real time port function is valid, the changed data are output at the next underflow of timer X. Before using this function, set the P5 2/RTP0, P53/RTP1 pins to output mode (set “1” to bits 2, 3 of port P5 direction register). ■ Note on CNTR0 interrupt active edge selection CNTR 0 interrupt active edge depends on the CNTR0 active edge switch bit.

Rev.2.00 May. 24, 2006 page 28 of 90 REJ03B0028-0200 Timer Y is a 16-bit timer and is equipped with the timer latch. The division ratio of timer Y is given by 1/(n+1), where n is the value in the timer latch. Timer Y is a down-counter. When the contents of timer Y reach “000016”, an underflow occurs at the next count pulse and the contents of the timer latch are reloaded into the timer and the count is continued. When the timer underflows, the timer Y interrupt request bit is set to “1”. Timer Y can be selected in one of four modes by the timer Y mode register. (1) Timer mode The timer counts f(XIN)/16 (or f(XCIN)/16 in low-speed mode). (2) Period measurement mode CNTR 1 interrupt request is generated at rising or falling edge of CNTR 1 pin input signal. Simultaneously, the value in timer Y latch is reloaded in timer Y and timer Y continues counting down. Except for this, the operation in period measurement mode is the same as in timer mode. The timer value just before the reloading at rising or falling of CNTR 1 pin input signal is retained until the next valid edge is input. The rising or falling timing of CNTR 1 pin input signal can be discriminated by CNTR1 interrupt. When using a timer in this mode, set the P55/CNTR 1 pin to input mode (set “0” to bit 5 of port P5 direction register). (3) Event counter mode The timer counts signals input through the CNTR1 pin. Except for this, the operation in event counter mode is the same as in timer mode. When using a timer in this mode, set the 5/CNTR 1 pin to input mode (set “0” to bit 5 of port P5 direction register). (4) Pulse width HL continuously measure- ment mode CNTR 1 interrupt request is generated at both rising and falling edges of CNTR1 pin input signal. Except for this, the operation in pulse width HL continuously measurement mode is the same as in period measurement mode. When using a timer in this mode, set the P5 5/CNTR 1 pin to input mode (set “0” to bit 5 of port P5 direction register). ■ Note on CNTR1 interrupt active edge selection CNTR 1 interrupt active edge depends on the value of the CNTR1 active edge switch bit. However, in pulse width HL continuously measurement mode, CNTR 1 interrupt request is generated at both rising and falling edges of CNTR1 pin input signal regardless of the value of CNTR1 active edge switch bit. Fig. 24 Structure of timer Y mode register T i m e r Y m o d e r e g i s t e r T Y M a d d r e s s b 7 b 0 N o t u s e d a t r e a d i n g T i m e r Y o p e r a t i n g m o d e b i t s b T i m e r m o d e P e r i o d m e a s u r e m e n t m o d e E v e n t c o u n t e r m o d e P u l s e w i d t h H L c o n t i n u o u s l y m e a s u r e m e n t m o d e C N T R 1 a c t i v e e d g e s w i t c h b i t C o u n t a t r i s i n g e d g e i n e v e n t c o u n t e r m o d e M e a s u r e t h e f a l l i n g e d g e t o f a l l i n g e d g e p e r i o d i n p e r i o d m e a s u r e m e n t m o d e F a l l i n g e d g e a c t i v e f o r C N T R 1 i n t e r r u p t C o u n t a t f a l l i n g e d g e i n e v e n t c o u n t e r m o d e M e a s u r e t h e r i s i n g e d g e p e r i o d i n p e r i o d m e a s u r e m e n t m o d e R i s i n g e d g e a c t i v e f o r C N T R 1 i n t e r r u p t T i m e r Y s t o p c o n t r o l b i t C o u n t s t a r t C o u n t s t o p

Rev.2.00 May. 24, 2006 page 29 of 90 REJ03B0028-0200 Timer 1, Timer 2, Timer 3 Timer 1, timer 2, and timer 3 are 8-bit timers and is equipped with the timer latch. The count source for each timer can be selected by the timer 123 mode register. The division ratio of each timer is given by 1/(n+1), where n is the value in the timer latch. All timers are down-counters. When the contents of the timer reach “00 16”, an underflow occurs at the next count pulse and the contents of the timer latch are reloaded into the timer and the count is continued. When the timer underflows, the interrupt request bit corresponding to that timer is set to “1”. When a value is written to the timer 1 register and the timer 3 reg- ister, a value is simultaneously set as the timer latch and the timer. When the timer 1 register, the timer 2 register, or the timer 3 regis- ter is read, the count value of the timer can be read.

• Timer 2 Write Control Which write can be selected by the timer 2 write control bit (bit 2) of the timer 123 mode register (address 0029 16), writing data to both the latch and the timer at the same time or writing data only to the latch. When the operation “writing data only to the latch” is selected, the value is set to the timer 2 latch by writing data to the timer 2 register and the timer 2 is updated at next underflow. After reset, the operation “writing data to both the latch and the timer at the same time” is selected, and the value is set to both the timer 2 latch and the timer 2 at the same time by writing data to the timer 2 register. If the value is written in latch only, a value is simultaneously set to the timer 2 and the timer 2 latch when the writing in the high- order register and the underflow of timer 2 are performed at the same timing.
• Timer 2 Output Control When the timer 2 (T OUT ) output is enabled by the TOUT /φ output enable bit and the TOUT /φ output selection bit, an inversion signal from the TOUT pin is output each time timer 2 underflows. In this case, set the P43/φ/TOUT pin to output mode (set “1” to bit 3 of port P4 direction register). ■ Note on Timer 1 to Timer 3 When the count source of timers 1 to 3 is changed, the timer counting value may become arbitrary value because a thin pulse is generated in count input of timer. If timer 1 output is selected as the count source of timer 2 or timer 3, when timer 1 is written, the counting value of timer 2 or timer 3 may become undefined value because a thin pulse is generated in timer 1 output. Therefore, set the value of timer in the order of timer 1, timer 2 and timer 3 after the count source selection of timer 1 to 3. Fig. 25 Structure of timer 123 mode register TO U T o u t p u t a c t i v e e d g e s w i t c h b i t S t a r t a t H o u t p u t S t a r t a t L o u t p u t TO U T/φ o u t p u t e n a b l e l b i t TO U T/φ o u t p u t d i s a b l e d TO U T/φ o u t p u t e n a b l e d T i m e r w r i t e c o n t r o l b i t W r i t e d a t a i n l a t c h a n d c o u n t e r W r i t e d a t a i n l a t c h o n l y T i m e r c o u n t s o u r c e s e l e c t i o n b i t T i m e r o u t p u t s i g n a l f XI N ) o r f XC I N ) i n l o w s p e e d m o d e T i m e r c o u n t s o u r c e s e l e c t i o n b i t T i m e r o u t p u t s i g n a l f XI N ) o r f XC I N ) i n l o w s p e e d m o d e T i m e r c o u n t s o u r c e s e l e c t i o n b i t f XI N ) o r f XC I N ) i n l o w s p e e d m o d e f XC I N ) N o t u s e d a t r e a d i n g T i m e r 1 2 3 m o d e r e g i s t e r T M a d d r e s s N o t e : S y s t e m c l o c k φ i s f ( XC I N ) / 2 i n t h e l o w - s p e e d m o d e . b 7 b 0

Rev.2.00 May. 24, 2006 page 30 of 90 REJ03B0028-0200 Serial I/O1 can be used as either clock synchronous or asynchro- nous (UART) serial I/O. A dedicated timer (baud rate generator) is also provided for baud rate generation. (1) Clock Synchronous Serial I/O Mode Clock synchronous serial I/O mode is selected by setting the se- rial I/O1 mode selection bit of the serial I/O1 control register to “1”. For clock synchronous serial I/O mode, the transmitter and the re- ceiver must use the same clock as an operation clock. When an internal clock is selected as an operation clock, transmit or receive is started by a write signal to the transmit buffer regis- ter. When an external clock is selected as an operation clock, serial I/ O1 becomes the state where transmit or receive can be performed by a write signal to the transmit buffer register. Transmit and re- ceive are started by input of an external clock. Fig. 26 Block diagram of clock synchronous serial I/O1 Fig. 27 Operation of clock synchronous serial I/O1 function P 46/ SC L K P 47/ SR D Y P 44/ R XD P 45/ TXD XI N 1 / 4 F / F S e r i a l I O s t a t u s r e g i s t e r S e r i a l I O c o n t r o l r e g i s t e r R e c e i v e b u f f e r r e g i s t e r A d d r e s s 0 0 1 81 R e c e i v e s h i f t r e g i s t e r R e c e i v e b u f f e r f u l l f l a g ( R B F ) R e c e i v e i n t e r r u p t r e q u e s t R e c e i v e cl o c k c o n t r o l c i r c u i t S h i f t c l o c k S e r i a l I / O 1 s y n c h r o n o u s c l o c k s e l e c t i o n b i t F r e q u e n c y d i v i s i o n r a t i o n B a u d r a t e g e n e r a t o r A d d r e s s 0 0 1 C 1 B R G c o u n t s o u r c e s e l e c t i o n b i t F a l l i n g e d g e d e t e c t o r D a t a b u s A d d r e s s 0 0 1 81 S h i f t c l o c k T r a n s m i t s h i f t r e g i s t e r s h i f t c o m p l e t i o n f l a g ( T S C ) T r a n s m i t b u f f e r e m p t y f l a g ( T B E ) T r a n s m i t i n t e r r u p t r e q u e s t T r a n s m i t i n t e r r u p t s o u r c e s e l e c t i o n b i t A d d r e s s 0 0 1 91 D a t a b u s A d d r e s s 0 0 1 A1 T r a n s m i t b u f f e r r e g i s t e r T r a n s m i t s h i f t r e g i s t e r T r a n s m i t cl o c k c o n t r o l c i r c u i t R e c e i v e e n a b l e s i g n a l SR D Y D 7D 0 D 1 D 2 D 3 D 4 D 5 D 6 R B F = “ 1 ” T S C ”T B E = “ 0 ” T B E = “ 1 ” T S C T r a n s m i t a n d r e c e i v e s h i f t c l o c k t o o f t h e i n t e r n a l c l o c k o r a n e x t e r n a l c l o c k S e r i a l o u t p u t TXD S e r i a l i n p u t R XD W r i t e s i g n a l t o r e c e i v e / t r a n s m i t b u f f e r r e g i s t e r a d d r e s s O v e r r u n e r r o r ( O E ) d e t e c t i o n N o t e s 1 : A f t e r d a t a t r a n s f e r r i n g , t h e T x D p i n k e e p s D 7 o u t p u t v a l u e . I f d a t a i s w r i t t e n t o t h e t r a n s m i t b u f f e r r e g i s t e r w h e n T S C t h e t r a n s m i t c l o c k i s g e n e r a t e d c o n t i n u o u s l y a n d s e r i a l d a t a c a n b e o u t p u t c o n t i n u o u s l y f r o m t h e TXD p i n S e l e c t t h e s e r i a l I O t r a n s m i t i n t e r r u p t r e q u e s t f a c t o r b e t w e e n w h e n t h e t r a n s m i t b u f f e r r e g i s t e r h a s e m p t i e d T B E o r a f t e r t h e t r a n s m i t s h i f t o p e r a t i o n h a s e n d e d T S C b y s e t t i n g t h e t r a n s m i t i n t e r r u p t s o u r c e s e l e c t i o n b i t T I C o f t h e s e r i a l I O c o n t r o l r e g i s t e r T h e s e r i a l I O r e c e i v e i n t e r r u p t r e q u e s t o c c u r s w h e n t h e r e c e i v e b u f f e r f u l l f l a g R B F b e c o m e s D 7D 0 D 1 D 2 D 3 D 4 D 5 D 6 ( N o t e 1 ) ( N o t e 3 ) ( N o t e 2 ) ( N o t e 3 ) ( N o t e 4 )

Rev.2.00 May. 24, 2006 page 31 of 90 REJ03B0028-0200 (2) Asynchronous Serial I/O (UART) Mode Clock asynchronous serial I/O mode (UART) is selected by setting the serial I/O1 mode selection bit of the serial I/O1 control register to “0”. Eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. The transmit and receive shift registers each have a buffer regis- ter, but the two buffers have the same address (0018 16) in memory. Since the shift register cannot be written to or read from directly, transmit data is written to the transmit buffer, and receive data is read from the receive buffer. The transmit buffer can also hold the next data to be transmitted during transmitting, and the receive buffer register can hold re- ceived one-byte data while the next one-byte data is being re- ceived. Fig. 28 Block diagram of UART serial I/O1 Fig. 29 Operation of UART serial I/O1 function XI N O E P E F E 1 / 1 6 1 / 1 6 D a t a b u s R e c e i v e b u f f e r r e g i s t e r A d d r e s s 0 0 1 81 R e c e i v e s h i f t r e g i s t e r R e c e i v e b u f f e r f u l l f l a g ( R B F ) R e c e i v e i n t e r r u p t r e q u e s t B a u d r a t e g e n e r a t o r F r e q u e n c y d i v i s i o n r a t i o 1 / ( n + 1 ) A d d r e s s 0 0 1 C 1 S T S P P A g e n e r a t o r T r a n s m i t b u f f e r r e g i s t e r D a t a b u s T r a n s m i t s h i f t r e g i s t e r A d d r e s s 0 0 1 81 T r a n s m i t s h i f t r e g i s t e r s h i f t c o m p l e t i o n f l a g ( T S C ) T r a n s m i t b u f f e r e m p t y f l a g ( T B E ) T r a n s m i t i n t e r r u p t r e q u e s t A d d r e s s 0 0 1 91 S T d e t e c t o r S P d e t e c t o r U A R T c o n t r o l r e g i s t e r A d d r e s s 0 0 1 B1 C h a r a c t e r l e n g t h s e l e c t i o n b i t A d d r e s s 0 0 1 A1 B R G c o u n t s o u r c e s e l e c t i o n b i t T r a n s m i t i n t e r r u p t s o u r c e s e l e c t i o n b i t S e r i a l I / O 1 s y n c h r o n i z a t i o n c l o c k s e l e c t i o n b i t C l o c k c o n t r o l c i r c u i t C h a r a c t e r l e n g t h s e l e c t i o n b i t b i t s b i t s S e r i a l I / O 1 c o n t r o l r e g i s t e r P 46/ SC L K S e r i a l I / O 1 s t a t u s r e g i s t e r P 44/ R XD P 45/ TXD T S C = “ 0 ” T B E R B F = “ 0 ” T B E = “ 0 ” T B E = “ 0 ” R B F = “ 1 ” R B F = “ 1 ” S TD 0 D 1 S P D 0 D 1S T S P T B E = “ 1 ” T S C S TD 0 D 1 S P D 0 D 1S T S P T r a n s m i t b u f f e r r e g i s t e r w r i t e s i g n a l ✽ G e n e r a t e d a t n d b i t i n s t o p b i t m o d e 1 s t a r t b i t o r d a t a b i t s o r p a r i t y b i t o r s t o p b i t s 1 : E r r o r f l a g d e t e c t i o n o c c u r s a t t h e s a m e t i m e t h a t t h e R B F f l a g b e c o m e s “ 1 ” ( a t 1 s t s t o p b i t f o r r e c e p t i o n ) . T h e s e r i a l I O r e c e i v e i n t e r r u p t r e q u e s t o c c u r s w h e n t h e r e c e i v e b u f f e r f u l l f l a g R B F b e c o m e s S e l e c t t h e s e r i a l I O t r a n s m i t i n t e r r u p t r e q u e s t o c c u r r e n c e f a c t o r b e t w e e n w h e n t h e t r a n s m i t b u f f e r r e g i s t e r h a s e m p t i e d T B E o r a f t e r t h e t r a n s m i t s h i f t o p e r a t i o n h a s e n d e d T S C b y s e t t i n g t h e t r a n s m i t i n t e r r u p t s o u r c e s e l e c t i o n b i t T I C o f t h e s e r i a l I O c o n t r o l r e g i s t e r N o t e s S e r i a l o u t p u t T x D S e r i a l i n p u t R x D R e c e i v e b u f f e r r e g i s t e r r e a d s i g n a l T r a n s m i t o r r e c e i v e c l o c k ( N o t e s 1 , 2 ) ( N o t e s 1 , 2 )

Rev.2.00 May. 24, 2006 page 32 of 90 REJ03B0028-0200 [Transmit Buffer/Receive Buffer Register (TB/ RB)] 001816 The transmit buffer register and the receive buffer register are lo- cated at the same address. The transmit buffer register is write- only and the receive buffer register is read-only. If a character bit length is 7 bits, the MSB of data stored in the receive buffer regis- ter is “0”. [Serial I/O1 Status Register (SIO1STS)] 001916 The read-only serial I/O1 status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial I/O1 function and various errors. Three of the flags (bits 4 to 6) are valid only in UART mode. The receive buffer full flag (bit 1) is set to “0” when the receive buffer register is read. If there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer reg- ister, and the receive buffer full flag is set to “1”. A write signal to the serial I/O1 status register sets all the error flags (OE, PE, FE, and SE) (bit 3 to bit 6, respectively) to “0”. Writing “0” to the serial I/O1 enable bit (SIOE) also sets all the status flags to “0”, includ- ing the error flags. All bits of the serial I/O1 status register are set to “0” at reset, but if the transmit enable bit of the serial I/O1 control register has been set to “1”, the transmit shift register shift completion flag and the transmit buffer empty flag become “1”. [Serial I/O1 Control Register (SIO1CON)] 001A16 The serial I/O1 control register contains eight control bits for the serial I/O1 function. [UART Control Register (UARTCON)] 001B16 The UART control register consists of the bits which set the data format of an data transmit and receive, and the bit which sets the output structure of the P45/TXD pin. [Baud Rate Generator (BRG)] 001C16 The baud rate generator is the 8-bit counter equipped with a reload register. Set the division value of the BRG count source to the baud rate generator. The baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate generator. ■ Notes on serial I/O When setting the transmit enable bit to “1”, the serial I/O1 transmit interrupt request bit is automatically set to “1”. When not requiring the interrupt occurrence synchronous with the transmission en- abled, take the following sequence. ➀ Set the serial I/O1 transmit interrupt enable bit to “0” (disabled). ➁ Set the transmit enable bit to “1”. ➂ Set the serial I/O1 transmit interrupt request bit to “0” after 1 or more instructions have been executed. ➃ Set the serial I/O1 transmit interrupt enable bit to “1” (enabled).

Rev.2.00 May. 24, 2006 page 33 of 90 REJ03B0028-0200 Fig. 30 Structure of serial I/O1 control registers B R G c o u n t s o u r c e s e l e c t i o n b i t ( C S S ) f XI N ) f XI N ) S e r i a l I O s y n c h r o n o u s c l o c k s e l e c t i o n b i t S C S B R G o u t p u t d i v i d e d b y w h e n c l o c k s y n c h r o n o u s s e r i a l I O i s s e l e c t e d B R G o u t p u t d i v i d e d b y w h e n U A R T i s s e l e c t e d E x t e r n a l c l o c k i n p u t w h e n c l o c k s y n c h r o n o u s s e r i a l I O i s s e l e c t e d E x t e r n a l c l o c k i n p u t d i v i d e d b y w h e n U A R T i s s e l e c t e d SR D Y o u t p u t e n a b l e b i t S R D Y P p i n o p e r a t e s a s o r d i n a r y I O p i n P p i n o p e r a t e s a s SR D Y o u t p u t p i n T r a n s m i t i n t e r r u p t s o u r c e s e l e c t i o n b i t T I C I n t e r r u p t w h e n t r a n s m i t b u f f e r h a s e m p t i e d I n t e r r u p t w h e n t r a n s m i t s h i f t o p e r a t i o n i s c o m p l e t e d T r a n s m i t e n a b l e b i t T E T r a n s m i t d i s a b l e d T r a n s m i t e n a b l e d R e c e i v e e n a b l e b i t R E R e c e i v e d i s a b l e d R e c e i v e e n a b l e d S e r i a l I O m o d e s e l e c t i o n b i t S I O M A s y n c h r o n o u s s e r i a l I O U A R T C l o c k s y n c h r o n o u s s e r i a l I O S e r i a l I O e n a b l e b i t S I O E S e r i a l I O d i s a b l e d p i n s P 44– P o p e r a t e a s o r d i n a r y I O p i n s S e r i a l I O e n a b l e d p i n s P 44– P o p e r a t e a s s e r i a l I O p i n s S e r i a l I / O 1 c o n t r o l r e g i s t e r S I O C O N a d d r e s s b 7 b T r a n s m i t b u f f e r e m p t y f l a g ( T B E ) B u f f e r f u l l B u f f e r e m p t y R e c e i v e b u f f e r f u l l f l a g R B F B u f f e r e m p t y B u f f e r f u l l T r a n s m i t s h i f t r e g i s t e r s h i f t c o m p l e t i o n f l a g T S C T r a n s m i t s h i f t i n p r o g r e s s T r a n s m i t s h i f t c o m p l e t e d O v e r r u n e r r o r f l a g O E N o e r r o r O v e r r u n e r r o r P a r i t y e r r o r f l a g P E N o e r r o r P a r i t y e r r o r F r a m i n g e r r o r f l a g F E N o e r r o r F r a m i n g e r r o r S u m m i n g e r r o r f l a g S E O E U P E U F E O E U P E U F E N o t u s e d a t r e a d i n g S e r i a l I / O 1 s t a t u s r e g i s t e r S I O S T S a d d r e s s b 7 b U A R T c o n t r o l r e g i s t e r U A R T C O N a d d r e s s C h a r a c t e r l e n g t h s e l e c t i o n b i t ( C H A S ) b i t s b i t s P a r i t y e n a b l e b i t P A R E P a r i t y c h e c k i n g d i s a b l e d P a r i t y c h e c k i n g e n a b l e d P a r i t y s e l e c t i o n b i t P A R S E v e n p a r i t y O d d p a r i t y S t o p b i t l e n g t h s e l e c t i o n b i t S T P S s t o p b i t s t o p b i t s P 45/ TXD P c h a n n e l o u t p u t d i s a b l e b i t P O F F C M O S o u t p u t i n o u t p u t m o d e N c h a n n e l o p e n d r a i n o u t p u t i n o u t p u t m o d e N o t u s e d a t r e a d i n g b 7 b

Rev.2.00 May. 24, 2006 page 34 of 90 REJ03B0028-0200 Serial I/O2 can be used only for clock synchronous serial I/O. For serial I/O2, the transmitter and the receiver must use the same clock as a synchronous clock. When an internal clock is se- lected as a synchronous clock, the serial I/O2 is initialized and, transmit and receive is started by a write signal to the serial I/O2 register. When an external clock is selected as an synchronous clock, the serial I/O2 counter is initialized by a write signal to the serial I/O2 register, serial I/O2 becomes the state where transmission or re- ception can be performed. Write to the serial I/O2 register while S CLK21 is “H” state when an external clock is selected as an syn- chronous clock. Either P6 2/SCLK21 or P63/SCLK22 pin can be selected as an output pin of the synchronous clock. In this case, the pin that is not se- lected as an output pin of the synchronous clock functions as a I/ O port. [Serial I/O2 Control Register (SIO2CON)] 001D16 The serial I/O2 control register contains eight control bits for the serial I/O2 functions. After setting to this register, write data to the serial I/O2 register and start transmit and receive. Fig. 31 Structure of serial I/O2 control register Fig. 32 Block diagram of serial I/O2 function S e r i a l I / O 2 c o n t r o l r e g i s t e r S I O C O N a d d r e s s D 1 b 7 I n t e r n a l s y n c h r o n o u s c l o c k s e l e c t b i t s f XI N ) f XI N ) f XI N ) f XI N ) f XI N ) f XI N ) S e r i a l I O p o r t s e l e c t i o n b i t I O p o r t SO U T SC L K SC L K s i g n a l o u t p u t P 61/ SO U T P c h a n n e l o u t p u t d i s a b l e b i t C M O S o u t p u t i n o u t p u t m o d e N c h a n n e l o p e n d r a i n o u t p u t i n o u t p u t m o d e T r a n s f e r d i r e c t i o n s e l e c t i o n b i t L S B f i r s t M S B f i r s t S e r i a l I O s y n c h r o n o u s c l o c k s e l e c t i o n b i t E x t e r n a l c l o c k I n t e r n a l c l o c k S y n c h r o n o u s c l o c k o u t p u t p i n s e l e c t i o n b i t SC L K SC L K b 0 b 2 b 1 b 0 D o n o t s e l e c t XI N “ 1 ” “ 0 ” “ 0 ” “ 1 ” “ 0 ” “ 1 ” SC L K ( N o t e ) 1 / 1 6 1 / 3 2 1 / 6 4 1 / 1 2 8 1 / 2 5 6 D a t a b u s S e r i a l I / O 2 i n t e r r u p t r e q u e s t S e r i a l I / O 2 p o r t s e l e c t i o n b i t S e r i a l I / O 2 c o u n t e r ( 3 ) S e r i a l I / O 2 r e g i s t e r ( 8 ) S y n c h r o n o u s c i r c u i t S e r i a l I / O 2 s y n c h r o n o u s c l o c k s e l e c t i o n b i t E x t e r n a l c l o c k I n t e r n a l s y n c h r o n o u s c l o c k s e l e c t b i t s D i v i d e r P 63 l a t c h P 63/ SC L K P 62/ SC L K P 61/ SO U T P 60/ SI N P 62 l a t c h P 61 l a t c h ( N o t e ) N o t e : I t i s s e l e c t e d b y t h e s e r i a l I / O 2 s y n c h r o n o u s c l o c k s e l e c t i o n b i t , t h e s y n c h r o n o u s c l o c k o u t p u t p i n s e l e c t i o n b i t a n d t h e s e r i a l I O p o r t s e l e c t i o n b i t

Rev.2.00 May. 24, 2006 page 35 of 90 REJ03B0028-0200 Fig. 33 Timing of serial I/O2 function D 7D 0 D 1 D 2 D 3 D 4 D 5 D 6 S y n c h r o n o u s c l o c k N o t e S e r i a l I / O 2 o u t p u t SO U T S e r i a l I / O 2 i n p u t SI N S e r i a l I / O 2 r e g i s t e r w r i t e s i g n a l ( N o t e s 2 , 3 ) S e r i a l I / O 2 i n t e r r u p t r e q u e s t b i t = “ 1 ” 1 : W h e n t h e i n t e r n a l c l o c k i s s e l e c t e d a s t h e s y n c h r o n o u s c l o c k , t h e d i v i d e r a t i o c a n b e s e l e c t e d b y s e t t i n g b i t s 0 t o 2 o f t h e s e r i a l I O c o n t r o l r e g i s t e r W h e n t h e i n t e r n a l c l o c k i s s e l e c t e d a s t h e s y n c h r o n o u s c l o c k t h e SO U T p i n g o e s t o h i g h i m p e d a n c e a f t e r t r a n s f e r c o m p l e t i o n W h e n t h e e x t e r n a l c l o c k i s s e l e c t e d a s t h e s y n c h r o n o u s c l o c k t h e SO U T p i n k e e p s D 7 o u t p u t l e v e l a f t e r t r a n s f e r c o m p l e t i o n . H o w e v e r i f s y n c h r o n o u s c l o c k s i n p u t a r e c a r r i e d o n t h e t r a n s m i t d a t a w i l l b e o u t p u t c o n t i n u o u s l y f r o m t h e SO U T p i n b e c a u s e s h i f t s o f s e r i a l I O s h i f t r e g i s t e r i s c o n t i n u e d a s l o n g a s s y n c h r o n o u s c l o c k s a r e i n p u t N o t e s

• Serial I/O2 Operating The serial I/O2 counter is initialized to “7” by writing to the serial I/O2 register. After writing, whenever a synchronous clock changes from “H” to “L”, data is output from the S OUT2 pin. Moreover, whenever a syn- chronous clock changes from “L” to “H”, data is taken in from the SIN2 pin, and 1 bit shift of the serial I/O2 register is carried out si- multaneously. When the internal clock is selected as a synchronous clock, it is as follows if a synchronous clock is counted 8 times.
• Serial I/O2 counter = “0”
• Synchronous clock stops in “H” state
• Serial I/O2 interrupt request bit = “1” The S OUT2 pin is in a high impedance state after transfer is com- pleted. When the external clock is selected as a synchronous clock, if a synchronous clock is counted 8 times, the serial I/O2 interrupt re- quest bit is set to “1”, and the SOUT2 pin holds the output level of D 7. However, if a synchronous clock continues being input, the shift of the serial I/O2 register is continued and transmission data continues being output from the SOUT2 pin.

Rev.2.00 May. 24, 2006 page 36 of 90 REJ03B0028-0200 PULSE WIDTH MODULATION (PWM) The 3826 group has a PWM function with an 8-bit resolution, using f(XIN) or f(XIN)/2 as a count source. Data Setting The PWM output pins are shared with ports P50 and P51. Set the PWM period by the PWM prescaler, and set the period during which the output pulse is an “H” by the PWM register. If PWM count source is f(X IN) and the value in the PWM prescaler is n and the value in the PWM register is m (where n = 0 to 255 and m = 0 to 255) : PWM period = 255 ✕ (n+1)/f(X IN) = 31.875 ✕ (n+1) µs (when f(XIN) = 8 MHz) Output pulse “H” period = PWM period ✕ m/255 (when f(XIN) = 8 MHz) PWM Operation When either bit 1 (PWM0 function enable bit) or bit 2 (PWM1 func- tion enable bit) of the PWM control register or both bits are enabled, operation starts from initializing status, and pulses are output starting at “H”. When one PWM output is enabled and that the other PWM output is enabled, PWM output which is enabled to output later starts pulse output from halfway of PWM period (see Figure 37). When the PWM register or PWM prescaler is updated during PWM output, the pulses will change in the cycle after the one in which the change was made. Fig. 34 Timing of PWM cycle Fig. 35 Block diagram of PWM function 31.875 ✕ m ✕ (n+1) 255 µs PWM output m: Contents of PWM register n : Contents of PWM prescaler T : PWM cycle (when f(XIN) = 8 MHz) D a t a b u s C o u n t s o u r c e s e l e c t i o n b i t “ 0 ” “ 1 ” P W M p r e s c a l e r p r e l a t c h P W M r e g i s t e r p r e l a t c h P W M p r e s c a l e r l a t c h P W M r e g i s t e r l a t c h T r a n s f e r c o n t r o l c i r c u i t P W M c i r c u i t XI N P W M 0 f u n c t i o n e n a b l e b i t P 51 / P W M 1 P W M p r e s c a l e r P W M 1 f u n c t i o n e n a b l e b i t P o r t P 51 l a c t h P o r t P 50 l a c t h P 50 / P W M 0

Rev.2.00 May. 24, 2006 page 37 of 90 REJ03B0028-0200 Fig. 37 PWM output timing when PWM register or PWM prescaler is changed Fig. 36 Structure of PWM control register b 7 b 0 P W M c o n t r o l r e g i s t e r P W M C O N a d d r e s s C o u n t s o u r c e s e l e c t i o n b i t 0:f XI N ) 1:f XI N ) P W M 0 f u n c t i o n e n a b l e b i t 0:P W M 0 d i s a b l e d 1:P W M 0 e n a b l e d P W M 1 f u n c t i o n e n a b l e b i t 0:P W M 1 d i s a b l e d 1:P W M 1 e n a b l e d N o t u s e d a t r e a d i n g T T2 CB T PWM register write signal PWM prescaler write signal (Changes from “A” to “B” during “H” period) (Changes from “T” to “T2” during PWM period) PWM (internal) A B T C T2= stop PWM 0 function enable bit PWM 1 function enable bit PWM 0 output Port PortPWM 1 output Port stop Port When the contents of the PWM register or PWM prescaler have changed, the PWM output will change from the next period after the change.

Rev.2.00 May. 24, 2006 page 38 of 90 REJ03B0028-0200 [AD Conversion Low-Order Register (ADL)] 001416 [AD Conversion High-Order Register (ADH)] 003516 The AD conversion registers are read-only registers that store the result of an A/D conversion. When reading this register during an A/D conversion, the previous conversion result is read. The high-order 8 bits of a conversion result is stored in the AD conversion high-order register (address 0035 16), and the low-or- der 2 bits of the same result are stored in bit 7 and bit 6 of the AD conversion low-order register (address 001416). Bit 0 of the AD conversion low-order register is the conversion mode selection bit. When this bit is set to “0”, that becomes the 10-bit A/D mode. When this bit is set to “1”, that becomes the 8-bit A/D mode. [AD Control Register (ADCON)] 003416 The AD control register controls the A/D conversion process. Bits 0 to 2 of this register select specific analog input pins. Bit 3 indi- cates the completion of an A/D conversion. The value of this bit re- mains at “0” during an A/D conversion, then it is set to “1” when the A/D conversion is completed. Writing “0” to this bit starts the A/D conversion. Bit 4 is the V REF input switch bit which controls connection of the resistor ladder and the reference voltage input pin (VREF ). The resistor ladder is always connected to VREF when bit 4 is set to “1”. When bit 4 is set to “0”, the resistor ladder is cut off from VREF except for A/D conversion performed. When bit 5, which is the AD external trigger valid bit, is set to “1”, A/D conversion starts also by a falling edge of an ADT input. When using an A/D external trigger, set the P5 7/ADT pin to input mode (set “0” to bit 7 of port P5 direc- tion register). Comparison Voltage Generator The comparison voltage generator divides the voltage between AV SS and VREF by 256 (when 8-bit A/D mode) or 1024 (when 10- bit A/D mode), and outputs the divided voltages. Channel Selector The channel selector selects one of the input ports P67/AN7–P60/AN0. Comparator and Control Circuit The comparator and control circuit compare an analog input volt- age with the comparison voltage and store the result in the AD conversion register. When an A/D conversion is completed, the control circuit sets the AD conversion completion bit and the A/D conversion interrupt request bit to “1”. Note that because the comparator consists of a capacitor coupling, set f(X IN) to 500 kHz or more during an A/D conversion. Use the clock divided from the main clock f(XIN) as the system clock Fig. 38 Structure of A/D converter-related registers AD control register (ADCON : address 003416) AD conversion completion bit 0 : Conversion in progress 1 : Conversion completed Analog input pin selection bits b2b1b0 0 0 0 : P60/AN0 0 0 1 : P61/AN1 0 1 0 : P62/AN2 0 1 1 : P63/AN3 1 0 0 : P64/AN4 1 0 1 : P65/AN5 1 1 0 : P66/AN6 1 1 1 : P67/AN7 VREF input switch bit 0 : AUTO 1 : ON AD external trigger valid bit 0 : A/D external trigger invalid 1 : A/D external trigger valid Interrupt source selection bit 0 : Interrupt request at AD conversion completed 1 : Interrupt request at ADT input falling Not used (“0” at reading) AD conversion low-order register (ADL : address 0014 16) Conversion mode selection bit 0 : 10-bit A/D mode 1 : 8-bit A/D mode Not used (“0” at reading)

• For 10-bit A/D mode A/D conversion result
• For 8-bit A/D mode Not used (undefined at reading) b7 b0

Rev.2.00 May. 24, 2006 page 39 of 90 REJ03B0028-0200 Fig. 40 A/D converter block diagram Fig. 39 Read of AD conversion register

• 10-bit reading (Read address 003516, then 001416) AD conversion high-order register (ADH: Address 003516) AD conversion low-order register (ADL: Address 001416) b7 b0 b7 b6 b5 b4b3 b2 b7 b0 b9 b8 b7 b6 b5 b4 b3 b2 b7 b0 (high-order) (low-order) Note : Bits 0 to 5 of address 001416 become “0” at reading. b1 b0
• 8-bit reading (Read only address 003516) AD conversion high-order register (ADH: Address 0035) Conversion mode selection bit 0 : 10-bit A/D mode 1 : 8-bit A/D mode Comparator A/D control circuit ADT/A/D interrupt request AV SS VRE F P60/SIN2/AN0 Data bus AD control register b b AD conversion high-order register Resistor ladder Channel selector P67/AN7 P66/AN6 P65/AN5 P64/AN4 P63/SCLK22 /AN3 P62/SCLK21 /AN2 P61/SOUT2 /AN1 P57/ADT/DA2 (Address 003516) AD conversion low-order register (Address 001416)

Rev.2.00 May. 24, 2006 page 40 of 90 REJ03B0028-0200 The 3826 group has a D/A converter with 8-bit resolution and 2 channels (DA1, DA2). The D/A converter is started by setting the DTMF/DA1 selection bit and the CTCSS/DA 2 selection bit to “0” and setting the value in the DA conversion register. When the DTMF/DA1 output enable bit and the CTCSS/DA2 output enable bit is set to “1”, the result of D/ A conversion is output from the corresponding DA1 pin or DA2 pin. When using the D/A converter, set the P56/DA1 pin and the P57/ DA 2 pin to input mode (set “0” to bits 6, 7 of port P5 direction reg- ister) and the pull-up resistor should be in the OFF state previously. The output analog voltage V is determined by the value n (base 10) in the DA conversion register as follows: V=V REF ✕ n/256 (n=0 to 255) Where VREF is the reference voltage. At reset, the DA conversion registers are set to “0016”, the DTMF/ DA 1 output enable bit and the CTCSS/DA2 output enable bit are set to “0”, and the P56/DA1 pin and the P57/DA2 pin goes to high impedance state. The D/A converter is not buffered, so connect an external buffer when driving a low-impedance load. ■ Note on applied voltage to V REF pin When the P56/DA1 pin and the P57/DA2 pin are used as an I/O port, be sure to apply Vcc to VREF pin. When these pins are used as D/A conversion output pins, the Vcc level is recommended for the applied voltage to VREF pin. When the voltage below Vcc level is applied, the D/A conversion accuracy may be worse. Fig. 41 Structure of DA control register Fig. 42 Block diagram of D/A converter b7 b0 DA control register (DACON : address 003616) DTM F/DA 1 output enable bit 0 : Disabled 1 : Enabled CTCSS timer write control bit 0 : Write value in latch only 1 : Write value in latch and counter High/Low group timer write control bit 0 : Write value in latch only 1 : Write value in latch and counter High group ROM data selection bit 0 : Sine wave 1 : “0” fixed Low group ROM data selection bit 0 : Sine wave 1 : “0” fixed CTCSS/DA 2 selection bit 0 : DA2 function 1 : CTCSS function DTMF/DA 1 selection bit 0 : DA1 function 1 : DTMF function CTCSS/DA 2 output enable bit 0 : Disabled 1 : Enabled P56/DA1 P57/DA2 5-bit adder Selector Low group ROM 5bit ✕ 32Selector 8-bit timer 8-bit timer XIN/2 CTCSS ROM 8bit ✕ 64 10-bit timer Selector High group ROM 5bit ✕ 32 Selector Selector Data bus DA1 conversion register (8) DA 1 output enable bit DA 2 output enable bit Data bus R-2R resistor ladder R-2R resistor ladder DA2 conversion register (8) When DTMF is selected, the high-order 6 bits are automatically set as the DTMF output. The low-order 2 bits is set by writing data to the D-A1 conversion register.*

Rev.2.00 May. 24, 2006 page 41 of 90 REJ03B0028-0200 DTMF Function (Dual Tone Multi Frequency) DTMF function is used to output the result which generated auto- matically the waveform of sine wave of two kinds of different frequency, and added two kinds of this sine wave as an analog value. DTMF output waveform can be output from DA 1 pin. DTMF wave- form is output by setting “1” (enabled) to the DTMF/DA1 output enable bit (bit 0 of address 003616), and setting “1” to the DTMF/ DA 1 selection bit (bit 2 of address 003616). At this time, set “0” (in- put state) to the direction register of ports P56/DA1 pin and pull-up resistor to be OFF state. In order to set two kinds of frequency which generates DTMF waveform, write a value in the DTMF high group timer and the DTMF low group timer, respectively. The value written in each above-mentioned timer is n, the sine wave of the following fre- quency can be generated. f = (Hz) Set “06 16” or more to the DTMF high group timer and the DTMF low group timer. After reset release, “0616” is automatically set to them. f(XIN)/2 (n+1) ✕ 32 The digital value for one period of high group and low group out- put is shown in Figure 43. DTMF output is automatically input to high-order 6 bits of the D/A1 conversion register as 6-bit D/A data. The low-order 2 bits of the D/A1 conversion register are fixed to the value written in the D/A1 conversion register. Moreover, only the sine wave of high group can be output by set- ting “1” to the bit 4 of the D/A control register. By setting “1” to the bit 5 of the D/A control register similarly, only the sine wave of low group can be output. Writing to the DTMF high group timer and the DTMF low group timer can also be changed to “writing to latch and timer simultaneously” by setting “1” to the bit 6 of the D/A con trol register. “Writing to only latch” is set after reset release. If the D/A1 conversion register is read when the DTMF function is selected,the digital value of DTMF output can be read. Fig. 43 Waveform data of high group and low group DA 1 value (8bit) 0 5 10 15 20 25 30 1416 2816 3C 16 5016 6416 7816 016 0 5 10 15 20 25 30 DA 1 value (8bit) 1416 2816 3C 16 5016 6416 7816 016 DA data of low group waveform (1 period) for DTMF DA data of high group waveform (1 period) for DTMF * This is the value set to DA1 conversion register when the low-order 2 bits are “0”. Conversion time of high group ROMConversion time of low group ROM

Rev.2.00 May. 24, 2006 page 42 of 90 REJ03B0028-0200 Low Groupt Frequency, High Group Frequency Low group frequency and high group frequency are as follows. (1) Low group frequency

• 697 Hz
• 770 Hz
• 852 Hz
• 941 Hz (2) High group frequency
• 1209 Hz
• 1336 Hz
• 1477 Hz
• 1633 Hz Table 9 shows the example of frequency accuracy (at f(X IN)=4 MHz). Fig. 44 Key matrix of telephone and rating frequencyTable 9 Example of frequency accuracy (at f(XIN) = 4 MHz) Rating frequency (Hz) 697 770 852 941 1209 1336 1477 1633 n (Timer value) Error frequency (Hz) –2.6 1.6 4.2 5.9 –7.1 –6.3 11.1 11.7 Deviation (%) –0.367 0.208 0.488 0.630 –0.580 –0.460 0.750 0.720 Output frequency (Hz) 694.4 771.6 856.2 946.9 1201.9 1329.7 1488.1 1644.7 1 2 3 4 5 6 B 7 8 9 * 0 # A C D 697Hz 770Hz 852Hz 941Hz 1209Hz1336Hz1477Hz1633Hz Low group frequency High group frequency

Rev.2.00 May. 24, 2006 page 43 of 90 REJ03B0028-0200 (Continuous Tone-Controlled Squelch System) The CTCSS function is used to generate the sine wave of single frequency automatically. The CTCSS output waveform can be out- put from DA 2 pin. CTCSS waveform is outputted by setting “1” to the CTCSS/DA 2 output enable bit (bit 1 of address 003616), and setting “1” to the CTCSS/DA2 selection bit (bit 3 of address 003616). In order to set the frequency of CTCSS output, value is written in the CTCSS timer. The CTCSS timer consists of a 10-bit timer. When writing a value to the CTCSS timer, write the low-or- der byte first. Rating frequency (Hz) 67.0 77.0 88.5 100.0 107.2 114.8 123.0 131.8 141.3 151.4 162.2 173.8 186.2 203.5 218.1 233.6 250.3 n (Timer value) 465 405 352 312 291 271 253 236 220 205 192 179 167 153 142 133 124 Error frequency (Hz) 0.06 –0.03 0.027 –0.16 –0.18 0.09 0.03 0.06 0.10 0.30 –0.28 –0.19 –0.19 –0.58 0.43 –0.39 –0.30 Deviation (%) 0.089 –0.038 0.030 –0.160 –0.167 0.078 0.026 0.043 0.073 0.198 –0.174 –0.109 –0.101 –0.284 0.198 –0.167 –0.120 Output frequency (Hz)] 67.06 76.97 88.53 99.84 107.02 114.89 123.03 131.86 141.40 151.70 161.92 173.61 186.01 202.92 218.53 233.20 250.00 Table 10 Example of frequency accuracy (at f(XIN) = 4 MHz) f (XIN)/2 (n+1) ✕ 64 Vcc When reading a value from the CTCSS timer, read the high-order byte first. By the value written in the CTCSS timer is n, the sine wave of the following frequency is generated. f = (Hz) Set “006 16” or more to the CTCSS timer. “0016” is automatically set to the high-order of the CTCSS timer and “0616” is automati- cally set to the low-order of the CTCSS timer after reset release. The amplitude of CTCSS output is obtained by the following for- mula. C = If the D/A2 conversion register is read when the CTCSS function is selected, the digital value of CTCSS output can be read. Table 10 shows the example of frequency accuracy (at f(XIN) = 4 MHz). Fig. 45 Equivalent connection circuit of D/A converter AV SS VREF “0” “1” MSB “0” “1” R R R R R R R 2R 2R LSB DA i DAi conversion register DA i output enable bit

Rev.2.00 May. 24, 2006 page 44 of 90 REJ03B0028-0200 The 3826 group has the Liquid Crystal Display (LCD) drive control circuit consisting of the following.

• LCD display RAM
• Segment output enable register
• LCD mode register
• Voltage multiplier
• Selector
• Timing controller
• Common driver
• Segment driver
• Bias control circuit A maximum of 40 segment output pins and 4 common output pins can be used. Up to 160 pixels can be controlled for LCD display. When the LCD Fig. 46 Structure of segment output enable register and LCD mode register enable bit is set to “1” (LCD ON) after data is set in the LCD mode register, the segment output enable register and the LCD display RAM, the LCD drive control circuit starts reading the display data automatically, performs the bias control and the duty ratio control, and displays the data on the LCD panel. Table 9 Maximum number of display pixels at each duty ratio Duty ratio Maximum number of display pixel 80 dots or 8 segment LCD 10 digits 120 dots or 8 segment LCD 15 digits 160 dots or 8 segment LCD 20 digits S e g m e n t o u t p u t e n a b l e b i t 0 O u t p u t p o r t s P 30– P S e g m e n t o u t p u t S E G 1 S E G 2 S e g m e n t o u t p u t e n a b l e b i t O u t p u t p o r t s P 36, P S e g m e n t o u t p u t S E G 2 S E G 2 S e g m e n t o u t p u t e n a b l e b i t I O p o r t s P 00– P S e g m e n t o u t p u t S E G 2 S E G 3 S e g m e n t o u t p u t e n a b l e b i t I O p o r t s P 06, P S e g m e n t o u t p u t S E G 3 S E G 3 S e g m e n t o u t p u t e n a b l e b i t I O p o r t P S e g m e n t o u t p u t S E G 3 S e g m e n t o u t p u t e n a b l e b i t I O p o r t s P 11– P S e g m e n t o u t p u t S E G 3 S E G 3 L C D o u t p u t e n a b l e b i t D i s a b l e d E n a b l e d N o t u s e d a t r e a d i n g W r i t e t o t h i s b i t a t w r i t i n g S e g m e n t o u t p u t e n a b l e r e g i s t e r S E G a d d r e s s b 7 b 0 L C D m o d e r e g i s t e r L M a d d r e s s D u t y r a t i o s e l e c t i o n b i t s b b N o t u s e d d u t y u s e C O M 0, C O M 1) d u t y u s e C O M 0– C O M 2) d u t y u s e C O M 0– C O M 3) B i a s c o n t r o l b i t b i a s b i a s L C D e n a b l e b i t L C D O F F L C D O N V o l t a g e m u l t i p l i e r c o n t r o l b i t V o l t a g e m u l t i p l i e r d i s a b l e V o l t a g e m u l t i p l i e r e n a b l e L C D c i r c u i t d i v i d e r d i v i s i o n r a t i o s e l e c t i o n b i t s b b C l o c k i n p u t d i v i s i o n o f C l o c k i n p u t d i v i s i o n o f C l o c k i n p u t d i v i s i o n o f C l o c k i n p u t L C D C K c o u n t s o u r c e s e l e c t i o n b i t N o t e f XC I N ) f XI N ) f XC I N ) i n l o w s p e e d m o d e N o t e : L C D C K i s a c l o c k f o r a L C D t i m i n g c o n t r o l l e r . b 7 b 0

Rev.2.00 May. 24, 2006 page 45 of 90 REJ03B0028-0200 Fig. 47 Block diagram of LCD controller/driver D a t a b u s T i m i n g c o n t r o l l e r L C D d i v i d e r f ( XI N ) / 8 1 9 2 f XC I N ) i n l o w s p e e d m o d e f ( XC I N ) / 3 2 C O M 0 C O M 1 C O M 2 C O M 3VS S VL 1 VL 2 VL 3S E G 3S E G 2S E G 1S E G 0 A d d r e s s 0 0 4 01

6 A d d r e s s 0 0 4 11

“ 1 ” “ 0 ” L C D C K L C D C K c o u n t s o u r c e s e l e c t i o n b i t L C D c i r c u i t d i v i d e r d i v i s i o n r a t i o s e l e c t i o n b i t s B i a s c o n t r o l b i t L C D e n a b l e b i t D u t y r a t i o s e l e c t i o n b i t s 2 2 S e l e c t o rS e l e c t o rS e l e c t o r S e l e c t o r S e l e c t o rS e l e c t o r L C D d i s p l a y R A MA d d r e s s 0 0 5 31 P 14/ S E G 3 8P 30/ S E G 1

8 P 15/ S E G 3

s h i f t L e v e l s h i f t L e v e l s h i f t L e v e l s h i f t L e v e l s h i f t L e v e l s h i f t C o m m o n d r i v e r C o m m o n d r i v e r C o m m o n d r i v e r C o m m o n d r i v e r C 1 C 2 V o l t a g e m u l t i p l i e r c o n t r o l b i t L e v e l S h i f t L e v e l S h i f t L e v e l S h i f t L e v e l S h i f t S e g m e n t d r i v e r S e g m e n t d r i v e r S e g m e n t d r i v e r S e g m e n t d r i v e r S e g m e n t d r i v e r S e g m e n t d r i v e r B i a s c o n t r o l L C D o u t p u t e n a b l e b i t VC C

Rev.2.00 May. 24, 2006 page 46 of 90 REJ03B0028-0200 Voltage Multiplier (3 Times) The voltage multiplier performs threefold boosting. This circuit in- puts a reference voltage for boosting from LCD power input pin VL1. Set each bit of the segment output enable register and the LCD mode register in the following order for operating the voltage mul- tiplier. 1. Set the segment output enable bits (bits 0 to 5) of the seg- ment output enable register to “0” or “1”. 2. Set the duty ratio selection bits (bits 0 and 1), the bias con- trol bit (bit 2), the LCD circuit divider division ratio selection bits (bits 5 and 6), and the LCDCK count source selection bit (bit 7) of the LCD mode register to “0” or “1”. 3. Set the LCD output enable bit (bit 6) of the segment output enable register to “1” (enabled). Apply the limit voltage or less to the VL1 pin. 4. Set the voltage multiplier control bit (bit 4) of the LCD mode register to “1” (voltage multiplier enabled). However, be sure to select 1/3 bias for bias control. When voltage is input to the VL1 pin during operating the voltage multiplier, voltage that is twice as large as VL1 occurs at the VL2 pin, and voltage that is three times as large as VL1 occurs at the VL3 pin. ■ Notes on Voltage Multiplier When using the voltage multiplier, apply the limit voltage or less to the VL1 pin, then set the voltage multiplier control bit to “1” (en- abled). When not using the voltage multiplier, set the LCD output enable bit to “1”, then apply proper voltage to the LCD power input pins L1–VL3). When the LCD output enable bit is set to “0” (disabled) (during reset is included), the VL3 pin is connected to VCC inside of this microcomputer. When the voltage exceeding VCC is applied to VL3, apply VL3 voltage after setting the LCD output enable bit to “1” (enabled). Fig. 48 Example of circuit at each bias Table 10 Bias control and applied voltage to VL1–VL3 Bias value 1/3 bias 1/2 bias Voltage value VL3=V LCD VL2=2/3 VLCD VL1=1/3 VLCD VL3=V LCD VL2=V L1=1/2 VLCD Note : VLCD is the maximum value of supplied voltage for the LCD panel. Bias Control and Applied Voltage to LCD Power Input Pins To the LCD power input pins (VL1–V L3), apply the voltage shown in Table 10 according to the bias value. Select a bias value by the bias control bit (bit 2 of the LCD mode register). R R R R b i a s R R R VC C VL VL C 2 C 1 VL R R R VC C VL VL C 2 C 1 VL VL VL C 2 C 1 VL O p e n O p e n C o n t r a s t c o n t r o l O p e n O p e n C o n t r a s t c o n t r o l 1 / 3 b i a s w h e n n o t u s i n g t h e v o l t a g e m u l t i p l i e r 1 / 3 b i a s w h e n u s i n g t h e v o l t a g e m u l t i p l i e r

Rev.2.00 May. 24, 2006 page 47 of 90 REJ03B0028-0200 (frequency of count source for LCDCK) (divider division ratio for LCD)f(LCDCK)= f(LCDCK) duty ratioFrame frequency= Fig. 49 LCD display RAM map Common Pin and Duty Ratio Control The common pins (COM 0–COM 3) to be used are determined by duty ratio. Select duty ratio by the duty ratio selection bits (bits 0 and 1 of the LCD mode register). After reset, the V CC (VL3) voltage is output from the common pins. LCD Display RAM Addresses 004016 to 005316 are the designated RAM for the LCD display. When “1” are written to these addresses, the correspond- ing segments of the LCD display panel are turned on. LCD Drive Timing The frequency of internal signal LCDCK decided LCD drive timing and the frame frequency can be determined with the following equation:Table 11 Duty ratio control and common pins used Duty ratio Common pins used Notes 1: COM 2 and COM 3 are open. 2: COM 3 is open. Bit 1 Bit 0 COM 0, COM 1 (Note 1) COM 0–COM 2 (Note 2) COM 0–COM 3 Duty ratio selection bits Segment Signal Output Pins Segment signal output pins are classified into the segment-only pins (SEG0–SEG 17), the segment or output port pins (SEG18– SEG 25), and the segment or I/O port pins (SEG26–SEG 39). Segment signals are output according to the bit data of the LCD RAM corresponding to the duty ratio. After reset, a V CC (=VL3) voltage is output to the segment-only pins and the segment/out- put port pins are the high impedance condition and pulled up to V CC (=VL3) voltage. Also, the segment/I/O port pins (SEG26–SEG 39) are set to input mode as I/O ports, and VCC (=VL3) is applied to them by pull-up resistor. 0 0 4 01 C 1 D 1 B i t A d d r e s s S E G 1 S E G 3 S E G 5 S E G 7 S E G 9 S E G 1 S E G 1 S E G 1 S E G 1 S E G 1 S E G 2 S E G 2 S E G 2 S E G 2 S E G 2 S E G 3 S E G 3 S E G 3 S E G 3 S E G 3 7 6 5 4 3 2 1 0 C O M 3 C O M 0C O M 2 C O M 1 C O M 0 C O M 3 C O M 2 C O M 1 S E G 0 S E G 2 S E G 4 S E G 6 S E G 8 S E G 1 S E G 1 S E G 1 S E G 1 S E G 1 S E G 2 S E G 2 S E G 2 S E G 2 S E G 2 S E G 3 S E G 3 S E G 3 S E G 3 S E G 3

Rev.2.00 May. 24, 2006 page 48 of 90 REJ03B0028-0200 Fig. 50 LCD drive waveform (1/2 bias) I n t e r n a l s i g n a l L C D C K t i m i n g 1 / 4 d u t y V o l t a g e l e v e l VL VL 2= VL VS S VL VS S C O M 0 C O M 1 C O M 2 C O M 3 S E G 0 O F F O N O F F O N C O M 3 C O M 2 C O M 1 C O M 0 C O M 3 C O M 2 C O M 1 C O M 0 1 / 3 d u t y VL VL 2= VL VS S VL VS S O F FO N O N O F F O N O F F 1 / 2 d u t y C O M 0 C O M 1 C O M 2 S E G 0 C O M 0 C O M 1 S E G 0 VL VL 2= VL VS S VL VS S O F FO N O F FO N O F FO N O F FO N C O M 0 C O M 2 C O M 1 C O M 0 C O M 2 C O M 1 C O M 0 C O M 2 C O M 1 C O M 0 C O M 1 C O M 0 C O M 1 C O M 0 C O M 1 C O M 0

Rev.2.00 May. 24, 2006 page 49 of 90 REJ03B0028-0200 Fig. 51 LCD drive waveform (1/3 bias) I n t e r n a l s i g n a l L C D C K t i m i n g 1 / 4 d u t y V o l t a g e l e v e l VL VS S C O M 0 C O M 1 C O M 2 C O M 3 S E G 0 O F F O N O F F O N C O M 3 C O M 2 C O M 1 C O M 0 C O M 3 C O M 2 C O M 1 C O M 0 1 / 3 d u t y O F FO N O N O F F O N O F F 1 / 2 d u t y C O M 0 C O M 1 C O M 2 S E G 0 C O M 0 C O M 1 S E G 0 O F FO N O F FO N O F FO N O F FO N VL VL VS S VL VL VL VS S VL VL VS S VL VL VS S VL VL VS S C O M 0 C O M 2 C O M 1 C O M 0 C O M 2 C O M 1 C O M 0 C O M 2 C O M 1 C O M 0 C O M 1 C O M 0 C O M 1 C O M 0 C O M 1 C O M 0

Rev.2.00 May. 24, 2006 page 50 of 90 REJ03B0028-0200 The watchdog timer gives a mean of returning to the reset status when a program cannot run on a normal loop (for example, be- cause of a software runaway). The watchdog timer consists of an 8-bit watchdog timer L and a 6- bit watchdog timer H. At reset or writing to the watchdog timer control register (address 0037 16), the watchdog timer is set to “3FFF16”. When any data is not written to the watchdog timer con- trol register (address 003716) after reset, the watchdog timer is stopped. The watchdog timer starts to count down from “3FFF16” by writing to the watchdog timer control register and an internal re- set occurs at an underflow. Accordingly, when using the watchdog timer function, write the watchdog timer control register before an underflow. The watchdog timer does not function when writing to the watchdog timer control register has not been done after reset. When not using the watchdog timer, do not write to it. When the watchdog timer control register is read, the following values are read:

• value of high-order 6-bit counter
• value of STP instruction disable bit
• value of count source selection bit. When the STP instruction disable bit is “0”, the STP instruction is enabled. The STP instruction is disabled when this bit is set to “1”. If the STP instruction which is disabled is executed, it is processed as an undefined instruction, so that a reset occurs internally. This bit can be set to “1” but cannot be set to “0” by program. This bit is “0” after reset. When the watchdog timer H count source selection bit is “0”, the detection time is set to 8.19 s at f(X CIN) = 32 kHz and 32.768 ms at f(XIN) = 8 MHz. When the watchdog timer H count source selection bit is “0”, the detection time is set to 32 ms at f(X CIN) = 32 kHz and 128 µs at f(XIN) = 8 MHz. There is no difference in the detection time be- tween the middle-speed mode and the high-speed mode. Fig. 52 Block diagram of watchdog timer Fig. 53 Structure of watchdog timer control register Fig. 54 Timing of reset output XIN Data bus XCIN “1” “0” Internal system clock selection bit (Note) “0” “1”1/16 Watchdog timer H count source selection bit Reset circuit Undefined instruction Reset “3F16” is set when watchdog timer is written to. Internal reset RESET Reset release time wait “FF16” is set when watchdog timer is written to. STP instruction STP instruction disable bit Watchdog timer H (6) Watchdog timer L (8) Note: This is the bit 7 of CPU mode register and is used to switch the middle-/high-speed mode and low-speed mode. b 7 b 0 W a t c h d o g t i m e r r e g i s t e r W D T C O N a d d r e s s S T P i n s t r u c t i o n d i s a b l e b i t S T P i n s t r u c t i o n e n a b l e d S T P i n s t r u c t i o n d i s a b l e d W a t c h d o g t i m e r H c o u n t s o u r c e s e l e c i o n b i t W a t c h d o g t i m e r L u n d e r f l o w f XI N ) o r f XC I N ) W a t c h d o g t i m e r H ( f o r r e a d - o u t o f h i g h - o r d e r 6 b i t ) F F i s s e t t o t h e w a t c h d o g t i m e r b y w r i t i n g v a l u e s t o t h i s a d d r e s s I n t e r n a l r e s e t s i g n a l W a t c h d o g t i m e r d e t e c t i o n A p p r o x . 1 m s ( f ( XI N ) = 8 M H Z) f ( XI N )

Rev.2.00 May. 24, 2006 page 51 of 90 REJ03B0028-0200 TOUT /φ OUTPUT FUNCTION The system clock φ or timer 2 divided by 2 (TOUT output) can be output from port P43 by setting the TOUT /φ output enable bit of the timer 123 mode register and the TOUT /φ output control register. Set the P43/φ/TOUT pin to output mode (set “1” to bit 3 of port P4 direction register) when outputting TOUT /φ. Fig. 55 Structure of TOUT /φφφφφ output-related registers TO U T/φ o u t p u t c o n t r o l b i t S y s t e m c l o c k φ o u t p u t TO U T o u t p u t N o t u s e d a t r e a d i n g TO U T/φ o u t p u t c o n t r o l r e g i s t e r C K O U T a d d r e s s b 7 b 0 T i m e r 1 2 3 m o d e r e g i s t e r T M a d d r e s s TO U T o u t p u t a c t i v e e d g e s w i t c h b i t S t a r t a t H o u t p u t S t a r t a t L o u t p u t TO U T/φ o u t p u t e n a b l e b i t TO U T/φ o u t p u t d i s a b l e d TO U T/φ o u t p u t e n a b l e d T i m e r w r i t e c o n t r o l b i t W r i t e d a t a i n l a t c h a n d t i m e r W r i t e d a t a i n l a t c h o n l y T i m e r c o u n t s o u r c e s e l e c t i o n b i t T i m e r o u t p u t f XI N ) o r f XC I N ) i n l o w s p e e d m o d T i m e r c o u n t s o u r c e s e l e c t i o n b i t T i m e r o u t p u t f XI N ) o r f XC I N ) i n l o w s p e e d m o d T i m e r c o u n t s o u r c e s e l e c t i o n b i t f XI N ) o r f XC I N ) i n l o w s p e e d m o d f XC I N ) N o t u s e d a t r e a d i n g b 7 b 0

Rev.2.00 May. 24, 2006 page 52 of 90 REJ03B0028-0200 Fig. 56 Example of reset circuit RESET CIRCUIT When the power source voltage is within limits, and main clock XIN-XOUT is stable, or a stabilized clock is input to the XIN pin, if the RESET pin is held at an “L” level for 2 µs or more, the micro- computer is in an internal reset state. Then the RESET pin is returned to an “H” level, reset is released after approximate 8200 cycles of f(X IN), the program in address FFFD16 (high-order byte) Fig. 57 Reset Sequence and address FFFC16 (low-order byte). Make sure that the reset in- put voltage is less than 0.2 VCC (min.) for the power source voltage of VCC (min.). *VCC (min.) = Minimum value of power supply voltage limits applied to VCC pin VC CR E S E T VC CR E S E T P o w e r s o u r c e v o l t a g e d e t e c t i o n c i r c u i t VC C R E S E T P o w e r o n 0 . 2 VC C l e v e l O s c i l l a t i o n s t a b i l i z e d 2 µs XI N 0 V 0 V 0 V N o t e N o t e: R e s e t r e l e a s e v o l t a g e V c c = V c c ( m i n . ) A D L F F F C F F F D A D H ,U n d e f i n e d XI N : A p p r o x . 8 2 0 0 c y c l e s N o t e : T h e f r e q u e n c y o f s y s t e m c l o c k φ i s f ( XI N ) d i v i d e d b y 8 . R e s e t a d d r e s s f r o m v e c t o r t a b l e R E S E T I n t e r n a l r e s e t A d d r e s s D a t a S Y N C S y s t e m c l o c k φ XI N A D H A D LU n d e f i n e d U n d e f i n e d U n d e f i n e d

Rev.2.00 May. 24, 2006 page 53 of 90 REJ03B0028-0200 Fig. 58 Internal state of microcomputer immediately after reset Note: The contents of all other registers and RAM are undefined after reset, so they must be initialized by software. ✕ : Undefined Register contentsAddress 0001 000316 000516 000716 000916 000B16 000D 16 000F16 001416 001616 001716 001916 001A16 001B16 001D 16 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 003216 003316 003416 003616 003716 003816 003916 003A16 003B16 003C 16 003D 16 003E16 003F16 (PS) (PCH ) (PCL) (10) (11) (12) (13) (14) (15) (16) (17) (18) (19) (20) (21) (22) (23) (24) (25) (26) (27) (28) (33) (34) (1) (2) (3) (4) (5) (6) (7) (8) (9) (35) (36) (37) (38) (39) (40) (41) (42) (43) Timer Y low-order register Port P5 direction register Port P6 direction register PULL register B Timer Y high-order register Serial I/O1 control register UART control register Timer X high-order register Timer X low-order register Timer X mode register Timer Y mode register Timer 123 mode register Serial I/O1 status register Port P7 direction register AD control register Segment output enable register LCD mode registerPULL register A Interrupt edge selection register CPU mode register Interrupt request register 1 Interrupt request register 2 Interrupt control register 1 Interrupt control register 2 Processor status register Program counter Port P4 direction register Port P2 direction register Port P3 output control register Port P1 direction register Port P0 direction register Timer 1 register Timer 2 register Timer 3 register AD conversion low-order register 111000 0 0 100000 0 0 0011 11 11 1 0 0 1 0 000 0016 0016 0016 0016 0016 0016 FF16 0016 0016 0016 0016 0016 0016 0016 0016 FF16 FF16 0016 0016 0016 3F16 0016 0016 0016 0016 0016 0016 0016 0016 FF16 FF16 Contents of address FFFD16 Contents of address FFFC16 DA control register Watchdog timer control register DA1 conversion register DA2 conversion register Serial I/O2 control register TOUT /φ output control register PWM control register Watchdog timer (high-order)(48) Watchdog timer (low-order) FF16 0116 0016 0 0 0 1 0 000 3F16 FF16(49) 001516Key input control register 0016 ✕✕ 0000 1 0 002E16 002F16 (29) (30) 0616 0016 CTCSS timer (low-order) CTCSS timer (high-order) 003016 003116 (31) (32) 0616 0616 DTMF high group timer DTMF low group timer (44) (45) (46) (47) Register contentsAddress

Rev.2.00 May. 24, 2006 page 54 of 90 REJ03B0028-0200 Fig. 59 Oscillator circuit Fig. 60 External clock input circuit CLOCK GENERATING CIRCUIT The 3826 group has two built-in oscillation circuits: main clock XIN-XOUT oscillation circuit and sub-clock XCIN-XCOUT oscillation circuit. An oscillation circuit can be formed by connecting an oscil- lator between X IN and XOUT (XCIN and XCOUT ). Use the circuit constants in accordance with the oscillator manufacturer’s recom- mended values. A feed-back resistor exists on-chip (An external feed-back resistor may be needed depending on conditions.). However, an external feed-back resistor is needed between X CIN and XCOUT since a resistor does not exist between them. To supply a clock signal externally, input it to the XIN pin and make the XOUT pin open. The sub-clock oscillation circuit cannot directly input clocks that are externally generated. Accordingly, be sure to cause an external oscillator to oscillate. Immediately after poweron, only the X IN oscillation circuit starts oscillating, and XCIN and XCOUT pins go to high-impedance state. Frequency Control (1) Middle-speed mode The clock input to the XIN pin is divided by 8 and it is used as the system clock φ. After reset, this mode is selected. (2) High-speed mode The clock input to the XIN pin is divided by 2 and it is used as the system clock φ. (3) Low-speed mode

• The clock input to the XCIN pin is divided by 2 and it is used as the system clock φ.
• A low-power consumption operation can be realized by stopping the main clock in this mode. To stop the main clock, set the main clock stop bit of the CPU mode register to “1”. When the main clock is restarted, after setting the main clock stop bit to “0”, set enough time for oscillation to stabilize by pro- gram. Note: If you switch the mode between middle/high-speed and low- speed, stabilize both X IN and XCIN oscillations. The suffi- cient time is required for the sub clock to stabilize, espe- cially immediately after poweron and at returning from stop mode. When switching the mode between middle/high- speed and low-speed, set the frequency in the condition that f(X IN) > 3•f(XCIN). Oscillation Control (1) Stop mode If the STP instruction is executed, the system clock φ stops at an “H” level, and main and sub clock oscillators stop. In this time, values set previously to timer 1 latch and timer 2 latch are loaded automatically to timer 1 and timer 2. Before the STP instruction, set the values to generate the wait time required for oscillation stabilization to timer 1 latch and timer 2 latch (low-order 8 bits are set to timer 1, high-order 8 bits are set to timer 2). Either f(X IN) or f(XCIN) divided by 16 is input to timer 1 as count source, and the output of timer 1 is connected to timer 2. The bits of the timer 123 mode register except bit 4 are set to “0”. Set the timer 1 and timer 2 interrupt enable bits to “0” before ex- ecuting the STP instruction. Oscillation restarts at reset or when an external interrupt is re- ceived, but the system clock φ is not supplied to the CPU until timer 2 underflows. This allows time for the clock circuit oscillation to stabilize when a ceramic resonator is used. (2) Wait mode If the WIT instruction is executed, only the system clock φ stops at an “H” state. The states of main clock and sub clock are the same as the state before the executing the WIT instruction, and oscilla- tion does not stop. Since supply of internal clock φ is started im- mediately after the interrupt is received, the instruction can be ex- ecuted immediately. XCIN C IN C OUTC CIN C COUT Rf Rd XCOUT XIN XOUT N otes : Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive capacity setting. Use the value recommended by the maker of the oscillator. Also, if the oscillator manufacturer's data sheet specifies that a feedback resistor be added external to the chip though a feedback resistor exists on-chip, insert a feedback resistor between X IN and XOUT following the instruction. Rd (Note) XI N XO U T E x t e r n a l o s c i l l a t i o n c i r c u i t O p e n VC C VS S C C I N C C O U T R f R d XC I N XC O U T

Rev.2.00 May. 24, 2006 page 55 of 90 REJ03B0028-0200 Fig. 61 Clock generating circuit block diagram WIT instruction STP instruction System clock φ S R Q STP instruction S R Q Main clock stop bit S R Q Timer 2Timer 11/2 1/4 XIN XOUT XCOUTXCIN Interrupt request Reset Timer 1 count source selection bit Timer 2 count source selection bit Low-speed mode Middle-/High-speed mode System clock selection bit (Note 1) Middle-speed mode High-speed mode or Low-speed mode Notes 1: When using the sub clock for the system clock φ, set the X C switch bit to “1”. Main clock division ratio selection bit “1” “0” “1” “0” Interrupt disable flag I XC switch bit (Note 1) “1” “0” (Note 2) Although a feed-back resistor exists on-chip, an external feed-back resistor may be needed depending on conditions.2:

Rev.2.00 May. 24, 2006 page 56 of 90 REJ03B0028-0200 Fig. 62 State transitions of system clock N o t e s 1 : S w i t c h t h e m o d e a c c o r d i n g t o t h e a r r o w s s h o w n b e t w e e n t h e m o d e b l o c k s . ( D o n o t s w i t c h b e t w e e n t h e m o d e d i r e c t l y w i t h o u t a n a r r o w . ) T h e a l l m o d e s c a n b e s w i t c h e d t o t h e s t o p m o d e o r t h e w a i t m o d e a n d r e t u r n e d t o t h e s o u r c e m o d e w h e n t h e s t o p m o d e o r t h e w a i t m o d e i s e n d e d W h e n t h e s t o p m o d e i s e n d e d a d e l a y t i m e c a n b e s e t b y t i m e r a n d t i m e r T i m e r a n d L C D o p e r a t e i n t h e w a i t m o d e W a i t u n t i l o s c i l l a t i o n s t a b i l i z e s a f t e r o s c i l l a t i n g t h e m a i n c l o c k b e f o r e t h e s w i t c h i n g f r o m t h e l o w s p e e d m o d e t o m i d d l e h i g h s p e e d m o d e T h e e x a m p l e a s s u m e s t h a t M H z i s b e i n g a p p l i e d t o t h e XI N p i n a n d k H z t o t h e XC I N p i n φ i n d i c a t e s t h e s y s t e m c l o c k C M 4 : X c s w i t c h b i t O s c i l l a t i o n s t o p XC I N , XC O U T C M 5 M a i n c l o c k XI N – XO U s t o p b i t O s c i l l a t i n g S t o p p e d C M 6 M a i n c l o c k d i v i s i o n r a t i o s e l e c t i o n b i t f XI N ) h i g h s p e e d m o d e f XI N ) m i d d l e s p e e d m o d e C M 7 S y s t e m c l o c k s e l e c t i o n b i t XI N – XO U T s e l e c t e d m i d d l e h i g h s p e e d m o d e XC I N – XC O U T s e l e c t e d l o w s p e e d m o d e C P U m o d e r e g i s t e r C P U M a d d r e s s b 7 b 4 R e s e t C M 6 “ 0 ”“ 1 ” C M 6 “ 0 ”“ 1 ” C M 5 “ 0 ”“ 1 ” C M 5 “ 0 ”“ 1 ” “ 0 C M5 C “ 0 ” “ 1 ” “ 0 ” “ 1 ” C M C M 6“ 1 ” “ 1 “ 0 C M 6 “ 0 ”“ 1 ” C M 7 “ 0 ”“ 1 ” C M 7 “ 0 ”“ 1 ” C M 7 = 0 ( 8 M H z s e l e c t e d ) C M 6 M i d d l e s p e e d C M 5 M H z o s c i l l a t i n g C M 4 k H z s t o p p e d M i d d l e - s p e e d m o d e f M H z ) C M 6 “ 0 ”“ 1 ” C M 4 “ 0 ”“ 1 ” C M 4 “ 0 ”“ 1 ” C M 7 = 0 ( 8 M H z s e l e c t e d ) C M 6 H i g h s p e e d C M 5 M H z o s c i l l a t i n g C M 4 k H z s t o p p e d H i g h - s p e e d m o d e f M H z C M 7 = 0 ( 8 M H z s e l e c t e d ) C M 6 M i d d l e s p e e d C M 5 M H z o s c i l l a t i n g C M 4 k H z o s c i l l a t i n g M i d d l e - s p e e d m o d e f M H z C M 7 = 0 ( 8 M H z s e l e c t e d ) C M 6 H i g h s p e e d C M 5 M H z o s c i l l a t i n g C M 4 k H z o s c i l l a t i n g H i g h - s p e e d m o d e f M H z C M4 C M6 “ 0 ” “ 1 ” “ 0 ” “ 1 ” C M C M 6“ 1 ” “ 1 “ 0 “ 0 C M 7 = 1 ( 3 2 k H z s e l e c t e d ) C M 6 M i d d l e s p e e d C M 5 M H z o s c i l l a t i n g C M 4 k H z o s c i l l a t i n g L o w- s p e e d m o d e f (φ) k H z C M 7 = 1 ( 3 2 k H z s e l e c t e d ) C M 6 H i g h s p e e d C M 5 M H z o s c i l l a t i n g C M 4 k H z o s c i l l a t i n g L o w- s p e e d m o d e f k H z C M 7 = 1 ( 3 2 k H z s e l e c t e d ) C M 6 M i d d l e s p e e d C M 5 M H z s t o p p e d C M 4 k H z o s c i l l a t i n g L o w- s p e e d m o d e f k H z C M 7 = 1 ( 3 2 k H z s e l e c t e d ) C M 6 H i g h s p e e d C M 5 M H z s t o p p e d C M 4 k H z o s c i l l a t i n g L o w- s p e e d m o d e f k H z

Rev.2.00 May. 24, 2006 page 57 of 90 REJ03B0028-0200 The contents of the processor status register (PS) after a reset are undefined, except for the interrupt disable flag (I) which is “1”. Af- ter a reset, initialize flags (T flag, D flag, etc.) which affect program execution. Interrupt When the contents of an interrupt request bits are changed by the program, execute a BBC or BBS instruction after at least one in- struction. This is for preventing executing a BBC or BBS instruction to the contents before change. Decimal Calculations To calculate in decimal notation, set the decimal mode flag (D) to “1”, then execute an ADC or SBC instruction. After executing an ADC or SBC instruction, execute at least one instruction before executing a SEC, CLC, or CLD instruction. In decimal mode, the values of the negative (N), overflow (V), and zero (Z) flags are invalid. Multiplication and Division Instructions The index mode (T) and the decimal mode (D) flags do not affect the MUL and DIV instruction. The execution of these instructions does not change the contents of the processor status register. Ports Use instructions such as LDM and STA, etc., to set the port direc- tion registers. The contents of the port direction registers cannot be read. The following cannot be used:

• LDA instruction
• The memory operation instruction when the T flag is “1”
• The bit-test instruction (BBC or BBS, etc.)
• The read-modify-write instruction (calculation instruction such as ROR etc., bit manipulation instruction such as CLB or SEB etc.)
• The addressing mode which uses the value of a direction regis- ter as an index Serial I/O In clock synchronous serial I/O, if the receive side is using an ex- ternal clock and it is to output the SRDY signal, set the transmit en- able bit, the receive enable bit, and the SRDY output enable bit to “1”. The TxD pin of serial I/O1 retains the level then after transmission is completed. In serial I/O2 selecting an internal clock, the S OUT2 pin goes to high impedance state after transmission is completed. In serial I/O2 selecting an external clock, the SOUT2 pin retains the level then after transmission is completed. A/D Converter The input to the comparator is combined by internal capacitors. Therefore, since conversion accuracy may be worse by losing of an electric charge when the conversion speed is not enough, make sure that f(X IN) is at least 500 kHz during an A/D conver- sion. The normal operation of A/D conversion cannot be guaranteed when performing the next operation:
• When writing to CPU mode register during A/D conversion op- eration
• When writing to AD control register during A/D conversion op- eration
• When executing STP instruction or WIT instruction during A/D conversion operation Instruction Execution Time The instruction execution time is obtained by multiplying the fre- quency of the system clock φ by the number of cycles needed to execute an instruction. The number of cycles required to execute an instruction is shown in the list of machine instructions. The frequency of the system clock φ depends on the main clock division ratio selection bit and the system clock selection bit.

Rev.2.00 May. 24, 2006 page 58 of 90 REJ03B0028-0200 Countermeasures Against Noise (1) Shortest wiring length ➀ Wiring for RESET pin Make the length of wiring which is connected to the RESET pin as short as possible. Especially, connect a capacitor across the RESET pin and the V SS pin with the shortest possible wiring (within 20 mm).

• Reason The width of a pulse input into the RESET pin is determined by the timing necessary conditions. If noise having a shorter pulse width than the standard is input to the RESET pin, the reset is released before the internal state of the microcomputer is com- pletely initialized. This may cause a program runaway. Fig. 64 Wiring for clock I/O pins (2) Connection of bypass capacitor across V SS line and VCC line In order to stabilize the system operation and avoid the latch-up, connect an approximately 0.1 µF bypass capacitor across the VSS line and the VCC line as follows:
• Connect a bypass capacitor across the VSS pin and the VCC pin at equal length.
• Connect a bypass capacitor across the VSS pin and the VCC pin with the shortest possible wiring.
• Use lines with a larger diameter than other signal lines for VSS line and VCC line.
• Connect the power source wiring via a bypass capacitor to the VSS pin and the VCC pin. Fig. 63 Wiring for the RESET pin ➁ Wiring for clock input/output pins
• Make the length of wiring which is connected to clock I/O pins as short as possible.
• Make the length of wiring (within 20 mm) across the grounding lead of a capacitor which is connected to an oscillator and the VSS pin of a microcomputer as short as possible.
• Separate the VSS pattern only for oscillation from other VSS patterns.
• Reason If noise enters clock I/O pins, clock waveforms may be de- formed. This may cause a program failure or program runaway. Also, if a potential difference is caused by the noise between the V SS level of a microcomputer and the VSS level of an oscil- lator, the correct clock will not be input in the microcomputer. Fig. 65 Bypass capacitor across the VSS line and the VCC line RESETReset circuit Noise VSSVSS Reset circuit VSS RESET VSS N.G. O.K. Noise XIN XOUT VSS XIN XOUT VSS N.G. O.K. VSS VCC /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines VSS VCC /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines N.G. O.K.

Rev.2.00 May. 24, 2006 page 59 of 90 REJ03B0028-0200 (3) Oscillator concerns In order to obtain the stabilized operation clock on the user system and its condition, contact the oscillator manufacturer and select the oscillator and oscillation circuit constants. Be careful espe- cially when range of voltage or/and temperature is wide. Also, take care to prevent an oscillator that generates clocks for a microcomputer operation from being affected by other signals. ➀ Keeping oscillator away from large current signal lines Install a microcomputer (and especially an oscillator) as far as possible from signal lines where a current larger than the toler- ance of current value flows.

• Reason In the system using a microcomputer, there are signal lines for controlling motors, LEDs, and thermal heads or others. When a large current flows through those signal lines, strong noise oc- curs because of mutual inductance. ➁ Installing oscillator away from signal lines where potential levels change frequently Install an oscillator and a connecting pattern of an oscillator away from signal lines where potential levels change frequently. Also, do not cross such signal lines over the clock lines or the signal lines which are sensitive to noise.
• Reason Signal lines where potential levels change frequently (such as the CNTR pin signal line) may affect other lines at signal rising edge or falling edge. If such lines cross over a clock line, clock waveforms may be deformed, which causes a microcomputer failure or a program runaway. ➀ Keeping oscillator away from large current signal lines ➁ Installing oscillator away from signal lines where potential levels change frequently Fig. 66 Wiring for a large current signal line/Wiring of signal lines where potential levels change frequently (4) Analog input The analog input pin is connected to the capacitor of a compara- tor. Accordingly, sufficient accuracy may not be obtained by the charge/discharge current at the time of A/D conversion when the analog signal source of high-impedance is connected to an analog input pin. In order to obtain the A/D conversion result stabilized more, please lower the impedance of an analog signal source, or add the smoothing capacitor to an analog input pin. (5) Difference of memory type and size When Mask ROM and PROM version and memory size differ in one group, actual values such as an electrical characteristics, A/D conversion accuracy, and the amount of proof of noise incorrect operation may differ from the ideal values. When these products are used switching, perform system evalua- tion for each product of every after confirming product specification. XI N XO U T VS S M i c r o c o m p u t e r M u t u a l i n d u c t a n c e L a r g e c u r r e n t G N D M XI N XO U T VS S C N T RD o n o t c r o s s N . G .

Rev.2.00 May. 24, 2006 page 60 of 90 REJ03B0028-0200 When the power source voltage value of a microcomputer is less than the value which is indicated as the recommended operating conditions, the microcomputer does not operate normally and may perform unstable operation. In a system where the power source voltage drops slowly when the power source voltage drops or the power supply is turned off, reset a microcomputer when the power source voltage is less than the recommended operating conditions and design a system not to cause errors to the system by this unstable operation. ROM ORDERING METHOD 1.Mask ROM Order Confirmation Form 2.Mark Specification Form 3.Data to be written to ROM, in EPROM form (three identical cop- ies) or one floppy disk.

• For the mask ROM confirmation and the mark specifications, refer to the “Renesas Technology Corp.” Homepage (http://www.renesas.com/en/rom)

Rev.2.00 May. 24, 2006 page 61 of 90 REJ03B0028-0200

ELECTRICAL CHARACTERISTICS

Table 12 Absolute maximum ratings RECOMMENDED OPERATING CONDITIONS Table 13 Recommended operating conditions (1) (VCC = 1.8 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted) Power source voltage Power source voltage A/D, D/A conversion reference voltage Analog power source voltage Analog input voltage AN 0–AN 7 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 2.1 V CC VCC VCC VSS VLI VREF AV SS VIA Symbol Parameter Limits Min. V V V V V V V V V V V V V V Unit 4.5 4.0 3.0 2.0 3.0 2.0 1.8 1.8 0.15 ✕ f+1.3 1.3 2.0 AV SS 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 1.8 Typ. Max. Power source voltage (Note 1) VO VO VO Pd Topr Tstg –0.3 to 6.5 VPower source voltage Input voltage P0 0–P07, P10–P1 7, P20–P27, P40–P47, P50–P5 7, P60–P67 Input voltage P70–P77 Input voltage VL1 Input voltage VL2 Input voltage VL3 Input voltage C1, C2 Input voltage RESET, XIN Output voltage C1, C2 VCC VI Symbol Parameter Conditions Ratings Unit All voltages are based on VSS . When an input voltage is mea- sured, output transistors are cut off. VI VI VI VI VI VI VO VO VO Output voltage P00–P07, P10–P15, P30–P3 7 Output voltage P16, P17, P20–P2 7, P40–P4 7, P50–P57, P60–P6 7, P71–P77 Output voltage VL3 Output voltage VL2, SEG0–SEG 17 Output voltage XOUT Power dissipation Operating temperature Storage temperature At output port At segment output Ta = 25°C –0.3 to VCC +0.3 –0.3 to VCC +0.3 –0.3 to VL2 VL1 to VL3 VL2 to 6.5 –0.3 to 6.5 –0.3 to VCC +0.3 –0.3 to 6.5 –0.3 to VCC –0.3 to VL3 –0.3 to VCC +0.3 –0.3 to 6.5 –0.3 to VL3 –0.3 to VCC +0.3 300 –20 to 85 –40 to 125 V V V V V V V V V V V V V V mW High-speed mode Middle-speed mode Low-speed mode At start oscillating (Note 2) At using voltage multiplier f(X IN) = 10 MHz f(XIN) = 8 MHz f(XIN) = 6 MHz f(XIN) = 4 MHz f(XIN) = 10 MHz f(XIN) = 8 MHz f(XIN) = 6 MHz Notes 1: When using the A/D or D/A converter, refer to “A/D Converter Characteristics” or “D/A Converter characteristics”. 2: The oscillation start voltage and the oscillation start time differ in accordance with an oscillator, a circuit constant, or temperature, etc. When power suppl voltage is low and high frequency oscillator is used, an oscillation start will require sufficient conditions. f: This is an oscillator’s oscillation frequency. For example, when oscillation frequency is 8 MHz, substitute “8”.

Rev.2.00 May. 24, 2006 page 62 of 90 REJ03B0028-0200 V V “H” input voltage P0 0–P07, P10–P1 7, P40, P43, P45, P47, P50–P5 3, P56, P61, P64–P6 7, P71–P7 7 “H” input voltage P2 0–P27, P41, P42, P44, P46, P54, P55, P57, P60, P62, P63, P70 RESET XIN “L” input voltage P0 0–P07, P10–P1 7, P40, P43, P45, P47, P50–P5 3, P56, P61, P64–P6 7, P71–P7 7 “L” input voltage P2 0–P27, P41, P42, P44, P46, P54, P55, P57, P60, P62, P63, P70 RESET XIN Table 14 Recommended operating conditions (2) (VCC = 1.8 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted) Symbol Parameter Limits Min. UnitTyp. Max. “H” input voltage “H” input voltage VIH VIH VIH VIH VIL VIL VIL VIL “L” input voltage “L” input voltage

0.7 VCC

0.8 VCC

0.3 VCC

0.2 VCC

V V V V V V P00–P0 7, P10–P1 7, P20–P2 7, P30–P3 7 (Note 1) P41–P4 7, P50–P5 7, P60–P67 (Note 1) P00–P0 7, P10–P1 7, P20–P2 7, P30–P3 7 (Note 1) P41–P4 7, P50–P5 7, P60–P67 (Note 1) P40, P71–P7 7 (Note 1) P00–P0 7, P10–P1 7, P20–P2 7, P30–P3 7 (Note 1) P41–P4 7, P50–P5 7, P60–P67 (Note 1) P00–P0 7, P10–P1 7, P20–P2 7, P30–P3 7 (Note 1) P41–P4 7, P50–P5 7, P60–P67 (Note 1) P40, P71–P7 7 (Note 1) P00–P0 7, P10–P1 5, P30–P37 (Note 2) “H” peak output current P1 6, P17, P20–P2 7, P41–P47, P50–P5 7, P60–P67 (Note 2) 0–P0 7, P10–P1 5, P30–P37 (Note 2) “L” peak output current P1 6, P17, P20–P2 7, P41–P47, P50–P5 7, P60–P67 (Note 2) 0, P71–P7 7 (Note 2) P00–P0 7, P10–P1 5, P30–P37 (Note 3) P16, P17, P20–P2 7, P41–P47, P50–P5 7, P60–P67 (Note 3) 0–P0 7, P10–P1 5, P30–P37 (Note 3) “L” average output current P1 6, P17, P20–P2 7, P41–P47, P50–P5 7, P60–P67 (Note 3) 0, P71–P7 7 (Note 3) –20 –20 –10 –10 –1.0 Table 15 Recommended operating conditions (3) (V CC = 1.8 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted) Notes1: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured over 100 ms. The total peak current is the peak value of all the currents. 2:The peak output current is the peak current flowing in each port. 3:The average output current is an average value measured over 100 ms. “H” total peak output current “H” total peak output current “L” total peak output current “L” total peak output current “L” total peak output current “H” total average output current “H” total average output current “L” total average output current “L” total average output current “L” total average output current ΣIOH(peak) ΣIOH(peak) ΣIOL(peak) ΣIOL(peak) ΣIOL(peak) ΣIOH(avg) ΣIOH(avg) ΣIOL(avg) ΣIOL(avg) ΣIOL(avg) IOH(peak) Symbol Parameter Limits Min. mA mA mA mA mA mA mA mA mA mA mA Unit Typ. Max. “H” peak output current “L” peak output current “L” peak output current “H” average output current “H” average output current “L” average output current “L” average output current I OH(peak) IOL(peak) IOL(peak) IOL(peak) IOH(avg) IOH(avg) IOL(avg) IOL(avg) –5.0 5.0 –0.5 –2.5 2.5 5.0 mA mA mA mA mA mA mA mA I OL(avg) mA10

Rev.2.00 May. 24, 2006 page 63 of 90 REJ03B0028-0200 Table 16 Recommended operating conditions (4) (VCC = 1.8 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted) Input frequency for timers X and Y (duty cycle 50%) f(CNTR0) f(CNTR1) Symbol Parameter Limits Min. MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz kHz Unit Typ. Max. (VCC < 2.0 V) High-speed mode High-speed mode High-speed mode Middle-speed mode (Note 3) Middle-speed mode (Note 3) Middle-speed mode (Note 3) 32.768 5.0 2✕ VCC –4 VCC 5✕ VCC –8 10.0 4✕ VCC –8 2✕ VCC 10.0 8.0 6.0 Main clock input oscillation frequency (Note 1) Sub-clock input oscillation frequency (At duty 50 %) (Notes 2, 3) f(X IN) f(XCIN) Test conditions Notes 1: When using the A/D or D/A converter, refer to “A/D Converter Characteristics” or “D/A Converter characteristics”. 2: When using the microcomputer in low-speed mode, set the clock input oscillation frequency on condition that f(XCIN) < f(XIN)/3. 3: The oscillation start voltage and the oscillation start time differ in accordance with an oscillator, a circuit constant, or temperature, etc. When power suppl voltage is low and high frequency oscillator is used, an oscillation start will require sufficient conditions.

Rev.2.00 May. 24, 2006 page 64 of 90 REJ03B0028-0200 IOL = 10 mA IOL = 3.0 mA IOL = 2.5 mA VCC = 2.2 V IOL = 5 mA IOL = 1.5 mA IOL = 1.25 mA VCC = 2.2 V VOL IOH = –1 mA IOH = –0.25 mA VCC = 2.2 V IOH = –5 mA IOH = –1.5 mA IOH = –1.25 mA VCC = 2.2 V VVCC –2.0“H” output voltage P00–P0 7, P10–P1 5, P30–P3 7 Symbol Parameter Limits Min. Unit 0.5 Typ. Max.Test conditions VOH 2.0 0.5 Table 17 Electrical characteristics (1) (VCC =4.0 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted) IOL = 10 mA IOL = 5 mA VCC = 2.2 V VCC = 2.0 V to 5.0 V VI = VCC VI = VCC VI = VCC VI = VSS Pull-ups “off” V CC = 5 V, VI = VSS Pull-ups “on” V CC = 2.2 V, VI = VSS Pull-ups “on” VI = VSS VI = VSS VCC = 5.0 V, VO = VCC , Pullup ON Output transistors “off” VCC = 2.2 V,VO = VCC , Pullup ON Output transistors “off” VO = VCC , Pullup OFF Output transistors “off” VO = VSS , Pullup OFF Output transistors “off” “H” output voltage P16, P17, P20–P2 7, P41–P4 7, P50–P5 7, P60–P6 7 “L” output voltage P00–P0 7, P10–P1 5, P30–P3 7 “L” output voltage P16, P17, P20–P2 7, P41–P4 7, P50–P5 7, P60–P6 7 “L” output voltage P40, P71–P7 7 Hysteresis INT0–INT2, ADT, CNTR0, CNTR 1, P20–P27 Hysteresis S CLK , RXD, SIN2 Hysteresis RESET “H” input current P00–P0 7, P10–P1 7, P20–P2 7, P40–P4 7, P50–P5 7, P60–P6 7, P70–P7 7 “H” input current RESET “H” input current XIN “L” input current P00–P07,P10–P1 7, P20–P27,P41–P4 7, P50–P5 7, P60–P6 7 “L” input current P40, P70–P7 7 “L” input current RESET “L” input current XIN Output load current P30–P3 7 VOH VOL VOL VT+ – VT– VT+ – VT– VT+ – VT– IIH IIH IIH ILOAD VCC –2.0 VCC –0.5 –60.0 –5.0 0.5 0.5 4.0 –120.0 –20.0 –4.0 2.0 0.5 0.5 5.0 5.0 –5.0 –240.0 –40.0 –5.0 –5.0 –240.0 –40.0 V V V V V V V V V V µA µA µA µA µA µA µA µA IIL VCC –0.8 VCC –0.8 V V V0.8 V0.8 0.3 V µA µA µA Output leak current P30–P3 7 ILEAK 5.0 –5.0 µA µA –120.0 –20.0 –60.0 –5.0

Rev.2.00 May. 24, 2006 page 65 of 90 REJ03B0028-0200 Table 18 Electrical characteristics (2) (VCC = 1.8 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted) V5.5

• High-speed mode, VCC = 5 V f(XIN) = 10 MHz f(XCIN) = 32.768 kHz Output transistors “off” A/D converter in operating
• High-speed mode, V CC = 5 V f(XIN) = 8 MHz f(XCIN) = 32.768 kHz Output transistors “off” A/D converter in operating
• High-speed mode, V CC = 5 V f(XIN) = 8 MHz (in WIT state) f(XCIN) = 32.768 kHz Output transistors “off” A/D converter stop
• Low-speed mode, V CC = 5 V, Ta ≤ 55°C f(XIN) = stopped f(XCIN) = 32.768 kHz Output transistors “off”
• Low-speed mode, VCC = 5 V, Ta = 25°C f(XIN) = stopped f(XCIN) = 32.768 kHz (in WIT state) Output transistors “off”
• Low-speed mode, VCC = 3 V, Ta ≤ 55°C f(XIN) = stopped f(XCIN) = 32.768 kHz Output transistors “off”
• Low-speed mode, VCC = 3 V, Ta = 25°C f(XIN) = stopped f(XCIN) = 32.768 kHz (in WIT state) Output transistors “off” All oscillation stopped (in STP state) Output transistors “off” V L1 = 1.8 V Symbol Parameter Limits Min. UnitTyp. Max. Ta = 25 °C Ta = 85 °C Test conditions ICC Power source current 5.5 VRAM RAM retention voltage At clock stop mode 1.8 IL1 Power source current (VL1) (Note) Note:When the voltage multiplier control bit of the LCD mode register (bit 4 at address 003916) is “1”. 4.5 1.2 4.5 9.0 2.4 9.0 1.0 mA mA µA µA µA µA µA mA11.0 µA µA 0.1 4.0

Rev.2.00 May. 24, 2006 page 66 of 90 REJ03B0028-0200 Table 19 A/D converter characteristics (1) (VCC = 2.7 to 5.5 V, VSS = AVSS = 0 V, Ta = –20 to 85°C, f(XIN) = 500 kHz to 10 MHz, in middle/high-speed mode unless otherwise noted) 8-bit A/D mode (when conversion mode selection bit (bit 0 of address 001416) is “1”) Symbol Parameter Limits Min. UnitTyp. Max.Test conditions – Resolution Absolute accuracy (excluding quantization error) VCC = VREF = 2.7 to 5.5 V Bits LSB 150 µSf(XIN) = 8 MHzConversion time Ladder resistor Reference power source input current tCONV R LADDER IVREF kΩ µA µA Table 21 D/A converter characteristics (VCC = 2.7 to 5.5 V, VCC = VREF , VSS = AVSS = 0 V, Ta = –20 to 85°C, in middle/high-speed mode unless otherwise noted) Symbol Parameter Limits Min. UnitTyp. Max.Test conditions – Resolution VCC = VREF = 5 V VCC = VREF = 2.7 V Bits µs kΩ mA 2.5 1.0 2.0 Note:Using one D/A converter, with the value in the DA conversion register of the other D/A converter being “0016”, and excluding currents flowing through the A/D resistance ladder. (Note) Setting time Output resistor tsu R O 4 3.2 Absolute accuracy Analog port input currentIIA IVREF Reference power source input current 100 200 5.0 VREF = 5 V Table 20 A/D converter characteristics (2) (VCC = 2.7 to 5.5 V, VSS = AVSS = 0 V, Ta = –20 to 85°C, f(XIN) = 500 kHz to 10 MHz, in middle/high-speed mode unless otherwise noted) 10-bit A/D mode (when conversion mode selection bit (bit 0 of address 001416) is “0”) 12.5 (Note) Symbol Parameter Limits Min. UnitTyp. Max.Test conditions – Resolution Absolute accuracy (excluding quantization error) VCC = VREF = 2.7 to 5.5 V Bits LSB 150 µSf(XIN) = 8 MHzConversion time Ladder resistor Reference power source input current tCONV R LADDER IVREF kΩ µA Analog port input currentIIA µA 100 200 5.0 VREF = 5 V 15.5 (Note) Note: When the internal trigger is used in the middle-speed mode, the max. value of tCONV is 14 µS. Note: When the internal trigger is used in the middle-speed mode, the max. value of tCONV is 17 µS.

Rev.2.00 May. 24, 2006 page 67 of 90 REJ03B0028-0200 Table 22 Timing requirements (1) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted) 100 1000/(4✕ Vcc-8) 200 1000/(2✕ Vcc-4) 105 105 800 370 370 220 100 1000 400 400 200 200 Note:When bit 6 of address 001A16 is “1”. Divide this value by four when bit 6 of address 001A16 is “0”. Reset input “L” pulse width Main clock input cycle time (XIN input) Main clock input “H” pulse width Main clock input “L” pulse width CNTR 0, CNTR1 input cycle time CNTR 0, CNTR1 input “H” pulse width CNTR 0, CNTR1 input “L” pulse width INT0 to INT3 input “H” pulse width INT0 to INT3 input “L” pulse width Serial I/O1 clock input cycle time (Note) Serial I/O1 clock input “H” pulse width (Note) Serial I/O1 clock input “L” pulse width (Note) Serial I/O1 input set up time Serial I/O1 input hold time Serial I/O2 clock input cycle time Serial I/O2 clock input “H” pulse width Serial I/O2 clock input “L” pulse width Serial I/O2 input set up time Serial I/O2 input hold time tw(RESET) tc(XIN) twH(X IN) twL(XIN) tc(CNTR) twH(CNTR) twL(CNTR) twH(INT) twL(INT) tc(SCLK1 ) twH(S CLK1 ) twL(SCLK1 ) tsu(RXD–S CLK1 ) th(SCLK1 –R XD) tc(SCLK2 ) twH(S CLK2 ) twL(SCLK2 ) tsu(RXD–S CLK2 ) th(SCLK2 –R XD) Symbol Parameter Limits Min. µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit Typ. Max.

Rev.2.00 May. 24, 2006 page 68 of 90 REJ03B0028-0200 Table 23 Timing requirements (2) (VCC = 1.8 to 4.0 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted) 125 1000/(10✕ Vcc-12) 1000/V CC 1000/(5✕ Vcc-8) tc(CNTR)/2–20 tc(CNTR)/2–20 Reset input “L” pulse width Main clock input cycle time (XIN input) Main clock input “H” pulse width Main clock input “L” pulse width CNTR 0, CNTR1 input cycle time CNTR 0, CNTR1 input “H” pulse width CNTR 0, CNTR1 input “L” pulse width INT0 to INT3 input “H” pulse width INT0 to INT3 input “L” pulse width Serial I/O1 clock input cycle time (Note) Serial I/O1 clock input “H” pulse width (Note) Serial I/O1 clock input “L” pulse width (Note) Serial I/O1 input set up time Serial I/O1 input hold time Serial I/O2 clock input cycle time Serial I/O2 clock input “H” pulse width Serial I/O2 clock input “L” pulse width Serial I/O2 input set up time Serial I/O2 input hold time tw(RESET) tc(XIN) twH(X IN) twL(XIN) tc(CNTR) twH(CNTR) twL(CNTR) Symbol Parameter Limits Min. µs ns ns ns ns ns ns ns ns ns ns Unit Typ. Max. Note:When bit 6 of address 001A16 is “1”. Divide this value by four when bit 6 of address 001A16 is “0”. twH(INT) twL(INT) tc(SCLK1 ) twH(S CLK1 ) twL(SCLK1 ) tsu(RXD–S CLK1 ) th(SCLK1 –R X D) tc(SCLK2 ) twH(S CLK2 ) twL(SCLK2 ) tsu(RXD–S CLK2 ) th(SCLK2 –R X D) 230 230 2000 950 950 400 200 2000 950 950 400 200 ns ns ns ns ns ns ns ns ns ns ns ns (VCC < 2.0 V) (VCC < 2.0 V) (VCC < 2.0 V) (VCC < 2.0 V)

Rev.2.00 May. 24, 2006 page 69 of 90 REJ03B0028-0200 Table 24 Switching characteristics (1) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted) Note:When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”. Serial I/O1 clock output “H” pulse width Serial I/O1 clock output “L” pulse width Serial I/O1 output delay time (Note) Serial I/O1 output valid time (Note) Serial I/O1 clock output rising time Serial I/O1 clock output falling time Serial I/O2 clock output “H” pulse width Serial I/O2 clock output “L” pulse width Serial I/O2 output delay time Serial I/O2 output valid time Serial I/O2 clock output falling time 140 0.2 ✕ tC (SCLK2 ) Symbol Parameter Limits Min. ns ns ns ns ns ns ns ns ns ns ns Unit tC (SCLK1 )/2–30 tC (SCLK1 )/2–30 –30 Typ. Max. twH(S CLK1 ) twL(SCLK1 ) td(SCLK1 –TXD) tv(SCLK1 –TXD) tr(SCLK1 ) tf(SCLK1 ) twH(S CLK2 ) twL(SCLK2 ) td(SCLK2 –S OUT2 ) tv(SCLK2 –S OUT2 ) tf(SCLK2 ) Table 25 Switching characteristics (2) (VCC = 1.8 to 4.0 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted) ns ns ns ns ns ns ns ns ns ns ns Unit Note:When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”. Serial I/O1 clock output “H” pulse width Serial I/O1 clock output “L” pulse width Serial I/O1 output delay time (Note) Serial I/O1 output valid time (Note) Serial I/O1 clock output rising time Serial I/O1 clock output falling time Serial I/O2 clock output “H” pulse width Serial I/O2 clock output “L” pulse width Serial I/O2 output delay time Serial I/O2 output valid time Serial I/O2 clock output falling time 350 100 100 0.2 ✕ tC (SCLK2 ) 100 Symbol Parameter Limits Min. tC (SCLK1 )/2–100 tC (SCLK1 )/2–100 –30 Max. twH(S CLK1 ) twL(SCLK1 ) td(SCLK1 –TXD) tv(SCLK1 –TXD) tr(SCLK1 ) tf(SCLK1 ) twH(S CLK2 ) twL(SCLK2 ) td(SCLK2 –S OUT2 ) tv(SCLK2 –S OUT2 ) tf(SCLK2 ) Typ. tC (SCLK2 )/2–160 tC (SCLK2 )/2–160 tC (SCLK2 )/2–240 tC (SCLK2 )/2–240 Fig. 65 Circuit for measuring output switching characteristics M e a s u r e m e n t o u t p u t p i n 1 0 0 p F C M O S o u t p u t N o t e : W h e n P 71– P 77, P 40 a n d b i t 4 o f t h e U A R T c o n t r o l r e g i s t e r a d d r e s s i s N c h a n n e l o p e n d r a i n o u t p u t m o d e N - c h a n n e l o p e n - d r a i n o u t p u t ( N o t e ) 1 kΩ 1 0 0 p F M e a s u r e m e n t o u t p u t p i n

Rev.2.00 May. 24, 2006 page 70 of 90 REJ03B0028-0200 Fig. 66 Timing diagram I N N C N T R 0, C N T R 1 VC C tW L I N T VC C tW H I N T VC C VC C VC C VC C VC C tW L XI N ) VC C tW H XI N tC XI N ) XI N VC C VC C tW R E S E T R E S E T tf tr VC C tW L C N T R VC C tW H C N T R tC C N T R td SC L K TXD td SC L K -SO U T tv SC L K TXD tv SC L K -SO U T tC SC L K tC SC L K tW L SC L K tW L SC L K 2) tW H SC L K tW H SC L K t SC L K -R XD th( SC L K -SI N 2 ts u R XD -SC L K ts u SI N -SC L K TXD SO U T R XD SI N SC L K SC L K

Rev.2.00 May. 24, 2006 page 71 of 90 REJ03B0028-0200 c DO NOT INCLUDE MOLD FLASH. NOTE) DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. y Index mark x 12 5 5175 100 F ZE ZD E D HD HE bp Detail F A2A1 L A c ZE ZD bp HE HD y 0.08 e 0.5 c 0° 8° x L 0.35 0.5 0.65 0.05 0.1 0.15 A 1.7 15.8 16.0 16.2 15.8 16.0 16.2 A2 1.4 E 13.9 14.0 14.1 D 13.9 14.0 14.1 Reference Symbol Dimension in Millimeters Min Nom Max 0.15 0.20 0.25 0.09 0.145 0.20 0.08 1.0 1.0 0.18 0.125 1.0 Previous CodeJEITA Package Code RENESAS Code PLQP0100KB-A 100P6Q-A / FP-100U / FP-100UV MASS[Typ.] 0.6gP-LQFP100-14x14-0.50 e Previous CodeJEITA Package Code RENESAS Code PLQP0100JB-A 100P6K-A MASS[Typ.] 1.2gP-HLQFP100-14x20-0.65 9.0 0.13 0.1750.1250.105 0.370.320.27 MaxNomMin Dimension in Millimeters Symbol Reference 20.120.019.9D 14.114.013.9E 1.4A2 22.222.021.8 16.216.015.8 1.7A 0.20.1250.05 0.650.50.35L x 8°0° c 0.65e 0.10y HD HE bp D2 15.0 INCLUDE TRIM OFFSET. DIMENSION "*3" DOES NOT NOTE) DO NOT INCLUDE MOLD FLASH. 5081 100 F 51 80 100 130 x 5180 y Index mark1 bp HE E HD D A c Detail F A2A1 Le

Rev.2.00 May. 24, 2006 page 72 of 90 REJ03B0028-0200 Fig. 3.3.1 Initialization of processor status register ➁ How to reference the processor status register To reference the contents of the processor status register (PS), execute the PHP instruction once then read the contents of (S+1). If necessary, execute the PLP instruction to return the PS to its original status.

3.3 Notes on use

3.3.1 Notes on programming

(1) Processor status register ➀ Initializing of processor status register Flags which affect program execution must be initialized after a reset. In particular, it is essential to initialize the T and D flags because they have an important effect on calculations.

• Reason After a reset, the contents of the processor status register (PS) are undefined except for the I flag which is “1”. Fig. 3.3.3 Stack memory contents after PHP instruction execution Reset Initializing of flags Main program S S 1 S t o r e d P S

Rev.2.00 May. 24, 2006 page 73 of 90 REJ03B0028-0200 (2) Decimal calculations ■ Execution of decimal calculations The ADC and SBC are the only instructions which will yield proper decimal notation, set the decimal mode flag (D) to “1” with the SED instruction. After executing the ADC or SBC instruction, execute another instruction before executing the SEC , CLC , or CLD instruction. ■ Notes on status flag in decimal mode When decimal mode is selected, the values of three of the flags in the status register (the N, V, and Z flags) are invalid after a ADC or SBC instruction is executed. The carry flag (C) is set to “1” if a carry is generated as a result of the calculation, or is cleared to “0” if a borrow is generated. To determine whether a calculation has generated a carry, the C flag must be initialized to “0” before each calculation. To check for a borrow, the C flag must be initialized to “1” before each calculation. (3) Multiplication and Division Instructions

• The index X mode (T) and the decimal mode (D) flags do not affect the MUL and DIV instruction.
• The execution of these instructions does not change the contents of the processor status register. (4) JMP instruction When using the JMP instruction in indirect addressing mode, do not specify the last address on a page as an indirect address. (5) BRK instruction When the BRK instruction is executed with the following conditions satisfied, the interrupt execution is started from the address of interrupt vector which has the highest priority.
• Interrupt request bit and interrupt enable bit are set to “1”.
• Interrupt disable flag (I) is set to “1” to disable interrupt. Set D flag to “1” ADC or SBC instruction NOP instruction SEC , CLC , or CLD instruction Fig. 3.3.4 Status flag at decimal calculations

Rev.2.00 May. 24, 2006 page 74 of 90 REJ03B0028-0200 (6) Read-modify-write instruction Do not execute a read-modify-write instruction to the read invalid address (memory and SFR). The read-modify-write instruction operates in the following sequence: read one-byte of data from memory, modify the data, write the data back to original memory. The following instructions are classified as the read-modify-write instructions in the 740 Family.

• Bit management instructions: CLB, SEB
• Shift and rotate instructions: ASL, LSR, ROL, ROR, RRF
• Add and subtract instructions: DEC, INC
• Logical operation instructions (1’s complement): COM Add and subtract/logical operation instructions (ADC, SBC, AND, EOR, and ORA) when T flag = “1” operate in the way as the read-modify-write instruction. Do not execute the read invalid memory and SFR. [Reason] When the read-modify-write instruction is executed to read invalid memory and SFR, the instruction may cause the following consequence: the instruction reads unspecified data from the memory due to the read invalid condition. Then the instruction modifies this unspecified data and writes the data to the memory. The result will be random data written to the memory or some unexpected event. (7) Instruction execution time Each instruction execution time is obtained from the cycle time of system clock φ multiplied by the number of instruction cycles listed in the machine instruction table. Note that the cycle time of system clock φ is defined by the system clock division ratio selection bit and the system clock selection bit.

Rev.2.00 May. 24, 2006 page 75 of 90 REJ03B0028-0200

3.3.2 Notes on I/O port

(1) Modifying output data with bit managing instruction When the port latch of an I/O port is modified with the bit managing instruction (Note), the value of the unspecified bit may be changed.

• Reason I/O ports can be set to input or output mode in a bit unit. When reading or writing are performed to the port Pi (i = 0–7) register, the microcomputer operates as follows.
• Port in input mode -Read-access: reads pin’s level (The contents of port latch and pin’s level are unrelated.) -Write-access: writes data to port latch (The contents of port latch and pin’s level are unrelated.)
• Port in output mode -Read-access: reads port latch (The contents of port latch and pin’s level are unrelated.) -Write-access: writes data to port latch (The contents of port latch are output from the pin.) The bit managing instructions are read-modify-write form instructions (refer to “3.3.1 Notes on programming (6)”) for reading and writing data by a byte unit. Therefore, when the bit managing instructions are executed to the port set to input mode, the instruction read the pin’s states, modify the specification bit, and then write data to the port latch. At this time, if the contents of the original port latch are different from the pins’s level, the contents of the port latch of bit which is not specified by instruction will change. In addition to this, if the bit managing instructions are executed to the port Pi register in order to setting output data when port Pi is configured as a mixed input and output port, the contents of the port latch of bit in the input mode which is not specified by instruction may change. Note: Bit managing instructions: SEB instruction, CLB instruction (2) The port direction registers are write-only registers. Therefore, the following instructions cannot be used to this register:
• LDA instruction
• Memory operation instruction when T flag is “1”
• Instructions operating in addressing mode that modifies direction register
• Bit test instructions such as BBC and BBS
• Bit modification instructions such as CLB and SEB
• Arithmetic instructions using read-modify-write form instructions such as ROR The LDM, STA instructions etc. are used for setting of the direction register. (3) Pull-up Operation When using each port which built in pull-up resistor as an output port, the pull-up control bit of corresponding port becomes invalid, and pull-up resistor is not connected.
• Reason Pull-up control is effective only when each direction register is set to the input mode.

Rev.2.00 May. 24, 2006 page 76 of 90 REJ03B0028-0200

3.3.3 Termination of unused pins

(1) Terminate unused pins Perform the following wiring at the shortest possible distance (20 mm or less) from microcomputer pins. ➀ Output ports Open them. ➁ Input ports Connect each pin to V CC or VSS through each resistor of 1 kΩ to 10 kΩ . A for pins whose potential affects to operation modes such as the INTi pin or others, select the V CC pin or the VSS pin according to their operation mode. ➂ I/O ports Set the I/O ports for the input mode and connect each pin to VCC or VSS through each resistor of 1 kΩ to 10 kΩ . The port which can select a built-in pull-up resistor can also use the built- in pull-up resistor. When using the I/O ports as the output mode, open them at “L” or “H”.

• When opening them in the output mode, the input mode of the initial status remains until the mode of the ports is switched over to the output mode by the program after reset. Thus, the potential at these pins is undefined and the power source current may increase in the input mode. With regard to an effects on the system, thoroughly perform system evaluation on the user side.
• Since the direction register setup may be changed because of a program runaway or noise, set direction registers by program periodically to increase the reliability of program. (2) Termination remarks ■ Input ports Do not open them.
• Reason
• The power source current may increase depending on the first-stage circuit.
• An effect due to noise may be easily produced as compared with proper termination ➁ shown on the above. ■ I/0 ports setting as input mode [1] Do not open in the input mode.
• Reason
• The power source current may increase depending on the first-stage circuit.
• An effect due to noise may be easily produced as compared with proper termination ➂ shown on the above. [2] I/O ports : Do not connect to V CC or VSS directly.
• Reason If the direction register setup changes for the output mode because of a program runaway or noise, a short circuit may occur. [3] I/O ports : Do not connect multiple ports in a lump to VCC or VSS through a resistor.
• Reason If the direction register setup changes for the output mode because of a program runaway or noise, a short circuit may occur between ports.

Rev.2.00 May. 24, 2006 page 77 of 90 REJ03B0028-0200

3.3.4 Notes on interrupts

(1) Unused interrupts Set the interrupt enable bit for unused interrupts to “0” (disabled). (2) Change of relevant register settings When setting the followings, the interrupt request bit may be set to “1”.

• When switching external interrupt active edge Related register: •Interrupt edge selection register (address 3A 16)
• Timer X mode register (address 2716)
• Timer Y mode register (address 2816)
• When switching interrupt sources of an interrupt vector address where two or more interrupt sources are allocated Related register:•Interrupt source selection bit of AD control register (bit 6 of address 3416) When not requiring for the interrupt occurrence synchronous with these setting, take the following sequence. Fig. 3.3.5 Sequence of changing relevant register ■ Reason When setting the followings, the interrupt request bit of the corresponding interrupt may be set to “1”.
• When switching external interrupt active edge Concerned register: INT0 interrupt edge selection bit (bit 0 of Interrupt edge selection register (address 3A16)) INT1 interrupt edge selection bit (bit 1 of Interrupt edge selection register (address 3A16)) INT2 interrupt edge selection bit (bit 2 of Interrupt edge selection register (address 3A16)) CNTR 0 active edge switch bit (bit 6 of timer X mode register (address 2716)) CNTR 1 active edge switch bit (bit 6 of timer Y mode register (address 2816))
• When switching interrupt sources of an interrupt vector address where two or more interrupt sources are allocated. Concerned register: Interrupt source selection bit (bit 6 of AD control register (address 3416)) Set the corresponding interrupt enable bit to “0” (disabled) . Set the interrupt edge select bit, active edge switch bit, or the interrupt source select bit. NOP (One or more instructions) Set the corresponding interrupt request bit to “0” (no interrupt request issued). Set the corresponding interrupt enable bit to “1” (enabled).

Rev.2.00 May. 24, 2006 page 78 of 90 REJ03B0028-0200 Set the interrupt request bit to “0” (no interrupt issued) NOP (one or more instructions) Execute the BBC or BBS instruction Fig. 3.3.6 Sequence of check of interrupt request bit ■ Reason If the BBC or BBS instruction is executed immediately after an interrupt request bit of an interrupt request register is cleared to “0”, the value of the interrupt request bit before being cleared to “0” is read. (3) Check of interrupt request bit When executing the BBC or BBS instruction to an interrupt request bit of an interrupt request register immediately after this bit is set to “0”, take the following sequence.

Rev.2.00 May. 24, 2006 page 79 of 90 REJ03B0028-0200

3.3.5 Notes on timer

This clause describes notes for the various operation modes of Timer X, Timer Y, Timer 1, Timer 2, and Timer 3. (1) Timer X ■ For all modes ◆ When reading and writing to the timer X high-order and low-order registers, be sure to read/write both the timer X high- and low-order registers. When reading the timer X high-order and low-order registers, read the high-order register first. When writing to the timer X high-order and low-order registers, write the low-order register first. The timer X cannot perform the correct operation if the next operation is performed.

• Write operation to the high- or low-order register before reading the timer X low-order register
• Read operation from the high- or low-order register before writing to the timer X high-order register ◆ When the operation “writing data only to the latch” is selected by the timer X write control bit (bit 0 of timer X mode register (address 27 16)) is selected, a value is simultaneously set to the timer X and the timer X latch if the writing in the high-order register and the underflow of timer X are performed at the same timing. Unexpected value may be set in the high-order timer on this occasion. ■ Pulse output mode ◆ When reading port P5 4 (bit 4 of port P5 register (address 0A16)) in the pulse output mode, the pin state is read instead of the contents of the port latch. ■ Real time port function ◆ After reset is released, the port P5 direction register is set as the input mode and ports P50–P5 7 functions as regular ports. To use as the RTP function pin, set the corresponding bit of the port P5 direction register to the output mode. ■ CNTR 0 active edge selection ◆ The CNTR 0 active edge selection bit (bit 6 of timer X mode register) also effects the active edge of the generation of the CNTR0 interrupt request. (2) Timer Y ■ For all modes ◆ When reading and writing to the timer Y high-order and low-order registers, be sure to read/write both the timer Y high- and low-order registers. When reading the timer Y high-order and low-order registers, read the high-order register first. When writing to the timer Y high-order and low-order registers, write the low-order register first. The timer Y cannot perform the correct operation if the next operation is performed.
• Write operation to the high- or low-order register before reading the timer Y low-order register
• Read operation from the high- or low-order register before writing to the timer Y high-order register ■ CNTR 1 active edge selection ◆ The CNTR 1 active edge selection bit (bit 6 of timer Y mode register (address 2816)) also effects the active edge of the generation of the CNTR1 interrupt request. However, both edges are valid for the request generation regardless of the bit state in the continuous HL pulse-width measurement mode.

Rev.2.00 May. 24, 2006 page 80 of 90 REJ03B0028-0200 (3) Timers 1–3 Set the value of timer in the order of the timer 1 register, the timer 2 register, and the timer 3 register after the count source selection of timer 1 to 3. <Reason>

• When the count source of timers 1 to 3 is changed, the timer counting value may become arbitrary value because a thin pulse is generated in count input of timer.
• If timer 1 output is selected as the count source of timer 2 or timer 3, when timer 1 is written, the counting value of timer 2 or timer 3 may become undefined value because a thin pulse is generated in timer 1 output. (4) Timer 2 If the value is written in latch only, a value is simultaneously set to the timer 2 and the timer 2 latch when the writing in the high-order register and the underflow of timer 2 are performed at the same timing. (5) All timers ■ The count source for timers is effected by system clock φ which is selected by the system clock selection bit (bit 7 of CPU mode register (address 3B16)). ■ Set the timer which is not used as follows:
• Stop the count (when using a timer with stop control)
• Set “0” to the corresponding interrupt enable bit

Rev.2.00 May. 24, 2006 page 81 of 90 REJ03B0028-0200

3.3.6 Notes on serial I/O1

(1) Writing to baud rate generator (BRG) Write data to BRG while the transmission and reception operations are stopped. (2) Setting procedure when using serial I/O1 transmit interrupt When the serial I/O1 transmit interrupt is used, take the following sequence. ➀ Set the serial I/O1 transmit interrupt enable bit (bit 3 of interrupt control register 1 (address 3E 16)) to “0” (disabled). ➁ Set the transmit enable bit (bit 4 of serial I/O1 control register (address 1A16)) to “1”. ➂ Set the serial I/O1 transmit interrupt request bit (bit 3 of interrupt request register 1 (address 3C 16)) to “0” (no interrupt request issued) after 1 or more instruction has executed. ➃ Set the serial I/O1 transmit interrupt enable bit to “1” (enabled). <Reason> When the transmission enable bit is set to “1”, the transmit buffer empty flag (bit 0 of serial I/O1 status register (address 1916)) and the transmit shift register completion flag (bit 2 of serial I/O1 status register) are set to “1”. Therefore, the serial I/O1 transmit interrupt request bit is set to “1” regardless of the state of the transmit interrupt source selection bit (bit 3 of serial I/O1 control register). (3) Data transmission control with referring to transmit shift register completion flag After the transmit data is written to the transmit buffer register (address 1816), the transmit shift register completion flag changes from “1” to “0” with a delay of 0.5 to 1.5 shift clocks. When data transmission is controlled with referring to the flag after writing the data to the transmit buffer register, note the delay. (4) Setting serial I/O1 control register again Set the serial I/O1 control register again after the transmission and the reception circuits are reset by setting both the transmit enable bit and the receive enable bit to “0”. Fig. 3.3.7 Sequence of setting serial I/O1 control register again Set both the transmit enable bit (TE) and the receive enable bit (RE) to “0” Set the bits 0 to 3 and bit 6 of the serial I/O1 control register Set both the transmit enable bit (TE) and the receive enable bit (RE), or one of them to “1” Can be set with the LDM instruction at the same time

Rev.2.00 May. 24, 2006 page 82 of 90 REJ03B0028-0200 (5) Pin state after transmit completion The TxD pin holds the state of the last bit of the transmission after transmission completion. When the internal clock is selected for the transmit clock in the clock synchronous serial I/O mode, the S CLK1 pin holds “H”. (6) Serial I/O1 enable bit during transmit operation When the serial I/O1 enable bit (bit 7 of serial I/O1 control register) is set to “0” (serial I/O1 disabled) when data transmission is in progress, the transmission progress internally. However, the external data transfer is terminated because the pins become regular I/O ports. In addition to this, when data is written to the transmission buffer register, data transmission is started internally. When the serial I/O1 enable bit is set to “1”, the transmission is output to the TxD pin in the middle of the transfer. (7) Transmission control when external clock is selected When an external clock is used as the synchronous clock for data transmission, set the transmit enable bit to “1” at “H” of the S CLK1 input level. Also, write the transmit data to the transmit buffer register at “H” of the SCLK1 input level. (8) Receive operation in clock synchronous serial I/O mode When receiving data in the clock synchronous serial I/O mode, set not only the receive enable bit but also the transmit enable bit to “1”. Then write dummy data to the transmission buffer register. When the internal clock is selected as the synchronous clock, the synchronous clock is output at this point and the receive operation is started. When the external clock is selected as the transfer clock, the serial I/O becomes ready for data receive at this point and, when the external clock is input to the clock input pin, the receive operation is started. The P4 5/TxD pin outputs the dummy data written in the transmission buffer register. (9) Transmit and receive operation in clock synchronous serial I/O mode When stopping transmitting and receiving operations in the clock synchronous serial I/O mode, set the receive enable bit and the transmit enable bit to “0” simultaneously. If only one of them is stopped the receive or transmit operation may loose synchronization, causing a bit slippage.

3.3.7 Notes on serial I/O2

(1) Switching synchronous clock When switching the synchronous clock by the serial I/O2 synchronous clock selection bit (bit 6 of serial I/O2 control register (address 1D 16)), initialize the serial I/O2 counter (write data to serial I/ O2 register (address 1F16)). (2) Notes when selecting external clock When an external clock is selected as the synchronous clock, the SOUT2 pin holds the output level of D7 after transmission is completed. However, if the clock is input to the serial I/O continuously, the serial I/O2 register continue the shift operation and output data from the SOUT2 pin continuously. A write operation to the serial I/O2 register must be performed when the SCLK21 pin is “H”. When the internal clock is selected as the synchronous clock, the SOUT2 pin holds the high- impedance state after transmission.

Rev.2.00 May. 24, 2006 page 83 of 90 REJ03B0028-0200

3.3.8 Notes on PWM output circuit

• “L” level output before starting PWM output When at least one of two is set to “1” when both the PWM0 function enable bit and the PWM1 function enable bit are “0”, “L” level is output from the corresponding PWM pin during the period shown below. Then, PWM output is started from “H” level.
• Count source selection bit = “0”, where n is the value set in the prescaler sec.
• Count source selection bit = “1”, where n is the value set in the prescaler sec. n + 1 2 • f(XIN) n + 1 f(XIN)
• Change of PWM output When the PWM prescaler and the PWM register are changed during PWM output, the PWM waveforms corresponding to updated data will be output from the next repetitive cycle. Figure 3.3.8 shows the change of PWM output. Fig. 3.3.8 Change of PWM output PWM output Changes PWM prescaler and PWM register From the next repetitive cycle, output modified waveform

Rev.2.00 May. 24, 2006 page 84 of 90 REJ03B0028-0200

3.3.9 Notes on A/D converter

(1) Analog input pin Make the signal source impedance for analog input low, or equip an analog input pin with an external capacitor of 0.01 µF to 1 µF. Further, be sure to verify the operation of application products on the user side.

• Reason An analog input pin includes the capacitor for analog voltage comparison. Accordingly, when signals from signal source with high impedance are input to an analog input pin, charge and discharge noise generates. This may cause the A/D conversion precision to be worse. (2) Analog power source input pin AVss The AV SS pin is an analog power source input pin. Regardless of using the A/D conversion function or not, connect it as following :
• AV SS : Connect to the VSS line
• Reason If the AVSS pin is opened, the microcomputer may have a failure because of noise or others. (3) Reference voltage input pin VREF Connect an approximately 1000 pF capacitor across the AVss pin and the VREF pin. Besides, connect the capacitor across the VREF pin and the AVss pin at equal length as close as possible. (4) Clock frequency during A/D conversion Use the A/D converter in the following conditions:
• Select XIN-XOUT as system clock φ by the system clock selection bit (bit 7 of CPU mode register (address 3B16)). When selecting XCIN-XCOUT as system clock φ, the A/D conversion function cannot be used.
• f(XIN) is 500 kHz or more.
• Do not execute the STP or WIT instruction during A/D conversion.
• Reason The comparator consists of a capacity coupling, and a charge of the capacity will be lost if the clock frequency is too low. This may cause the A/D conversion precision to be worse. (5) When the falling edge is input to the ADT pin during A/D conversion at the time of A/D external trigger effective, the conversion processing is interrupted and the A/D conversion starts again. In addition, even if “0” is set to the AD conversion completion bit by the program during A/D conversion, re-conversion is not performed but the original conversion is continued. (6) The A/D converter will not operate normally if one of the following operation is applied during the A/D conversion:
• Writing to CPU mode register
• Writing to AD control register
• Executing the STP instruction and WIT instruction

Rev.2.00 May. 24, 2006 page 85 of 90 REJ03B0028-0200

3.3.10 Notes on D/A converter

(1) Pin states at reset The P5 6/DA1 pin and the P57/ADT/DA 2 pin go to high impedance state at reset. (2) Connecting low-impedance device The DAi output pin have no buffer, so connect an external buffer when driving a low-impedance load. (3) Reference voltage input pin VREF

• When the P5 6/DA1 pin and the P57/ADT/DA 2 pin are used as DAi output pins, the Vcc level is recommended for the applied voltage to the VREF pin. When the voltage below Vcc level is applied, the D/A conversion accuracy may be worse.
• Connect an approximately 1000 pF capacitor across the AVss pin and the VREF pin. Besides, connect the capacitor across the VREF pin and the AVss pin at equal length as close as possible.

Rev.2.00 May. 24, 2006 page 86 of 90 REJ03B0028-0200

3.3.11 Notes on LCD drive control circuit

(1) Count source for LCDCK The LCDCK count source selection bit (bit 7 of LCD mode register (address 3916)) is set to “0” after reset, selecting f(XCIN )/32. The sub clock has stopped after reset. Therefore, turn on LCD after starting the oscillation and stabilizing the oscillation. Select the LCDCK count source after the corresponding clock source becomes stable. (2) STP instruction When executing the STP instruction, execute the STP instruction after setting the LCD enable bit to “0”. If the STP instruction is executed during LCD lighting, direct-current voltage will be applied to the LCD panel. (3) When not using LCD When not using an LCD, leave the LCD segment and common pins open. Connect the V L1 pin to Vss, and the VL2 and VL3 pins to Vcc. (4) Using voltage multiplier circuit When using the voltage multiplier, apply the limit voltage or less to the VL1 pin, then set the voltage multiplier control bit to “1” (enabled). If above the limit voltage is applied to the VL1 pin, current may flow in the voltage multiplier circuit at the time of the voltage multiplier circuit operation start. For the limit value, refer to “3.1 Electrical characteristics”. When not using the voltage multiplier, set the LCD output enable bit to “1”, then apply proper voltage to the LCD power input pins (VL1–V L3). When the LCD output enable bit is set to “0” (disabled), the Vcc voltage is applied to the VL3 pin inside of this microcomputer. (5) LCD drive power supply Power supply capacitor may be insufficient with the division resistance for LCD power supply, and the characteristic of the LCD panel. In this case, there is the method of connecting the bypass capacitor about 0.1–0.33 µF to V L1–V L3 pins. The example of a strengthening measure of the LCD drive power supply is shown in Figure 3.3.9. Fig. 3.3.9 Strengthening measure example of LCD drive power supply VL3 VL2 VL1

• Connect by the shortest possible wiring.
• Connect the bypass capacitor to the VL1–VL3 pins as short as possible. (Referential value: 0.1–0.33 µF) 3826 group

Rev.2.00 May. 24, 2006 page 87 of 90 REJ03B0028-0200 (6) Data setting to LCD display RAM When writing a data into the LCD display RAM during LCD being turned ON (LCD enable bit = “1”), write the confirmed data. Do not write temporarily on the LCD display RAM because this might cause the LCD display flickering. Figure 3.3.10 shows the write procedure for LCD display RAM when LCD is on. Fig. 3.3.10 Write procedure for LCD display RAM when LCD is on (1)Right process example LCD ON LCD ON or OFF

• Sets determinate data to LCD display RAM Sets LCD display RAM data LRAM0 (Address : 4016) ← “FF16” LCD display ON or OFF ?
• Sets turn off data to LCD display RAM
• Sets determinate data to LCD diplay RAM (2) Error process example LCD ON LCD ON or OFF LCD OFF OFF OFF ON ON Contents of addres 004016 are “FF16” LCD display ON or OFF ? Sets LCD display RAM data LRAM0 (Address : 4016) ← “FF16” Sets LCD display RAM data LRAM0 (Address : 4016) ← “0016” Sets LCD display RAM data LRAM0 (Address : 4016) ← “0016” Contents of addres 004016 are “FF16”

Rev.2.00 May. 24, 2006 page 88 of 90 REJ03B0028-0200

3.3.12 Notes on watchdog timer

(1) The watchdog timer is operating during the wait mode. Write data to the watchdog timer control register to prevent timer underflow. (2) The watchdog timer stops during the stop mode. However, the watchdog timer is running during the clock stabilization period and the watchdog timer control register must be written just before executing the STP instruction. (3) The count source of the watchdog timer is affected by the system clock φ selected by the system clock selection bit (bit 7 of CPU mode register (address 3B16)).

3.3.13 Notes on reset circuit

(1) Reset input voltage control Make sure that the reset input voltage is less than 0.2 Vcc for Vcc(min). (2) Countermeasures for reset signal slow rising In case where the RESET signal rise time is long, connect a ceramic capacitor or others across the RESET pin and the Vss pin. Use a 1000 pF or more capacitor for high frequency use. When connecting the capacitor, note the following:

• Make the length of the wiring which is connected to a capacitor as short as possible.
• Be sure to verify the operation of application products on the user side.
• Reason If the several nanosecond or several ten nanosecond impulse noise enters the RESET pin, it may cause a microcomputer failure. (3) Port state immediately after reset Table 3.3.1 shows the each pin state during RESET pin is “L”. Table 3.3.1 Each pin state during RESET pin is “L” Pin name P0, P1 (SEG 26–SEG 39) P2, P41–P4 7, P5, P6 P3 (SEG 18–SEG 25) P7 0 P4 0, P71–P7 7 SEG 0–SEG 17 COM 0–COM 3 Pin state Input mode (with pull-up) Input mode (high-impedance) Pulled up to Vcc level High-impedance Input mode (high-impedance) Vcc level output Vcc level output

Rev.2.00 May. 24, 2006 page 89 of 90 REJ03B0028-0200

3.3.14 Notes on clock generating circuit

• Mode transition Both the main clock (XIN-XOUT ) and sub-clock (XCIN-XCOUT ) need time for the oscillations to stabilize. The mode transition between middle-/high-speed and low-speed mode must be performed after the corresponding clock becomes stable. The sub-clock, needs extra time to stabilize particularly when executing operations after power-on and stop mode. The main and sub clocks require the following condition for mode transition. f(X IN) > 3✕ f(XCIN )

Rev.2.00 May. 24, 2006 page 90 of 90 REJ03B0028-0200

3.3.15 Notes on standby function

(1) Once the STP instruction is disabled by the STP instruction disable bit (bit 6 of watchdog timer control register (address 3716)), the microcomputer cannot be return to the STP instruction enable state. (2) When using the standby function, note the following. The power dissipation may increase depending on functions and pin states. Take the following countermeasures for reduce the power dissipation. ■ Countermeasures for reduce power dissipation

• Input ports: Fix to “H” or “L” externally
• Output ports: Fix to level that avoid leak-current. (Example: Fix the pin to “H“ when the circuit which current flows and LED turns on at “L” output.)
• A/D input pins: Fix to “H” or “L” externally
• PWMi function enable bits (bits 1 and 2 of PWM control register (address 2B 16)): “0”
• LCD enable bit: “0”
• Complete A/D conversion (Confirm the AD conversion completion bit (bit 3 of AD control register (address 34 16)) is “1”)
• VREF input switch bit (bit 4 of AD control register): “0”
• D/Ai conversion register (addresses 3216, 3316): “0016” (3) When using stop mode ■ Operation after restoration by occurrence of interrupt request
• All the timer 123 mode register bits are automatically set to “0” except for bit 4.
• When an interrupt request occurs in the stop mode, the stop mode is released and the clock stopped by STP starts the oscillation. The oscillation stabilizing time of main clock is secured to restoration from the stop mode when both the main and sub clocks are oscillating and the main clock is set for the system clock when executing the STP instruction. Note that the oscillation of sub clock may not be stable after main clock oscillation being stable. ■ When LCD display Execute the STP instruction after turning LCD to OFF by setting the LCD enable bit (bit 3 of LCD mode register (address 39 16)) to “0”. If the STP instruction is executed while the LCD is ON, direct voltage will be applied to the LCD panel. ■ Watchdog timer The watchdog timer stops during the stop mode but operates during the oscillation stabilizing time. Therefore, the watchdog timer control register must be written just before executing the STP instruction to prevent its underflow. (4) When using wait mode ■ Restoration by reset input When the sub clock is selected as the system clock and the main clock is stopped at the time WIT instruction is executed, if the RESET pin input level is set to “L”, the sub clock oscillation stops and the main clock oscillation starts. Oscillation is unstable at first and requires an oscillation stabilizing time. Retain the RESET pin input level at “L” until the oscillation is stabilized. After the oscillation has stabilized, retain the RESET pin at “L” for 2 µs or more in order to set the internal reset state. ■ Watchdog timer The watchdog timer operates during the wait mode. The watchdog timer control register must be written to prevent its underflow.

REVISION HISTORY

Rev. Date Description Page Summary

3826 Group (A version) Data Sheet

1.00 Feb. 18, 2003 1.02 Jul. 31, 2003 First edition issued Power dissipation revised. Table 1 Pin description (1) V CC VSS ; Function description revised. Fig.5 Memory expansion plan revised. Fig.14 Port block diagram (1); (4) Ports P1 6, P17,P2, P41, P42 and (5) Port P44 revised. Fig.15 Port block diagram (2); (7) Port P4 6 and (11) Port P54 revised. Fig.16 Port block diagram (3); (14) Port P5 5, (15) Ports P56, P57 and (17) Port P60 revised. Fig.17 Port block diagram (4); (19) Port P6 2 revised. Fig.40 A-D converter block diagram Voltage Multiplier (3 Times) Description of order for operating the voltage multiplier revised. ROM ORDERING METHOD revised. Table 16 Recommended operating conditions (4); f(CNTR 0) f(CNTR1) revised. Table 18 Electrical characteristics (2); ICC revised. Table 19 A-D converter characteristics (1); Note revised. Table 20 A-D converter characteristics (2); Note revised. Table 22 Timing requirements (1); tc(S CLK ), tWH (SCLK ), tWL (SCLK ), tsu(RxD-SCLK ), th(SCLK -RxD); revised. Table 23 Timing requirements (2); tc(S CLK ), tWH (SCLK ), tWL (SCLK ), tsu(RxD-SCLK ), th(SCLK -RxD); revised. Table 25 Switching characteristics (2) ; tr(SCLK1) tf(SCLK1) revised. Package revised. Word standardized: “A/D converter”, “D/A converter”, “Serial interface” FEATURES: • A/D converter revised. APPLICATIONS: “household appliances” added. Fig. 4: Description of RAM added. Fig. 5: Development status: “under development” → “mass production” Table 3: Date revised. SFR: AD conversion low-order register (ADL) added to address 0014 16 and AD conversion high-order register (ADH) added to address 003516. A/D CONVERTER: Description revised and ADL added to Fig. 38. Fig. 39 added and Fig. 40 revised. Fig. 58: AD conversion low-order register added. Description revised. Fig. 59: Note added. Fig. 61: Note 2 added. Note on Power supply voltage added. 2.00May.24, 2006 (1/2)

Rev. Date Description Page Summary ROM ORDERING METHOD: URL revised. Table 19: “f(X IN) = 8 MHz” added to Test condition of tCONV revised. Table 20 A/D converter characteristics (2) [10-bit A/D mode] added. Table 22: “(Note)” of tc(S CLK2 ), twH (SCLK2 ), twL(SCLK2 ) eliminated. Table 23: “(Note)” of tc(SCLK2 ), twH (SCLK2 ), twL(SCLK2 ) eliminated. Table 25: Note 2 eliminated. APPENDIX added. 2.00 May.24, 2006 (2/2)

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