3825

3825 RENESAS | Alldatasheet

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Technical content

Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp. The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices and power devices. Renesas Technology Corp. Customer Support Dept. April 1, 2003 To all our customers

DESCRIPTION

The 3825 group is the 8-bit microcomputer based on the 740 fam- ily core technology. The 3825 group has the LCD drive control circuit, an 8-channel A- D converter, and a Serial I/O as additional functions. The various microcomputers in the 3825 group include variations of internal memory size and packaging. For details, refer to the section on part numbering. For details on availability of microcomputers in the 3825 Group, refer the section on group expansion.

FEATURES

(at 8 MHz oscillation frequency)

• Memory size
• Software pull-up/pull-down resistors (Ports P0–P8) (includes key input interrupt)
• LCD drive control circuit
• 2 Clock generating circuits (connect to external ceramic resonator or quartz-crystal oscillator)
• Power source voltage (M version: 2.2 to 5.5 V) (Extended operating temperature version: 3.0 to 5.5 V) (M version: 2.2 to 5.5 V) (Extended operating temperature version: 3.0 to 5.5 V)
• Power dissipation (at 8 MHz oscillation frequency, at 5 V power source voltage) (at 32 kHz oscillation frequency, at 3 V power source voltage) (Extended operating temperature version: –40 to 85°C)

APPLICATIONS

Camera, household appliances, consumer electronics, etc.

3825 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Package type : 100P6S-A (100-pin plastic-molded QFP) Fig. 1 Pin configuration of M38258MCMXXXFP (The pin configuration of 100D0 is same as this.) PIN CONFIGURATION (TOP VIEW) 1 2 3 4 5 6 7 8 9 1 01 11 21 31 02 12 22 32 42 52 62 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 162 63 64 65 66 67 68 69 707 172 737 4 7 5 7 6 7 7 7 8 7 9 8 M38258MCMXXXFP S E G 9 P S E G 1 P S E G 1 P S E G 2 P S E G 2 P S E G 2 S E G S E G S E G S E G S E G S E G P S E G 2 P S E G 2 P S E G 2 P S E G 2 P S E G 2 P S E G 2 P S E G 2 P S E G 3 P S E G 3 P S E G 3 P S E G 3 P S E G 3 P S E G 3 P S E G 3 P S E G 3 P S E G 3 P S E G 3 C 1 VL P A N 7 P A N 6 P A N 5 P A N 4 P A N 3 P A N 2 P A N 1 P A N 0 P A D T P TO U T P C N T R 1 P C N T R 0 P 53/ R T P 52/ R T P I N P I N P SC L K P TXD P R XD P I N P I N P f XI N ) f XI N ) P f XI N ) f XI N ) P P P P C 2 VL2 VL3 C O M C O M C O M VR E F A V S S VCC SEG 8 SEG 0 S E G S E G S E G S E G S E G S E G S E G P72 P73 P71 P P XC I N P XC O U T XI N XO U T VS S P27 P26 P P24 P P P P P20 P17 R E S E T S E G S E G C O M P SR D Y

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PIN CONFIGURATION (TOP VIEW) Fig. 2 Pin configuration of M38258MCMXXXGP , M38258MCMXXXHP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 5 2 5 3 5 4 5 5 5 6 5 7585 9 6 0 6 1626 364 65 66 67 686 9707 1 7 273 74 75 0 1 M M C M X X X G P M M C M X X X H P S E G 1 S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G SEG 1 S E G VC C VR E F AV SS C O M C O M C O M COM 0 VL VL C 2 C 1 VL P A N 7 P A N 6 P A N 5 P A N 4 P A N 3 P A N 2 P A N 1 P A N 0 P A D T P TO U T P C N T R 1 P C N T R 0 P R T P R T P I N P I N P SC L K P TXD P R XD P I N P I N P f XI N ) f XI N ) P f XI N ) f XI N ) P P SR D Y P P73 P P70 P XC I N P80/XCOUT XI N XO U T VSS P P P25 P P P P P P P R E S E T P P75 P P S E G 3 P S E G 3 P S E G 1 P S E G 1 P S E G 2 P S E G 2 P S E G 2 S E G S E G S E G P S E G 2 P S E G 2 P S E G 2 P S E G 2 P S E G 2 P S E G 2 P S E G 2 P S E G 3 P S E G 3 P S E G 3 P S E G 3 P S E G 3 P S E G 3 P S E G 3 P S E G 3 S E G S E G

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS FUNCTIONAL BLOCK DIAGRAM (Package : 100P6S-A) Fig. 3 Functional block diagram A D T C N T R 0, C N T R 1 TO U T C P U A X Y S P C H P C L P S R O M S I / O ( 8 ) VL VL VL C O M C O M C O M C O M 3 8 φ L C D d r i v e c o n t r o l c i r c u i t R A M L C D d i s p l a y R A M b y t e s T i m e r X ( 1 6 ) T i m e r Y ( 1 6 ) T i m e r 1 ( 8 )T i m e r 2 ( 8 ) T i m e r 3 ( 8 ) D a t a b u s C l o c k g e n e r a t i n g c i r c u i t C l o c k i n p u t X I N C l o c k o u t p u t XO U T XC O U T S u b c l o c k o u t p u t XC I N S u b c l o c k i n p u t VC C R e s e t i n p u t (

5 V )

R E S E T K e y - o n w a k e u p R e a l t i m e p o r t f u n c t i o n I N T 0, I N T1 A D c o n v e r t e r R T P0, R T P1 3 9 3 VS S ( 0 V ) 9 9 9 8 9 7 9 6 9 5 9 4 S E G 1 S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G O u t p u t p o r t P 0 P 0 ( 8 ) 3 6 2 6 1 6 9 5 O u t p u t p o r t P 1 P 1 ( 8 ) 5 5 4 5 3 5 2 5 1 5 I / O p o r t P 2 P 2 ( 8 ) 7 4 6 4 5 4 3 4 P 4 ( 8 ) I / O p o r t P 4 5 2 4 2 3 2 1 2 I / O p o r t P 5 P 5 ( 8 ) 7 1 6 1 5 1 3 1 I N T2, I N T3 VR E F A VS S

0 V )

P 6 ( 8 ) 3 1 I / O p o r t P 6 9 8 7 65 4 P 8 ( 2 ) XC I N XC O U T I / O p o r t P 8 10 0 C 1 C 2 S E G 1 S E G S E G S E G S E G S E G O u t p u t p o r t P 3 P 3 ( 8 ) 2 7 1 7 0 6 9 6 8 6 7 6 P 7 ( 8 ) I / O p o r t P 7 3 3 2 3 1 3 0 2 9 2

Table 1. Pin description (1)

• Apply voltage of power source to VCC , and 0 V to VSS . (For the limits of VCC, refer to “Recom- mended operating conditions”.)
• Reference voltage input pin for A-D converter.
• GND input pin for A-D converter.
• Connect to VSS .
• Reset input pin for active “L”
• Input and output pins for the main clock generating circuit.
• Feedback resistor is built in between XIN pin and XOUT pin.
• Connect a ceramic resonator or a quartz-crystal oscillator between the XIN and XOUT pins to set the oscillation frequency.
• If an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open.
• This clock is used as the oscillating source of system clock.
• Input 0 ≤ VL1 ≤ VL2 ≤ VL3 ≤ VCC voltage
• Input 0 – VL3 voltage to LCD
• External capacitor pins for a voltage multiplier (3 times) of LCD contorl.
• LCD common output pins
• COM 2 and COM 3 are not used at 1/2 duty ratio.
• COM 3 is not used at 1/3 duty ratio.
• LCD segment output pins
• 8-bit output port
• CMOS 3-state output structure
• Pull-down control is enabled.
• Port output control is enabled.
• 6-bit output port
• CMOS 3-state output structure
• Pull-down control is enabled.
• Port output control is enabled.
• 2-bit I/O port
• CMOS compatible input level
• CMOS 3-state output structure
• I/O direction register allows each pin to be individually programmed as either input or output.
• Pull-up control is enabled.
• 8-bit Input port
• CMOS compatible input level
• CMOS 3-state output structure
• I/O direction register allows each pin to be individually programmed as either input or output.
• Pull-up control is enabled.
• 8-bit output port
• CMOS 3-state output structure
• Pull-down control is enabled.
• Port output control is enabled.
• LCD segment pins
• Key input (key-on wake up) interrupt input pins
• LCD segment pins Pin V CC , VSS VREF AV SS RESET XIN XOUT VL1 – VL3 C 1, C2 COM 0 – COM 3 SEG 0 – SEG 17 P00/SEG 26 – P07/SEG 33 P10/SEG 34 – P15/SEG 39 P16, P17 P20 – P27 P30/SEG 18 – P37/SEG 25 Name Power source Analog reference voltage Analog power source Reset input Clock input Clock output LCD power source Charge-pump capacitor pin Common output Segment output Output port P0 Output port P1 I/O port P1 I/O port P2 Output port P3 Function except a port function

• 8-bit I/O port
• CMOS compatible input level
• CMOS 3-state output structure
• I/O direction register allows each pin to be individually programmed as either input or output.
• Pull-up control is enabled.
• 8-bit I/O port
• CMOS compatible input level
• CMOS 3-state output structure
• I/O direction register allows each pin to be individually programmed as either input or output.
• Pull-up control is enabled.
• 8-bit I/O port
• CMOS compatible input level
• CMOS 3-state output structure
• I/O direction register allows each pin to be individually programmed as either input or output.
• Pull-up control is enabled.
• 1-bit input port
• CMOS compatible input level
• 7-bit I/O port
• CMOS compatible input level
• CMOS 3-state output structure
• I/O direction register allows each pin to be individually programmed as either input or output.
• Pull-up control is enabled.
• 2-bit I/O port
• CMOS compatible input level
• CMOS 3-state output structure
• I/O direction register allows each pin to be individually programmed as either input or output.
• Pull-up control is enabled. Pin 0/f(XIN)/ f(XIN)/2, P41/f(XIN)/5/ f(XIN)/10 P42/INT0, P43/INT1 P44/RXD, P45/TXD, P46/SCLK , P47/SRDY P50/INT2, P51/INT3 P52/RTP0, P53/RTP1 P54/CNTR 0, P55/CNTR 1 P56/TOUT P57/ADT P60/AN0– P67/AN7 P70 P71–P77 P80/XCOUT , P81/XCIN Name I/O port P4 I/O port P5 I/O port P6 Input port P7 I/O port P7 I/O port P8 Function except a port function
• Clock output pins
• Interrupt input pins
• Serial I/O function pins
• Interrupt input pins
• Real time port function pins
• Timers X, Y functions pins
• Timer 2 output pin
• A-D trigger input pin
• A-D conversion input pins

Table 2. Pin description (2)

• Sub-clock generating circuit I/O pins (Connect a resonator. External clock cannot be used.)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 4 Part numbering M 3 8 2 5 8 M C M X X X H PProduct ROM/PROM size : 4096 bytes : 8192 bytes : 12288 bytes : 16384 bytes : 20480 bytes : 24576 bytes : 28672 bytes : 32768 bytes T h e f i r s t b y t e s a n d t h e l a s t b y t e s o f R O M a r e r e s e r v e d a r e a s t h e y c a n n o t b e u s e d M e m o r y t y p e M E : Mask ROM version : EPROM or One Time PROM version R A M s i z e : 192 bytes : 256 bytes : 384 bytes : 512 bytes : 640 bytes : 768 bytes : 896 bytes : 1024 bytes : 1536 bytes : 2048 bytes R O M n u m b e r O m i t t e d i n O n e T i m e P R O M v e r s i o n s h i p p e d i n b l a n k a n d E P R O M v e r s i o n N o r m a l l y , u s i n g h y p h e n W h e n e l e c t r i c a l c h a r a c t e r i s t i c o r d i v i s i o n o f q u a l i t y i d e n t i f i c a t i o n c o d e u s i n g a l p h a n u m e r i c c h a r a c t e r S t a n d a r d D E x t e n d e d o p e r a t i n g t e m p e r a t u r e v e r s i o n M M v e r s i o n P a c k a g e t y p e F P H P G P F S : 100P6S-A package : 100PFB-A package : 100P6Q-A package : 100D0 package A B C D E F : 36864 bytes : 40960 bytes : 45056 bytes : 49152 bytes : 53248 bytes : 57344 bytes : 61440 bytes

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS GROUP EXPANSION (STANDARD, ONE TIME PROM VERSION, EPROM VERSION) Mitsubishi plans to expand the 3825 group(Standard, One Time PROM version, EPROM version) as follows. Memory Type Support for mask ROM, One Time PROM, and EPROM versions. Memory Size Packages Memory Expansion Plan Fig. 5 Memory expansion plan 6 0 K 6 K 2 K 8 K 4 K 6 K 32K 2 8 K 24K 2 0 K 16K 1 2 K 4 K 40K R O M s i z e ( b y t e s ) 256 1 , 0 2 41 , 5 3 6 2,048 R A M s i z e ( b y t e s ) M a s s p r o d u c t Mass product M a s s p r o d u c t M38254M6 M a s s p r o d u c t 5 1 27 6 86 4 0 M 3 8 2 5 4 M 4 M 3 8 2 5 7 M 8 / E 8 M38259EF

Currently products are listed below. Table 3. List of products As of Dec. 2000

temperature version) as follows. Support for mask ROM, one time PROM version. Currently products are listed below. Table 4. List of products for extended operating temperature version As of Dec. 2000

Mitsubishi plans to expand the 3825 group (M version) as follows. Support for mask ROM version. Currently products are listed below. Table 5. List of products for low power source version As of Dec. 2000

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS CENTRAL PROCESSING UNIT (CPU) The 3825 group uses the standard 740 family instruction set. Re- fer to the table of 740 family addressing modes and machine instructions or the 740 Family Software Manual for details on the instruction set. Machine-resident 740 family instructions are as follows: The FST and SLW instruction cannot be used. The STP, WIT, MUL, and DIV instruction can be used. [Accumulator (A)] The accumulator is an 8-bit register. Data operations such as data transfer, etc., are executed mainly through the accumulator. [Index Register X (X)] The index register X is an 8-bit register. In the index addressing modes, the value of the OPERAND is added to the contents of register X and specifies the real address. [Index Register Y (Y)] The index register Y is an 8-bit register. In partial instruction, the value of the OPERAND is added to the contents of register Y and specifies the real address. [Stack Pointer (S)] The stack pointer is an 8-bit register used during subroutine calls and interrupts. This register indicates start address of stored area (stack) for storing registers during subroutine calls and interrupts. The low-order 8 bits of the stack address are determined by the contents of the stack pointer. The high-order 8 bits of the stack address are determined by the stack page selection bit. If the stack page selection bit is “0” , the high-order 8 bits becomes “00 16”. If the stack page selection bit is “1”, the high-order 8 bits becomes “0116”. The operations of pushing register contents onto the stack and popping them from the stack are shown in Figure 9. Store registers other than those described in Figure 9 with pro- gram when the user needs them during interrupts or subroutine calls. [Program Counter (PC)] The program counter is a 16-bit counter consisting of two 8-bit registers PC H and PCL. It is used to indicate the address of the next instruction to be executed. Fig. 8 740 Family CPU register structure A Accumulator b7 b0 b7 b15 b0 b7 b0 X Index register X Y Index register Y S Stack pointer PC L Program counter PCH N V T B D I Z C Processor status register (PS) Carry flag Zero flag Interrupt disable flag Decimal mode flag Break flag Index X mode flag Overflow flag Negative flag

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Table 6 Push and pop instructions of accumulator or processor status register Accumulator Processor status register Push instruction to stack PHA PHP Pop instruction from stack PLA PLP Fig. 9 Register push and pop at interrupt generation and subroutine call N o t e: C o n d i t i o n f o r a c c e p t a n c e o f a n i n t e r r u p t I n t e r r u p t e n a b l e f l a g i s “ 1 ” E x e c u t e J S R O n g o i n g R o u t i n e M S P C H ) S S M S P C E x e c u t e R T S P C L)M S S S S S S S P C H )M S S u b r o u t i n e P O P re t u r n a d d r e s s f r o m s t a c k P u s h r e t u r n a d d r e s s o n s t a c k M S P S E x e c u t e R T I P S S S S S S I n t e r r u p t S e r v i c e R o u t i n e P O P c o n t e n t s o f p r o c e s s o r s t a t u s r e g i s t e r f r o m s t a c k M S P C H ) S S M S P C S S P C L)M S S S S S P C H )M S P O P r e t u r n a d d r e s s f r o m s t a c k I F l a g i s s e t f r o m “ 0 ” t o “ 1 ” F e t c h t h e j u m p v e c t o r P u s h r e t u r n a d d r e s s o n s t a c k P u s h c o n t e n t s o f p r o c e s s o r s t a t u s r e g i s t e r o n s t a c k I n t e r r u p t r e q u e s t N o t e I n t e r r u p t d i s a b l e f l a g i s “ 0 ”

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS [Processor status register (PS)] The processor status register is an 8-bit register consisting of 5 flags which indicate the status of the processor after an arithmetic operation and 3 flags which decide MCU operation. Branch opera- tions can be performed by testing the Carry (C) flag , Zero (Z) flag, Overflow (V) flag, or the Negative (N) flag. In decimal mode, the Z, V, N flags are not valid.

• Bit 0: Carry flag (C) The C flag contains a carry or borrow generated by the arithmetic logic unit (ALU) immediately after an arithmetic operation. It can also be changed by a shift or rotate instruction.
• Bit 1: Zero flag (Z) The Z flag is set if the result of an immediate arithmetic operation or a data transfer is “0”, and cleared if the result is anything other than “0”.
• Bit 2: Interrupt disable flag (I) The I flag disables all interrupts except for the interrupt generated by the BRK instruction. Interrupts are disabled when the I flag is “1”.
• Bit 3: Decimal mode flag (D) The D flag determines whether additions and subtractions are executed in binary or decimal. Binary arithmetic is executed when this flag is “0”; decimal arithmetic is executed when it is “1”. Decimal correction is automatic in decimal mode. Only the ADC
• Bit 4: Break flag (B) The B flag is used to indicate that the current interrupt was generated by the BRK instruction. The BRK flag in the processor status register is always “0”. When the BRK instruction is used to generate an interrupt, the processor status register is pushed onto the stack with the break flag set to “1”.
• Bit 5: Index X mode flag (T) When the T flag is “0”, arithmetic operations are performed between accumulator and memory. When the T flag is “1”, direct arithmetic operations and direct data transfers are enabled between memory locations.
• Bit 6: Overflow flag (V) The V flag is used during the addition or subtraction of one byte of signed data. It is set if the result exceeds +127 to -128. When the BIT instruction is executed, bit 6 of the memory location operated on by the BIT instruction is stored in the overflow flag.
• Bit 7: Negative flag (N) The N flag is set if the result of an arithmetic operation or data transfer is negative. When the BIT instruction is executed, bit 7 of the memory location operated on by the BIT instruction is stored in the negative flag. Table 7 Set and clear instructions of each bit of processor status register Set instruction Clear instruction C flag SEC CLC Z flag I flag SEI CLI D flag SED CLD B flag T flag SET CLT V flag CLV N flag

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS [CPU Mode Register (CPUM)] 003B16 The CPU mode register contains the stack page selection bit and the internal system clock selection bit. The CPU mode register is allocated at address 003B 16. Fig. 10 Structure of CPU mode register N o t a v a i l a b l e Processor mode bits b1 b0 0 0 : Single-chip mode 0 1 : 1 0 : 1 1 : Stack page selection bit 0 : 0 page 1 : 1 page Not used (returns “1” when read) (Do not write “0” to this bit) Port X C switch bit 0 : I/O port function (stop oscillating) 1 : X CIN–XCOUT oscillating function Main clock (XIN–XOUT ) stop bit 0 : Oscillating 1 : Stopped Main clock division ratio selection bit 0 : f(X IN)/2 (high-speed mode) 1 : f(XIN)/8 (middle-speed mode) Internal system clock selection bit 0 : XIN–XOUT selected (middle-/high-speed mode) 1 : XCIN–XCOUT selected (low-speed mode) CPU mode register ( C P U M ( C M ) : a d d r e s s 0 0 3 B1 b 7 b0

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Special Function Register (SFR) Area The Special Function Register area in the zero page contains con- trol registers such as I/O ports and timers. RAM RAM is used for data storage and for stack area of subroutine calls and interrupts. ROM The first 128 bytes and the last 2 bytes of ROM are reserved for device testing and the rest is user area for storing programs. Interrupt Vector Area The interrupt vector area contains reset and interrupt vectors. Zero Page The 256 bytes from addresses 000016 to 00FF16 are called the zero page area. The internal RAM and the special function regis- ters (SFR) are allocated to this area. The zero page addressing mode can be used to specify memory and register addresses in the zero page area. Access to this area with only 2 bytes is possible in the zero page addressing mode. Special Page The 256 bytes from addresses FF0016 to FFFF16 are called the special page area. The special page addressing mode can be used to specify memory addresses in the special page area. Ac- cess to this area with only 2 bytes is possible in the special page addressing mode. Fig. 11 Memory map diagram 192 256 384 512 640 768 896 1024 1536 2048 FF16 013F16 01BF 16 023F16 02BF 16 033F16 03BF 16 043F16 063F16 083F16 RAM area R A M s i z e b y t e s A d d r e s s X X X 4096 8192 12288 16384 20480 24576 28672 32768 36864 40960 45056 49152 53248 57344 61440 F00016 E00016 D000 16 C000 16 B00016 A00016 900016 800016 700016 600016 500016 400016 300016 200016 100016 F08016 E08016 D080 16 C080 16 B08016 A08016 908016 808016 708016 608016 508016 408016 308016 208016 108016 ROM area ROM size (bytes) A d d r e s s Y Y Y A d d r e s s Z Z Z 010016 000016 004016 084016 FF0016 FFDC 16 F F F E1 FFFF 16 XXXX 16 YYYY 16 ZZZZ 16 RAM R O M 005416 R eserved area S F R a r e a N ot used I n t e r r u p t v e c t o r a r e a R eserved ROM area (128 bytes) Z e r o p a g e Special page LCD display RAM area R e s e r v e d R O M a r e a

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 12 Memory map of special function register (SFR) 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 0 0 2 C 1 0 2 D 1 002E16 002F16 003016 003116 003216 003316 003416 003516 003616 003716 003816 003916 003A16 003B16 0 3 C 1 003D 16 003E16 003F16 0 0 0 000116 000216 0 0 3 0 0 4 000516 0 0 6 0 0 7 0 0 8 0 0 9 000A16 0 0 000C 16 000D 16 0 0 000F16 001016 001116 001216 0 1 3 0 1 4 001516 001616 001716 0 1 8 0 1 9 001A16 001B16 001C 16 001D 16 001E16 0 1 P o r t P 0 ( P 0 ) Port P1 (P1) P o r t P 1 o u t p u t c o n t r o l r e g i s t e r ( P 1 C ) P o r t P 2 ( P 2 ) Port P2 direction register (P2D) P o r t P 3 ( P 3 ) P o r t P 4 ( P 4 ) P o r t P 4 d i r e c t i o n r e g i s t e r ( P 4 D ) Port P5 (P5) P o r t P 5 d i r e c t i o n r e g i s t e r ( P 5 D ) P o r t P 6 ( P 6 ) P o r t P 6 d i r e c t i o n r e g i s t e r ( P 6 D ) P o r t P 7 ( P 7 ) P o r t P 7 d i r e c t i o n r e g i s t e r ( P 7 D ) Serial I/O status register (SIOSTS) Serial I/O control register (SIO1CON) U A R T c o n t r o l r e g i s t e r ( U A R T C O N ) Baud rate generator (BRG) I n t e r r u p t c o n t r o l r e g i s t e r 2 ( I C O N 2 ) T i m e r 3 ( T 3 ) Timer X mode register (TXM) I n t e r r u p t e d g e s e l e c t i o n r e g i s t e r ( I N T E D G E ) C P U m o d e r e g i s t e r ( C P U M ) Interrupt request register 1(IREQ1) Interrupt request register 2(IREQ2) I n t e r r u p t c o n t r o l r e g i s t e r 1 ( I C O N 1 ) Timer X (low ) (TXL) T i m e r Y ( l o w ) ( T Y L ) Timer 1 (T1) Timer 2 (T2) T i m e r X ( h i g h ) ( T X H ) T i m e r Y ( h i g h ) ( T Y H ) PULL register A (PULLA) P U L L r e g i s t e r B ( P U L L B ) Timer Y mode register (TYM) Timer 123 mode register (T123M) Clock output control register (TCON) Segment output enable register (SEG) L C D m o d e r e g i s t e r ( L M ) A-D control register (ADCON) A-D conversion register (AD) Transmit/R eceive buffer register(TB/RB) P o r t P 8 ( P 8 ) Port P8 direction register (P8D)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS The 3825 group has 43 programmable I/O pins arranged in seven I/O ports (ports P16, P17, P2, P4–P6, P71–P77, P80 and P81). The I/O ports have direction registers which determine the input/output direction of each individual pin. (Ports P1 6 and P17 are shared with bits 6 and 7 of the port P1 output control register). Each bit in a direction register corresponds to one pin, and each pin can be set to be input port or output port. When “0” is written to the bit corresponding to a pin, that pin be- comes an input pin. When “1” is written to that bit, that pin be- comes an output pin. If data is read from a pin set to output, the value of the port output latch is read, not the value of the pin itself. Pins set to input are floating. If a pin set to input is written to, only the port output latch is written to and the pin remains floating. Port P1 Output Control Register Bit 0 of the port P1 output control register (address 000316) en- ables control of the output of ports P10 to P15. When the bit is set to “1”, the port output function is valid. In this case, setting of the PULL register A to ports P10 to P15 is invalid. When resetting, bit 0 of the port P1 output control register is set to “0” (the port output function is invalid.) Pull-up/Pull-down Control By setting the PULL register A (address 001616) or the PULL reg- ister B (address 001716), ports P0 to P8 except P70 can control ei- ther pull-down or pull-up (pins that are shared with the segment output pins for LCD are pull-down; all other pins are pull-up) with a program. However, the contents of PULL register A and PULL register B do not affect ports programmed as the output ports. (except for ports P0 and P3). Ports P0 and P3 share the port output control function with bit 0 of the PULL register A. When set to “1”, the port output function is in- valid (Pull-down is valid). When set to “0”, the port output function is valid (Pull-down is in- valid). The PULL register A setting is invalid for pins set to segment out- put with the segment output enable register. Fig. 13 Structure of PULL register A and PULL register B P 0 , P 10– P 15, P 3 p u l l - d o w n s h a r e d w i t h P a n d P o u t p u t c o n t r o l r e f e r t o t h e t e x t P 16– P p u l l u p P 20– P p u l l u p P 80, P p u l l u p P 40– P p u l l u p P 44– P p u l l u p N o t u s e d r e t u r n w h e n r e a d PULL register A (PULLA : address 001616) b7 b 0 P 50– P 53 p u l l - u p P 54– P p u l l u p P 60– P p u l l u p P 64– P p u l l u p P 71– P p u l l u p P 74– P p u l l u p N o t u s e d r e t u r n w h e n r e a d 0 : D i s a b l e E n a b l e P U L L r e g i s t e r B P U L L B a d d r e s s b7 b 0 N ote:The contents of PULL register A and PULL register B do not affect ports programmed as the output port.

Table 8. I/O ports functions Note 1: When using double-function ports as functional I/O pins, refer the method to the relevant sections. 2: Make sure that the input level at each pin is either 0 V or VCC during execution of the STP instruction. When an input level is at an intermediate potential, a current will flow from VCC to VSS through the input-stage gate.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 14 Port block diagram (1) ( 3 ) P o r t P 44 Pull-up control S e r i a l I / O e n a b l e b i t Serial I/O input D ata bus Direction register Port latch (4) Port P45 P u l l - u p c o n t r o l Direction register D ata bus Port latch Serial I/O output P 45/ TXD P - c h a n n e l o u t p u t d i s a b l e b i t Serial I/O enable bit Transmission enable bit (6) Port P47 Serial I/O ready output S e r i a l I / O m o d e s e l e c t i o n b i t S e r i a l I O e n a b l e b i t SR D Y o u t p u t e n a b l e b i t D a t a b u s Pull-up control D i r e c t i o n r e g i s t e r Port latch (7) Ports P52, P53 R eal time control bit P u l l - u p c o n t r o l D ata bus P o r t l a t c h D i r e c t i o n r e g i s t e r R eal time port data ( 1 ) P o r t s P 0 , P 10– P 15, P 3 VL 2/ VL 3/ VC C D a t a b u s P o r t l a t c h I n t e r f a c e l o g i c l e v e l s h i f t c i r c u i t Pull-down Port S e g m e n t VL 1/ VS S Segment/PortL C D d r i v e t i m i n g P o r t / S e g m e n t S e g m e n t d a t a P o r t O N / O F F ( 2 ) P o r t s P 16, P 17, P 2 , P 40– P 43, P 50, P 51 K e y - o n w a k e u p i n t e r r u p t i n p u t I N T0– I N i n t e r r u p t i n p u t Pull-up control D ata bus Port latch Direction register Except P16, P17, P40, P41 (5) Port P46 Serial I/O enable bit Serial I/O clock input Pull-up control D a t a b u s Serial I/O clock output Serial I/O synchronization clock selection bit D i r e c t i o n r e g i s t e r P o r t l a t c h Serial I/O mode selection bit Serial I/O enable bit R e c e p t i o n e n a b l e b i t

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 15 Port block diagram (2) ( 9 ) P o r t s P 55, P 57 D ata bus P u l l - u p c o n t r o l C N T R 1 i n t e r r u p t i n p u t A D t r i g g e r i n t e r r u p t i n p u t Direction register P o r t l a t c h (10) Port P6 D ata bus P u l l - u p c o n t r o l Direction register P o r t l a t c h A - D c o n v e r s i o n i n p u t A n a l o g i n p u t p i n s e l e c t i o n b i t ( 1 3 ) P o r t P 80 D a t a b u s P o r t X c s w i t c h b i t + P u l l - u p c o n t r o l Port XC switch bit O scillation circuit Port P81 Port XC switch bit D i r e c t i o n r e g i s t e r P o r t l a t c h ( 1 5 ) C O M 0– C O M 3 VL3 VL VL

1 The gate input signal of each

transistor is controlled by the LCD duty ratio and the bias value. VS S(16) SEG 0–SEG 17 T h e v o l t a g e a p p l i e d t o t h e s o u r c e s o f P c h a n n e l a n d N c h a n n e l t r a n s i s t o r s i s t h e c o n t r o l l e d v o l t a g e b y t h e b i a s v a l u e VL 2/ VL VL1/VSS P u l s e o u t p u t m o d e C N T R 0 i n t e r r u p t i n p u t T i m e r o u t p u t D i r e c t i o n r e g i s t e r P o r t l a t c hD a t a b u s P 54 o n l y ( 1 1 ) P o r t P 70 (12) Ports P71–P77 D a t a b u s Direction register P o r t l a t c h (14) Port P81 D ata bus P o r t XC s w i t c h b i t Sub-clock generating circuit input D i r e c t i o n r e g i s t e r Port latch Pull-up control D a t a b u s P u l l - u p c o n t r o l ( 8 ) P o r t s P 54, P 56 P o r t X c s w i t c h b i t + P u l l - u p c o n t r o l

Notes 1: Vector addresses contain interrupt jump destination addresses. 2: Reset function in the same way as an interrupt with the highest priority. Interrupt enable bits can be set or cleared by software. flag disables all interrupts except the BRK instruction interrupt. received according to priority.

1. The contents of the program counter and the processor status

register are automatically pushed onto the stack.

1. The interrupt disable flag is set and the corresponding interrupt
2. The interrupt jump destination address is read from the vector

table into the program counter. Table 9. Interrupt vector addresses and priority

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 16 Interrupt control Fig. 17 Structure of interrupt-related registers I n t e r r u p t r e q u e s t b i t I n t e r r u p t e n a b l e b i t I n t e r r u p t d i s a b l e f l a g ( I ) B R K i n s t r u c t i o n R e s e t I n t e r r u p t r e q u e s t b 7 b 0 I n t e r r u p t e d g e s e l e c t i o n r e g i s t e r I N T0 i n t e r r u p t e d g e s e l e c t i o n b i t I N i n t e r r u p t e d g e s e l e c t i o n b i t I N i n t e r r u p t e d g e s e l e c t i o n b i t I N i n t e r r u p t e d g e s e l e c t i o n b i t N o t u s e d r e t u r n w h e n r e a d (INTEDGE : address 003A16) I n t e r r u p t r e q u e s t r e g i s t e r 1 I N T0 i n t e r r u p t r e q u e s t b i t I N i n t e r r u p t r e q u e s t b i t S e r i a l I O r e c e i v e i n t e r r u p t r e q u e s t b i t S e r i a l I O t r a n s m i t i n t e r r u p t r e q u e s t b i t T i m e r X i n t e r r u p t r e q u e s t b i t T i m e r Y i n t e r r u p t r e q u e s t b i t T i m e r i n t e r r u p t r e q u e s t b i t T i m e r i n t e r r u p t r e q u e s t b i t I n t e r r u p t c o n t r o l r e g i s t e r 1 I N T0 i n t e r r u p t e n a b l e b i t I N i n t e r r u p t e n a b l e b i t S e r i a l I O r e c e i v e i n t e r r u p t e n a b l e b i t S e r i a l I O t r a n s m i t i n t e r r u p t e n a b l e b i t T i m e r X i n t e r r u p t e n a b l e b i t T i m e r Y i n t e r r u p t e n a b l e b i t T i m e r i n t e r r u p t e n a b l e b i t T i m e r i n t e r r u p t e n a b l e b i t 0 : N o i n t e r r u p t r e q u e s t i s s u e d I n t e r r u p t r e q u e s t i s s u e d ( I R E Q 1 : a d d r e s s 0 0 3 C 1 ( I C O N 1 : a d d r e s s 0 0 3 E1 I n t e r r u p t r e q u e s t r e g i s t e r 2 CNTR 0 interrupt request bit CNTR 1 interrupt request bit Timer 1 interrupt request bit INT2 interrupt request bit INT3 interrupt request bit Key input interrupt request bit ADT/AD conversion interrupt request bit Not used (returns “0” when read) ( I R E Q 2 : a d d r e s s 0 0 3 D 1 Interrupt control register 2 C N T R 0 i n t e r r u p t e n a b l e b i t C N T R 1 i n t e r r u p t e n a b l e b i t T i m e r i n t e r r u p t e n a b l e b i t I N i n t e r r u p t e n a b l e b i t I N i n t e r r u p t e n a b l e b i t K e y i n p u t i n t e r r u p t e n a b l e b i t A D T A D c o n v e r s i o n i n t e r r u p t e n a b l e b i t N o t u s e d r e t u r n s w h e n r e a d D o n o t w r i t e t o t h i s b i t 0 : I n t e r r u p t s d i s a b l e d I n t e r r u p t s e n a b l e d (ICON2 : address 003F16) 0 : F a l l i n g e d g e a c t i v e R i s i n g e d g e a c t i v e b 7 b 0 b7 b 0 b 7 b0 b7 b0 I Notes on interrupts When setting the followings, the interrupt request bit may be set to “1”.

• When setting external interrupt active edge Related register: Interrupt edge selection register (address 3A16) Timer X mode register (address 2716) Timer Y mode register (address 2816)
• When switching interrupt sources of an interrupt vector address where two or more interrupt sources are allocated Related register: A-D control regsiter (address 34 16) When not requiring for the interrupt occurrence synchronized with these setting, take the following sequence. ➀ Set the corresponding interrupt enable bit to “0” (disabled). ➁ Set the interrupt edge select bit or the interrupt source select bit to “1”. ➂ Set the corresponding interrupt request bit to “0” after 1 or more instructions have been executed. ➃ Set the corresponding interrupt enable bit to “1” (enabled).

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Key Input Interrupt (Key-on Wake Up) A Key-on wake up interrupt request is generated by applying a falling edge to any pin of port P2 that have been set to input mode. In other words, it is generated when AND of input level goes from “1” to “0”. An example of using a key input interrupt is shown in Figure 18, where an interrupt request is generated by pressing one of the keys consisted as an active-low key matrix which inputs to ports P2 0–P23. Fig. 18 Connection example when using key input interrupt and port P2 block diagram ✽ ✽ ✽ ✽ ✽ P o r t P 20 l a t c h Port P20 direction register = “0” P o r t P 21 l a t c h Port P21 direction register = “0” Port P22 latch Port P22 direction register = “0” P o r t P 23 l a t c h Port P23 direction register = “0” Port P24 latch Port P24 direction register = “1” Port P25 latch Port P25 direction register = “1” P o r t P 26 l a t c h P o r t P 26 d i r e c t i o n r e g i s t e r P o r t P 27 l a t c h P o r t P 27 d i r e c t i o n r e g i s t e r P 20 i n p u t P21 input P i n p u t P23 input P24 output P25 output P 6 o u t p u t P27 output P U L L r e g i s t e r A B i t Port P2 Input reading circuit P o r t P X x L l e v e l o u t p u t ✽ P c h a n n e l t r a n s i s t o r f o r p u l l u p C M O S o u t p u t b u f f e r K e y i n p u t i n t e r r u p t r e q u e s t

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS The 3825 group has five timers: timer X, timer Y, timer 1, timer 2, and timer 3. Timer X and timer Y are 16-bit timers, and timer 1, timer 2, and timer 3 are 8-bit timers. All timers are down count timers. When the timer reaches “00 16”, an underflow occurs at the next count pulse and the correspond- ing timer latch is reloaded into the timer and the count is contin- ued. When a timer underflows, the interrupt request bit corre- sponding to that timer is set to “1”. Read and write operation on 16-bit timer must be performed for both high- and low-order bytes. When reading a 16-bit timer, read the high-order byte first. When writing to a 16-bit timer, write the low-order byte first. The 16-bit timer cannot perform the correct op- eration when reading during the write operation, or when writing during the read operation. Fig. 19 Timer block diagram CNTR 0 active edge switch bit T i m e r 1 c o u n t s o u r c e s e l e c t i o n b i t R eal time port control bit “0” “ 1 ” P55/CNTR 1 “0” f(XIN)/16 (f(XCIN)/16 in low-speed mode]) C N T R 1 a c t i v e e d g e s w i t c h b i t “10” Timer Y stop control bit Falling edge detection Period measurement mode Timer Y interrupt request Pulse width HL continuously measurement mode Rising edge detection T i m e r Y o p e r a t i n g m o d e b i t s Timer X interrupt request Timer X mode register write signal P 54/ C N T R 0 Q Q T S P 54 d i r e c t i o n r e g i s t e r Pulse output mode P54 latch T i m e r X s t o p c o n t r o l b i t “0” “1” T i m e r X w r i t e c o n t r o l b i t Q D L a t c h Q D L a t c h “1” “0” “ 1 ” 1 0 ”Timer X operat- ing mode bits f ( XI N ) / 1 6 f XC I N ) i n l o w s p e e d m o d e✽) Pulse width measurement mode C N T R 0 a c t i v e e d g e s w i t c h b i t Pulse output mode Q Q T S “0” P56 direction register P 56 l a t c h“ 1 ” TO U T o u t p u t a c t i v e e d g e s w i t c h b i t T i m e r 2 w r i t e c o n t r o l b i t “0” “1” TOUT output control bit “ 1 ” P 56/ TO U T XCIN T i m e r 3 c o u n t s o u r c e s e l e c t i o n b i t “0” “ 1 ” Timer 2 interrupt request Timer 3 interrupt request TO U T o u t p u t c o n t r o l b i t Timer 2 count source selection bit Timer 1 interrupt request D a t a b u s f ( XI N ) / 1 6 f XC I N ) i n l o w s p e e d m o d e]) f(XIN)/16 (f(XCIN)/16 in low-speed mode]) f(XIN)/16(f(XCIN)/16 in low-speed mode]) ✽ Internal clock φ = XCIN/2. CNTR 0 interrupt request C N T R 1 i n t e r r u p t r e q u e s t Timer Y operating mode bits “11” P52 direction register “0” R e a l t i m e p o r t c o n t r o l b i t P52 P 52 l a t c h P 53 d i r e c t i o n r e g i s t e r “ 0 ” R eal time port control bit “1” P 53 P 53 l a t c h P 52 d a t a f o r r e a l t i m e p o r t P53 data for real time port Timer Y (low) (8) Timer Y (high) (8) Timer 3 latch (8) Timer 3 (8) T i m e r 1 l a t c h ( 8 ) Timer 1 (8) T i m e r 2 l a t c h ( 8 ) Timer 2 (8) T i m e r X l o w ) T i m e r X h i g h T i m e r X l o w l a t c h i m e r X h i g h l a t c h Timer Y (low) latch (8) Timer Y (high) latch (8)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Timer X is a 16-bit timer that can be selected in one of four modes and can be controlled the timer X write and the real time port by setting the timer X mode register. (1) Timer mode The timer counts f(XIN)/16 (or f(XCIN)/16 in low-speed mode). (2) Pulse output mode Each time the timer underflows, a signal output from the CNTR0 pin is inverted. Except for this, the operation in pulse output mode is the same as in timer mode. When using a timer in this mode, set the corresponding port P5 4 direction register to output mode. (3) Event counter mode The timer counts signals input through the CNTR0 pin. Except for this, the operation in event counter mode is the same as in timer mode. When using a timer in this mode, set the corre- sponding port P5 4 direction register to input mode. (4) Pulse width measurement mode The count source is f(XIN)/16 (or f(XCIN)/16 in low-speed mode). If CNTR 0 active edge switch bit is “0”, the timer counts while the in- put signal of CNTR0 pin is at “H ”. If it is “1”, the timer counts while the input signal of CNTR0 pin is at “L”. When using a timer in this mode, set the corresponding port P54 direction register to input mode. G Timer X Write Control If the timer X write control bit is “0”, when the value is written in the address of timer X, the value is loaded in the timer X and the latch at the same time. If the timer X write control bit is “1”, when the value is written in the address of timer X, the value is loaded only in the latch. The value in the latch is loaded in timer X after timer X underflows. If the value is written in latch only, unexpected value may be set in the high-order counter when the writing in high-order latch and the underflow of timer X are performed at the same timing. G Real Time Port Control While the real time port function is valid, data for the real time port are output from ports P5 2 and P5 3 each time the timer X underflows. (However, if the real time port control bit is changed from “0” to “1” after set of the real time port data, data are output independent of the timer X operation.) If the data for the real time port is changed while the real time port function is valid, the changed data are output at the next underflow of timer X. Before using this function, set the corresponding port direction registers to output mode. I Note on CNTR0 interrupt active edge selection CNTR 0 interrupt active edge depends on the CNTR0 active edge switch bit. Fig. 20 Structure of timer X mode register T i m e r X m o d e r e g i s t e r T X M a d d r e s s T i m e r X w r i t e c o n t r o l b i t W r i t e v a l u e i n l a t c h a n d c o u n t e r W r i t e v a l u e i n l a t c h o n l y R e a l t i m e p o r t c o n t r o l b i t R e a l t i m e p o r t f u n c t i o n i n v a l i d R e a l t i m e p o r t f u n c t i o n v a l i d P d a t a f o r r e a l t i m e p o r t P d a t a f o r r e a l t i m e p o r t T i m e r X o p e r a t i n g m o d e b i t s b b T i m e r m o d e P u l s e o u t p u t m o d e E v e n t c o u n t e r m o d e P u l s e w i d t h m e a s u r e m e n t m o d e C N T R 0 a c t i v e e d g e s w i t c h b i t C o u n t a t r i s i n g e d g e i n e v e n t c o u n t e r m o d e S t a r t f r o m H o u t p u t i n p u l s e o u t p u t m o d e M e a s u r e H p u l s e w i d t h i n p u l s e w i d t h m e a s u r e m e n t m o d e F a l l i n g e d g e a c t i v e f o r C N T R 0 i n t e r r u p t C o u n t a t f a l l i n g e d g e i n e v e n t c o u n t e r m o d e S t a r t f r o m L o u t p u t i n p u l s e o u t p u t m o d e M e a s u r e L p u l s e w i d t h i n p u l s e w i d t h m e a s u r e m e n t m o d e R i s i n g e d g e a c t i v e f o r C N T R 0 i n t e r r u p t T i m e r X s t o p c o n t r o l b i t C o u n t s t a r t C o u n t s t o p b7 b 0

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Timer Y is a 16-bit timer that can be selected in one of four modes. (1) Timer mode The timer counts f(XIN)/16 (or f(XCIN)/16 in low-speed mode). (2) Period measurement mode CNTR 1 interrupt request is generated at rising/falling edge of CNTR 1 pin input signal. Simultaneously, the value in timer Y latch is reloaded in timer Y and timer Y continues counting down. Ex- cept for the above-mentioned, the operation in period measure- ment mode is the same as in timer mode. The timer value just before the reloading at rising/falling of CNTR pin input signal is retained until the timer Y is read once after the reload. The rising/falling timing of CNTR 1 pin input signal is found by CNTR 1 interrupt. When using a timer in this mode, set the corre- sponding port P55 direction register to input mode. (3) Event counter mode The timer counts signals input through the CNTR1 pin. Except for this, the operation in event counter mode is the same as in timer mode. When using a timer in this mode, set the corre- sponding port P5 5 direction register to input mode. (4) Pulse width HL continuously measure- ment mode CNTR 1 interrupt request is generated at both rising and falling edges of CNTR1 pin input signal. Except for this, the operation in pulse width HL continuously measurement mode is the same as in period measurement mode. When using a timer in this mode, set the corresponding port P5 5 direction register to input mode. I Note on CNTR1 interrupt active edge selection CNTR 1 interrupt active edge depends on the CNTR1 active edge switch bit. However, in pulse width HL continuously measurement mode, CNTR 1 interrupt request is generated at both rising and falling edges of CNTR1 pin input signal regardless of the setting of CNTR 1 active edge switch bit. Fig. 21 Structure of timer Y mode register T i m e r Y m o d e r e g i s t e r T Y M a d d r e s s b 7 b 0 Not used (return “0” when read) Timer Y operating mode bits b5 b4 0 0 : Timer mode 0 1 : Period measurement mode 1 0 : Event counter mode 1 1 : Pulse width HL continuously measurement mode CNTR 1 active edge switch bit 0 : Count at rising edge in event counter mode Measure the falling edge to falling edge period in period measurement mode Falling edge active for CNTR 1 interrupt 1 : Count at falling edge in event counter mode Measure the rising edge period in period measurement mode Rising edge active for CNTR 1 interrupt Timer Y stop control bit 0 : Count start 1 : Count stop

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Timer 1, Timer 2, Timer 3 Timer 1, timer 2, and timer 3 are 8-bit timers. The count source for each timer can be selected by timer 123 mode register. The timer latch value is not affected by a change of the count source. How- ever, because changing the count source may cause an inadvert- ent count down of the timer. Therefore, rewrite the value of timer whenever the count source is changed. G Timer 2 Write Control If the timer 2 write control bit is “0”, when the value is written in the address of timer 2, the value is loaded in the timer 2 and the latch at the same time. If the timer 2 write control bit is “1”, when the value is written in the address of timer 2, the value is loaded only in the latch. The value in the latch is loaded in timer 2 after timer 2 underflows. G Timer 2 Output Control When the timer 2 (T OUT ) is output enabled, an inversion signal from pin TOUT is output each time timer 2 underflows. In this case, set the port P56 shared with the port TOUT to the out- put mode. I Note on Timer 1 to Timer 3 When the count source of timers 1 to 3 is changed, the timer counting value may be changed large because a thin pulse is gen- erated in count input of timer. If timer 1 output is selected as the count source of timer 2 or timer 3, when timer 1 is written, the counting value of timer 2 or timer 3 may be changed large be- cause a thin pulse is generated in timer 1 output. Therefore, set the value of timer in the order of timer 1, timer 2 and timer 3 after the count source selection of timer 1 to 3. Fig. 22 Structure of timer 123 mode register TOUT output active edge switch bit 0 : Start at “H ” output 1 : Start at “L” output TOUT output control bit 0 : TOUT output disabled 1 : TOUT output enabled Timer 2 write control bit 0 : Write data in latch and counter 1 : Write data in latch only Timer 2 count source selection bit 0 : Timer 1 output 1 : f(X IN)/16 (or f(XCIN)/16 in low-speed mode) Timer 3 count source selection bit 0 : Timer 1 output 1 : f(X IN)/16 (or f(XCIN)/16 in low-speed mode) Timer 1 count source selection bit 0 : f(XIN)/16 (or f(XCIN)/16 in low-speed mode) 1 : f(XCIN) Not used (return “0” when read) T i m e r 1 2 3 m o d e r e g i s t e r T M a d d r e s s N o t e : I n t e r n a l c l o c k φ i s f ( XC I N ) / 2 i n t h e l o w - s p e e d m o d e . b 7 b0

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Serial I/O can be used as either clock synchronous or asynchro- nous (UART) serial I/O. A dedicated timer (baud rate generator) is also provided for baud rate generation. (1) Clock Synchronous Serial I/O Mode Clock synchronous serial I/O mode can be selected by setting the mode selection bit of the serial I/O control register to “1”. For clock synchronous serial I/O, the transmitter and the receiver must use the same clock. If an internal clock is used, transfer is started by a write signal to the TB/RB (address 0018 16). Fig. 23 Block diagram of clock synchronous serial I/O Fig. 24 Operation of clock synchronous serial I/O function P 46/ SC L K P 47/ SR D Y P 44/ R XD P45/TXD f ( XI N ) 1 / 4 F / F S e r i a l I O s t a t u s r e g i s t e r Serial I/O control register R e c e i v e b u f f e r r e g i s t e r A d d r e s s 0 0 1 81 Receive shift register R eceive buffer full flag (RBF) R e c e i v e i n t e r r u p t r e q u e s t ( R I ) Clock control circuit S h i f t c l o c k Serial I/O synchronization clock selection bit Frequency division ratio 1/(n+1) B a u d r a t e g e n e r a t o r Address 001C 16 BRG count source selection bit Clock control circuitF a l l i n g e d g e d e t e c t o r D ata bus Address 001816 S h i f t c l o c k Transmit shift register shift completion flag (TSC) Transmit buffer empty flag (TBE) Transmit interrupt request (TI) Transmit interrupt source selection bit A d d r e s s 0 0 1 91 D ata bus A d d r e s s 0 0 1 A1 T r a n s m i t b u f f e r r e g i s t e r ( T B ) T r a n s m i t s h i f t r e g i s t e r ( f ( XC I N ) i n l o w - s p e e d m o d e ) R e c e i v e e n a b l e s i g n a l SR D Y D 7D 0 D 1 D 2 D 3 D 4 D 5 D 6 RBF = 1 TSC = 1T B E = 0 TBE = 1 TSC = 0 T r a n s f e r s h i f t c l o c k t o o f t h e i n t e r n a l c l o c k o r a n e x t e r n a l c l o c k Serial output TXD S e r i a l i n p u t R XD W r i t e s i g n a l t o r e c e i v e / t r a n s m i t b u f f e r r e g i s t e r a d d r e s s O verrun error (OE) detection N o t e s 1 : T h e t r a n s m i t i n t e r r u p t ( T I ) c a n b e g e n e r a t e d e i t h e r w h e n t h e t r a n s m i t b u f f e r r e g i s t e r h a s e m p t i e d ( T B E = 1 ) o r a f t e r t h e t r a n s m i t s h i f t o p e r a t i o n h a s e n d e d T S C b y s e t t i n g t h e t r a n s m i t i n t e r r u p t s o u r c e s e l e c t i o n b i t T I C o f t h e s e r i a l I O c o n t r o l r e g i s t e r I f d a t a i s w r i t t e n t o t h e t r a n s m i t b u f f e r r e g i s t e r w h e n T S C t h e t r a n s m i t c l o c k i s g e n e r a t e d c o n t i n u o u s l y a n d s e r i a l d a t a i s o u t p u t c o n t i n u o u s l y f r o m t h e TXD p i n T h e r e c e i v e i n t e r r u p t R I i s s e t w h e n t h e r e c e i v e b u f f e r f u l l f l a g R B F b e c o m e s D 7D 0 D 1 D 2 D 3 D 4 D 5 D 6

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS (2) Asynchronous Serial I/O (UART) Mode Clock asynchronous serial I/O mode (UART) can be selected by clearing the serial I/O mode selection bit of the serial I/O control register to “0”. Eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. The transmit and receive shift registers each have a buffer regis- ter, but the two buffers have the same address in memory. Since the shift register cannot be written to or read from directly, transmit data is written to the transmit buffer, and receive data is read from the receive buffer. The transmit buffer can also hold the next data to be transmitted, and the receive buffer register can hold a character while the next character is being received. Fig. 25 Block diagram of UART serial I/O Fig. 26 Operation of UART serial I/O function f(XIN) O E P E F E D ata bus R e c e i v e b u f f e r r e g i s t e r A d d r e s s 0 0 1 81 R e c e i v e s h i f t r e g i s t e r R e c e i v e b u f f e r f u l l f l a g ( R B F ) R e c e i v e i n t e r r u p t r e q u e s t ( R I ) Baud rate generator Frequency division ratio 1/(n+1) Address 001C 16 ST/SP/PA generator Transmit buffer register D ata bus T r a n s m i t s h i f t r e g i s t e r Address 001816 Transmit shift register shift completion flag (TSC) Transmit buffer empty flag (TBE) Transmit interrupt request (TI) Address 001916 S T d e t e c t o r S P d e t e c t o r U A R T c o n t r o l r e g i s t e r Address 001B16 C h a r a c t e r l e n g t h s e l e c t i o n b i t A d d r e s s 0 0 1 A1 B R G c o u n t s o u r c e s e l e c t i o n b i t Transmit interrupt source selection bit Serial I/O synchronization clock selection bit C l o c k c o n t r o l c i r c u i t C h a r a c t e r l e n g t h s e l e c t i o n b i t b i t s b i t s S e r i a l I / O c o n t r o l r e g i s t e r P 46/ SC L K Serial I/O status register P44/R XD P45/TXD ( f ( XC I N ) i n l o w - s p e e d m o d e T S C = 0 T B E RBF =0 T B E = 0 TBE =0 R B F = 1 R B F = 1 S TD 0 D 1 S P D 0 D 1S T SP TBE =1 TSC=1 ✽ STD 0 D 1 SP D 0 D 1ST S P T r a n s m i t b u f f e r w r i t e s i g n a l ✽ Generated at 2nd bit in 2-stop-bit mode 1 s t a r t b i t o r d a t a b i t s o r p a r i t y b i t o r s t o p b i t s 1 : E r r o r f l a g d e t e c t i o n o c c u r s a t t h e s a m e t i m e t h a t t h e R B F f l a g b e c o m e s “ 1 ” ( a t 1 s t s t o p b i t , d u r i n g r e c e p t i o n ) . T h e t r a n s m i t i n t e r r u p t T I c a n b e g e n e r a t e d t o o c c u r w h e n e i t h e r t h e T B E o r T S C f l a g b e c o m e s d e p e n d i n g o n t h e s e t t i n g o f t h e t r a n s m i t i n t e r r u p t s o u r c e s e l e c t i o n b i t T I C o f t h e s e r i a l I O c o n t r o l r e g i s t e r T h e r e c e i v e i n t e r r u p t R I i s s e t w h e n t h e R B F f l a g b e c o m e s A f t e r d a t a i s w r i t t e n t o t h e t r a n s m i t b u f f e r r e g i s t e r w h e n T S C t o c y c l e s o f t h e d a t a s h i f t c y c l e i s n e c e s s a r y u n t i l c h a n g i n g t o T S C N o t e s Serial output TXD S e r i a l i n p u t R XD R e c e i v e b u f f e r r e a d s i g n a l T r a n s m i t o r r e c e i v e c l o c k

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS [Transmit Buffer/Receive Buffer Register (TB/ RB)] 001816 The transmit buffer register and the receive buffer register are lo- cated at the same address. The transmit buffer register is write- only and the receive buffer register is read-only. If a character bit length is 7 bits, the MSB of data stored in the receive buffer regis- ter is “0”. [Serial I/O Status Register (SIOSTS)] 001916 The read-only serial I/O status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial I/O function and various errors. Three of the flags (bits 4 to 6) are valid only in UART mode. The receive buffer full flag (bit 1) is cleared to “0” when the receive buffer is read. If there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer reg- ister, and the receive buffer full flag is set. A write to the serial I/O status register clears all the error flags OE, PE, FE, and SE (bit 3 to bit 6, respectively). Writing “0” to the serial I/O enable bit SIOE (bit 7 of the Serial I/O Control Register) also clears all the status flags, including the error flags. All bits of the serial I/O status register are initialized to “0” at reset, but if the transmit enable bit (bit 4) of the serial I/O control register has been set to “1”, the transmit shift register shift completion flag (bit 2) and the transmit buffer empty flag (bit 0) become “1”. [Serial I/O Control Register (SIOCON)] 001A16 The serial I/O control register contains eight control bits for the se- rial I/O function. [UART Control Register (UARTCON)] 001B16 The UART control register consists of four control bits (bits 0 to 3) which are valid when asynchronous serial I/O is selected and set the data format of an data transfer. One bit in this register (bit 4) is always valid and sets the output structure of the P4 5/TXD pin. [Baud Rate Generator (BRG)] 001C16 The baud rate generator determines the baud rate for serial trans- fer. The baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate genera- tor. I Notes on serial I/O When setting the transmit enable bit to “1”, the serial I/O transmit interrupt request bit is automatically set to “1”. When not requiring the interrupt occurrence synchronized with the transmission enalbed, take the following sequence. ➀ Set the serial I/O transmit interrupt enable bit to “0” (disabled). ➁ Set the transmit enable bit to “1”. ➂ Set the serial I/O transmit interrupt request bit to “0” after 1 or more instructions have been executed. ➃ Set the serial I/O transmit interrupt enable bit to “1” (enabled).

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 27 Structure of serial I/O control registers B R G c o u n t s o u r c e s e l e c t i o n b i t ( C S S ) f XI N ) f XC I N ) i n l o w s p e e d m o d e f XI N ) f XC I N ) i n l o w s p e e d m o d e S e r i a l I O s y n c h r o n i z a t i o n c l o c k s e l e c t i o n b i t S C S B R G o u t p u t d i v i d e d b y w h e n c l o c k s y n c h r o n i z e d s e r i a l I O i s s e l e c t e d B R G o u t p u t d i v i d e d b y w h e n U A R T i s s e l e c t e d E x t e r n a l c l o c k i n p u t w h e n c l o c k s y n c h r o n i z e d s e r i a l I O i s s e l e c t e d E x t e r n a l c l o c k i n p u t d i v i d e d b y w h e n U A R T i s s e l e c t e d SR D Y o u t p u t e n a b l e b i t S R D Y P p i n o p e r a t e s a s o r d i n a r y I O p i n P p i n o p e r a t e s a s SR D Y o u t p u t p i n T r a n s m i t i n t e r r u p t s o u r c e s e l e c t i o n b i t T I C I n t e r r u p t w h e n t r a n s m i t b u f f e r h a s e m p t i e d I n t e r r u p t w h e n t r a n s m i t s h i f t o p e r a t i o n i s c o m p l e t e d T r a n s m i t e n a b l e b i t T E T r a n s m i t d i s a b l e d T r a n s m i t e n a b l e d R e c e i v e e n a b l e b i t R E R e c e i v e d i s a b l e d R e c e i v e e n a b l e d S e r i a l I O m o d e s e l e c t i o n b i t S I O M A s y n c h r o n o u s s e r i a l I O U A R T C l o c k s y n c h r o n o u s s e r i a l I O S e r i a l I O e n a b l e b i t S I O E S e r i a l I O d i s a b l e d p i n s P 44– P o p e r a t e a s o r d i n a r y I O p i n s S e r i a l I O e n a b l e d p i n s P 44– P o p e r a t e a s s e r i a l I O p i n s Serial I/O control register (SIOCON : address 001A16) b7 b0 T r a n s m i t b u f f e r e m p t y f l a g ( T B E ) B u f f e r f u l l B u f f e r e m p t y R e c e i v e b u f f e r f u l l f l a g R B F B u f f e r e m p t y B u f f e r f u l l T r a n s m i t s h i f t r e g i s t e r s h i f t c o m p l e t i o n f l a g T S C T r a n s m i t s h i f t i n p r o g r e s s T r a n s m i t s h i f t c o m p l e t e d O v e r r u n e r r o r f l a g O E N o e r r o r O v e r r u n e r r o r P a r i t y e r r o r f l a g P E N o e r r o r P a r i t y e r r o r F r a m i n g e r r o r f l a g F E N o e r r o r F r a m i n g e r r o r S u m m i n g e r r o r f l a g S E O E U P E U F E O E U P E U F E N o t u s e d r e t u r n s w h e n r e a d S e r i a l I / O s t a t u s r e g i s t e r S I O S T S a d d r e s s b7 b0 U A R T c o n t r o l r e g i s t e r U A R T C O N a d d r e s s B Ch aracter length selection bit (CHAS) 0: 8 bits 1: 7 bits Parity enable bit (PARE) 0: Parity checking disabled 1: Parity checking enabled Parity selection bit (PARS) 0: Even parity 1: Odd parity Stop bit length selection bit (STPS) 0: 1 stop bit 1: 2 stop bits 5/TXD P-channel output disable bit (POFF) 0: CMOS output (in output mode) 1: N-channel open-drain output (in output mode) Not used (return “1” when read) b7 b0

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS The functional blocks of the A-D converter are described below. [A-D Conversion Register (AD)] 003516 The A-D conversion register is a read-only register that contains the result of an A-D conversion. When reading this register during an A-D conversion, the previous conversion result is read. [A-D Control Register (ADCON)] 003416 The A-D control register controls the A-D conversion process. Bits 0 to 2 of this register select specific analog input pins. Bit 3 signals the completion of an A-D conversion. The value of this bit remains at “0” during an A-D conversion, then changes to “1” when the A- D conversion is completed. Writing “0” to this bit starts the A-D conversion. Bit 4 controls the transistor which breaks the through current of the resistor ladder. When bit 5, which is the AD external trigger valid bit, is set to “1”, this bit enables A-D conversion even by a falling edge of an ADT input. Set ports which share with ADT pins to input when using an A-D external trigger. Comparison Voltage Generator The comparison voltage generator divides the voltage between AV SS and VREF by 256, and outputs the divided voltages. Channel Selector The channel selector selects one of the input ports P67/AN7–P6 0/ AN 0. Comparator and Control Circuit The comparator and control circuit compare an analog input volt- age with the comparison voltage and store the result in the A-D conversion register. When an A-D conversion is completed, the control circuit sets the AD conversion completion bit and the AD interrupt request bit to “1”. Note that the comparator is constructed linked to a capacitor, so set f(X IN) to at least 500kHz during A-D conversion. Use the clock divided from the main clock XIN as the internal clock Fig. 29 A-D converter block diagram Fig. 28 Structure of A-D control register A - D c o n t r o l r e g i s t e r A D C O N a d d r e s s A D c o n v e r s i o n c o m p l e t i o n b i t C o n v e r s i o n i n p r o g r e s s C o n v e r s i o n c o m p l e t e d A n a l o g i n p u t p i n s e l e c t i o n b i t s P 60/ A N 0 P 61/ A N 1 P 62/ A N 2 P 63/ A N 3 P 64/ A N 4 P 65/ A N 5 P 66/ A N 6 P 67/ A N 7 VR E F i n p u t s w i t c h b i t O F F O N A D e x t e r n a l t r i g g e r v a l i d b i t A D e x t e r n a l t r i g g e r i n v a l i d A D e x t e r n a l t r i g g e r v a l i d b7 b 0 I n t e r r u p t s o u r c e s e l e c t i o n b i t I n t e r r u p t r e q u e s t a t A D c o n v e r s i o n c o m p l e t e d I n t e r r u p t r e q u e s t a t A D T i n p u t f a l l i n g N o t u s e d ( r e t u r n s “ 0 ” w h e n r e a d ) C o m p a r a t o r A - D c o n t r o l c i r c u i t A D T / A - D i n t e r r u p t r e q u e s t AV SS VR E F P 60/ A N 0 D a t a b u s A - D c o n t r o l r e g i s t e r b 7 b 0 A-D conversion register R esistor ladder C h a n n e l s e l e c t o r P 67/ A N 7 P 66/ A N 6 P 65/ A N 5 P 64/ A N 4 P 63/ A N 3 P 62/ A N 2 P 61/ A N 1 P 57/ A D T

control circuit consisting of the following.

• LCD display RAM
• Segment output enable register
• LCD mode register
• Voltage multiplier
• Selector
• Timing controller
• Common driver
• Segment driver
• Bias control circuit A maximum of 40 segment output pins and 4 common output pins can be used. Up to 160 pixels can be controlled for LCD display. When the LCD Fig. 30 Structure of segment output enable register and LCD mode register enable bit is set to “1” after data is set in the LCD mode register, the segment output enable register and the LCD display RAM, the LCD drive control circuit starts reading the display data automati- cally, performs the bias control and the duty ratio control, and dis- plays the data on the LCD panel.

Table 10. Maximum number of display pixels at each duty ratio N o t e : L C D C K i s a c l o c k f o r a L C D t i m i n g c o n t r o l l e r .

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 31 Block diagram of LCD controller/driver D a t a b u s T i m i n g c o n t r o l l e r L C D d i v i d e r f ( XI N ) / 8 1 9 2 f XC I N ) i n l o w s p e e d m o d e f ( XC I N ) / 3 2 C O M 0 C O M 1 C O M 2 C O M 3VS S VL 1 VL 2 VL E G E G E G E G A d d r e s s 0 0 4 01

6 A d d r e s s 0 0 4 11

1 ” 0 ” L C D C K L C D C K c o u n t s o u r c e s e l e c t i o n b i t L C D c i r c u i t d i v i d e r d i v i s i o n r a t i o s e l e c t i o n b i t s B i a s c o n t r o l b i t L C D e n a b l e b i t D u t y r a t i o s e l e c t i o n b i t s 2 2 S e l e c t o rS e l e c t o rS e l e c t o r S e l e c t o r S e l e c t o rS e l e c t o r L C D d i s p l a y R A MA d d r e s s 0 0 5 3 P 4/ S E G 3 0/ S E G 1 8 P 5/ S E G 3 L e v e l s h i f t L e v e l s h i f t L e v e l s h i f t L e v e l s h i f t L e v e l s h i f t L e v e l s h i f t C o m m o n d r i v e r C o m m o n d r i v e r C o m m o n d r i v e r C o m m o n d r i v e r C 1 C 2 V o l t a g e m u l t i p l i e r c o n t r o l b i t L e v e l S h i f t L e v e l S h i f t L e v e l S h i f t L e v e l S h i f t S e g m e n t d r i v e r S e g m e n t d r i v e r S e g m e n t d r i v e r S e g m e n t d r i v e r S e g m e n t d r i v e r S e g m e n t d r i v e r B i a s c o n t r o l

controls the voltage multiplier. in Table 11 according to the bias value. Table 11. Bias control and applied voltage to VL1–VL3 Table 12. Duty ratio control and common pins used Notes 1: COM 2 and COM 3 are open.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Address 004016 to 005316 is the designated RAM for the LCD dis- play. When “1” are written to these addresses, the corresponding segments of the LCD display panel are turned on. LCD Drive Timing The LCDCK timing frequency (LCD drive timing) is generated in- ternally and the frame frequency can be determined with the fol- lowing equation; (frequency of count source for LCDCK) (divider division ratio for LCD)f(LCDCK)= f(LCDCK) duty ratioFrame frequency= Fig. 33 LCD display RAM map 0 0 4 01 C 1 D 1 B i t Address S E G 1 S E G 3 S E G 5 S E G 7 S E G 9 S E G 1 S E G 1 S E G 1 S E G 1 S E G 1 S E G 2 S E G 2 S E G 2 S E G 2 S E G 2 S E G 3 S E G 3 S E G 3 S E G 3 S E G 3 76543210 C O M 3 COM 0C O M 2 COM 1 C O M 0 C O M 3 C O M 2 C O M 1 S E G 0 S E G 2 S E G 4 S E G 6 S E G 8 S E G 1 S E G 1 S E G 1 S E G 1 S E G 1 S E G 2 S E G 2 S E G 2 S E G 2 S E G 2 S E G 3 S E G 3 S E G 3 S E G 3 S E G 3

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 34 LCD drive waveform (1/2 bias) Internal logic LCDCK timing 1 / 4 d u t y V o l t a g e l e v e l VL VL 2= VL VS S VL VS S C O M C O M C O M C O M SEG 0 OFF ON OFF ON COM 3 COM 2 COM 1 COM 0 COM 3 COM 2 COM 1 COM 0 / 3 d u t y VL3 VL2=VL1 VSS VL3 VSS O F F O N ON O F F O NO F F / 2 d u t y COM C O M C O M S E G C O M C O M S E G VL VL 2= VL VS S VL VS S O F F O N OFF ON OFFO N OFFO N C O M 0 C O M

2 COM 1 COM 0 COM 2 COM 1 COM 0 C

C O M 1 C O M

0 COM 1 COM 0 COM 1 COM 0 COM 1 C

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 35 LCD drive waveform (1/3 bias) I n t e r n a l l o g i c L C D C K t i m i n g 1 / 4 d u t y V o l t a g e l e v e l VL VS S C O M C O M C O M C O M S E G OFF ON OFF ON COM 3 C O M

2 COM 1 C

0 COM 3 COM 2 C

/ 3 d u t y OFFO N O NO F F O NO F F 1/2 duty COM 0 COM 1 C O M SEG 0 C O M COM 1 S E G OFFO N O F F O N O F F O N O F FON VL3 VL2 VSS VL1 VL3 VL2 VSS VL1 VL VSS VL3 VL2 VSS VL1 VL3 VSS C O M 0 C O M

0 COM 1 COM 0 COM 1 COM 0

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Input/output ports P40 and P41 can output clock. The input/output ports and clock output function are put under double function con- trolled by the clock output control register (address 002A16). Selection of Input/Output Ports and Clock Output Function Bits 0 and 1 of the clock output control register can select between the input/output ports and the clock output function. When selecting the clock output function, clocks are output while the direction register of ports P4 0 and P41 are set to output. At the next cycle of rewriting the clock output control bit, P40 is switched between the port output and the clock output. In synchronization with the fall of the clock (resulting from dividing XIN by 5) on rewriting the clock output control bit, P41 is switched between the port output and the clock output. Fig. 37 Clock output function block diagram Fig. 36 Structure of clock output control register Selection of Output Clock Frequency Bit 2 (output clock frequency selection bit) of the clock output con- trol register selects an output clock frequency. When setting the output clock frequency selection bit to “0”, port 0 becomes the frequency of f(XIN) and port P41 becomes the frequency of f(XIN)/5. At this time, the output pulse of port P40 depends on the XIN input pulse, while the output pulse of port P41 has duty ratio of about 40%. When setting the output clock frequency selection bit to “1”, port 0 becomes the frequency of f(XIN)/2 and port P41 becomes the frequency of f(XIN)/10. At this time, the output pulses of both ports P40 and P41 have duty ratio of 50%. P40 clock output control bit 0 : I/O port 1 : Clock output P41 clock output control bit 0 : I/O port 1 : Clock output Output clock frequency selection bit 0 : P4 0← f(XIN), P41← f(XIN)/5 1 : P40← f(XIN)/2, P41← f(XIN)/10 Not used (return “0” when read) Clock output control register (TCON : address 002A16) b 7 b 0 P40 1 / 2 P 40 d i r e c t i o n r e g i s t e r P 40 c l o c k o u t p u t c o n t r o l b i t“0” “1” P40 port latch “0” “1” O u t p u t c l o c k f r e q u e n c y s e l e c t i o n b i t XIN P41 1 / 2 P 41 d i r e c t i o n r e g i s t e r P 41 c l o c k o u t p u t c o n t r o l b i t“ 0 ” 1 ” P 41 p o r t l a t c h 0 ” 1 ” O utput clock frequency selection bit

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 39 Internal state of microcomputer immediately after re- set Fig. 38 Example of reset circuit RESET CIRCUIT To reset the microcomputer, RESET pin should be held at an “L” level for 2 µs or more. Then the RESET pin is returned to an “H ” level (the power source voltage should be between VCC (min.) and

5.5 V, and the quartz-crystal oscillator should be stable), reset is

released. After the reset is completed, the program starts from the address contained in address FFFD 16 (high-order byte) and ad- dress FFFC16 (low-order byte). Make sure that the reset input voltage meets VIL spec. when a power source voltage passes VCC (min.). P o w e r o n P o w e r s o u r c e v o l t a g e R e s e t i n p u t v o l t a g e Power source voltage detection circuit VI L s p e c . 0 V V VCCR E S E T VCCRESET N ote: The contents of all other registers and RAM are undefined after reset, so they must be initialized by software. ✕ : Undefined R e g i s t e r c o n t e n t sA d d r e s s 000016 000216 000316 000416 000516 000616 000816 000916 000A16 000B16 0 0 0 C 1 0 0 0 D 1 000E16 0 0 0 F1 001016 001116 001616 001716 001916 001A16 001B16 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 003416 003816 003916 003A16 003B16 0 0 3 C 1 0 0 3 D 1 003E16 0 0 3 F1 ( P S ) ( P C H ) ( P C L) ( 1 0 ) ( 1 1 ) ( 1 2 ) ( 1 3 ) ( 1 4 ) ( 1 5 ) ( 1 6 ) ( 1 7 ) ( 1 8 ) ( 1 9 ) ( 2 0 ) (21) (22) (23) (24) (25) ( 2 6 ) ( 2 7 ) ( 2 8 ) ( 2 9 ) ( 3 0 ) ( 3 1 ) ( 3 2 ) ( 3 3 ) ( 3 4 ) ( 1 ) ( 2 ) ( 3 ) ( 4 ) ( 5 ) ( 6 ) ( 7 ) ( 8 ) ( 9 ) ( 3 5 ) ( 3 6 ) ( 3 7 ) ( 3 8 ) ( 3 9 ) ( 4 0 ) ( 4 1 ) ( 4 2 ) ( 4 3 ) Timer Y (low) Port P5 direction register Port P6 Port P6 direction register PULL register B Timer Y (high) Serial I/O control register UART control register Timer X (high) Timer X (low) Timer X mode register Timer Y mode register Timer 123 mode register Serial I/O status register Port P7 Port P7 direction register Port P8 A-D control register Segment output enable register LCD mode register PULL register A Interrupt edge selection register CPU mode register Interrupt request register 1 Interrupt request register 2 Interrupt control register 1 Interrupt control register 2 Processor status register Program counter Port P5 Port P4 direction register Port P4 Port P3 Port P2 direction register Port P2 Port P1 output control register Port P1 Port P0 Port P8 direction register Timer 1 Timer 2 Timer 3 Clock output control register 111000 0 0 100000 0 0 000010 0 0 1 0 0 1 000 0 0 01 0016 0016 0016 F F1 F F1 F F1 F F1 F F1 FF16 0016 0016 0016 0016 0016 C o n t e n t s o f a d d r e s s F F F D 1 C o n t e n t s o f a d d r e s s F F F C 1

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 40 Reset sequence AD L FFFC FFFD A D H ,? ? ? ? XIN : about 8000 clock cycles N o t e s 1 : XI N a n d φ a r e i n t h e r e l a t i o n s h i p f ( XI N ) = 8 • f (φ) A q u e s t i o n m a r k i n d i c a t e s a n u n d e f i n e d s t a t u s t h a t d e p e n d s o n t h e p r e v i o u s s t a t u s R e s e t a d d r e s s f r o m v e c t o r t a b l e R E S E T I n t e r n a l r e s e t A d d r e s s D a t a S Y N C φ XI N A D H A D L

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS The 3825 group has two built-in oscillation circuits. An oscillation circuit can be formed by connecting a resonator between XIN and XOUT (XCIN and XCOUT ). Use the circuit constants in accordance with the resonator manufacturer's recommended values. No exter- nal resistor is needed between XIN and XOUT since a feed-back resistor exists on-chip. However, an external feed-back resistor is needed between X CIN and XCOUT . To supply a clock signal externally, input it to the XIN pin and make the XOUT pin open. The sub-clock XCIN-XCOUT oscillation circuit cannot directly input clocks that are externally generated. Accord- ingly, be sure to cause an external resonator to oscillate. Immediately after poweron, only the X IN oscillation circuit starts oscillating, and XCIN and XCOUT pins function as I/O ports. Frequency Control (1) Middle-speed mode The internal clock φ is the frequency of XIN divided by 8. After reset, this mode is selected. (2)High-speed mode The internal clock φ is half the frequency of XIN. (3) Low-speed mode

• The internal clock φ is half the frequency of XCIN.
• A low-power consumption operation can be realized by stopping the main clock XIN in this mode. To stop the main clock, set bit 5 of the CPU mode register to “1”. When the main clock XIN is restarted, set enough time for oscil- lation to stabilize by programming. Note: If you switch the mode between middle/high-speed and low- speed, stabilize both XIN and XCIN oscillations. The suffi- cient time is required for the sub-clock to stabilize, espe- cially immediately after power-on and at returning from stop mode. When switching the mode between middle/high- speed and low-speed, set the frequency in the condition that f(X IN) > 3•f(XCIN). Fig. 41 Ceramic resonator circuit Fig. 42 External clock input circuit Oscillation Control (1) Stop mode If the STP instruction is executed, the internal clock φ stops at an “H ” level, and XIN and XCIN oscillators stop. Timer 1 is set to “FF16” and timer 2 is set to “0116”. Either XIN or XCIN divided by 16 is input to timer 1 as count source, and the output of timer 1 is connected to timer 2. The bits of the timer 123 mode register except bit 4 are cleared to “0”. Set the timer 1 and timer 2 interrupt enable bits to disabled (“0”) before executing the STP instruction. Oscillator restarts at reset or when an external interrupt is re- ceived, but the internal clock φ is not supplied to the CPU until timer 2 underflows. This allows time for the clock circuit oscillation to stabilize. (2) Wait mode If the WIT instruction is executed, the internal clock φ stops at an “H ” level. The states of XIN and XCIN are the same as the state be- fore the executing the WIT instruction. The internal clock restarts at reset or when an interrupt is received. Since the oscillator does not stop, normal operation can be started immediately after the clock is restarted. XC I N C I N C O U TC C I N C C O U T R f Rd XC O U T XI N XO U T XI N XO U T External oscillation circuit O p e n V CC VS S C C I N C C O U T Rf R d X C I N XC O U T

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 43 Clock generating circuit block diagram W I T i n s t r u c t i o n STP instruction Tim ing φ (Internal clock) S R Q STP instruction S R Q M a i n c l o c k s t o p b i t S R Q T i m e r 2Timer 11 / 2 1/4 XI N XO U T XCOUTXC I N Interrupt request R eset P o r t XC s w i t c h b i t 1 ”“ 0 ” T i m e r 1 c o u n t s o u r c e s e l e c t i o n b i t Timer 2 count source selection bit L o w - s p e e d m o d e M i d d l e - / H i g h - s p e e d m o d e I n t e r n a l s y s t e m c l o c k s e l e c t i o n b i t N o t e Middle-speed mode H i g h - s p e e d m o d e o r L o w s p e e d m o d e N ote: Wh en using the low-speed mode, set the port XC switch bit to “1”. M ain clock division ratio selection bit “ 1 ” 0 ” “1” “0” “ 1 ” “0” I n t e r r u p t d i s a b l e f l a g I / 2 “1” 0 ”

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 44 State transitions of internal clock φ N otes1: Sw itch the mode by the allows shown between the mode blocks. (Do not switch between the mode directly without an allow.) 2: The all modes can be switched to the stop mode or the wait mode and returned to the source mode when the stop mode or the wait mode is ended. 3: Timer and LCD operate in the wait mode. 4: When the stop mode is ended, a delay of approximately 1 ms occurs automatically by timer 1 and timer 2 in middle-/high-speed mode. 5: When the stop mode is ended, a delay of approximately 0.25 s occurs automatically by timer 1 and timer 2 in low-speed mode. 6: Wait until oscillation stabilizes after oscillating the main clock XIN before the switching from the low-speed mode to middle-/high- speed mode. 7: The example assumes that 8 MHz is being applied to the XIN pin and 32 kHz to the XCIN pin. f indicates the internal clock. CM 4 : Port Xc switch bit 0: I/O port 1: XCIN, XCOUT CM 5 : Main clock (XIN–XOUT ) stop bit 0: Oscillating 1: Stopped CM 6 : Main clock division ratio selection bit 0: f(XIN)/2 (high-speed mode) 1: f(XIN)/8 (middle-speed mode) CM 7 : Internal system clock selection bit 0: XIN–XOUT selected (middle-/high-speed mode) 1: X CIN–XCOUT selected (low-speed mode) CPU mode register (CPUM : address 003B16) b7 b4 R e s e t C M 6 “0”“ 1 ” C M 0 ”“ 1 ” C M 7 M H z s e l e c t e d C M 6 M i d d l e s p e e d C M 5 M H z o s c i l l a t i n g C M 4 k H z s t o p p e d M i d d l e s p e e d m o d e f (φ) M H z C M = 0 ( 8 M H z s e l e c t e d ) C M 6 M i d d l e s p e e d C M 5 M H z o s c i l l a t i n g C M 4 k H z o s c i l l a t i n g Middle-speed mode (f(φ) = 1 MHz) CM 7 = 0 (8 MHz selected) CM 6 = 0 (High-speed) CM 5 = 0 (8 MHz oscillating) CM 4 = 0 (32 kHz stopped) High-speed mode (f(φ) = 4 MHz) CM 7 = 0 (8 MHz selected) CM 6 = 0 (High-speed) CM 5 = 0 (8 MHz oscillating) CM 4 = 1 (32 kHz oscillating) H i g h s p e e d m o d e f (φ) M H z CM 7 = 1 (32 kHz selected) CM 6 = 1 (Middle-speed) CM 5 = 0 (8 MHz oscillating) CM 4 = 1 (32 kHz oscillating) Low-speed mode (f(φ) =16 kHz) CM 7 = 1 (32 kHz selected) CM 6 = 0 (High-speed) CM 5 = 0 (8 MHz oscillating) CM 4 = 1 (32 kHz oscillating) Low-speed mode (f(φ) =16 kHz) CM 7 = 1 (32 kHz selected) CM 6 = 1 (Middle-speed) CM 5 = 1 (8 MHz stopped) CM 4 = 1 (32 kHz oscillating) L o w - s p e e d m o d e ( f (φ) = 1 6 k H z ) CM 7 = 1 (32 kHz selected) CM 6 = 0 (High-speed) CM 5 = 1 (8 MHz stopped) CM 4 = 1 (32 kHz oscillating) Low-speed mode (f(φ) =16 kHz) CM 6 “0” “1” CM 6 “0” “ 1 ” CM 6 “ 0 ” “1” C M 0 ”“ 1 ” C M 0 ”“ 1 ” C M 0 ”“ 1 ” C M 0 ” “ 1 ” C M 0 ” “ 1 ” C M C M6 “ 0 ” 1 ” 0 ” 1 ” C M C M “ 0 C M C “ 0 ” 1 ” 0 ” 1 ” C M C M “ 0

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS The contents of the processor status register (PS) after a reset are undefined, except for the interrupt disable flag (I) which is “1”. Af- ter a reset, initialize flags which affect program execution. In particular, it is essential to initialize the index X mode (T) and the decimal mode (D) flags because of their effect on calculations. Interrupt The contents of the interrupt request bits do not change immedi- ately after they have been written. After writing to an interrupt re- quest register, execute at least one instruction before performing a BBC or BBS instruction. Decimal Calculations To calculate in decimal notation, set the decimal mode flag (D) to “1”, then execute an ADC or SBC instruction. Only the ADC and SBC instructions yield proper decimal results. After executing an ADC or SBC instruction, execute at least one instruction before executing a SEC, CLC, or CLD instruction. In decimal mode, the values of the negative (N), overflow (V), and zero (Z) flags are invalid. Timers If a value n (between 0 and 255) is written to a timer latch, the fre- quency division ratio is 1/(n + 1). Multiplication and Division Instructions The index mode (T) and the decimal mode (D) flags do not affect the MUL and DIV instruction. The execution of these instructions does not change the contents of the processor status register. Ports The contents of the port direction registers cannot be read. The following cannot be used:

• The data transfer instruction (LDA, etc.)
• The operation instruction when the index X mode flag (T) is “1”
• The addressing mode which uses the value of a direction regis- ter as an index
• The bit-test instruction (BBC or BBS, etc.) to a direction register
• The read-modify-write instruction (ROR, CLB, or SEB, etc.) to a direction register Use instructions such as LDM and STA, etc., to set the port direc- tion registers. Serial I/O In clock synchronous serial I/O, if the receive side is using an ex- ternal clock and it is to output the S RDY signal, set the transmit en- able bit, the receive enable bit, and the SRDY output enable bit to “1”. Serial I/O continues to output the final bit from the TXD pin after transmission is completed. A-D Converter The comparator uses internal capacitors whose charge will be lost if the clock frequency is too low. Make sure that f(X IN) is at least 500kHz during an A-D conversion. Do not execute the STP or WIT instruction during an A-D conver- sion. Instruction Execution Time The instruction execution time is obtained by multiplying the fre- quency of the internal clock φ by the number of cycles needed to execute an instruction. The number of cycles required to execute an instruction is shown in the list of machine instructions. The frequency of the internal clock φ is half of the X IN frequency.

Table 13. Programming adapter Figure 45 is recommended to verify programming.

Table 14. Absolute maximum ratings (Standard, One time PROM version) All voltages are based on VSS . Output transistors are cut off. Table 15. Recommended operating conditions (Standard, One time PROM version)

Table 16. Recommended operating conditions (Standard, One time PROM version) age value measured over 100 ms. The total peak current is the peak value of all the currents. 2:The peak output current is the peak current flowing in each port. 3:The average output current is an average value measured over 100 ms. 4:When the oscillation frequency has a duty cycle of 50%.

Table 17. Electrical characteristics (Standard, One time PROM version)

Table 18. Electrical characteristics (Standard, One time PROM version)

• High-speed mode, V CC = 5 V f(XIN) = 8 MHz f(XCIN) = 32.768 kHz Output transistors “off” A-D converter in operating
• High-speed mode, VCC = 5 V f(XIN) = 8 MHz (in WIT state) f(XCIN) = 32.768 kHz Output transistors “off” A-D converter in operating
• Low-speed mode, VCC = 5 V, Ta ≤ 55°C f(XIN) = stopped f(XCIN) = 32.768 kHz Output transistors “off”
• Low-speed mode, VCC = 5 V, Ta = 25°C f(XIN) = stopped f(XCIN) = 32.768 kHz (in WIT state) Output transistors “off”
• Low-speed mode, VCC = 3 V, Ta ≤ 55°C f(XIN) = stopped f(XCIN) = 32.768 kHz Output transistors “off”
• Low-speed mode, VCC = 3 V, Ta = 25°C f(XIN) = stopped f(XCIN) = 32.768 kHz (in WIT state) Output transistors “off” All oscillation stopped (in STP state) Output transistors “off” Symbol Parameter Limits Min. UnitTyp. Max. Ta = 25 °C Ta = 85 °C Test conditions ICC Power source current 6.4 1.6 7.0 4.5 0.1 1.8 3.0 VRAM RAM retention voltage At clock stop mode 2.0 5.5 V When using voltage multiplier V L1 = 1.8 V VL1 < 1.3 V VL1 IL1 Power source voltage Power source current (VL1) (Note) 1.3 Note : When the voltage multiplier control bit of the LCD mode register (bit 4 at address 003916) is “1”.

Table 19. A-D converter characteristics (Standard, One time PROM version) Note : When an internal trigger is used in middle-speed mode, it is 14 µs.

IN) = 8 MHz and bit 6 of address 001A16 is “1” (Clock synchronous). Divide this value by four when f(XIN) = 8 MHz and bit 6 of address 001A16 is “0” (UART). Table 20. Timing requirements 1 (Standard, One time PROM version) Note: When f(XIN) = 8 MHz and bit 6 of address 001A16 is “1” (Clock synchronous). Divide this value by four when f(XIN) = 8 MHz and bit 6 of address 001A16 is “0” (UART). Table 21. Timing requirements 2 (Standard, One time PROM version)

Notes 1 : When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”. 2 : XOUT and XCOUT pins are excluded. Table 22. Switching characteristics 1 (Standard, One time PROM version) Notes 1 : When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”. 2 : XOUT and XCOUT pins are excluded. Table 23. Switching characteristics 2 (Standard, One time PROM version)

All voltages are based on VSS . Output transistors are cut off. Table 25. Recommended operating conditions (Extended operating temperature version) Table 24. Absolute maximum ratings (Extended operating temperature version)

Table 26. Recommended operating conditions (Extended operating temperature version) erage value measured over 100 ms. The total peak current is the peak value of all the currents. 2 : The peak output current is the peak current flowing in each port. 3 : The average output current is an average value measured over 100 ms. 4 : When the oscillation frequency has a duty cycle of 50%.

Table 27. Electrical characteristics (Extended operating temperature version)

• High-speed mode, V CC = 5 V f(XIN) = 8 MHz f(XCIN) = 32.768 kHz Output transistors “off” A-D converter in operating
• High-speed mode, VCC = 5 V f(XIN) = 8 MHz (in WIT state) f(XCIN) = 32.768 kHz Output transistors “off” A-D converter in operating
• Low-speed mode, VCC = 5 V, Ta ≤ 55°C f(XIN) = stopped f(XCIN) = 32.768 kHz Output transistors “off”
• Low-speed mode, VCC = 5 V, Ta = 25°C f(XIN) = stopped f(XCIN) = 32.768 kHz (in WIT state) Output transistors “off”
• Low-speed mode, VCC = 3 V, Ta ≤ 55°C f(XIN) = stopped f(XCIN) = 32.768 kHz Output transistors “off”
• Low-speed mode, VCC = 3 V, Ta = 25°C f(XIN) = stopped f(XCIN) = 32.768 kHz (in WIT state) Output transistors “off” All oscillation stopped (in STP state) Output transistors “off” Symbol Parameter Limits Min. UnitTyp. Max. Ta = 25°C Ta = 85°C Test conditions ICC Power source current 6.4 1.6 7.0 4.5 0.1 1.8 3.0 VRAM RAM retention voltage At clock stop mode 2.0 5.5 V When using voltage multiplier V L1 = 1.8 V VL1 < 1.3 V VL1 IL1 Power source voltage Power source current (VL1) (Note) 1.3 Note : When the voltage multiplier control bit of the LCD mode register (bit 4 at address 003916) is “1”.

Table 29. A-D converter characteristics (Extended operating temperature version) Table 28. Electrical characteristics (Extended operating temperature version) Note : When an internal trigger is used in middle-speed mode, it is 14 µs.

Table 30. Timing reguirements 1 (Extended operating temperature version) IN) = 8 MHz and bit 6 of address 001A16 is “1” (Clock synchronous). Divide this value by four when f(XIN) = 8 MHz and bit 6 of address 001A16 is “0” (UART). Table 31. Timing reguirements 2 (Extended operating temperature version) Note: When f(XIN) = 8 MHz and bit 6 of address 001A16 is “1” (Clock synchronous). Divide this value by four when f(XIN) = 8 MHz and bit 6 of address 001A16 is “0” (UART).

Table 32. Switching characteristics 1 (Extended operating temperature version) Notes 1 : When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”. 2 : XOUT and XCOUT pins are excluded. Table 33. Switching characteristics 2 (Extended operating temperature version) Notes 1 : When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”. 2 : XOUT and XCOUT pins are excluded.

Table 34. Absolute maximum ratings (M version) All voltages are based on VSS . Output transistors are cut off. Table 35. Recommended operating conditions (M version)

Table 36. Recommended operating conditions (M version) erage value measured over 100 ms. The total peak current is the peak value of all the currents. 2 : The peak output current is the peak current flowing in each port. 3 : The average output current is an average value measured over 100 ms. 4 : When the oscillation frequency has a duty cycle of 50%.

Table 37. Electrical characteristics (M version)

• High-speed mode, V CC = 5 V f(XIN) = 8 MHz f(XCIN) = 32.768 kHz Output transistors “off” A-D converter in operating
• High-speed mode, VCC = 5 V f(XIN) = 8 MHz (in WIT state) f(XCIN) = 32.768 kHz Output transistors “off” A-D converter in operating
• Low-speed mode, VCC = 5 V, Ta ≤ 55°C f(XIN) = stopped f(XCIN) = 32.768 kHz Output transistors “off”
• Low-speed mode, VCC = 5 V, Ta = 25°C f(XIN) = stopped f(XCIN) = 32.768 kHz (in WIT state) Output transistors “off”
• Low-speed mode, VCC = 3 V, Ta ≤ 55°C f(XIN) = stopped f(XCIN) = 32.768 kHz Output transistors “off”
• Low-speed mode, VCC = 3 V, Ta = 25°C f(XIN) = stopped f(XCIN) = 32.768 kHz (in WIT state) Output transistors “off” All oscillation stopped (in STP state) Output transistors “off” Symbol Parameter Limits Min. UnitTyp. Max. Ta = 25°C Ta = 85°C Test conditions ICC Power source current 6.4 1.6 7.0 4.5 0.1 1.8 3.0 VRAM RAM retention voltage At clock stop mode 2.0 5.5 V When using voltage multiplier V L1 = 1.8 V VL1 < 1.3 V VL1 IL1 Power source voltage Power source current (VL1) (Note) 1.3 Note : When the voltage multiplier control bit of the LCD mode register (bit 4 at address 003916) is “1”.

Table 39. A-D converter characteristics (M version) Table 38. Electrical characteristics (M version) Note : When an internal trigger is used in middle-speed mode, it is 14 µs.

Table 40. Timing reguirements 1 (M Version) IN) = 8 MHz and bit 6 of address 001A16 is “1” (Clock synchronous). Divide this value by four when f(XIN) = 8 MHz and bit 6 of address 001A16 is “0” (UART). Table 41. Timing reguirements 2 (M Version) Note: When f(XIN) = 8 MHz and bit 6 of address 001A16 is “1” (Clock synchronous). Divide this value by four when f(XIN) = 8 MHz and bit 6 of address 001A16 is “0” (UART).

Table 42. Switching characteristics 1 (M version) Notes 1 : When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”. 2 : XOUT and XCOUT pins are excluded. Table 43. Switching characteristics 2 (M version) Notes 1 : When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”. 2 : XOUT and XCOUT pins are excluded. 001B16) is “1” (N-channel open-drain output mode).

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 47 Timing diagram tW(RESET) 0 . 8 VC C 0 . 2 VC CR E S E T tC(XIN) tC(CNTR) tW H C N T R ) tW L C N T R 0 . 8 VC C 0.2VC C C N T R 0, C N T R 1 tWH(INT) tW L I N T 0 . 8 VC C 0 . 2 VC CI N T 0– I N T3 tWH(X IN) tW L XI N ) 0 . 8 VC C 0.2VC CXI N tC(SCLK ) tWL(S CLK ) tWH(S CLK ) 0 . 2 VC C 0.8VC C SC L K trtf td SC L TXD ) tv SC L TXD TXD R XD 0 . 2 VC C 0 . 8 VC C ts u R XD SC L K) th SC L R XD

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS QFP100-P-1420-0.65 1.58 Weight(g) JEDEC CodeEIAJ Package Code Lead Material Alloy 42 100P6S-A Plastic 100pin 14✕ 20mm body QFP 0.1 0.2 – – Symbol Min Nom Max A b c D E H E L y Dimension in Millimeters H D 0.35 – –I2 1.3 – –M D 14.6 – –M E 20.6 10°0° 0.1 1.4 0.8 0.6 0.4 23.1 22.8 22.5 17.1 16.8 16.5 0.65 20.2 20.0 19.8 14.2 14.0 13.8 0.2 0.15 0.13 0.4 0.3 0.25 2.8 3.05 e e e E c H E H D D M D M E A F A1 A2 L y Recommended Mount Pad Detail F 100 x – – 0.13 b x M MMP LQFP100-P-1414-0.50 Weight(g) – 0.63 JEDEC CodeEIAJ Package Code Lead Material Cu Alloy 100P6Q-A Plastic 100pin 14✕ 14mm body LQFP 0.1 0.2 – – Symbol Min Nom Max A b c D E H E L y Dimension in Millimeters H D 0.225 – –I2 0.9 – –M D 14.4 – –M E 14.4 10°0° 0.1 1.0 0.7 0.5 0.3 16.2 16.0 15.8 16.2 16.0 15.8 0.5 14.1 14.0 13.9 14.1 14.0 13.9 0.175 0.125 0.105 0.28 0.18 0.13 1.4 1.7 e e E H E 5026 H D D A F y 100 Lp 0.45 0.6 0.25 0.75 0.08x b x M A1 A2 L Detail F Lp c M D l2 b2 M E e Recommended Mount Pad MMP

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS TQFP100-P-1212-0.40 Weight(g) – 0.37 JEDEC CodeEIAJ Package Code Lead Material Cu Alloy 100PFB-A Plastic 100pin 12✕ 12mm body TQFP – – – – Symbol Min Nom Max A b c D E H E L y Dimension in Millimeters H D A1 0.15 0.1 0.225 – –I2 1.0 – –M D 12.4 – –M E 12.4 10°0° 0.08 0.07 1.0 0.6 0.5 0.4 14.2 14.0 13.8 14.2 14.0 13.8 0.4 12.1 12.0 11.9 12.1 12.0 11.9 0.175 0.125 0.105 0.23 0.18 0.13 1.0 0.05 1.2 e H E E D H D 76100 26 50 Fe A y A1 A2 L Lp Detail F c Lp 0.45 0.6 0.25 0.75 x b x M M D e M E Recommended Mount Pad MMP Weight(g)JEDEC CodeEIAJ Package Code 100D0 Glass seal 100pin QFN – – 51 80 30 11.075TYP 0.45TYP 0.65TYP INDEX 3.5TYP 5.0MAX 0.65TYP 1.075TYP 0.35TYP 0.65TYP 12.35±0.15 15.6±0.13 21.0±0.13 18.85±0.15 100

© 2001 MITSUBISHI ELECTRIC CORP. Specifications subject to change without notice. Notes regarding these materials

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• If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.
• Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein. Keep safety first in your circuit designs!
• Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap.