3823

Renesas Technology Corp

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Manufacturer: Renesas Technology Corp

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Technical content

DESCRIPTION

The 3823 group is the 8-bit microcomputer based on the 740 fam- ily core technology. The 3823 group has the LCD drive control circuit, an 8-channel A/ D converter, a serial interface, a watchdog timer, a ROM correc- tion function, and as additional functions. The various microcomputers in the 3823 group include variations of internal memory size and packaging. For details, refer to the section on part numbering.

FEATURES

(at f(XIN) = 10 MHz, High-speed mode)

Memory size
Software pull-up/pull-down resistors (Ports P0-P7 except port P40) (includes key input interrupt)
LCD drive control circuit (connect to external ceramic resonator or quartz-crystal oscillator)
Sub-clock generating circuits (connect to external quartz-crystal oscillator or on-chip oscillator)
Power source voltage
Power dissipation (at f(XIN) = 8 MHz, Vcc = 5 V, Ta = 25 °C) (at f(XIN) stopped, f(XCIN) = 32 kHz, Vcc = 2.5 V, Ta = 25 °C) (at f(XIN) stopped, f(XCIN) = stopped, Vcc = 2.5 V, Ta = 25 °C)

APPLICATIONS

Camera, audio equipment, household appliances, consumer elec- tronics, etc.

3823 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER REJ03B0146-0202 Rev.2.02 Jun.19.2007 Rev.2.02 Jun 19, 2007 page 1 of 73 REJ03B0146-0202

Rev.2.02 Jun 19, 2007 page 2 of 73 REJ03B0146-0202 PIN CONFIGURATION (TOP VIEW) Fig. 2 M3823XGX-XXXHP pin configuration 1 2 3 4 7 8 9 10 11 12 13 14 15 16 17 18 19 205 6 4142434445464748495051525354555657585960 4/SEG 5/SEG P16/SEG 30 P17/SEG 31 P42/INT0 VCC XIN XOUT VSS RESET P70/XCOUT P71/XCIN P41/φ P40 P43/INT1 SEG 5/SEG 6/SEG 7/SEG 0/SEG 3/SEG 4/SEG 5/SEG 6/SEG 7/SEG 1/SEG 2/SEG 0/SEG 1/SEG 2/SEG 3/SEG COM 3 0/AN 7/ADT 6/T OUT 4/CNTR 3/RTP 2/RTP 1/INT 5/CNTR 6/S CLK 5/T XD 0/INT 7/S RDY OUT 4/R XD SEG 1 SEG 2 SEG 3 SEG 4 SEG 6 SEG 5 SEG 7 SEG 0 SEG 8 SEG 9 COM 2 COM 1 COM 0 VL3 VL2 VL1 VREF AV SS 1/AN 2/AN 3/AN 4/AN 5/AN 6/AN 7/AN SEG 4/SEG M3823XGX-XXXHP M3823XGXHP P27/KW 7 P26/KW 6 P25/KW 5 P24/KW 4 P23/KW 3 P22/KW 2 P21/KW 1 P20/KW 0 Fig. 1 M3823XGX-XXXFP pin configuration PIN CONFIGURATION (TOP VIEW) S E G 8 S E G 9 P 34/ S E G 1 P 35/ S E G 1 P 00/ S E G 1 P 03/ S E G 1 P 04/ S E G 2 P 05/ S E G 2 P 06/ S E G 2 P 07/ S E G 2 P 11/ S E G 2 P 12/ S E G 2 P 13/ S E G 2 P 14/ S E G 2 P 15/ S E G 2 P 16/ S E G 3 P 17/ S E G 3 V P 67/ A N 7 M X G X X X X F P M X G X F P P 57/ A D T P 50/ I N P 46/ SC L K P 45/ TXD P 43/ I N P 42/ I N A VS S VR E F VC C S E G 0 P41/φ P40 XIN XOUT VSS P27/KW 7 P26/KW 6 P25/KW 5 P24/KW 4 P23/KW 3 P22/KW 2 P21/KW 1 P 20/ K W 0 R E S E T P 51/ I N P 55/ C N T R 1 P 54/ C N T R 0 P 53/ R T P 52/ R T P 56/ TO U T P 10/ S E G 2 P 01/ S E G 1 P 02/ S E G 1 P 47/ SR D SO U T S E G 1 S E G 1 P 36/ S E G 1 P 37/ S E G 1 P 70/ XC O U T P 71/ XC I N C O M 0 V P 66/ A N 6 P 65/ A N 5 P 64/ A N 4 P 63/ A N 3 P 62/ A N 2 P 61/ A N 1 P 60/ A N 0 V C O M 1 C O M 2 C O M 3 SEG 1 S E G 2 S E G 3 S E G 4 S E G 5 S E G 6 S E G 7 P 44/ R XD 1 23 4 56789 1 11 21 31 41 51 61 71 81 92 02 12 2 2 414243444546474849505152535455565758596061626364

Rev.2.02 Jun 19, 2007 page 3 of 73 REJ03B0146-0202 Table 1 Performance overview Parameter 0.4 µs (Minimum instruction, f(XIN) 10 MHz, High-speed mode)

10 MHz (Maximum)

16 K to 60 K bytes

4-bit ✕ 1, 1-bit ✕ 1 (4 pins sharing SEG) 8-bit ✕ 5, 7-bit ✕ 1, 2 bit ✕ 1 (16 pins sharing SEG) 17 sources, 16 vectors (includes key input interrupt) 8-bit ✕ 3, 16-bit ✕ 2 8-bit ✕ 1 (UART or Clock-synchronized) 10-bit ✕ 8 channels or 8 bit ✕ 8 channels 8-bit ✕ 1 32 bytes ✕ 2 blocks 1/2, 1/3 2, 3, 4 Built-in feedback resistor (connect to external ceramic rasonator or quartz-crystal oscillator) Built-in feedback resistor (connect to external quartz-crystal oscillator or on-chip oscillator) 4.5 to 5.5V 4.0 to 5.5V 2.5 to 5.5V 2.0 to 5.5V 1.8 to 5.5V 2.5 to 5.5V 2.0 to 5.5V 1.8 to 5.5V 1.8 to 5.5V Std. 18 mW (Vcc = 5V, f(X IN) = 8MHz, Ta = 25 °C) Std. 18 µW (Vcc = 2.5V, f(XIN) = stopped, f(XCIN) = 32kHz, Ta = 25 °C) Std. 35 µW (Vcc = 2.5V, f(XIN) = stopped, f(XCIN) = stopped, Ta = 25 °C) VCC 10mA -20 to 85 °C CMOS sillicon gate 80-pin plastic molded LQFP/QFP Number of basic instructions Instruction execution time Oscillation frequency Memory sizes ROM RAM Input port P3 4-P37, P40 I/O port P0-P2, P4 1-P47, P5, P6, P70, P71 Interrupt Timer Serial interface A/D converter W atchdog timer ROM correction function LCD drive control Bias circuit Duty Common output Segment output Main clock generating circuits Sub-clock generating circuits Power source voltage In frequency/2 mode (f(X IN) ≤ 10MHz) In frequency/2 mode (f(XIN) ≤ 8MHz) In frequency/4 mode (f(XIN) ≤ 10MHz) In frequency/4 mode (f(XIN) ≤ 8MHz) In frequency/4 mode (f(XIN) ≤ 5MHz) In frequency/8 mode (f(XIN) ≤ 10MHz) In frequency/8 mode (f(XIN) ≤ 8MHz) In frequency/8 mode (f(XIN) ≤ 5MHz) In low-speed mode Power dissipation In frequency/2 mode In low-speed mode at XCIN In low-speed mode at on-chip oscillator Input/Output Input/Output withstand voltage characteristics Output current Operating temperature range Device structure Package Function

Rev.2.02 Jun 19, 2007 page 4 of 73 REJ03B0146-0202 FUNCTIONAL BLOCK DIAGRAM (Package type : PLQP0080KB-A) Fig. 3 Functional block diagram K e y o n w a k e u p R e a l t i m e p o r t f u n c t i o n I N T2, I N T3 C N T R C N T R T O U T A D T I N T0, I N T1 XC I N R T P R T P D a t a b u s C P U A X Y S P C H P C L P S R E S E T V C C V S S R e s e t I n p u t ( 5 V ( 0 V ) R O M R A M L C D d i s p l a y R A M ( 1 b y t e s 2 5 7 1 3 0 I / O P o r t P P 4 I / O P o r t P I / O P o r t P P 2 I / O P o r t P P 0 I / O P o r t P P 1 P 6 I n p u t P o r t P P 3 I / O P o r t P P 5 I / O P o r t P P 7 8 0 7 9 7 8 7 7 7 6 7 5 7 4 7 0 6 9 6 8 6 7 6 6 6 5 6 4 6 3 6 2 6 1 6 0 5 9 4 7 4 8 4 9 5 0 5 1 5 2 5 3 5 4 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 5 5 5 6 5 7 5 8 1 9 2 0 2 1 2 2 2 3 2 4 1 7 1 8 2 6 2 7 7 3 7 2 1 0 1 1 1 2 1 3 1 4 1 5 1 6 C l o c k g e n e r a t i n g c i r c u i t M a i n C l o c k I n p u t X I N M a i n C l o c k O u t p u t X O U T X C O U T S u b C l o c k O u t p u t X C I N S u b C l o c k I n p u t S I O V R E F A V S S ( 0 V A D c o n v e r t e r T i m e r X T i m e r Y T i m e r T i m e r T i m e r L C D d r i v e c o n t r o l c i r c u i t V L V L V L C O M C O M C O M C O M S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G φ X C I NX C O U T 2 8 2 9 O n c h i p o s c i l l a t o r R O M c o r r e c t i o n f u n c t i o n W a t c h d o g t i m e r R e s e t

Rev.2.02 Jun 19, 2007 page 5 of 73 REJ03B0146-0202 Table 2 Pin description (1) VCC , VSS FunctionPin Name Function except a port function

LCD segment output pins Power source • Apply voltage of power source to VCC , and 0 V to VSS . (For the limits of VCC , refer to “Recom- mended operating conditions”). VREF AV SS RESET XIN XOUT VL1–VL3 COM 0–COM 3 SEG 0–SEG 11 P00/SEG 16– P07/SEG 23 P10/SEG 24– P17/SEG 31 P20/KW 0 – P27/KW 7 P3 4/SEG 12 – P3 7/SEG 15 Analog refer- ence voltage Analog power source Reset input Clock input Clock output LCD power source Common output Segment output I/O port P0 I/O port P1 I/O port P2
Reference voltage input pin for A/D converter.
GND input pin for A/D converter.
Connect to V SS .
Reset input pin for active “L”.
Input and output pins for the main clock generating circuit.
Feedback resistor is built in between XIN pin and XOUT pin.
Connect a ceramic resonator or a quartz-crystal oscillator between the XIN and XOUT pins to set the oscillation frequency.
If an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open.
This clock is used as the oscillating source of system clock.
Input 0 ≤ VL1 ≤ VL2 ≤ VL3 voltage.
Input 0 – VL3 voltage to LCD.
LCD common output pins.
COM 2 and COM 3 are not used at 1/2 duty ratio.
COM 3 is not used at 1/3 duty ratio.
LCD segment output pins.
8-bit I/O port.
CMOS compatible input level.
CMOS 3-state output structure.
I/O direction register allows each port to be individually programmed as either input or output.
Pull-down control is enabled.
8-bit I/O port.
CMOS compatible input level.
CMOS 3-state output structure.
I/O direction register allows each pin to be individually programmed as either input or output.
Pull-up control is enabled.
4-bit input port.
CMOS compatible input level.
Pull-down control is enabled.
Key input (key-on wake-up) interrupt input pins
LCD segment output pinsInput port P3

Rev.2.02 Jun 19, 2007 page 6 of 73 REJ03B0146-0202 Table 3 Pin description (2) FunctionPin Function except a port function P40 P42/INT0, P43/INT1 P44/RXD, P45/TXD, P46/SCLK , P47/SRDY /SOUT P50/INT2, P51/INT3 P52/RTP0, P53/RTP1 P54/CNTR 0, P55/CNTR 1 P56/TOUT P57/ADT P60/AN0– P67/AN7 P70/XCOUT, P71/XCIN

1-bit Input port.
CMOS compatible input level.
7-bit I/O port.
CMOS compatible input level.
CMOS 3-state output structure.
I/O direction register allows each pin to be individually programmed as either input or output.
Pull-up control is enabled.
8-bit I/O port.
CMOS compatible input level.
CMOS 3-state output structure.
I/O direction register allows each pin to be individually programmed as either input or output.
Pull-up control is enabled.
8-bit I/O port.
CMOS compatible input level.
CMOS 3-state output structure.
I/O direction register allows each pin to be individually programmed as either input or output.
Pull-up control is enabled.
2-bit I/O port.
CMOS compatible input level.
CMOS 3-state output structure.
I/O direction register allows each pin to be individually programmed as either input or output.
Pull-up control is enabled.
φ clock output pin
Interrupt input pins
Interrupt input pins
Real time port function pins
Timer X, Y function pins
Timer 2 output pins
A/D conversion input pins
Sub-clock generating circuit I/O pins. (Connect a resonator. External clock cannot be used.) P41/φ
Serial interface function pins
A/D trigger input pins Name I/O port P4 I/O port P5 I/O port P6 I/O port P7 Input port P4 •QzROM program power pin

Rev.2.02 Jun 19, 2007 page 7 of 73 REJ03B0146-0202 Fig. 4 Part numbering Package code FP : PRQP0080GB-A package HP : PLQP0080KB-A package ROM number Omitted in the shipped in blank version. ROM/PROM size 1 : 4096 bytes 2 : 8192 bytes 3 : 12288 bytes 4 : 16384 bytes 5 : 20480 bytes 6 : 24576 bytes 7 : 28672 bytes 8 : 32768 bytes The first 128 bites and the last 2 bytes of ROM are reserved areas ; they cannot be used. Memory type G : QzROM version RAM size 0 : 192 bytes 1 : 256 bytes 2 : 384 bytes 3 : 512 bytes 4 : 640 bytes 5 : 768 bytes 6 : 896 bytes 7 : 1024 bytes 8 : 1536 bytes 9 : 2048 bytes A :2560 bytes Product M3823 4 G 6 -XXX FP 9 : 36864 bytes A : 40960 bytes B : 45056 bytes C : 49152 bytes D : 53248 bytes E : 57344 bytes F : 61440 bytes

Rev.2.02 Jun 19, 2007 page 8 of 73 REJ03B0146-0202 Mitsubishi plans to expand the 3823 group as follows: Memory Type Support for QzROM version. Memory Size Package Memory Expansion Plan Fig. 5 Memory expansion plan 32K 28K 24K 20K 16K 12K 256 384 512 640 768 896 1,024192 40K 48K 1,536 2,048 56K 60K ROM size (bytes) RAM size (bytes) 2,560 M3823AGF Mass production M38239GC M38238G8 Mass production Mass production M38235G6 M38234G4 Mass production Mass production

Rev.2.02 Jun 19, 2007 page 9 of 73 REJ03B0146-0202 Currently products are listed below. RemarksPackage Part No. RAM size (bytes) 61440 (61310) 49152 (49022) 32768 (32638) 24576 (24446) 16384 (16254) ROM size (bytes) ROM size for User in ( ) Table 4 List of products M3823AGF-XXXFP M3823AGF-XXXHP M3823AGFFP M3823AGFHP M38239GC-XXXFP M38239GC-XXXHP M38239GCFP M38239GCHP M38238G8-XXXFP M38238G8-XXXHP M38238G8FP M38238G8HP M38235G6-XXXFP M38235G6-XXXHP M38235G6FP M38235G6HP M38234G4-XXXFP M38234G4-XXXHP M38234G4FP M38234G4HP 2560 (Note 1) 2048 (Note 2) 1536 (Note 2) 768 (Note 2) 640 (Note 2) PRQP0080GB-A PLQP0080KB-A PRQP0080GB-A PLQP0080KB-A PRQP0080GB-A PLQP0080KB-A PRQP0080GB-A PLQP0080KB-A PRQP0080GB-A PLQP0080KB-A PRQP0080GB-A PLQP0080KB-A PRQP0080GB-A PLQP0080KB-A PRQP0080GB-A PLQP0080KB-A PRQP0080GB-A PLQP0080KB-A PRQP0080GB-A PLQP0080KB-A Blank Blank Blank Blank Blank Blank Blank Blank Blank Blank Note 1: RAM size includes RAM for LCD display and ROM corrections. Note 2: RAM size includes RAM for LCD display.

Rev.2.02 Jun 19, 2007 page 10 of 73 REJ03B0146-0202 CENTRAL PROCESSING UNIT (CPU) The 3823 group uses the standard 740 family instruction set. Re- fer to the table of 740 family addressing modes and machine instructions or the 740 Family Software Manual for details on the instruction set. Machine-resident 740 family instructions are as follows: The FST and SLW instruction cannot be used. The STP, WIT, MUL, and DIV instruction can be used. The central processing unit (CPU) has six registers. Figure 6 shows the 740 Family CPU register structure. [Accumulator (A)] The accumulator is an 8-bit register. Data operations such as data transfer, etc., are executed mainly through the accumulator. [Index Register X (X)] The index register X is an 8-bit register. In the index addressing modes, the value of the OPERAND is added to the contents of register X and specifies the real address. [Index Register Y (Y)] The index register Y is an 8-bit register. In partial instruction, the value of the OPERAND is added to the contents of register Y and specifies the real address. [Stack Pointer (S)] The stack pointer is an 8-bit register used during subroutine calls and interrupts. This register indicates start address of stored area (stack) for storing registers during subroutine calls and interrupts. The low-order 8 bits of the stack address are determined by the contents of the stack pointer. The high-order 8 bits of the stack ad- dress are determined by the stack page selection bit. If the stack page selection bit is “0” , the high-order 8 bits becomes “00 16”. If the stack page selection bit is “1”, the high-order 8 bits becomes “01 16”. The operations of pushing register contents onto the stack and popping them from the stack are shown in Figure 7. Store registers other than those described in Table 4 with program when the user needs them during interrupts or subroutine calls. [Program Counter (PC)] The program counter is a 16-bit counter consisting of two 8-bit registers PCH and PC L. It is used to indicate the address of the next instruction to be executed. Fig. 6 740 Family CPU register structure A Accumulator b7 b0 b7b15 b0 b7 b0 X Index register X Y Index register Y S Stack pointer PC L Program counterPC H N VTB DI ZC Processor status register (PS) Carry flag Zero flag Interrupt disable flag Decimal mode flag Break flag Index X mode flag Overflow flag Negative flag

Rev.2.02 Jun 19, 2007 page 11 of 73 REJ03B0146-0202 Table 5 Push and pop instructions of accumulator or processor status register Accumulator Processor status register Push instruction to stack PHA PHP Pop instruction from stack PLA PLP Fig. 7 Register push and pop at interrupt generation and subroutine call N o t e: C o n d i t i o n f o r a c c e p t a n c e o f a n i n t e r r u p t I n t e r r u p t e n a b l e f l a g i s “ 1 ” E x e c u t e J S R O n g o i n g R o u t i n e M S P C H ) S S M S P C L) E x e c u t e R T S P C L)M S S S S S S S P C H )M S S u b r o u t i n e P O P re t u r n a d d r e s s f r o m s t a c k P u s h r e t u r n a d d r e s s o n s t a c k M S P S E x e c u t e R T I P S S S S S S I n t e r r u p t S e r v i c e R o u t i n e P O P c o n t e n t s o f p r o c e s s o r s t a t u s r e g i s t e r f r o m s t a c k M S P C H ) S S M S P C L) S S P C L)M S S S S S P C H )M S P O P r e t u r n a d d r e s s f r o m s t a c k I F l a g i s s e t f r o m “ 0 ” t o “ 1 ” F e t c h t h e j u m p v e c t o r P u s h r e t u r n a d d r e s s o n s t a c k P u s h c o n t e n t s o f p r o c e s s o r s t a t u s r e g i s t e r o n s t a c k I n t e r r u p t r e q u e s t N o t e I n t e r r u p t d i s a b l e f l a g i s “ 0 ”

Rev.2.02 Jun 19, 2007 page 12 of 73 REJ03B0146-0202 [Processor status register (PS)] The processor status register is an 8-bit register consisting of 5 flags which indicate the status of the processor after an arithmetic operation and 3 flags which decide MCU operation. Branch opera- tions can be performed by testing the Carry (C) flag , Zero (Z) flag, Overflow (V) flag, or the Negative (N) flag. In decimal mode, the Z, V, N flags are not valid.

Bit 0: Carry flag (C) The C flag contains a carry or borrow generated by the arithmetic logic unit (ALU) immediately after an arithmetic operation. It can also be changed by a shift or rotate instruction.
Bit 1: Zero flag (Z) The Z flag is set if the result of an immediate arithmetic operation or a data transfer is “0”, and cleared if the result is anything other than “0”.
Bit 2: Interrupt disable flag (I) The I flag disables all interrupts except for the interrupt generated by the BRK instruction. Interrupts are disabled when the I flag is “1”.
Bit 3: Decimal mode flag (D) The D flag determines whether additions and subtractions are executed in binary or decimal. Binary arithmetic is executed when this flag is “0”; decimal arithmetic is executed when it is “1”. Decimal correction is automatic in decimal mode. Only the ADC and SBC instructions can be used for decimal arithmetic.
Bit 4: Break flag (B) The B flag is used to indicate that the current interrupt was generated by the BRK instruction. The BRK flag in the processor status register is always “0”. When the BRK instruction is used to generate an interrupt, the processor status register is pushed onto the stack with the break flag set to “1”.
Bit 5: Index X mode flag (T) When the T flag is “0”, arithmetic operations are performed between accumulator and memory. When the T flag is “1”, direct arithmetic operations and direct data transfers are enabled between memory locations.
Bit 6: Overflow flag (V) The V flag is used during the addition or subtraction of one byte of signed data. It is set if the result exceeds +127 to -128. When the BIT instruction is executed, bit 6 of the memory location operated on by the BIT instruction is stored in the overflow flag.
Bit 7: Negative flag (N) The N flag is set if the result of an arithmetic operation or data transfer is negative. When the BIT instruction is executed, bit 7 of the memory location operated on by the BIT instruction is stored in the negative flag. Table 6 Set and clear instructions of each bit of processor status register Set instruction Clear instruction C flag SEC CLC Z flag I flag SEI CLI D flag SED CLD B flag T flag SET CLT V flag CLV N flag

Rev.2.02 Jun 19, 2007 page 13 of 73 REJ03B0146-0202 [CPU Mode Register (CPUM)] 003B16 The CPU mode register contains the stack page selection bit and the internal system clock selection bit. The CPU mode register is allocated at address 003B16. Fig. 8 Structure of CPU mode register Not available Processor mode bits b1 b0 0 0 : Single-chip mode 0 1 : 1 0 : 1 1 : Stack page selection bit 0 : 0 page 1 : 1 page Not used (returns “1” when read) (Do not write “0” to this bit) Port X C switch bit (Note 1) 0 : I/O port function (stop oscillating) 1 : X CIN–XCOUT oscillating function Main clock (XIN–XOUT ) stop bit (Note 2) 0 : Oscillating 1 : Stopped Main clock division ratio selection bit 0 : f(XIN)/2 (frequency/2 mode), or f(XIN)/4 (frequency/4 mode) (Note 3) 1 : f(XIN)/8 (frequency/8 mode) Internal system clock selection bit 0 : XIN–XOUT selected (frequency/2/4/8 mode) 1 : XCIN–XCOUT, or on-chip oscillator selected (low-speed mode) (Note 4) CPU mode register (CPUM (CM) : address 003B16) b7 b0 Note 1: In low speed mode (XCIN is selected as the system clock φ), XCIN-XCOUT oscillation does not stop even if the port XC switch bit is set to "0". 2: In frequency/2/4/8 mode, XIN-XOUT oscillation does not stop even if the main clock (XIN-XOUT ) stop bit is set to "1". 3: When the system clock φ is divided by 4 of f(XIN), set the bit 6 in the CPU mode register to “0” after setting the bit 1 in the CPU mode extension register to “1”. 4:When using the on-chip oscillator in low-speed mode, set the bit 7 in the CPU mode register to “1” after setting the bit 0 in the CPU mode extension register to “1”. [CPU Mode Extension Register (EXPCM)] 002B16 f(XIN) divided by 4 for the system clock f and the on-chip oscillator for the system clock f in low-speed mode can be selected by set- ting the CPU mode extension register. When the system clock f is divided by 4 of f(X IN), set the bit 6 in the CPU mode register to “0” after setting the bit 1 in the CPU mode extension register to “1”. When using the on-chip oscillator in low-speed mode, set the bit 7 in the CPU mode register to “1” after setting the bit 0 in the CPU mode extension register to “1”. Fig. 9 Structure of CPU mode extension register On-chip oscillator control bit 0 : On-chip oscillator not used (On -chip oscillator sotpping) 1 : On-chip oscillator used (Note 1) (On -chip oscillator oscillating) Frequency/4 mode control bit (Note 2) 0 : Frequency/2 mode φ = f(X IN)/2 1 : Frequency/4 mode φ = f(XIN)/4 Not used (returns “0” when read) (Do not write “1” to this bit) CPU mode extension register (EXPCM : address 002B16) b7 b0 1 : The on-chip oscillator is selected for the operation clock in low-speed mod regardless of XCIN-XCOUT . 2 : Valid only when the main clock division ratio selection bit (bit 6 in the CPU mode register) is set to "0". When "1" (frequency/8 mode) is selected for the main clock division ratio selection bit or when the internal system clock selection bit is set to 1, set "0" to the frequency/4 mode control bit. Note

Rev.2.02 Jun 19, 2007 page 14 of 73 REJ03B0146-0202 Special Function Register (SFR) Area The Special Function Register area in the zero page contains con- trol registers such as I/O ports and timers. RAM RAM is used for data storage and for stack area of subroutine calls and interrupts. ROM The first 128 bytes and the last 2 bytes of ROM are reserved for device testing and the rest is user area for storing programs. Interrupt Vector Area The interrupt vector area contains reset and interrupt vectors. Zero Page The 256 bytes from addresses 000016 to 00FF16 are called the zero page area. The internal RAM and the special function regis- ter (SFR) are allocated to this area. The zero page addressing mode can be used to specify memory and register addresses in the zero page area. Access to this area with only 2 bytes is possible in the zero page addressing mode. Special Page The 256 bytes from addresses FF0016 to FFFF16 are called the special page area. The special page addressing mode can be used to specify memory addresses in the special page area. Access to this area with only 2 bytes is possible in the special page addressing mode. Fig. 10 Memory map diagram 6 4 0 0 2 B F1 RAM area R A M s i z e b y t e s A d d r e s s X X X 1 6 3 8 4 C 0 0 01 A C 0 8 01 A R O M a r e a R O M s i z e b y t e s A d d r e s s Y Y Y A d d r e s s Z Z Z 010016 000016 004016 0A4016 FF0016 F F D C 1 FFFE 16 FFFF 16 XXXX 16 ZZZZ 16 RAM R O M RAM for ROM correction SFR area N o t u s e d Interrupt vector area R e s e r v e d R O M a r e a Zero page S p e c i a l p a g e R e s e r v e d R O M a r e a 005016 LCD display RAM area R A M 1 f o r R O M c o r r e c t i o n R A M 2 f o r R O M c o r r e c t i o n 0A0016 0A1F16

0 A 2 01

0 A 3 F1

“0016” is written into ROM code protect address (other than the user ROM area) when selecting the protect bit write by using a se- rial programmer or selecting protect enabled for writing shipment by Renesas Technology corp.. When “00 16” is set to the ROM code protect address, the protect function is enabled, so that read- ing or writing from/to QzROM is disabled by a serial programmer. As for the QzROM product in blank, the ROM code is protected by selecting the protect bit write at ROM writing with a serial pro- grammer. As for the QzROM product shipped after writing, “00 16” (protect enabled) or “FF16” (protect disabled) is written into the ROM code protect address when Renesas Technology corp. performs writing. The writing of “0016" or “FF16” can be selected as ROM option setup (“MASK option” written in the mask file converter) when or- dering.

Rev.2.02 Jun 19, 2007 page 15 of 73 REJ03B0146-0202 Fig. 11 Memory map of special function register (SFR) 0 0 2 01 0 0 2 11 0 0 2 21 0 0 2 31 0 0 2 41 0 0 2 51 0 0 2 61 0 0 2 71 0 0 2 81 0 0 2 91 0 0 2 A1 0 0 2 B1 002C 16 002D 16 002E16 0 0 2 F1 0 0 3 01 0 0 3 11 0 0 3 21 0 0 3 31 0 0 3 41 0 0 3 51 0 0 3 61 0 0 3 71 003816 003916 003A16 0 0 3 B1 003C 16 003D 16 003E16 0 0 3 F1 0 0 0 01 0 0 0 11 0 0 0 21 0 0 0 31 0 0 0 41 0 0 0 51 0 0 0 61 0 0 0 71 0 0 0 81 0 0 0 91 0 0 0 A1 0 0 0 B1 0 0 0 C 1 0 0 0 D 1 000E16 0 0 0 F1 0 0 1 01 0 0 1 11 0 0 1 21 0 0 1 31 0 0 1 41 0 0 1 51 0 0 1 61 0 0 1 71 001816 001916 001A16 0 0 1 B1 0 0 1 C 1 001D 16 001E16 0 0 1 F1

6 I n t e r r u p t c o n t r o l r e g i s t e r 2 ( I C O N 2 )

T i m e r 3 r e g i s t e r ( T 3 ) T i m e r X m o d e r e g i s t e r ( T X M ) Interrupt edge selection register (INTEDGE) C P U m o d e r e g i s t e r ( C P U M ) Interrupt request register 1(IREQ1) Interrupt request register 2(IREQ2) I n t e r r u p t c o n t r o l r e g i s t e r 1 ( I C O N 1 ) T i m e r X l o w - o r d e r r e g i s t e r ( T X L ) T i m e r Y l o w - o r d e r r e g i s t e r ( T Y L ) T i m e r 1 r e g i s t e r ( T 1 ) T i m e r 2 r e g i s t e r ( T 2 ) T i m e r X h i g h - o r d e r r e g i s t e r ( T X H ) T i m e r Y h i g h - o r d e r r e g i s t e r ( T Y H ) T i m e r Y m o d e r e g i s t e r ( T Y M ) Timer 123 mode register (T123M) φ output control register (CKOUT) S e g m e n t o u t p u t e n a b l e r e g i s t e r ( S E G ) LCD mo de register (LM) A D c o n t r o l r e g i s t e r ( A D C O N ) A D c o n v e r s i o n h i g h - o r d e r r e g i s t e r ( A D H ) P o r t P 0 r e g i s t e r ( P 0 ) P o r t P 1 r e g i s t e r ( P 1 ) P o r t P 1 d i r e c t i o n r e g i s t e r ( P 1 D ) P o r t P 2 r e g i s t e r ( P 2 ) P o r t P 2 d i r e c t i o n r e g i s t e r ( P 2 D ) P o r t P 3 r e g i s t e r ( P 3 ) P o r t P 4 r e g i s t e r ( P 4 ) P o r t P 4 d i r e c t i o n r e g i s t e r ( P 4 D ) P o r t P 5 r e g i s t e r ( P 5 ) P o r t P 5 d i r e c t i o n r e g i s t e r ( P 5 D ) P o r t P 6 r e g i s t e r ( P 6 ) P o r t P 6 d i r e c t i o n r e g i s t e r ( P 6 D ) P o r t P 7 r e g i s t e r ( P 7 ) P o r t P 7 d i r e c t i o n r e g i s t e r ( P 7 D ) S e r i a l I / O s t a t u s r e g i s t e r ( S I O S T S ) Serial I/O control register (SIO1CON) UART control register (UARTCON) Baud rate generator (BRG) P U L L r e g i s t e r A ( P U L L A ) P U L L r e g i s t e r B ( P U L L B ) T r a n s m i t / R e c e i v e b u f f e r r e g i s t e r( T B / R B ) P o r t P 0 d i r e c t i o n r e g i s t e r ( P 0 D ) R O M c o r r e c t i o n a d d r e s s 1 h i g h - o r d e r r e g i s t e r ( R C A 1 H ) R O M c o r r e c t i o n a d d r e s s 1 l o w - o r d e r r e g i s t e r ( R C A 1 L ) R O M c o r r e c t i o n a d d r e s s 2 h i g h - o r d e r r e g i s t e r ( R C A 2 H ) R O M c o r r e c t i o n a d d r e s s 2 l o w - o r d e r r e g i s t e r ( R C A 2 L ) R O M c o r r e c t i o n e n a b l e r e g i s t e r ( R C R ) T e m p o r a r y d a t a r e g i s t e r 0 ( T D 0 ) T e m p o r a r y d a t a r e g i s t e r 1 ( T D 1 ) C P U m o d e e x p a n s i o n r e g i s t e r ( E X P C M ) T e m p o r a r y d a t a r e g i s t e r 2 ( T D 2 ) RRF register (RRFR) Peripheral function expansion register (EXP) A D c o n v e r s i o n l o w - o r d e r r e g i s t e r ( A D L ) W atchdog timer register (WDT) N o t e : D o n o t a c c e s s t o t h e S F R a r e a i n c l u d i n g n o t h i n g .

Rev.2.02 Jun 19, 2007 page 16 of 73 REJ03B0146-0202 Direction Registers (ports P2, P41-P47, and P5-P7) The 3823 group has 49 programmable I/O pins arranged in seven I/O ports (ports P0–P2, P41–P4 7 and P5-P7). The I/O ports P2, P4 1–P4 7 and P5-P7 have direction registers which determine the input/output direction of each individual pin. Each bit in a direction register corresponds to one pin, and each pin can be set to be in- put port or output port. When “0” is written to the bit corresponding to a pin, that pin be- comes an input pin. When “1” is written to that bit, that pin be- comes an output pin. If data is read from a pin set to output, the value of the port output latch is read, not the value of the pin itself. Pins set to input are floating. If a pin set to input is written to, only the port output latch is written to and the pin remains floating. Direction Registers (ports P0 and P1) Ports P0 and P1 have direction registers which determine the in- put/output direction of each individual port. Each port in a direction register corresponds to one port, each port can be set to be input or output. When “0” is written to the bit 0 of a direction register, that port becomes an input port. When “1” is written to that port, that port becomes an output port. Bits 1 to 7 of ports P0 and P1 direction registers are not used. Ports P3 and P40 These ports are only for input. Pull-up/Pull-down Control By setting the PULL register A (address 001616) or the PULL reg- ister B (address 001716), ports except for port P40 can control either pull-down or pull-up (pins that are shared with the segment output pins for LCD are pull-down; all other pins are pull-up) with a program. However, the contents of PULL register A and PULL register B do not affect ports programmed as the output ports. Fig. 12 Structure of PULL register A and PULL register B P00–P07 pull-down P10–P17 pull-down P20–P27 pull-up P34–P37 pull-down P70, P71 pull-up Not used (return “0” when read) PULL register A (PULLA: address 001616) b7 b 0 P41–P43 pull-up P44–P47 pull-up P50–P53 pull-up P54–P57 pull-up P60–P63 pull-up P64–P67 pull-up Not used (return “0” when read) 0 : D i s a b l e E n a b l e PULL register B (PULLB : address 001716) b7 b0 N ote: The contents of PULL register A and PULL register B do not affect ports programmed as the output port.

Rev.2.02 Jun 19, 2007 page 17 of 73 REJ03B0146-0202 Diagram No.Related SFRsInput/OutputNamePin Non-Port FunctionI/O Format Table 7 List of I/O port function P00/SEG 16– P07/SEG 23 P10/SEG 24– P17/SEG 31 P20/KW 0– P27/KW 7 P34/SEG 12– P37/SEG 15 P40 P41/φ P42/INT0, P43/INT1 P44/RXD P45/TXD P46/SCLK P4 7/SRDY /SOUT P50/INT2, P51/INT3 P52/RTP0, P53/RTP1 P54/CNTR 0 Port P0 Port P1 Port P2 Port P3 Port P4 Input/output, individual ports Input/output, individual bits Input Input Input/output, individual bits CMOS compatible input level CMOS 3-state output CMOS compatible input level CMOS 3-state output CMOS compatible input level CMOS compatible input level CMOS compatible input level CMOS 3-state output CMOS compatible input level CMOS 3-state output CMOS compatible input level CMOS 3-state output CMOS compatible input level CMOS 3-state output LCD segment output Key input (key-on wake-up) interrupt input LCD segment output φ clock output X CIN frequency signal output External interrupt input Serial I/O function input/output External interrupt input Timer X function I/O Timer Y function input Timer 2 function output PULL register A Segment output enable register PULL register A Interrupt control register 2 PULL register A Segment output enable register PULL register B φ output control register Peripheral function extension register PULL register B Interrupt edge selection register PULL register B Serial I/O control register Serial I/O status register UART control register Peripheral function extension register PULL register B Interrupt edge selection register PULL register B Timer X mode register PULL register B Timer X mode register PULL register B Timer Y mode register PULL register B Timer 123 mode register PULL register B A/D control register PULL register A CPU mode register (1) (2) (3) (4) (6) (5) (2) (8) (7) Port P5 (9) (2)Input/output, individual bits (10) P55/CNTR 1 (11) (12) (13) (12) (14) P56/TOUT P57/ADT P60/AN0– P67/AN7 (15)P70/XCOUT P71/XCIN COM 0–COM 3 SEG 0–SEG 11 (16) (17) (18) Input/output, individual bits Input/output, individual bits Output Output Sub-clock generating circuit I/O LCD common output LCD segment output Port P6 Port P7 Common Segment LCD mode register Notes 1: For details of how to use double function ports as function I/O ports, refer to the applicable sections. 2: When an input level is at an intermediate potential, a current will flow from VCC to VSS through the input-stage gate. Especially, power source current may increase during execution of the STP and WIT instructions. Fix the unused input pins to “H” or “L” through a resistor. QzROM program power pin

Rev.2.02 Jun 19, 2007 page 18 of 73 REJ03B0146-0202 Fig. 13 Port block diagram (1) ( 3 ) P o r t s P 34– P 37 VL 2/ VL VL1/VSS S e g m e n t o u t p u t e n a b l e b i t VL 2/ VL VL 1/ VS S N o t e ( 2 ) P o r t s P 2 , P 42, P 43, P 50, P 51 D i r e c t i o n r e g i s t e r (5) Port P41 ( 6 ) P o r t P 44 R e c e i v e e n a b l e b i t Direction register ( 4 ) P o r t P 40 D a t a b u s Pull-down control S e g m e n t o u t p u t e n a b l e b i t D a t a b u s D i r e c t i o n r e g i s t e r P o r t l a t c h P u l l - d o w n c o n t r o l Segment output enable bit Data bus Port latch Pull-up control Key input (Key-on wake-up) interrupt input INT0–INT3 interrupt input Pull-up control Serial I/O enable bit Serial I/O input Data bus Port latch (1) Ports P0, P1 N o t e : B i t 0 o f d i r e c t i o n r e g i s t e r . Data bus Q ZROM pr ogrammable power source φ φ o u t p u t c o n t r o l b i t Port latchD a t a b u s D i r e c t i o n r e g i s t e r Pull-up control XCIN frequency signal O u t p u t c l o c k s e l e c t i o n b i t

Rev.2.02 Jun 19, 2007 page 19 of 73 REJ03B0146-0202 Fig. 14 Port block diagram (2) ( 7 ) P o r t P 45 ( 8 ) P o r t P 46 Serial I/O clock- synchronized selection bit Serial I/O enable bit Serial I/O mode selection bit Serial I/O enable bit Direction register Port latch S e r i a l I / O c l o c k o u t p u t D a t a b u s S e r i a l I / O c l o c k i n p u t P u l l - u p c o n t r o l (10) Ports P52, P53 Direction register Port latchData bus Pull-up control R e a l t i m e p o r t c o n t r o l b i t D a t a f o r r e a l t i m e p o r t Direction register Port latchD a t a b u s Pull-up control ( 1 2 ) P o r t s P 55 P 57 CNTR 1 interrupt input A/D trigger interrupt input ( 1 1 ) P o r t P 54 D i r e c t i o n r e g i s t e r P o r t l a t c hD a t a b u s Pull-up control T i m e r X o p e r a t i n g m o d e b i t T i m e r o u t p u t CNTR 0 interrupt input (Pulse output mode selection) D a t a b u s Serial I/O enable bit Transmit enable bit S e r i a l I / O o u t p u t s y n c h r o n o u s o r a s y n c h r o n o u s P-Channel output disabled selection bit P o r t l a t c h D i r e c t i o n r e g i s t e r P u l l u p c o n t r o l P 45/ T x D P 47/ SR D SO U T P c h a n n e l o u t p u t d i s a b l e b i t As y n c h r o n o u s s e r i a l I O o u t p u t Sy n c h r o n o u s s e r i a l I O o u t p u t p i n s e l e c t i o n b i t D a t a b u s S e r i a l I O r e a d y o u t p u t Port latch Serial I/O mode selection bit Serial I/O enable bit SRDY ,SOUT output enable bit D i r e c t i o n r e g i s t e r Pull-up controlP-Channel output disabled selection bit Synchronous serial I/O output pin selection bit Synchronous serial I/O output P 45/ T x D P 47/ SR D SO U T P c h a n n e l o u t p u t d i s a b l e b i t (9) Port P47

Rev.2.02 Jun 19, 2007 page 20 of 73 REJ03B0146-0202 Fig. 15 Port block diagram (3) VL 2/ VL VL 1/ VS S ( 1 3 ) P o r t P 56 D a t a b u s D i r e c t i o n r e g i s t e r P o r t l a t c h P u l - u p c o n t r o l TO U T o u t p u t c o n t r o l b i t T i m e r o u t p u t ( 1 4 ) P o r t P 6 Data bus Direction register Port latch P u l l - u p c o n t r o l A / D c o n v e r s i o n i n p u t A n a l o g i n p u t p i n s e l e c t i o n b i t ( 1 5 ) P o r t P 70 D a t a b u s D i r e c t i o n r e g i s t e r P o r t l a t c h P o r t XC s w i t c h b i t + P u l l - u p c o n t r o l P o r t XC s w i t c h b i t O s c i l l a t i o n c i r c u i t P o r t P 71 P o r t XC s w i t c h b i t ( 1 6 ) P o r t P 71 D a t a b u s Direction register Port latch Port XC switch bit P o r t XC s w i t c h b i t + P u l l - u p c o n t r o l S u b - c l o c k g e n e r a t i n g c i r c u i t i n p u t VL VL VL ( 1 7 ) C O M 0– C O M 3 ( 1 8 ) S E G 0– S E G 1 T h e g a t e i n p u t s i g n a l o f e a c h t r a n s i s t o r i s c o n t r o l l e d b y t h e L C D d u t y r a t i o a n d t h e b i a s v a l u e T h e v o l t a g e a p p l i e d t o t h e s o u r c e s o f P c h a n n e l a n d N c h a n n e l t r a n s i s t o r s i s t h e c o n t r o l l e d v o l t a g e b y t h e b i a s v a l u e

Rev.2.02 Jun 19, 2007 page 21 of 73 REJ03B0146-0202 Termination of unused pins

Termination of common pins I/O ports: Select an input port or an output port and follow each processing method. Output ports: Open. Input ports: If the input level become unstable, through current flow to an input circuit, and the power supply current may increase. Especially, when expecting low consumption current (at STP or WIT instruction execution etc.), pull-up or pull-down input ports to prevent through current (built-in resistor can be used). Pull-down the P40/ (VPP ) pin. We recommend processing unused pins through a resistor which can secure IOH(avg) or IOL(avg). Because, when an I/O port or a pin which have an output function is selected as an input port, it may operate as an output port by incorrect operation etc.

Rev.2.02 Jun 19, 2007 page 22 of 73 REJ03B0146-0202 Table 8 Termination of unused pins Pin P00/SEG 16–P1 7/SEG 23 P10/SEG 24–P1 7/SEG 31 P20/KW 0–P2 7/KW 7 P34/SEG 12–P3 7/SEG 15 P40/(VPP ) P41/φ P42/INT0 P43/INT1 P44/RxD P45/TxD P46/SCLK P47/SRDY /SOUT P50/INT2 P51/INT3 P52/RTP0 P53/RTP1 P54/CNTR 0 P55/CNTR 1 P56/TOUT P57/ADT P60/AN0–P6 7/AN7 P70/XCOUT P71/XCIN VL3 (Note) VL2 (Note) VL1 (Note) COM 0–COM 3 SEG 0–SEG 11 AV SS VREF XOUT Termination 2 When selecting SEG output, open. When selecting KW function, perform termination of input port. When selecting SEG output, open. When selecting φ output, open. When selecting INT0 function, perform termination of input port. When selecting INT1 function, perform termination of input port. When selecting RXD function, perform termination of input port. When selecting TXD function, perform termination of output port. When selecting external clock input, perform termination of input port. When selecting SRDY function, perform termination of output port. When selecting INT2 function, perform termination of input port. When selecting INT3 function, perform termination of input port. When selecting RTP0 function, perform termination of output port. When selecting RTP1 function, perform termination of output port. When selecting CNTR0 input function, perform termination of input port. When selecting CNTR1 function, perform termination of input port. When selecting TOUT function, perform termination of output port. When selecting ADT function, perform termination of input port. When selecting AN function, these pins can be opened. (A/D conversion result cannot be guaranteed.) Do not select X CIN-XCOUT oscillation function by program. Termination 3 When selecting internal clock output, perform termination of output port. When selecting SOUT function, perform termination of output port. When selecting CNTR0 output function, perform termination of output port. Termination 1 (recommend) I/O port Input port Input port (pull-down) I/O port Connect to V SS Connect to VSS Connect to VSS Open Open Connect to V SS Connect to VCC or VSS When an external clock is input to the XIN pin, leave the XOUT pin open. Note : The termination of VL3, VL2 and VL1 is applied when the bit 3 of the LCD mode register is “0”

Rev.2.02 Jun 19, 2007 page 23 of 73 REJ03B0146-0202 The 3823 group interrupts are vector interrupts with a fixed prior- ity scheme, and generated by 16 sources among 17 sources: 8 external, 8 internal, and 1 software. The interrupt sources, vector addresses (1) , and interrupt priority are shown in Table 9. Each interrupt except the BRK instruction interrupt has the inter- rupt request bit and the interrupt enable bit. These bits and the interrupt disable flag (I flag) control the acceptance of interrupt re- quests. Figure 16 shows an interrupt control diagram. Notes1: Vector addresses contain interrupt jump destination addresses. 2: Reset function in the same way as an interrupt with the highest priority. Table 9 Interrupt vector addresses and priority RemarksInterrupt Request Generating Conditions At reset At detection of either rising or falling edge of INT0 input At detection of either rising or falling edge of INT1 input At completion of serial interface data reception At completion of serial interface transmit shift or when transmis- sion buffer is empty Interrupt Source LowHigh Priority Vector Addresses (Note 1) Reset (Note 2) INT0 INT1 Serial I/O reception Serial I/O transmission Timer X Timer Y Timer 2 Timer 3 CNTR 0 CNTR 1 Timer 1 INT2 INT3 Key input (Key-on wake-up) ADT A/D conversion BRK instruction FFFD FFFB 16 FFF9 16 FFF7 16 FFF5 16 FFF3 16 FFF1 16 FFEF 16 FFED 16 FFEB 16 FFE9 16 FFE7 16 FFE5 16 FFE3 16 FFE1 16 FFDF 16 FFDD 16 FFFC 16 FFFA 16 FFF8 16 FFF6 16 FFF4 16 FFF2 16 FFF0 16 FFEE 16 FFEC 16 FFEA 16 FFE8 16 FFE6 16 FFE4 16 FFE2 16 FFE0 16 FFDE 16 FFDC 16 At timer X underflow At timer Y underflow At timer 2 underflow At timer 3 underflow At detection of either rising or falling edge of CNTR0 input At detection of either rising or falling edge of CNTR1 input At timer 1 underflow At detection of either rising or falling edge of INT 2 input At detection of either rising or falling edge of INT3 input At falling of conjunction of input level for port P2 (at input mode) At falling of ADT input At completion of A/D conversion At BRK instruction execution Non-maskable External interrupt (active edge selectable) External interrupt (active edge selectable) Valid when serial interface is se- lected Valid when serial interface is se- lected External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (Valid at falling) Valid when ADT interrupt is se- lected, External interrupt (Valid at falling) Valid when A/D interrupt is se- lected Non-maskable software interrupt An interrupt requests is accepted when all of the following conditions are satisfied: Though the interrupt priority is determined by hardware, priority processing can be performed by software using the above bits and flag.

Rev.2.02 Jun 19, 2007 page 24 of 73 REJ03B0146-0202 Fig. 16 Interrupt control diagram I n t e r r u p t r e q u e s t b i t I n t e r r u p t e n a b l e b i t I n t e r r u p t d i s a b l e f l a g ( I ) B R K i n s t r u c t i o n R e s e t i n t e r r u p t r e q u e s t Interrupt Disable Flag The interrupt disable flag is assigned to bit 2 of the processor sta- tus register. This flag controls the acceptance of all interrupt requests except for the BRK instruction. When this flag is set to “1”, the acceptance of interrupt requests is disabled. When it is set to “0”, acceptance of interrupt requests is enabled. This flag is set to “1” with the SET instruction and set to “0” with the CLI instruc- tion. When an interrupt request is accepted, the contents of the proces- sor status register are pushed onto the stack while the interrupt disable flag remaines set to “0”. Subsequently, this flag is auto- matically set to “1” and multiple interrupts are disabled. To use multiple interrupts, set this flag to “0” with the CLI instruc- tion within the interrupt processing routine. The contents of the processor status register are popped off the stack with the RTI instruction. Interrupt Request Bits Once an interrupt request is generated, the corresponding inter- rupt request bit is set to “1” and remaines “1” until the request is accepted. When the request is accepted, this bit is automatically set to “0”. Each interrupt request bit can be set to “0”, but cannot be set to “1”, by software. Interrupt Enable Bits The interrupt enable bits control the acceptance of the corre- sponding interrupt requests. When an interrupt enable bit is set to “0”, the acceptance of the corresponding interrupt request is dis- abled. If an interrupt request occurs in this condition, the corresponding interrupt request bit is set to “1”, but the interrupt request is not accepted. When an interrupt enable bit is set to “1”, acceptance of the corresponding interrupt request is enabled. Each interrupt enable bit can be set to “0” or “1” by software. The interrupt enable bit for an unused interrupt should be set to “0”. Interrupt Source Selection The following combinations can be selected by the interrupt source selection bit of the AD control register (bit 6 of the address 0039 16).

ADT or A/D conversion (refer Table 9)

Rev.2.02 Jun 19, 2007 page 25 of 73 REJ03B0146-0202 Fig. 17 Structure of interrupt-related registers b 7 b 0 I n t e r r u p t e d g e s e l e c t i o n r e g i s t e r I N T0 i n t e r r u p t e d g e s e l e c t i o n b i t I N i n t e r r u p t e d g e s e l e c t i o n b i t I N i n t e r r u p t e d g e s e l e c t i o n b i t I N i n t e r r u p t e d g e s e l e c t i o n b i t N o t u s e d r e t u r n w h e n r e a d ( I N T E D G E : a d d r e s s 0 0 3 A1 I n t e r r u p t r e q u e s t r e g i s t e r 1 I N T0 i n t e r r u p t r e q u e s t b i t I N i n t e r r u p t r e q u e s t b i t S e r i a l I O r e c e i v e i n t e r r u p t r e q u e s t b i t S e r i a l I O t r a n s m i t i n t e r r u p t r e q u e s t b i t T i m e r X i n t e r r u p t r e q u e s t b i t T i m e r Y i n t e r r u p t r e q u e s t b i t T i m e r i n t e r r u p t r e q u e s t b i t T i m e r i n t e r r u p t r e q u e s t b i t Interrupt control register 1 I N T0 i n t e r r u p t e n a b l e b i t I N i n t e r r u p t e n a b l e b i t S e r i a l I O r e c e i v e i n t e r r u p t e n a b l e b i t S e r i a l I O t r a n s m i t i n t e r r u p t e n a b l e b i t T i m e r X i n t e r r u p t e n a b l e b i t T i m e r Y i n t e r r u p t e n a b l e b i t T i m e r i n t e r r u p t e n a b l e b i t T i m e r i n t e r r u p t e n a b l e b i t 0 : N o i n t e r r u p t r e q u e s t i s s u e d I n t e r r u p t r e q u e s t i s s u e d ( I R E Q 1 : a d d r e s s 0 0 3 C 1 ( I C O N 1 : a d d r e s s 0 0 3 E1 I n t e r r u p t r e q u e s t r e g i s t e r 2 C N T R 0 i n t e r r u p t r e q u e s t b i t C N T R 1 i n t e r r u p t r e q u e s t b i t T i m e r i n t e r r u p t r e q u e s t b i t I N i n t e r r u p t r e q u e s t b i t I N i n t e r r u p t r e q u e s t b i t K e y i n p u t i n t e r r u p t r e q u e s t b i t A D T A D c o n v e r s i o n i n t e r r u p t r e q u e s t b i t N o t u s e d r e t u r n s w h e n r e a d (IREQ2 : address 003D 16) Interrupt control register 2 CNTR 0 interrupt enable bit CNTR 1 interrupt enable bit Timer 1 interrupt enable bit INT2 interrupt enable bit INT3 interrupt enable bit Key input interrupt enable bit ADT/AD conversion interrupt enable bit Not used (returns “0” when read) (Do not write “1” to this bit.) 0 : Interrupts disabled 1 : Interrupts enabled (ICON2 : address 003F16) 0 : F a l l i n g e d g e a c t i v e R i s i n g e d g e a c t i v e b7 b 0 b7 b0 b 7 b0 b7 b0

Rev.2.02 Jun 19, 2007 page 26 of 73 REJ03B0146-0202 Interrupt Request Generation, Acceptance, and Handling Interrupts have the following three phases. (i) Interrupt Request Generation An interrupt request is generated by an interrupt source (ex- ternal interrupt signal input, timer underflow, etc.) and the corresponding request bit is set to “1”. (ii) Interrupt Request Acceptance Based on the interrupt acceptance timing in each instruction cycle, the interrupt control circuit determines acceptance con- ditions (interrupt request bit, interrupt enable bit, and interrupt disable flag) and interrupt priority levels for accepting interrupt requests. When two or more interrupt requests are generated simultaneously, the highest priority interrupt is accepted. The value of interrupt request bit for an unaccepted interrupt re- mains the same and acceptance is determined at the next interrupt acceptance timing point. (iii) Handling of Accepted Interrupt Request The accepted interrupt request is processed. Figure 18 shows the time up to execution in the interrupt process- ing routine, and Figure 19 shows the interrupt sequence. Figure 20 shows the timing of interrupt request generation, inter- rupt request bit, and interrupt request acceptance. Interrupt Handling Execution When interrupt handling is executed, the following operations are performed automatically. (1) Once the currently executing instruction is completed, an inter- rupt request is accepted. (2) The contents of the program counters and the processor status register at this point are pushed onto the stack area in order from 1 to 3. 1. High-order bits of program counter (PCH) 2. Low-order bits of program counter (PCL) 3. Processor status register (PS) (3) Concurrently with the push operation, the jump address of the corresponding interrupt (the start address of the interrupt pro- cessing routine) is transferred from the interrupt vector to the program counter. (4) The interrupt request bit for the corresponding interrupt is set to “0”. Also, the interrupt disable flag is set to “1” and multiple interrupts are disabled. (5) The interrupt routine is executed. (6) When the RTI instruction is executed, the contents of the reg- isters pushed onto the stack area are popped off in the order from 3 to 1. Then, the routine that was before running interrupt processing resumes. As described above, it is necessary to set the stack pointer and the jump address in the vector area corresponding to each inter- rupt to execute the interrupt processing routine. ■ Notes The interrupt request bit may be set to “1” in the following cases.

When setting the external interrupt active edge Related registers: Interrupt edge selection register (address 003A 16) Timer X mode register (address 002716) Timer Y mode register (address 002816) If it is not necessary to generate an interrupt synchronized with these settings, take the following sequence. (1) Set the corresponding enable bit to “0” (disabled). (2) Set the interrupt edge selection bit (the active edge switch bit) or the interrupt source bit. (3) Set the corresponding interrupt request bit to “0” after one or more instructions have been executed. (4) Set the corresponding interrupt enable bit to “1” (enabled). Fig. 18 Time up to execution in interrupt routine Fig. 19 Interrupt sequence Main routine Interrupt handling routine Interrupt request generated Interrupt request acceptance Interrupt routine starts Interrupt sequence 7 cycles 7 to 23 cycles * When executing DIV instruction Stack push and Vector fetch 0 to 16 cycles* φ SYNC RD WR Address bus Data bus PC Not used S,SPS S-1,SPS S-2,SPS BL BH AL,AH PC H PC L PS A L AH SYNC :CPU operation code fetch cycle (This is an internal signal that cannot be observed from the external unit.) BL, BH:Vector address of each interrupt AL, AH:Jump destination address of each interrupt SPS : “00 16” or “0116” ([SPS] is a page selected by the stack page selection bit of CPU mode register.) Push onto stack Vector fetch Execute interrupt routine

Rev.2.02 Jun 19, 2007 page 27 of 73 REJ03B0146-0202 Fig. 20 Timing of interrupt request generation, interrupt request bit, and interrupt acceptance Internal clock φ SYNC Instruction cycle T1 IR1 T2 T1 T2 T3: Interrupt acceptance timing points IR1 IR2: Timings points at which the interrupt request bit is set to “1”. Push onto stack Vector fetch Instruction cycle IR2 T3 Note: Period 2 indicates the last φ cycle during one instruction cycle. (1) The interrupt request bit for an interrupt request generated during period 1 is set to “1” at timing point IR1. (2) The interrupt request bit for an interrupt request generated during period 2 is set to “1” at timing point IR1 or IR2. The timing point at which the bit is set to “1” varies depending on conditions. When two or more interrupt requests are generated during the period 2, each request bit may be set to “1” at timing point IR1 or IR2 separately.

Rev.2.02 Jun 19, 2007 page 28 of 73 REJ03B0146-0202 Key Input Interrupt (Key-on wake-up) A Key-on wake-up interrupt request is generated by applying a falling edge to any pin of port P2 that have been set to input mode. In other words, it is gener1ated when AND of input level goes from “1” to “0”. An example of using a key input interrupt is shown in Figure 21, where an interrupt request is generated by pressing one of the keys consisted as an active-low key matrix which inputs to ports P20–P2 3. Fig. 21 Connection example when using key input interrupt and port P2 block diagram Port PXX “L” level output Port P27 direction register = “1” P 27 o u t p u t P 26 o u t p u t P U L L r e g i s t e r A b i t 2 = “ 1 ” P25 output P24 output P 23 i n p u t Port P26 latch Port P25 latch Port P24 latch Port P23 latch Port P27 latch Port P25 direction register = “1” Port P24 direction register = “1” P o r t P 23 d i r e c t i o n r e g i s t e r P22 input P 21 i n p u t P20 input Port P22 latch Port P21 latch Port P20 latch Port P22 direction register = “0” Port P21 direction register = “0” Port P20 direction register = “0” P o r t P 2 I n p u t r e a d i n g c i r c u i t ✽ P-channel transistor for pull-up ✽✽ CMOS output buffer Key input interrupt request P o r t P 26 d i r e c t i o n r e g i s t e r ✽ ✽ ✽ ✽✽ ✽ ✽✽ ✽ ✽✽ ✽ ✽✽ ✽ ✽✽ ✽ ✽✽ ✽ ✽✽

Rev.2.02 Jun 19, 2007 page 29 of 73 REJ03B0146-0202 The 3823 group has five timers: timer X, timer Y, timer 1, timer 2, and timer 3. Timer X and timer Y are 16-bit timers, and timer 1, timer 2, and timer 3 are 8-bit timers. All timers are down count timers. When the timer reaches “0016”, an underflow occurs at the next count pulse and the correspond- ing timer latch is reloaded into the timer and the count is continued. When a timer underflows, the interrupt request bit cor- responding to that timer is set to “1”. Read and write operation on 16-bit timer must be performed for both high and low-order bytes. When reading a 16-bit timer, read the high-order byte first. When writing to a 16-bit timer, write the low-order byte first. The 16-bit timer cannot perform the correct operation when reading during the write operation, or when writing during the read operation. Fig. 22 Timer block diagram CNTR 0 active edge switch bit Timer 1 count source selection bit Real time port control bit “0” “1” P55/CNTR 1 “0” f(XIN)/16 (f(SUB )16 in low-speed mode✽) CNTR 1 active edge switch bit “10” Timer Y stop control bit Falling edge detection Period measurement mode Timer Y interrupt request Pulse width HL continuously measurement mode Rising edge detection Timer Y operating mode bits Timer X interrupt request Timer X mode register write signal 4/CNTR 0 Q Q T S P54 direction register Pulse output mode P54 latch Timer X stop control bit “0” “1” Timer X write control bit Q D Latch Q D Latch “1” “0” “1” “10” Timer X operat- ing mode bits f(XIN)/16 (f(SUB)/16 in low-speed mode✽) Pulse width measurement mode CNTR 0 active edge switch bit Pulse output mode Q Q T S “0” P56 direction registerP56 latch“1” TOUT output active edge switch bit Timer 2 write control bit “0” “1” T OUT output control bit “1” P56/TOUT f(SUB) Timer 3 count source selection bit “0” “1” Timer 2 interrupt request Timer 3 interrupt request Timer 2 count source selection bit Timer 1 interrupt request Data bus f(XIN)/16 (f(SUB)/16 in low-speed mode]) f(XIN)/16 (f(SUB)/16 in low-speed mode✽) f(XIN)/16(f(SUB)/16 in low-speed mode✽) CNTR 0 interrupt request CNTR 1 interrupt request Timer Y operating mode bits “11” Real time port control bit “1” P52 latch Real time port control bit “1” P53 latch Timer Y (low) (8) Timer Y (high) (8) Timer 3 latch (8) Timer 3 (8) Timer 1 latch (8) Timer 1 (8) Timer 2 latch (8) Timer 2 (8) Timer X (low) (8) Timer X (high) (8) Timer X (low) latch (8) Timer X (high) latch (8) Timer Y (low) latch (8)Timer Y (high) latch (8) TOUT output control bit “0” “0” “0” P52 P53 P52 direction register P53 direction register P52 data for real time port P53 data for real time port ✽ f(SUB) is the source oscillation frequency in low-speed mode. f(SUB) shows the oscillation frequency of XCIN or the on-chip oscillator. Internal clock φ is f(SUB)/2 in the low-speed mode.

Rev.2.02 Jun 19, 2007 page 30 of 73 REJ03B0146-0202 Timer X is a 16-bit timer that can be selected in one of four modes and can be controlled the timer X write and the real time port by setting the timer X mode register. (1) Timer Mode The timer counts f(XIN)/16 (or f(SUB)/16 in low-speed mode). f(SUB) is the source oscillation frequency in low-speed mode. f(SUB) shows the oscillation frequency of XCIN or the on-chip os- cillator. Internal clock φ is f(XCIN)/2 in the low-speed mode. (2) Pulse Output Mode Each time the timer underflows, a signal output from the CNTR0 pin is inverted. Except for this, the operation in pulse output mode is the same as in timer mode. When using a timer in this mode, set the corresponding port P54 direction register to output mode. (3) Event Counter Mode The timer counts signals input through the CNTR0 pin. Except for this, the operation in event counter mode is the same as in timer mode. When using a timer in this mode, set the corre- sponding port P54 direction register to input mode. (4) Pulse Width Measurement Mode The count source is f(XIN)/16 (or f(SUB)/16 in low-speed mode). If CNTR 0 active edge switch bit is “0”, the timer counts while the in- put signal of CNTR0 pin is at “H”. If it is “1”, the timer counts while the input signal of CNTR0 pin is at “L”. When using a timer in this mode, set the corresponding port P54 direction register to input mode.

Timer X write control If the timer X write control bit is “0”, when the value is written in the address of timer X, the value is loaded in the timer X and the latch at the same time. If the timer X write control bit is “1”, when the value is written in the address of timer X, the value is loaded only in the latch. The value in the latch is loaded in timer X after timer X underflows. If the value is written in latch only, when writing in the timer latch at the timer underflow, the value is set in the timer and the latch at one time. Additionally, unexpected value may be set in the high-or- der counter when the writing in high-order latch and the underflow of timer X are performed at the same timing.
Real time port control While the real time port function is valid, data for the real time port are output from ports P5 2 and P5 3 each time the timer X underflows. (However, after rewriting a data for real time port, if the real time port control bit is changed from “0” to “1”, data are output independent of the timer X operation.) If the data for the real time port is changed while the real time port function is valid, the changed data are output at the next underflow of timer X. Before using this function, set the corresponding port direction registers to output mode. ■ Note on CNTR 0 interrupt active edge selection CNTR 0 interrupt active edge depends on the CNTR0 active edge switch bit. Fig. 23 Structure of timer X mode register T i m e r X m o d e r e g i s t e r T X M a d d r e s s T i m e r X w r i t e c o n t r o l b i t W r i t e v a l u e i n l a t c h a n d c o u n t e r W r i t e v a l u e i n l a t c h o n l y R e a l t i m e p o r t c o n t r o l b i t R e a l t i m e p o r t f u n c t i o n i n v a l i d R e a l t i m e p o r t f u n c t i o n v a l i d P d a t a f o r r e a l t i m e p o r t P d a t a f o r r e a l t i m e p o r t T i m e r X o p e r a t i n g m o d e b i t s b b T i m e r m o d e P u l s e o u t p u t m o d e E v e n t c o u n t e r m o d e P u l s e w i d t h m e a s u r e m e n t m o d e C N T R 0 a c t i v e e d g e s w i t c h b i t C o u n t a t r i s i n g e d g e i n e v e n t c o u n t e r m o d e S t a r t f r o m H o u t p u t i n p u l s e o u t p u t m o d e M e a s u r e H p u l s e w i d t h i n p u l s e w i d t h m e a s u r e m e n t m o d e F a l l i n g e d g e a c t i v e f o r C N T R 0 i n t e r r u p t C o u n t a t f a l l i n g e d g e i n e v e n t c o u n t e r m o d e S t a r t f r o m L o u t p u t i n p u l s e o u t p u t m o d e M e a s u r e L p u l s e w i d t h i n p u l s e w i d t h m e a s u r e m e n t m o d e R i s i n g e d g e a c t i v e f o r C N T R 0 i n t e r r u p t T i m e r X s t o p c o n t r o l b i t C o u n t s t a r t C o u n t s t o p b 7 b 0

Rev.2.02 Jun 19, 2007 page 31 of 73 REJ03B0146-0202 Timer Y is a 16-bit timer that can be selected in one of four modes. (1) Timer Mode The timer counts f(XIN)/16 (or f(SUB)/16 in low-speed mode). (2) Period Measurement Mode CNTR 1 interrupt request is generated at rising/falling edge of CNTR 1 pin input signal. Simultaneously, the value in timer Y latch is reloaded in timer Y and timer Y continues counting down. Ex- cept for the above-mentioned, the operation in period measurement mode is the same as in timer mode. The timer value just before the reloading at rising/falling of CNTR pin input signal is retained until the timer Y is read once after the reload. The rising/falling timing of CNTR1 pin input signal is found by CNTR 1 interrupt. When using a timer in this mode, set the corre- sponding port P55 direction register to input mode. (3) Event Counter Mode The timer counts signals input through the CNTR1 pin. Except for this, the operation in event counter mode is the same as in timer mode. When using a timer in this mode, set the corre- sponding port P55 direction register to input mode. (4) Pulse Width HL Continuously Measurement Mode C NTR 1 interrupt request is generated at both rising and falling edges of CNTR1 pin input signal. Except for this, the operation in pulse width HL continuously measurement mode is the same as in period measurement mode. When using a timer in this mode, set the corresponding port P5 5 direction register to input mode. ■ Note on CNTR1 interrupt active edge selection CNTR 1 interrupt active edge depends on the CNTR1 active edge switch bit. However, in pulse width HL continuously measurement mode, CNTR 1 interrupt request is generated at both rising and falling edges of CNTR1 pin input signal regardless of the setting of CNTR 1 active edge switch bit. Fig. 24 Structure of timer Y mode register T i m e r Y m o d e r e g i s t e r T Y M a d d r e s s b7 b 0 N o t u s e d ( r e t u r n “ 0 ” w h e n r e a d ) T i m e r Y o p e r a t i n g m o d e b i t s b b T i m e r m o d e P e r i o d m e a s u r e m e n t m o d e E v e n t c o u n t e r m o d e P u l s e w i d t h H L c o n t i n u o u s l y m e a s u r e m e n t m o d e C N T R 1 a c t i v e e d g e s w i t c h b i t C o u n t a t r i s i n g e d g e i n e v e n t c o u n t e r m o d e M e a s u r e t h e f a l l i n g e d g e t o f a l l i n g e d g e p e r i o d i n p e r i o d m e a s u r e m e n t m o d e F a l l i n g e d g e a c t i v e f o r C N T R 1 i n t e r r u p t C o u n t a t f a l l i n g e d g e i n e v e n t c o u n t e r m o d e M e a s u r e t h e r i s i n g e d g e p e r i o d i n p e r i o d m e a s u r e m e n t m o d e R i s i n g e d g e a c t i v e f o r C N T R 1 i n t e r r u p t T i m e r Y s t o p c o n t r o l b i t C o u n t s t a r t C o u n t s t o p

Rev.2.02 Jun 19, 2007 page 32 of 73 REJ03B0146-0202 Timer 1, Timer 2, Timer 3 Timer 1, timer 2, and timer 3 are 8-bit timers. The count source for each timer can be selected by timer 123 mode register. The timer latch value is not affected by a change of the count source. How- ever, because changing the count source may cause an inadvertent count down of the timer, rewrite the value of timer whenever the count source is changed.

Timer 2 write control If the timer 2 write control bit is “0”, when the value is written in the address of timer 2, the value is loaded in the timer 2 and the latch at the same time. If the timer 2 write control bit is “1”, when the value is written in the address of timer 2, the value is loaded only in the latch. The value in the latch is loaded in timer 2 after timer 2 underflows.
Timer 2 output control When the timer 2 (T OUT ) is output enabled, an inversion signal from the TOUT pin is output each time timer 2 underflows. In this case, set the port shared with the TOUT pin to the output mode. ■ Notes on timer 1 to timer 3 When the count source of timer 1 to 3 is changed, the timer count- ing value may be changed large because a thin pulse is generated in count input of timer . If timer 1 output is selected as the count source of timer 2 or timer 3, when timer 1 is written, the counting value of timer 2 or timer 3 may be changed large because a thin pulse is generated in timer 1 output. Therefore, set the value of timer in the order of timer 1, timer 2 and timer 3 after the count source selection of timer 1 to 3. Fig. 25 Structure of timer 123 mode register TO U T o u t p u t a c t i v e e d g e s w i t c h b i t S t a r t a t H o u t p u t S t a r t a t L o u t p u t TO U T o u t p u t c o n t r o l b i t TO U T o u t p u t d i s a b l e d TO U T o u t p u t e n a b l e d T i m e r w r i t e c o n t r o l b i t W r i t e d a t a i n l a t c h a n d c o u n t e r W r i t e d a t a i n l a t c h o n l y T i m e r c o u n t s o u r c e s e l e c t i o n b i t T i m e r o u t p u t f XI N ) o r f S U B i n l o w s p e e d m o d e T i m e r c o u n t s o u r c e s e l e c t i o n b i t T i m e r o u t p u t f XI N ) o r f S U B i n l o w s p e e d m o d e T i m e r c o u n t s o u r c e s e l e c t i o n b i t f XI N ) o r f S U B i n l o w s p e e d m o d e f S U B N o t u s e d r e t u r n w h e n r e a d T i m e r 1 2 3 m o d e r e g i s t e r T M a d d r e s s N o t e : f ( S U B ) i s t h e s o u r c e o s c i l l a t i o n f r e q u e n c y i n l o w - s p e e d m o d e f S U B s h o w s t h e o s c i l l a t i o n f r e q u e n c y o f XC I N o r t h e o n c h i p o s c i l l a t o r I n t e r n a l c l o c k φ i s f S U B i n t h e l o w s p e e d m o d e b7 b 0

Rev.2.02 Jun 19, 2007 page 33 of 73 REJ03B0146-0202 Serial I/O can be used as either clock synchronous or asynchro- nous (UART) serial I/O. A dedicated timer (baud rate generator) is also provided for baud rate generation. (1) Clock Synchronous Serial I/O Mode Clock synchronous serial I/O can be selected by setting the mode selection bit of the serial I/O control register to “1”. For clock synchronous serial I/O, the transmitter and the receiver must use the same clock. If an internal clock is used, transfer is started by a write signal to the transmit/receive buffer register. The MSB first transfer is selected as the transfer direction by setting the bit 0 in the peripheral function expansion register to “1”. Also, the synchronous serial I/O output switches to the P4 7/SRDY /SOUT pin by setting the bit 1 in the peripheral function expansion register to “1”. Fig. 26 Block diagram of clock synchronous serial I/O Fig. 27 Operation of clock synchronous serial I/O function P 46/ SC L K P47/SRDY1 /SOUT P44/R XD P45/TXD f ( XI N ) 1 / 4 F / F S e r i a l I O s t a t u s r e g i s t e r S e r i a l I O c o n t r o l r e g i s t e r R e c e i v e b u f f e r r e g i s t e r A d d r e s s 0 0 1 81 R e c e i v e s h i f t r e g i s t e r R e c e i v e b u f f e r f u l l f l a g ( R B F ) R e c e i v e i n t e r r u p t r e q u e s t ( R I ) C l o c k c o n t r o l c i r c u i t Shift clock S e r i a l I / O c l o c k s e l e c t i o n b i t F r e q u e n c y d i v i s i o n r a t i o n B a u d r a t e g e n e r a t o r A d d r e s s 0 0 1 C 1 B R G c o u n t s o u r c e s e l e c t i o n b i t Clock control circuitF a l l i n g e d g e d e t e c t o r D ata bus A d d r e s s 0 0 1 81 Shift clock Transm it shift register shift completion flag (TSC) T r a n s m i t b u f f e r e m p t y f l a g ( T B E ) T r a n s m i t i n t e r r u p t r e q u e s t ( T I ) T r a n s m i t i n t e r r u p t s o u r c e s e l e c t i o n b i t Address 001916 D a t a b u s A d d r e s s 0 0 1 A1 T r a n s m i t b u f f e r r e g i s t e r T r a n s m i t s h i f t r e g i s t e r ( f ( S U B ) i n l o w - s p e e d m o d e ) T r a n s f e r d i r e c t i o n s e l e c t i o n b i t Serial output pin selection bit S e r i a l o u t p u t p i n s e l e c t i o n b i t T r a n s f e r d i r e c t i o n s e l e c t i o n b i t N o t e : f ( S U B ) i s t h e s o u r c e o s c i l l a t i o n f r e q u e n c y i n l o w - s p e e d m o d e . f ( S U B ) s h o w s t h e o s c i l l a t i o n f r e q u e n c y o f XC I N o r t h e o n - c h i p o s c i l l a t o r . R e c e i v e e n a b l e s i g n a l SR D Y D 7D 0 D 1 D 2 D 3 D 4 D 5 D 6 RBF = 1 TSC = 1 T B E = 0 T B E = 1 T S C Transfer shift clock (1/2 to 1/2048 of the internal clock, or an external clock) Serial output TXD (or SOUT ) S e r i a l i n p u t R XD W r i t e s i g n a l t o r e c e i v e / t r a n s m i t b u f f e r r e g i s t e r a d d r e s s O v e r r u n e r r o r ( O E ) d e t e c t i o n N o t e s 1 : T h e t r a n s m i t i n t e r r u p t ( T I ) c a n b e g e n e r a t e d e i t h e r w h e n t h e t r a n s m i t b u f f e r r e g i s t e r h a s e m p t i e d ( T B E = 1 ) o r a f t e r t h e t r a n s m i t s h i f t o p e r a t i o n h a s e n d e d T S C b y s e t t i n g t h e t r a n s m i t i n t e r r u p t s o u r c e s e l e c t i o n b i t T I C o f t h e s e r i a l I O c o n t r o l r e g i s t e r I f d a t a i s w r i t t e n t o t h e t r a n s m i t b u f f e r r e g i s t e r w h e n T S C t h e t r a n s m i t c l o c k i s g e n e r a t e d c o n t i n u o u s l y a n d s e r i a l d a t a i s o u t p u t c o n t i n u o u s l y f r o m t h e TXD p i n T h e r e c e i v e i n t e r r u p t R I i s s e t w h e n t h e r e c e i v e b u f f e r f u l l f l a g R B F b e c o m e s D 7D 0 D 1 D 2 D 3 D 4 D 5 D 6 T x D a n d R x D a b o v e s h o w s t h e o p e r a t i o n w h e n s e l e c t i n g L S B f i r s t t r a n s f e r .

Rev.2.02 Jun 19, 2007 page 34 of 73 REJ03B0146-0202 (2) Asynchronous Serial I/O (UART) Mode Clock asynchronous serial I/O mode (UART) can be selected by clearing the serial I/O mode selection bit of the serial I/O control register to “0”. Eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. The transmit and receive shift registers each have a buffer regis- ter, but the two buffers have the same address in memory. Since the shift register cannot be written to or read from directly, transmit data is written to the transmit buffer, and receive data is read from the receive buffer. The transmit buffer can also hold the next data to be transmitted, and the receive buffer register can hold a character while the next character is being received. Fig. 28 Block diagram of UART serial I/O Fig. 29 Operation of UART serial I/O function f(XIN) O E P E F E 1 / 1 6 D ata bus R e c e i v e b u f f e r r e g i s t e r Address 001816 R e c e i v e s h i f t r e g i s t e r R e c e i v e b u f f e r f u l l f l a g ( R B F ) R e c e i v e i n t e r r u p t r e q u e s t ( R I ) Baud rate generator Frequency division ratio 1/(n+1) Address 001C 16 S T S P P A g e n e r a t o r Transmit buffer register D a t a b u s Transm it shift register Address 001816 Transm it shift register shift completion flag (TSC) Transm it buffer empty flag (TBE) Transm it interrupt request (TI) Address 001916 S T d e t e c t o r S P d e t e c t o r UART control register A d d r e s s 0 0 1 B1 C h a r a c t e r l e n g t h s e l e c t i o n b i t Address 001A16 B R G c o u n t s o u r c e s e l e c t i o n b i t T r a n s m i t i n t e r r u p t s o u r c e s e l e c t i o n b i t Serial I/O synchronous clock selection bit C l o c k c o n t r o l c i r c u i t C h a r a c t e r l e n g t h s e l e c t i o n b i t b i t s b i t s Serial I/O control register P 46/ SC L K Serial I/O status register P 44/ R XD P45/TXD ( f ( S U B ) i n l o w - s p e e d m o d e ) N o t e :f ( S U B ) i s t h e s o u r c e o s c i l l a t i o n f r e q u e n c y i n l o w - s p e e d m o d e . f ( S U B ) s h o w s t h e o s c i l l a t i o n f r e q u e n c y o f XC I N o r t h e o n - c h i p o s c i l l a t o r . I n t e r n a l c l o c k φ i s f S U B i n t h e l o w s p e e d m o d e T S C = 0 T B E R B F = 0 T B E = 0 TBE =0 RBF =1 RBF =1 S TD 0 D 1 S P D 0 D 1S T SP TBE =1 TSC=1 ✽ S TD 0 D 1 S P D 0 D 1ST S P T r a n s m i t b u f f e r w r i t e s i g n a l ✽ G e n e r a t e d a t n d b i t i n s t o p b i t m o d e 1 s t a r t b i t o r d a t a b i t s o r p a r i t y b i t o r s t o p b i t s 1 :Error flag detection occurs at the same time that the RBF flag becom es “1” (at 1st stop bit, during reception). 2 :The transmit interrupt (TI) can be selected to occur when either the TBE or TSC flag becomes “1” by the setting of the transmit interrupt source selection bit (TIC) of the serial I/O control register. 3 : The receive interrupt (RI) is set when the RBF flag becomes “1”. 4 : After data is written to the transmit buffer register when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0. N o t e s S e r i a l o u t p u t TXD S e r i a l i n p u t R XD R eceive buffer read signal Transmit or receive clock

Rev.2.02 Jun 19, 2007 page 35 of 73 REJ03B0146-0202 (3) Synchronous/Asynchronous Alternate Transmit Mode Synchronous/asynchronous alternate transmit mode is selected by setting the transmit enable bit in the serial I/O control register to “1” after setting the synchronous serial I/O output pin selection bit in the peripheral function expansion register to “1”. Set the syn- chronous serial I/O output pin selection bit to “1” when the serial I/ O mode selection bit is set to “0”. In this mode, transmit cannot be performed continuously. Write to the transmit buffer register after Fig. 30 Block diagram of synchronous/asynchronous alternate transmit Fig. 31 Operation of synchronous/asynchronous alternate transmit function confirming that the transmit shift register is set to “1”, and then changing the serial I/O mode selection bit. The SRDY output func- tion cannot be used when the clock synchronous serial I/O is selected. Also, when using the internal clock for the transfer clock (the serial I/O synchronous clock selection bit is set to “0”), apply “H” output to the P4 6 pin. The other operation is the same as clock synchronous serial I/O mode and asynchronous serial I/O mode (UART). S e r i a l I O s t a t u s r e g i s t e r P45/TXD N o t f S U B i s t h e s o u r c e o s c i l l a t i o n f r e q u e n c y i n l o w s p e e d m o d e f S U B s h o w s t h e o s c i l l a t i o n f r e q u e n c y o f XC I N o r t h e o n c h i p o s c i l l a t o r Baud rate generator Frequency division ratio 1/(n+1) Clock control circuit T r a n s m i t b u f f e r r e g i s t e r Date bus T r a n s m i t s h i f t r e g i s t e r Address 001816 T r a n s m i t s h i f t r e g i s t e r s h i f t c o m p l e t i o n f l a g T S C T r a n s m i t b u f f e r e m p t y f l a g T B E Transmit interrupt request (TI) A d d r e s s B R G c o u n t s o u r c e s e l e c t i o n b i t Serial I/O synchronous clock selection bit P46/SCLK P 47/ SR D SO U T f XI N ) f(SUB) in low-speed mode y n c h r o n o u s o u t p u (Asynchronous output) S e r i a l I O m o d e s e l e c t i o n b i t S I O M ) Shift clock (Note) T S C T B E

1 TSC=1

T S C S P D 1 D 7 D 0 T B E B E 0 T B E 0 T B E D 1 D 6 D 7 T B E T S C

0 TSC=0

TBE=1 TSC=0 D 0 T B E T S C P46/SCLK P 45/ TXD P 47/ SO U T y n c h r o n o u s o u t p u (Asynchronous output) s y n c h r o n o u s s e r i a l I O o u t p u t s e l e c t i o n b i t T r a n s m i t b u f f e r w r i t e s i g n a l S e r i a l I O m o d e s e l e c t i o n b i t A s y n c h r o n o u s t r a n s m i t A s y n c h r o n o u s t r a n s m i tS y n c h r o n o u s t r a n s m i t Synchronous transmit

Rev.2.02 Jun 19, 2007 page 36 of 73 REJ03B0146-0202 [Transmit Buffer/Receive Buffer Register (TB/RB)] 001816 The transmit buffer register and the receive buffer register are lo- cated at the same address. The transmit buffer register is write-only and the receive buffer register is read-only. If a charac- ter bit length is 7 bits, the MSB of data stored in the receive buffer register is “0”. [Serial I/O Status Register (SIOSTS)] 001916 The read-only serial I/O status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial I/O function and various errors. Three of the flags (bits 4 to 6) are valid only in UART mode. The receive buffer full flag (bit 1) is cleared to “0” when the receive buffer is read. If there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer reg- ister, and the receive buffer full flag is set. A write to the serial I/O status register clears all the error flags OE, PE, FE, and SE. Writ- ing “0” to the serial I/O enable bit (SIOE) also clears all the status flags, including the error flags. All bits of the serial I/O status register are initialized to “0” at reset, but if the transmit enable bit (bit 4) of the serial I/O control register has been set to “1”, the transmit shift register shift completion flag (bit 2) and the transmit buffer empty flag (bit 0) become “1”. [Serial I/O Control Register (SIOCON)] 001A16 The serial I/O control register contains eight control bits for the se- rial I/O function. [UART Control Register (UARTCON) ]001B16 The UART control register consists of four control bits (bits 0 to 3) which are valid when asynchronous serial I/O is selected and set the data format of an data transfer. One bit in this register (bit 4) is always valid and sets the output structure of the P4 5/TXD pin. [Baud Rate Generator (BRG)] 001C16 The baud rate generator determines the baud rate for serial trans- fer. The baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate genera- tor. ■ Notes on serial I/O When setting the transmit enable bit to “1”, the serial I/O transmit interrupt request bit is automatically set to “1”. When not requiring the interrupt occurrence synchronized with the transmission enalbed, take the following sequence. ➀ Set the serial I/O transmit interrupt enable bit to “0” (disabled). ➁ Set the transmit enable bit to “1”. ➂ Set the serial I/O transmit interrupt request bit to “0” after 1 or more instructions have been executed. ➃ Set the serial I/O transmit interrupt enable bit to “1” (enabled).

Rev.2.02 Jun 19, 2007 page 37 of 73 REJ03B0146-0202 Fig. 32 Structure of serial I/O control registers BRG count source selection bit (CSS) 0: f(XIN) (f(SUB) in low-speed mode) 1: f(XIN)/4 (f(SUB)/4 in low-speed mode) Serial I/O synchronization clock selection bit (SCS) 0: BRG output divided by 4 when clock synchronized serial I/O is selected. BRG output divided by 16 when UART is selected. 1: External clock input when clock synchronized serial I/O is selected. External clock input divided by 16 when UART is selected. S RDY , SOUT output enable bit (SRDY) 0: P47 pin operates as ordinary I/O pin 1: P47 pin operates as SRDY or SOUT output pin Set the transmit disable bit and SRDY , SOUT output enable bits to “0” to disable transmit when selecting SOUT . (Setting peripheral function extension register is necessary when selecting S OUT .) Transmit interrupt source selection bit (TIC) 0: Interrupt when transmit buffer has emptied 1: Interrupt when transmit shift operation is completed Transmit enable bit (TE) 0: Transmit disabled 1: Transmit enabled Receive enable bit (RE) 0: Receive disabled 1: Receive enabled Serial I/O mode selection bit (SIOM) 0: Asynchronous serial I/O (UART) 1: Clock synchronous serial I/O Serial I/O enable bit (SIOE) 0: Serial I/O disabled (pins P4 4–P47 operate as ordinary I/O pins) 1: Serial I/O enabled (pins P44–P47 operate as serial I/O pins) Serial I/O control register (SIOCON : address 001A16) b T r a n s m i t b u f f e r e m p t y f l a g ( T B E ) B u f f e r f u l l B u f f e r e m p t y R e c e i v e b u f f e r f u l l f l a g R B F B u f f e r e m p t y B u f f e r f u l l T r a n s m i t s h i f t r e g i s t e r s h i f t c o m p l e t i o n f l a g T S C T r a n s m i t s h i f t i n p r o g r e s s T r a n s m i t s h i f t c o m p l e t e d O v e r r u n e r r o r f l a g O E N o e r r o r O v e r r u n e r r o r P a r i t y e r r o r f l a g P E N o e r r o r P a r i t y e r r o r F r a m i n g e r r o r f l a g F E N o e r r o r F r a m i n g e r r o r S u m m i n g e r r o r f l a g S E O E U P E U F E O E U P E U F E N o t u s e d r e t u r n s w h e n r e a d S e r i a l I / O s t a t u s r e g i s t e r S I O S T S a d d r e s s b UART control register (UARTCON : address 001B16) Ch aracter length selection bit (CH AS) 0: 8 bits 1: 7 bits Parity enable bit (PARE) 0: Parity checking disabled 1: Parity checking enabled Parity selection bit (PARS) 0: Even parity 1: Odd parity Stop bit length selection bit (STPS) 0: 1 stop bit 1: 2 stop bits 5/TXD, P47/SRDY /SOUT P-channel output disable bit (POFF) (Note) 0: CMOS output (in output mode) 1: N-channel open-drain output (in output mode) Not used (return “1” when read) b7 b0 1 :T h e p e r i p h e r a l f u n c t i o n e x t e n s i o n r e g i s t e r i s u s e d t o c h o o s e P 45/ TXD , P 47/ SR D Y/ SO U S U B i s t h e s o u r c e o s c i l l a t i o n f r e q u e n c y i n l o w s p e e d m o d e f S U B s h o w s t h e o s c i l l a t i o n f r e q u e n c y o f XC I N o r t h e o n c h i p o s c i l l a t o r N otes

Rev.2.02 Jun 19, 2007 page 38 of 73 REJ03B0146-0202 [AD Conversion Register (ADH, ADL)] 003516 The AD conversion register is a read-only register that contains the result of an A/D conversion. When reading this register during an A/D conversion, the previous conversion result is read.The high-order 8 bits of a conversion result is stored in the AD conver- sion high-order register (address 0035 16),and the low-order 2 bits of the same result are stored in bit 7 and bit 6 of the AD conver- sion low-order register (address 003616). The bit 0 in the AD conversion low-order register is used as the conversion mode selection bit. 8-bit A/D mode is selected by set- ting this bit to “0” and 10-bit A/D mode is selected by setting it to “1”. [AD Control Register (ADCON)] 003416 The AD control register controls the A/D conversion process. Bits 0 to 2 of this register select specific analog input pins. Bit 3 signals the completion of an A/D conversion. The value of this bit remains at “0” during an A/D conversion, then changes to “1” when the A/D conversion is completed. Writing “0” to this bit starts the A/D conversion. Bit 4 is the V REF input switch bit which controls con- nection of the resistor ladder and the reference voltage input pin REF ). The resistor ladder is always connected to VREF when bit 4 is set to "1". When bit 4 is set to “0”, the resistor ladder is cut off from VREF except for A/D conversion performed. When bit 5, which is the AD external trigger valid bit, is set to “1”, this bit en- ables A/D conversion even by a falling edge of an ADT input. Set the P57/ADT pin to input mode (set "0" to bit 7 of port P5 direction register) when using an A/D external trigger. [Comparison Voltage Generator] The comparison voltage generator divides the voltage between AV SS and VREF , and outputs the divided voltages. [Channel Selector] The channel selector selects one of the input ports P67/AN7–P6 0/ AN 0, and inputs it to the comparator. [Comparator and Control Circuit] The comparator and control circuit compares an analog input volt- age with the comparison voltage and stores the result in the AD conversion register. When an A/D conversion is completed, the control circuit sets the AD conversion completion bit and the AD interrupt request bit to “1”. The comparator is constructed linked to a capacitor. The conver- sion accuracy may be low because the charge is lost if the conversion speed is not enough. Accordingly, set f(X IN) to at least 500kHz during A/D conversion in the middle-or high-speed mode. Also, do not execute the STP or WIT instruction during an A/D conversion. In the low-speed mode, since the A/D conversion is executed by the built-in self-oscillation circuit, the minimum value of f(X IN) fre- quency is not limited. Fig. 33 Structure of AD conversion-related registers A D c o n t r o l r e g i s t e r A D C O N a d d r e s s AD conversion completion bit 0 : Conversion in progress 1 : Conversion completed A n a l o g i n p u t p i n s e l e c t i o n b i t s P 60/ A N 0 P 61/ A N 1 P 62/ A N 2 P 63/ A N 3 P 64/ A N 4 P 65/ A N 5 P 66/ A N 6 P 67/ A N 7 VREF input switch bit 0 : ON during conversion 1 : Always ON AD external trigger valid bit 0 : A/D external trigger invalid 1 : A/D external trigger valid b7 b 0 Interrupt source selection bit 0 : Interrupt request at A/D conversion completed 1 : Interrupt request at ADT input falling N ot used (returns “0” when read) AD conversion low-order register (ADL : address 003616) AD conversion speed selection bit 00 : f(XIN)/2 (this can be used in CPUM7 = “0” ) 01 : f(XIN) (this can be used in CPUM7 = “0” ) 10 : On-chip oscillator (this can be used in CPUM7 = “0” and EXPCM0 = “1”) 11 : Disabled C onversion mode selection bit 0 : 8 bit A/D mode 1 : 10 bit A/D mode N ot used (returns “0” when read)

In 10-bit A/D mo de A/D conversion data storage
In 8-bit A/D mode Not used (Indefinite at read) b7 b 0

Rev.2.02 Jun 19, 2007 page 39 of 73 REJ03B0146-0202 Fig. 34 A/D conversion register reading Fig. 35 A/D converter block diagram AD conversion high-order register D a t a b u s A D c o n t r o l c i r c u i t R e s i s t o r l a d d e r AV SS VREF C o m p a r a t o r A D T A D i n t e r r u p t r e q u e s t b7 b0 A D c o n t r o l r e g i s t e r P 60/ SI N A N 0 P 61/ A N 1 P62/AN2 P 63/ A N 3 P 64/ A N 4 P 65/ A N 5 P66/AN6 P67/AN7 P 57/ A D T (Address 003516) (Address 003616) AD conversion low-order register C h a n n e l s e l e c t o r Conversion mode selection bit AD conversion speed selection bit A D c o n v e r s i o n l o w o r d e r r e g i s t e r A d d r e s s A D L A D c o n v e r s i o n h i g h o r d e r r e g i s t e r A d d r e s s A D H b1 b b 7 b0 b i t r e a d i n g R e a d a d d r e s s b e f o r e b b9 b8 b7 b6 b5 b4 b3 b2 (High-order) (low-order) Note: The bit 5 to bit 3 of address 003616 become "0" at reading.

8 bit reading (Read only address 003516) b7 b b b 2b 1b A d d r e s s 000

Rev.2.02 Jun 19, 2007 page 40 of 73 REJ03B0146-0202 The 3823 group has the built-in Liquid Crystal Display (LCD) drive control circuit consisting of the following.

LCD display RAM
Segment output enable register
LCD mode register
Selector
Timing controller
Common driver
Segment driver
Bias control circuit A maximum of 32 segment output pins and 4 common output pins can be used. Up to 128 pixels can be controlled for LCD display. When the LCD Fig. 36 Structure of segment output enable register and LCD mode register enable bit is set to “1” after data is set in the LCD mode register, the segment output enable register and the LCD display RAM, the LCD drive control circuit starts reading the display data automati- cally, performs the bias control and the duty ratio control, and displays the data on the LCD panel. Table 10 Maximum number of display pixels at each duty ratio Duty ratio Maximum number of display pixel 64 dots or 8 segment LCD 8 digits 96 dots or 8 segment LCD 12 digits 128 dots or 8 segment LCD 16 digits LCD mode register (LM : address 003916) S e g m e n t o u t p u t e n a b l e r e g i s t e r S E G a d d r e s s Duty ratio selection bits 0 0 : Not used 0 1 : 2 (use COM 0, COM1) 1 0 : 3 (use COM0–COM 2) 1 1 : 4 (use COM0–COM 3) Bias control bit 0 : 1/3 bias 1 : 1/2 bias LCD enable bit 0 : LCD OFF 1 : LCD ON No t used (returns “0” when read) (Do not write “1” to this bit) LCD circuit divider division ratio selection bits 0 0 : Clock input 0 1 : 2 division of clock input 1 0 : 4 division of clock input 1 1 : 8 division of clock input LCDCK count source selection bit (Note) 0 : f(SUB)/32 1 : f(X IN)/8192 (or f(SUB)/8192 in low-speed m ode) N o t e : L C D C K i s a c l o c k f o r a L C D t i m i n g c o n t r o l l e r . f S U B i s t h e s o u r c e o s c i l l a t i o n f r e q u e n c y i n l o w s p e e d m o d e f S U B s h o w s t h e o s c i l l a t i o n f r e q u e n c y o f XC I N o r t h e o n c h i p o s c i l l a t o r I n t e r n a l c l o c k φ i s f S U B i n t h e l o w s p e e d m o d e Segment output enable bit 0 0 : Input port P34–P37 1 : Segment output SEG12–SEG 15 Segment output enable bit 1 0 : I/O port P00,P01 1 : Segment output SEG16, SEG17 Segment output enable bit 2 0 : I/O port P02–P07 1 : Segment output SEG18–SEG 23 Segment output enable bit 3 0 : I/O port P10,P11 1 : Segment output SEG24, SEG25 Segment output enable bit 4 0 : I/O port P12 1 : Segment output SEG26 Segment output enable bit 5 0 : I/O port P13–P17 1 : Segment output SEG27–SEG 31 No t used (returns “0” when read) No t used (returns “0” when read) (Do not write “1” to this bit.) b 7b 0 b7 b0

Rev.2.02 Jun 19, 2007 page 41 of 73 REJ03B0146-0202 Fig. 37 Block diagram of LCD controller/driver C O M C O M C O M C O M V S S V L V L V L S E G S E G S E G S E G “ 1 “ 0 L C D C K P 17/ S E G P 16/ S E G P 34/ S E G f ( S U B f ( X I o r f S U B i n l o w s p e e d m o d e D a t a b u s A d d r e s s 0 0 A d d r e s s 0 0 A d d r e s s 0 0 F S e l e c t o r S e l e c t o r S e l e c t o r S e l e c t o r S e l e c t o r S e l e c t o r S e g m e n t d r i v e r S e g m e n t d r i v e r S e g m e n t d r i v e r S e g m e n t d r i v e r S e g m e n t d r i v e r S e g m e n t d r i v e r B i a s c o n t r o l L C D d i v i d e r T i m i n g c o n t r o l l e r C o m m o n d r i v e r D u t y r a t i o s e l e c t i o n b i t s C o m m o n d r i v e r C o m m o n d r i v e r C o m m o n d r i v e r B i a s c o n t r o l b i t L C D c i r c u i t d i v i d e r d i v i s i o n r a t i o s e l e c t i o n b i t s L C D C K c o u n t s o u r c e s e l e c t i o n b i t L C D d i s p l a y R A M L C D e n a b l e b i t V C C L C D e n a b l e b i t N o t e f S U B i s t h e s o u r c e o s c i l l a t i o n f r e q u e n c y i n l o w s p e e d m o d e f S U B s h o w s t h e o s c i l l a t i o n f r e q u e n c y o f X C I N o r t h e o n c h i p o s c i l l a t o r

Rev.2.02 Jun 19, 2007 page 42 of 73 REJ03B0146-0202 Bias Control and Applied Voltage to LCD Power Input Pins To the LCD power input pins (VL1–V L3), apply the voltage shown in Table 11 according to the bias value. Select a bias value by the bias control bit (bit 2 of the LCD mode register). Common Pin and Duty Ratio Control The common pins (COM 0–COM 3) to be used are determined by duty ratio. Select duty ratio by the duty ratio selection bits (bits 0 and 1 of the LCD mode register). Fig. 38 Example of circuit at each bias Table 12 Duty ratio control and common pins used Duty ratio Common pins used Notes1: COM 2 and COM 3 are open. 2: COM 3 is open. Bit 1 Bit 0 COM 0, COM 1 (Note 1) Duty ratio selection bit COM 0–COM 2 (Note 2) COM 0–COM 3 Table 11 Bias control and applied voltage to VL1–VL3 Bias value 1/3 bias Voltage value VL3=V LCD VL2=2/3 VLCD VL1=1/3 VLCD Note 1: V LCD is the maximum value of supplied voltage for the LCD panel. 1/2 bias VL3=V LCD VL2=V L1=1/2 VLCD C ontrast control 1 / 2 b i a s1 / 3 b i a s C ontrast control VL3 R 4 R 5 R 4 = R 5 R 1 R 3 R 1 = R 2 = R 3 VL VL1 VL3 VL VL1

Rev.2.02 Jun 19, 2007 page 43 of 73 REJ03B0146-0202 Address 004016 to 004F16 is the designated RAM for the LCD dis- play. When “1” are written to these addresses, the corresponding segments of the LCD display panel are turned on. Fig. 39 LCD display RAM map LCD Drive Timing The LCDCK timing frequency (LCD drive timing) is generated in- ternally and the frame frequency can be determined with the following equation; f(LCDCK) = Frame frequency = (frequency of count source for LCDCK) (divider division ratio for LCD) f(LCDCK) (duty ratio) B i t A d d r e s s 004016 004116 004216 004316 004416 004516 004616 004716 004816 004916 004A16 004B16 004C 16 004D 16 004E16 004F16 COM 3 0123456 COM 0COM 1 COM 2 COM 3 COM 0COM 1COM 2 SEG 1 SEG 3 SEG 5 SEG 7 SEG 9 SEG 11 SEG 13 SEG 15 SEG 17 SEG 19 SEG 21 SEG 23 SEG 25 SEG 27 SEG 29 SEG 31 SEG 0 SEG 2 SEG 4 SEG 6 SEG 8 SEG 10 SEG 12 SEG 14 SEG 16 SEG 18 SEG 20 SEG 22 SEG 24 SEG 26 SEG 28 SEG 30 STP Instruction Execution Execution of the STP instruction sets the LCD enable bit (bit 3 of the LCD mode register) to “0” and the LCD panel turns off.To make the LCD panel turn on after returning from the stop mode, set the LCD enable bit to “1”.

Rev.2.02 Jun 19, 2007 page 44 of 73 REJ03B0146-0202 Fig. 40 LCD drive waveform (1/2 bias) I n t e r n a l l o g i c L C D C K t i m i n g 1 / 4 d u t y Voltage level VL VL 2= VL VSS VL VS S C O M 0 C O M 1 C O M 2 C O M 3 S E G 0 O F FO N OFF O N C O M 3 COM 2 COM 1 COM 0 COM 3 C O M 2 C O M 1 C O M 0 1 / 3 d u t y VL VL2=VL1 VSS VL VSS O F FO N O NO F F O NO F F 1 / 2 d u t y C O M 0 COM 1 C O M 2 SEG 0 C O M 0 C O M 1 S E G 0 VL3 VL 2= VL VS S VL VS S OFFON OFFON OFFON OFFON C O M 0 C O M 2 C O M 1 COM 0 C O M 2 C O M 1 C O M 0 C O M 2 C O M 1 C O M 0 C O M 1 COM 0 C O M 1 C O M 0 C O M 1 C O M 0

Rev.2.02 Jun 19, 2007 page 45 of 73 REJ03B0146-0202 Fig. 41 LCD drive waveform (1/3 bias) I n t e r n a l l o g i c L C D C K t i m i n g 1 / 4 d u t y V o l t a g e l e v e l VL VS S C O M 0 COM 1 C O M 2 C O M 3 SEG 0 O F FO N O F FO N COM 3 COM 2 COM 1 COM 0 COM 3 COM 2 COM 1 COM 0 1 / 3 d u t y OFFO N ON OFF O NO F F 1/2 duty COM 0 C O M 1 C O M 2 SEG 0 C O M 0 C O M 1 SEG 0 OFFO N O F FO N O F FO N OFFO N VL VL VS S VL VL VL VSS VL VL3 VSS VL3 VL VSS VL VL VS S C O M 0 COM 2 COM 1 COM 0 C O M 2 C O M 1 C O M 0 C O M 2 C O M 1 C O M 0 C O M 1 C O M 0 C O M 1 C O M 0 C O M 1 C O M 0

Rev.2.02 Jun 19, 2007 page 46 of 73 REJ03B0146-0202 A part of program in ROM can be corrected. Set the start address of the corrected ROM data (i.e. an Op code address of the beginning instruction) to the ROM correction ad- dress low-order and high-order registers. The program for the correction is stored in RAM for ROM correction. When the program is being executed and the value of the program counter matches with the set address value in the the ROM cor- rection address registers,the program is branched to the start address of RAM for ROM correction and then the correction pro- gram is executed. Use the JMP instruction (3-byte instruction) to return the main program from the correction program. The correctable area is up to two. There are two blocks of RAM for ROM correction: Block 1: Address 0A00 Block 2: Address 0A2016 The ROM correction function is controlled by the ROM correction enable register. If the ROM correction function is not used, the ROM correction vector may be used as normal RAM. When using the ROM correc- tion vector as normal RAM, make sure to set bits 1 and 0 in the ROM correction enable register to “0” (Disable). Notes 1:When using the ROM correction function, set the ROM correction address registers and then enable the ROM correction with the ROM correction enable register. 2:Do not set addresses other than the ROM area in the ROM correction address registers. Do not set the same addresses in both the ROM correc- tion address 1 registers and the ROM correction address 2 registers. 3:It is necessary to contain the process in the program to transfer the correction program from an external EEPROM and others to the RAM for ROM correction. Fig. 42 ROM correction address register Fig. 44 Structure of ROM correction enable register 6ROM correction address 1 high-order register (RCA1H) 001216 001316 ROM correction address 1 low-order register (RCA1L) ROM correction address 2 low-order register (RCA2L) ROM correction address 2 high-order register (RCA2H) Note: Do not set addressed other than the ROM area. A d d r e s s e n a b l e b i t R C D i s a b l e E n a b l e A d d r e s s e n a b l e b i t R C D i s a b l e E n a b l e N o t u s e d r e t u r n s w h e n r e a d R O M c o r r e c t i o n e n a b l e r e g i s t e r A d d r e s s N o t e R C R b N o t e : S e t t h e R O M c o r r e c t i o n a d d r e s s r e g i s t e r s b e f o r e e n a b l i n g t h e R O M c o r r e c t i o n w i t h t h e R O M c o r r e c t i o n e n a b l e r e g i s t e r Fig. 43 RAM for ROM correction R A M 1 f o r R O M c o r r e c t i o n R A M 2 f o r R O M c o r r e c t i o n 0A0016 0A1F16 0A2016 0A3F16

Rev.2.02 Jun 19, 2007 page 47 of 73 REJ03B0146-0202 φφφφφ CLOCK SYSTEM OUTPUT FUNCTION The internal system clock φ or XCIN frequency signal can be out- put from port P41 by setting the φ output control register. Set bit 1 of the port P4 direction register to “1” when outputting φ clock. Fig. 45 Structure of φφφφφ output control register φ output control register (CKOUT : address 002A16) φ output control bit 0 : port function 1 : φ clock output or XCIN frequency signal output No t used (return “0” when read) b 7 b 0 Temporary data register The temporary data register (addresses 002C16 to 002E16) is the 8-bit register and does not have the control function. It can be used to store data temporarily. It is initialized after reset. RRF register The RRF register (address 002F16)is the 8-bit register and does not have the control function. As for the value written in this regis- ter, high-order 4 bits and low-order 4 bits interchange. It is initialized after reset. Fig. 46 Structure of temporary register, RPF register Set the bit 4 in the peripheral function expansion register to “1” when the XCIN frequency signal is output. b7 b0 T e m p o r a r y d a t a r e g i s t e r A d d r e s s C 1 D 1 D d a t a s t o r a g e D d a t a s t o r a g e D d a t a s t o r a g e D d a t a s t o r a g e D d a t a s t o r a g e D d a t a s t o r a g e D d a t a s t o r a g e D d a t a s t o r a g e TD 0,TD1,TD2 b R R F r e g i s t e r A d d r e s s D d a t a s t o r a g e D d a t a s t o r a g e D d a t a s t o r a g e D d a t a s t o r a g e D d a t a s t o r a g e D d a t a s t o r a g e D d a t a s t o r a g e D d a t a s t o r a g e R R F R

Rev.2.02 Jun 19, 2007 page 48 of 73 REJ03B0146-0202 The watchdog timer gives a mean of returning to the reset status when a program cannot run on a normal loop (for example, be- cause of a software run-away). The watchdog timer consists of an 8-bit counter. Initial Value of Watchdog Timer At reset or writing to the watchdog timer control register, each watchdog timer is set to “FF16.” Instructions such as STA, LDM and CLB to generate the write signals can be used. The written data in bits 0 to 5 are not valid, and the above values are set. Bits 7 and 6 can be rewritten only once after reset. After rewriting it is disable to write any data to this bit. These bits become “0” after reset. Standard Operation of Watchdog Timer The watchdog timer is in the stop state at reset and the watchdog timer starts to count down by writing an optional value in the watchdog timer control register. An internal reset occurs at an un- derflow of the watchdog timer. Then, reset is released after the reset release time is elapsed, the program starts from the reset vector address. Normally, writing to the watchdog timer control register before an underflow of the watchdog timer is pro- grammed. If writing to the watchdog timer control register is not executed, the watchdog timer does not operate. When reading the watchdog timer control register is executed, the contents of the high-order 6-bit counter and the STP instruction bit (bit 6), and the count source selection bit (bit 7) are read out. Bit 6 of Watchdog Timer Control Register

When bit 6 of the watchdog timer control register is “0”, the MCU enters the stop mode by execution of STP instruction. Just after releasing the stop mode, the watchdog timer restarts counting (Note). When executing the WIT instruction, the watch- dog timer does not stop.
When bit 6 is “1”, execution of STP instruction causes an internal reset. When this bit is set to “1” once, it cannot be rewritten to “0” by program. Bit 6 is “0” at reset. The time until the underflow of the watchdog timer register after writing to the watchdog timer control register is executed is as fol- lows (when the bit 7 of the watchdog timer control register is “0”) ;
at frequency/2/4/8 mode (f(X IN)) = 8 MHz): 32.768 ms
at low-speed mode (f(XCIN) = 32 KHz): 8.19s ■ Note The watchdog timer continues to count even during the wait time set by timer 1 and timer 2 to release the stop state and in the wait mode. Accordingly, do not underflow the watchdog timer in this time. Fig. 47 Block diagram of Watchdog timer Fig. 48 Structure of Watchdog timer control register Fig. 49 Timing of reset output I n t e r n a l r e s e t s i g n a l W a t c h d o g t i m e r d e t e c t i o n s e c f XI N ) M H Z) f XI N Watchdog timer H (for read-out of high-order 6 bit) “FF16” is set to watchdog timer by writing to these bits. Watchdog timer count source selection bit 0: f(XIN)/1024 (f(SUB )/1024 at low-speed mode) 1: f(XIN)/4 (f(SUB )/1024 at low-speed mode) STP instruction function selection bit 0: Entering stop mode by execution of STP instruction 1: Internal reset by execution of STP instruction Watchdog timer control register (Address 003716) WDTCON b7 b0 Note : Bits 6 and 7 can be rewritten only once after reset. After rewriting it is disable to write any data to this bit. XIN Data bus XCIN Internal system clock selection bit (bit 7 of the CPU mode register) Watchdog timer H (6) Watchdog timer count source selection bit Reset circuit Undefined instruction Reset “FF16” is set when watchdog timer control register is written to. Internal resetRESET Wait until reset release Watchdog timer L (2) STP instruction STP instruction bit “0” “1” “1” “0” On-chip oscillator mode control bitOn-chip oscillator

Rev.2.02 Jun 19, 2007 page 49 of 73 REJ03B0146-0202 PERIPHERAL FUNCTION EXTENSION REGISTER The serial I/O transfer direction can be switched by setting the bit 0 in the peripheral function expansion register to “1”. This function is valid only when the bit 6 in the serial I/O control register is set to “1” (when the clock synchronous serial I/O is selected). P4 7 can be selected as the output pin of the clock synchronous serial I/O by setting the bit 1 in the peripheral function expansion register to “1”. When setting P4 7 to the SOUT pin, set the bit 7 in the port P4 direction register to “1”. This function is valid only when the bit 6 in the serial I/O control register to “1” (when the clock synchronous serial I/O is selected). P-channel output of T XD and SOUT can be disabled by the bits 2 and 3 in the peripheral function expansion register. Set the bit 4 in the UART control register to “1” after se- lecting the pin to disable the P-channel output. X CIN frequency signal can be output from the port P41 by setting the bit 4 in the peripheral function expansion register to “1”. Set the bit 0 in the φ output control register and the bit 1 in the port P4 direction regis- ter to “1” to output the XCIN frequency signal. Fig. 50 Structure of peripheral function extension register Transfer direction selection bit (valid when UART is used) 0 : LSB first 1 : MSB first Synchronous serial I/O output pin selection bit 0:P4 5/TXD pin 1:P47/SRDY /SOUT pin P-channel output disabled selection bit 00: P45/TXD pin 01: The bit 4 in the UART control register is invalid 10: P45/TXD pin or P47/SRDY /SOUT pin 11: P47/SRDY /SOUT pin Output clock selection bit 0: φ clock output 1: XCIN frequency signal output Not used (returns “0” when read) (Do not write “1” to this bit) Peripheral function extension register (Address: 003016) EXP b

Rev.2.02 Jun 19, 2007 page 50 of 73 REJ03B0146-0202 To reset the microcomputer, RESET pin should be held at an “L” level for 2 µs or more. Then the RESET pin is returned to an “H” level (the power source voltage should be between V CC (min.) and

5.5 V, and the quartz-crystal oscillator should be stable), reset is

released. After the reset is completed, the program starts from the address contained in address FFFD 16 (high-order byte) and ad- dress FFFC16 (low-order byte). Make sure that the reset input voltage meets VIL spec. when a power source voltage passes VCC (min.). Fig. 51 Reset Circuit Example Fig. 52 Reset Sequence P o w e r o n P o w e r s o u r c e v o l t a g e R e s e t i n p u t v o l t a g e P o w e r s o u r c e v o l t a g e d e t e c t i o n c i r c u i t VI L s p e c . 0 V 0 V VC CR E S E T VC CR E S E T R E S E T I n t e r n a l r e s e t A d d r e s s D a t a S Y N C φ XIN XI N a b o u t 8 0 0 0 c y c l e s R e s e t a d d r e s s f r o m v e c t o r t a b l e N o t e s 1 : T h e f r e q u e n c y r e l a t i o n o f f ( XI N ) a n d f (φ) i s f ( XI N ) = 8 • f (φ) T h e q u e s t i o n m a r k s i n d i c a t e a n u n d e f i n e d s t a t e t h a t d e p e n d s o n t h e p r e v i o u s s t a t e F F F CF F F D A D H A D L AD L AD H ????

Rev.2.02 Jun 19, 2007 page 51 of 73 REJ03B0146-0202 Fig. 53 Initial status of microcomputer after reset P o r t P 0 d i r e c t i o n r e g i s t e r P o r t P d i r e c t i o n r e g i s t e r P o r t P d i r e c t i o n r e g i s t e r P o r t P d i r e c t i o n r e g i s t e r P o r t P d i r e c t i o n r e g i s t e r P o r t P d i r e c t i o n r e g i s t e r P o r t P d i r e c t i o n r e g i s t e r R O M c o r r e c t o i n e n a b l e r e g i s t e r R C R P U L L r e g i s t e r A P U L L r e g i s t e r B S i r i a l I O s t a t u s r e g i s t e r S i r i a l I O c o n t r o l r e g i s t e r U A R T c o n t r o l r e g i s t e r T i m e r X h i g h o r d e r r e g i s t e r T i m e r X l o w o r d e r r e g i s t e r T i m e r Y h i g h o r d e r r e g i s t e r T i m e r Y l o w o r d e r r e g i s t e r T i m e r r e g i s t e r T i m e r r e g i s t e r T i m e r r e g i s t e r T i m e r X m o d e r e g i s t e r T i m e r Y m o d e r e g i s t e r T i m e r m o d e r e g i s t e r φ o u t p u t c o n t r o l r e g i s t e r C P U m o d e e x t e n s i o n r e g i s t e r Te m p o r a r y d a t a r e g i s t e r T e m p o r a r y d a t a r e g i s t e r T e m p o r a r y d a t a r e g i s t e r R R F r e g i s t e r P e r i p h e r a l f u n c t i o n e x t e n s i o n r e g i s t e r A D c o n t r o l r e g i s t e r A D c o n v e r s i o n l o w o r d e r r e g i s t e r W a t c h d o g t i m e r c o n t r o l r e g i s t e r S e g m e n t o u t p u t e n a b l e r e g i s t e r L C D m o d e r e g i s t e r I n t e r r u p t e d g e s e l e c t i o n r e g i s t e r C P U m o d e r e g i s t e r I n t e r r u p t r e q u e s t r e g i s t e r I n t e r r u p t r e q u e s t r e g i s t e r I n t e r r u p t c o n t r o l r e g i s t e r I n t e r r u p t c o n t r o l r e g i s t e r P r o c e s s o r s t a t u s r e g i s t e r P r o g r a m c o u n t e r Note: The contents of all other registers and RAM are undefined after reset, so they must be initialized by software. ✕ : undefined R e g i s t e r C o n t e n t sAddress 0 01 F F F F F F C o n t e n t s o f a d d r e s s F F F D 1 C o n t e n t s o f a d d r e s s F F F C 1 ( 1 ) 000116 000316 000516 000916 000B16 000D 16 000F16 001416 001616 001716 001916 001A16 001B16 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C 16 002D 16 002E16 002F16 003016 003416 003616 003716 003816 003916 003A16 003B16 003C 16 003D 16 003E16 003F16 (PS) (PCH ) (PCL) 0 0001 00 0 1 1100 00 0 1 0000 00 0 0 0001 11 0 ✕✕ 000 00 0 00111 11 1 01001 00 0

Rev.2.02 Jun 19, 2007 page 52 of 73 REJ03B0146-0202 The 3823 group has two built-in oscillation circuits. An oscillation circuit can be formed by connecting a resonator between XIN and XOUT (XCIN and XCOUT ). Use the circuit constants in accordance with the resonator manufacturer's recommended values. The os- cillation start voltage and the oscillation start time differ in accordance with an oscillator, a circuit constant, or temperature, etc. When power supply voltage is low and the high frequency oscilla- tor is used, an oscillation start will require sufficient conditions. No external resistor is needed between X IN and XOUT since a feed- back resistor exists on-chip. (an external feed-back resistor may be needed depending on conditions.) However, an external feed- back resistor is needed between X CIN and XCOUT since a resistor does not exist between them. To supply a clock signal externally, input it to the XIN pin and make the XOUT pin open. The sub-clock XCIN-XCOUT oscillation circuit cannot directly input clocks that are externally generated. Accord- ingly, be sure to cause an external resonator to oscillate. Immediately after poweron, only the X IN oscillation circuit starts oscillating, and XCIN and XCOUT pins function as I/O ports. Fig. 55 External clock input circuit XI N E x t e r n a l o s c i l l a t i o n c i r c u i t Open VC C VS S C C I N C C O U T Rf Rd XC I N XC O U T XO U T Frequency Control (1) frequency/8 Mode The internal clock φ is the frequency of XIN divided by 8. After reset, this mode is selected. (2) frequency/4 Mode The internal clock φ is the frequency of XIN divided by 4. (3) frequency/2 Mode The internal clock φ is half the frequency of XIN. (4) Low-speed Mode

The internal clock φ is the frequency of XIN or on-chip oscillation frequency divided by 2.
A low-power consumption operation can be realized by stopping the main clock XIN in this mode. To stop the main clock, set bit 5 of the CPU mode register to “1”. When the main clock XIN is restarted, set enough time for oscil- lation to stabilize by programming. In low speed mode, the system clock φ can be switched to the on-chip oscillator or XCIN. Use the on-chip oscillator control bit (bit 0 in the CPU mode expansion register) for settings. To set this bit to “0” from “1”, wait until XCIN oscillation stabilizes. Note 1: If you switch the mode between frequency/2/4/8 mode and low-speed, stabilize both XIN and XCIN oscillations. The sufficient time is required for the sub-clock to stabi- lize, especially immediately after poweron and at returning from stop mode. When switching the mode be- tween middle/high-speed and low-speed, set the frequency on condition that f(X IN) > 3f(XCIN). 2: In frequency/2/4/8 mode, XIN-XOUT oscillation does not stop even if the main clock (XIN-XOUT ) stop bit is set to "1". 3: In low speed mode, XCIN-XCOUT oscillation does not stop even if the port XC switch bit is set to "0". Fig. 54 Ceramic resonator circuit example XCIN XCOUT XIN XOUT C IN C OUTC CIN C COUT Rf Rd Rd Note : Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive capacity setting. Use the value recommended by the maker of the oscillator. Also, if the oscillator manufacturer's data sheet specifies that a feedback resistor be added external to the chip though a feedback resistor exists on-chip, insert a feedback resistor between X IN and XOUT following the instruction.

Rev.2.02 Jun 19, 2007 page 53 of 73 REJ03B0146-0202 Fig. 56 Clock generating circuit block diagram Oscillation Control (1) Stop Mode If the STP instruction is executed, the internal clock φ stops at an “H” level, and XIN and XCIN oscillators stop. Timer 1 is set to “FF16” and timer 2 is set to “0116”. Either XIN or XCIN divided by 16 is input to timer 1 as count source, and the output of timer 1 is connected to timer 2. The bits of the timer 123 mode register except bit 4 are cleared to “0”. Set the timer 1 and timer 2 interrupt enable bits to disabled (“0”) be- fore executing the STP instruction. Oscillator restarts at reset or when an external interrupt is received, but the internal clock φ is not supplied to the CPU until timer 2 underflows. This allows timer for the clock circuit oscillation to stabilize. Execution of the STP instruction sets the LCD enable bit (bit 3 of the LCD mode register) to “0” and the LCD panel turns off.To make the LCD panel turn on after returning from the stop mode, set the LCD enable bit to “1”. (2) Wait Mode If the WIT instruction is executed, only the system clock φ stops at an "H" state. The states of main clock, on-chip oscillator and sub clock are the same as the state before executing the WIT instruc- tion, and oscillation does not stop. Since supply of system clock φ is started immediately after the interrupt is received, the instruc- tion can be executed immediately. Timing φ (Internal system clock) Main clock stop bit Timer 2Timer 11/2 1/4 XIN XOUT WIT instruction STP instruction S R Q STP instruction S R Q S R Q Interrupt request Interrupt disable flag 1 Reset “1” “0” Timer 1 count source selection bit “0” “1” Timer 2 count source selection bitLow-speed mode Frequency/2/4/8 mode (Note 1) Frequency/8 mode Frequency/2/4 mode or low- speed mode Internal system clock selection bit Main clock division ratio selection bit “1” “0” “0” “1” Notes 1:When using the low-speed mode, set the port X C switch bit to “1” . 2:Although a feed-back resistor exists on-chip, an external feed-back resistor may be needed depending on conditions. Frequency/4 mode control bit XCOUTXCIN Port XC switch bit “0”“1” On-chip oscillator On-chip oscillator control bit f(SUB) (Note 2)

Rev.2.02 Jun 19, 2007 page 54 of 73 REJ03B0146-0202 Notes 1 : Switch the mode by the allows shown between the mode blocks. (Do not switch between the mode directly without an allow.) 2 : The all modes can be switched to the stop mode or the wait mode and returned to the source mode when the stop mode or the wait mode is ended. 3 : Timer and LCD operate in the wait mode. 4 : When the stop mode is ended, a delay of approximately 1 ms occurs automatically by timer 1 and timer 2 in frequency/2/4/8 mode. 5 : When the stop mode is ended, a delay of approximately 0.25 s occurs automatically by timer 1 and timer 2 in low-speed mode. 6 : Wait until oscillation stabilizes after oscillating the main clock XIN before the switching from the low-speed mode to frequency/2/4/8 mode. 7 : The example assumes that 8 MHz is being applied to the XIN pin and 32 kHz to the XCIN pin. φ indicates the internal clock. 8 : f(SUB) is the source oscillation frequency in low-speed mode. f(SUB) shows the oscillation frequency of XCIN or the on-chip oscillator. Internal clock φ is f(SUB)/2 in the low-speed mode. 9 : Set the CPU mode expansion register in advance when switching to low-speed mode which uses mode divided by 4 and on-chip oscillator. 10: In low speed mode, the system clock φ can be switched to the on-chip oscillator or XCIN. Use the on-chip oscillator control bit (bit 0 in the CPU mode expansion register) for settings. To set this bit to "0" from "1", wait until XCIN oscillation stabilizes. CM 4 : Port Xc switch bit (Note 1) 0: I/O port (Oscillation stopped) 1: X CIN, XCOUT oscillating function CM 5 :M ain clock (XIN–XOUT ) stop bit (Note 2) 0: Oscillating 1: Stopped CM 6 :M ain clock division ratio selection bit 0: f(XIN)/2 (frequency/2 mode), or f(XIN)/4 (frequency/4 mode) (Note 3) 1: f(XIN)/8 (frequency/8 mode) CM 7 :Internal system clock selection bit 0: XIN–XOUT selected (frequency/2/4/8 mode) 1: XCIN–XCOUT , or on-chip oscillator selected (low-speed mode) (Note 4) CPU mode register (CPUM : address 003B16) b7 b4 Rese t CM 6 “0”“1” CM “0” “1” CM 7 = 0 (8 MHz selected) CM 6 = 1 (Frequency/8) CM 5 = 0 (8 MHz oscillating) CM 4 = 0 (Stopped) Frequency/8 mode (f(φ) = 1 MHz) Frequency/8 mode (f(φ) = 1 MHz) CM 7 = 0 (8 MHz selected) CM 6 = 0 (Frequency/2/4) CM 5 = 0 (8 MHz oscillating) CM 4 = 0 (Stopped) Frequency/2 mode (f(φ) = 4 MHz) or frequency/4 mode (f(φ) = 2 MHz) Frequency/2 mode (f(φ) = 4 MHz) or frequency/4 mode (f(φ) = 2 MHz) CM 7 = 1 (32 kHz or on-chip oscillator selected) CM 6 = 1 (Middle-speed) CM 5 = 0 (8 MHz oscillating) CM 4 = 1 (Oscillating) Low-speed mode (f(SUB)/2) CM 7 = 1 (32 kHz or on-chip oscillator selected) CM 6 = 0 (High-speed) CM 5 = 0 (8 MHz oscillating) CM 4 = 1 (Oscillating) Low-speed mode (f(SUB)/2) CM 7 = 1 (32 kHz or on-chip oscillator selected) CM 6 = 1 (Middle-speed) CM 5 = 1 (8 MHz stopped) CM 4 = 1 (Oscillating) Low-power dissipation mode (f(SUB)/2) CM 6 “0”“1” CM 6 “0”“1” CM 6 “0”“1” CM “0” “1” CM “0” “1”CM “0” “1” CM “0” “1”CM “0” “1” CM CM 6 “0” “1” “0” “1” CM CM “0” “1” “1” “0” CM CM 6 “0” “1” “0” “1” CM CM “0” “1” “1” “0” CM 7 = 0 (8 MHz selected) CM 6 = 1 (frequency/8) CM 5 = 0 (8 MHz oscillating) CM 4 = 1 (Oscillating) or EXPCM0 = 1 (On-chip oscillator oscillation) CM 7 = 1 (32 kHz or on-chip oscillator selected) CM 6 = 0 (high-speed) CM 5 = 1 (8 MHz stopped) CM 4 = 1 (Oscillating) Low-power dissipation mode (f(SUB)/2) CM 7 = 0 (8 MHz selected) CM 6 = 0 (Frequency/2/4) CM 5 = 0 (8 MHz oscillating) CM 4 = 1 (Oscillating) or EXPCM0 = 1 (On-chip oscillator oscillation) On-chip oscillator control bit 0 : On-chip oscillator not used (on-chip oscillator stopping) 1 : On-chip oscillator used (Note 1) (on-chip oscillator oscillating) Frequency/4 mode control bit (Note 2) (Valid only when high-speed mode) 0 : Frequency/2 mode φ = f(X IN)/2 1 : Frequency/4 mode φ = f(XIN)/4 Not used (returns “0” when read) (Do not write “1” to this bit) CPU mode extension register (EXPCM : address: 002B 16,) b7 b4 Note 1 : The on-chip oscillator is selected for the operation clock in low-speed mode regardless of XCIN-XCOUT . 2 : Valid only when the main clock division ratio selection bit (bit 6 in the CPU mode register) is set to "0". When "1" (frequency/8 mode) is selected for the main clock division ratio selection bit or when the internal system clock selection bit is set to 1, set "0" to the frequency/4 mode control bit. Note 1 : In low speed mode (XCIN is selected as the system clock Ó), XCIN-XCOUT oscillation does not stop even if the port XC switch bit is set to "0". 2 : In frequency/2/4/8 mode, X IN-XOUT oscillation does not stop even if the main clock (XIN-XOUT ) stop bit is set to "1". 3 : When the system clock φ is divided by 4 of f(XIN), set the bit 6 in the CPU mode register to “0” after setting the bit 1 in the CPU mode extension register to “1”. 4 : When using the on-chip oscillator in low-speed mode, set the bit 7 in the CPU mode register to “1” after setting the bit 0 in the CPU mode extension register to “1”. Fig. 57 State transitions of system clock

Rev.2.02 Jun 19, 2007 page 55 of 73 REJ03B0146-0202 In the QzROM writing mode, the user ROM area can be rewritten while the microcomputer is mounted on-board by using a serial programmer which is applicable for this microcomputer. Table 13 lists the pin description (QzROM writing mode) and Fig- ure 58 and Figure 59 show the pin connections. Refer to Figure 60 and Figure 61 for examples of a connection with a serial programmer. Contact the manufacturer of your serial programmer for serial pro- grammer. Refer to the user’s manual of your serial programmer for details on how to use it. Table 13 Pin description (QzROM writing mode)

Apply 1.8 to 5.5 V to V CC , and 0 V to VSS .
Reset input pin for active “L”. Reset occurs when RESET pin is hold at an “L” level for 16 cycles or more of XIN.
Set the same termination as the single-chip mode.
Input the reference voltage of A/D converter to VREF .
Connect AVss to Vss.
Input “H” or “L” level signal or leave the pin open.
QzROM programmable power source pin.
Serial data I/O pin.
Serial clock input pin.
Read/program pulse input pin. V CC , VSS RESET XIN XOUT VREF AV SS P00 –P07 P10 –P17 P20 –P27 P34 –P37 P41–P4 4 P50 –P57 P60 –P67 P40 P44 P42 P43 Power source Reset input Clock input Clock output Analog reference voltage Analog power source I/O port V PP input ESDA input/output ESCLK input ESPGMB input FunctionPin Name Input Input Input Output Input Input I/O Input I/O Input Input I/O

Rev.2.02 Jun 19, 2007 page 56 of 73 REJ03B0146-0202 Fig. 58 Pin connection diagram (M3823XGX-XXXFP) SEG SEG 4/SEG 5/SEG 0/SEG 3/SEG 4/SEG 5/SEG 6/SEG 7/SEG 1/SEG 2/SEG 3/SEG 4/SEG 5/SEG 6/SEG 7/SEG VL 7/AN M3823XGX-XXXFP M3823XGXFP 7/ADT 0/INT 6/S CLK 5/T XD 3/INT 2/INT AV SS VREF VCC SEG 0 P41/φ P40 XIN XOU T VSS P27/KW 7 P26/KW 6 P25/KW 5 P24/KW 4 P23/KW 3 P22/KW 2 P21/KW 1 P20/KW 0 RESET 1/INT 5/CNTR 4/CNTR 3/RTP 2/RTP 6/T OUT 0/SEG 1/SEG 2/SEG 7/S RDY OUT SEG SEG 6/SEG 7/SEG P70/XCOUT P71/XCIN COM 0 VL3 6/AN 5/AN 4/AN 3/AN 2/AN 1/AN 0/AN VL COM 1 COM 2 COM 3 SEG 1 SEG 2 SEG 3 SEG 4 SEG 5 SEG 6 SEG 7 4/R XD 123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 414243444546474849505152535455565758596061626364 *: Connect to oscillation circuit. : QzROM pin PRQP0080GB-A (80P6N-A) ESDA ESCLK ESPGMB GND RESET VPP GND VCC Fig. 59 Pin connection diagram (M3823XGX-XXXHP) 1 2 3 4 7 8 9 10 11 12 13 14 15 16 17 18 19 205 6 4142434445464748495051525354555657585960 4/SEG 5/SEG P16/SEG 30 P17/SEG 31 P42/INT0 VCC XIN XOUT VSS RESET P70/XCOUT P71/XCIN P41/φ P40 P43/INT1 SEG 5/SEG 6/SEG 7/SEG 0/SEG 3/SEG 4/SEG 5/SEG 6/SEG 7/SEG 1/SEG 2/SEG 0/SEG 1/SEG 2/SEG 3/SEG COM 3 0/AN 7/ADT 6/T OUT 4/CNTR 3/RTP 2/RTP 1/INT 5/CNTR 6/S CLK 5/T XD 0/INT 7/S RDY OUT 4/R XD SEG 1 SEG 2 SEG 3 SEG 4 SEG 6 SEG 5 SEG 7 SEG 0 SEG 8 SEG 9 COM 2 COM 1 COM 0 VL3 VL2 VL1 VREF AV SS 1/AN 2/AN 3/AN 4/AN 5/AN 6/AN 7/AN SEG 4/SEG M3823XGX-XXXHP M3823XGXHP P27/KW 7 P26/KW 6 P25/KW 5 P24/KW 4 P23/KW 3 P22/KW 2 P21/KW 1 P20/KW 0 PLQP0080KB-A (80P6Q-A ) *: Connect to oscillation circuit. : QzROM pin GND ESDA ESCLK ESPGMB GND RESET VPP VCC

Rev.2.02 Jun 19, 2007 page 57 of 73 REJ03B0146-0202 Fig. 60 When using E8 programmer, connection example 3 8 2 3 G r o u p RESET circuit Set the same termination as the single-chip mode. V c c P 44 ( E S D A ) P 42 ( E S C L K ) P43 (ESPGMB) R E S E T Vss A V s s XI N XOUT 4 . 7 kΩ * 1 : Open-collector buffer Note: For the programming circuit, the wiring capacity of each signal pin must not exceed 47 pF. V c c 1 2 1 0 1 3 1 1 P 40 4 . 7 kΩ

Rev.2.02 Jun 19, 2007 page 58 of 73 REJ03B0146-0202 Fig. 61 When using programmer of Sisei Electronics System Co., LTD, connection example 3 8 2 3 G r o u p T _ V D D T _ V P P T_RXD T _ S C L K T _ P G M / O E / M D T_RESET G N D RESET circuit S e t t h e s a m e t e r m i n a t i o n a s t h e s i n g l e c h i p m o d e Vcc P40 P44 (ESDA) P42 (ESCLK) P43 (ESPGMB) RESET Vss AVss XI N XOUT 4.7 kΩ 4 . 7 kΩ Note: For the programming circuit, the wiring capacity of each signal pin must not exceed 47 pF. T _ T X D T_BUSY N.C.

Rev.2.02 Jun 19, 2007 page 59 of 73 REJ03B0146-0202 The contents of the processor status register (PS) after a reset are undefined, except for the interrupt disable flag (I) which is “1”. Af- ter a reset, initialize flags which affect program execution. In particular, it is essential to initialize the index X mode (T) and the decimal mode (D) flags because of their effect on calculations. Initialize these flags at the beginning of the program. Interrupt The contents of the interrupt request bits do not change immedi- ately after they have been written. After writing to an interrupt request register, execute at least one instruction before perform- ing a BBC or BBS instruction. Decimal Calculations

T o calculate in decimal notation, set the decimal mode flag (D) to “1”, then execute an ADC or SBC instruction. After executing an ADC or SBC instruction, execute at least one instruction be- fore executing a SEC, CLC, or CLD instruction.
In decimal mode, the values of the negative (N), overflow (V), and zero (Z) flags are invalid. Timers If a value n (between 0 and 255) is written to a timer latch, the fre- quency division ratio is 1/(n + 1). Multiplication and Division Instructions The index mode (T) and the decimal mode (D) flags do not affect the MUL and DIV instruction. The execution of these instructions does not change the contents of the processor status register. Ports The contents of the port direction registers cannot be read. The following cannot be used:
The data transfer instruction (LDA, etc.)
The operation instruction when the index X mode flag (T) is “1”
The addressing mode which uses the value of a direction regis- ter as an index
The bit-test instruction (BBC or BBS, etc.) to a direction register
The read-modify-write instruction (ROR, CLB, or SEB, etc.) to a direction register Use instructions such as LDM and STA, etc., to set the port direc- tion registers. Serial Interface In clock synchronous serial I/O, if the receive side is using an ex- ternal clock and it is to output the S RDY signal, set the transmit enable bit, the receive enable bit, and the SRDY output enable bit to “1”. Serial I/O continues to output the final bit from the T XD pin after transmission is completed. A/D Converter The comparator is constructed linked to a capacitor. The conver- sion accuracy may be low because the charge is lost if the conversion speed is not enough. Accordingly, set f(X IN) to at least 500kHz during A/D conversion in the middle-or high-speed mode. Also, do not execute the STP or WIT instruction during an A/D conversion. In the low-speed mode, since the A/D conversion is executed by the on-chip oscillator, the minimum value of f(X IN) frequency is not limited. LCD Drive Control Circuit Execution of the STP instruction sets the LCD enable bit (bit 3 of the LCD mode register) to “0” and the LCD panel turns off.To make the LCD panel turn on after returning from the stop mode, set the LCD enable bit to “1”. Instruction Execution Time The instruction execution time is obtained by multiplying the fre- quency of the internal clock φ by the number of cycles needed to execute an instruction. The number of cycles required to execute an instruction is shown in the list of machine instructions. The frequency of the internal clock φ is half of the X IN frequency.

Rev.2.02 Jun 19, 2007 page 60 of 73 REJ03B0146-0202 Countermeasures against noise (1) Shortest wiring length ➀ Wiring for RESET pin Make the length of wiring which is connected to the RESET pin as short as possible. Especially, connect a capacitor across the RESET pin and the V SS pin with the shortest possible wiring (within 20mm).

Reason The width of a pulse input into the RESET pin is determined by the timing necessary conditions. If noise having a shorter pulse width than the standard is input to the RESET pin, the reset is released before the internal state of the microcomputer is com- pletely initialized. This may cause a program runaway. (2) Connection of bypass capacitor across V SS line and VCC line In order to stabilize the system operation and avoid the latch-up, connect an approximately 0.1 µF bypass capacitor across the VSS line and the VCC line as follows:
Connect a bypass capacitor across the VSS pin and the VCC pin at equal length.
Connect a bypass capacitor across the VSS pin and the VCC pin with the shortest possible wiring.
Use lines with a larger diameter than other signal lines for VSS line and VCC line.
Connect the power source wiring via a bypass capacitor to the VSS pin and the VCC pin. ➁ Wiring for clock input/output pins
Make the length of wiring which is connected to clock I/O pins as short as possible.
Make the length of wiring (within 20 mm) across the grounding lead of a capacitor which is connected to an oscillator and the VSS pin of a microcomputer as short as possible.
Separate the VSS pattern only for oscillation from other VSS patterns.
Reason If noise enters clock I/O pins, clock waveforms may be de- formed. This may cause a program failure or program runaway. Also, if a potential difference is caused by the noise between the V SS level of a microcomputer and the VSS level of an oscil- lator, the correct clock will not be input in the microcomputer. RESETReset circuit Noise VSSVSS Reset circuit VSS RESET VSS N.G. O.K. Noise XIN XOUT VSS XIN XOUT VSS N.G. O.K. VSS VCC /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines VSS VCC /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines N.G. O.K. Fig. 63 Wiring for clock I/O pins Fig. 62 Wiring for the RESET pin Fig. 64 Bypass capacitor across the VSS line and the VCC line

Rev.2.02 Jun 19, 2007 page 61 of 73 REJ03B0146-0202 (3) Oscillator concerns In order to obtain the stabilized operation clock on the user system and its condition, contact the oscillator manufacturer and select the oscillator and oscillation circuit constants. Be careful espe- cially when range of votage and temperature is wide. Also, take care to prevent an oscillator that generates clocks for a microcomputer operation from being affected by other signals. ➀ Keeping oscillator away from large current signal lines Install a microcomputer (and especially an oscillator) as far as possible from signal lines where a current larger than the toler- ance of current value flows.

Reason In the system using a microcomputer, there are signal lines for controlling motors, LEDs, and thermal heads or others. When a large current flows through those signal lines, strong noise oc- curs because of mutual inductance. ➁ Installing oscillator away from signal lines where potential levels change frequently Install an oscillator and a connecting pattern of an oscillator away from signal lines where potential levels change frequently. Also, do not cross such signal lines over the clock lines or the signal lines which are sensitive to noise.
Reason Signal lines where potential levels change frequently (such as the CNTR pin signal line) may affect other lines at signal rising edge or falling edge. If such lines cross over a clock line, clock waveforms may be deformed, which causes a microcomputer failure or a program runaway. ➀ Keeping oscillator away from large current signal lines ➁ Installing oscillator away from signal lines where potential levels change frequently Fig. 66 Wiring for the P40/(VPP) pinFig. 65 Wiring for a large current signal line/W iring of signal lines where potential levels change frequently A p p r o x . 5 kΩ T h e s h o r t e s t P 40/ ( VP VS S P 40/ ( VP VS S T h e s h o r t e s t T h e s h o r t e s t A p p r o x . 5 kΩ ( N o t e ) ( N o t e ) ( N o t e ) ( N o t e ) N o t e . S h o w s t h e m i c r o c o m p u t e r ' s p i n . (4) Analog input The analog input pin is connected to the capacitor of a voltage comparator. Accordingly, sufficient accuracy may not be obtained by the charge/discharge current at the time of A/D conversion when the analog signal source of high-impedance is connected to an analog input pin. In order to obtain the A/D conversion result stabilized more, please lower the impedance of an analog signal source, or add the smoothing capacitor to an analog input pin. (5) Difference of memory size When memory size differ in one group, actual values such as an electrical characteristics, A/D conversion accuracy, and the amount of -proof of noise incorrect operation may differ from the ideal values. When these products are used switching, perform system evalua- tion for each product of every after confirming product specification. (6) Wiring to P4 0/(VPP) pin When using P40/(VPP ) pin as an input port, connect an approximately 5 kΩ resistor to the P40/(VPP ) pin the shortest possible in series. When not using P40/(VPP ) pin, connect the pin the shortest pos- sible to the GND pattern which is supplied to the Vss pin of the microcomputer. In addition connecting an approximately 5 kΩ re- sistor in series to the GND could improve noise immunity. In this case as well as the above mention, connect the pin the shortest possible to the GND pattern which is supplied to the Vss pin of the microcomputer.
Reason The P4 0/(VPP ) pin of the QzROM version is the power source input pin for the built-in QzROM. When programming in the QzROM, the im- pedance of the VPP pin is low to allow the electric current for writing to flow into the built-in QzROM. Because of this, noise can enter easily. If noise enters the P4 0/(VPP ) pin, abnormal instruction codes or data are read from the QzROM, which may cause a program runaway. XIN XOUT VSS Microcomputer Mutual inductance Large current GND M XIN XOUT VSS CNTRDo not cross N.G. (1) When using P40/(VPP ) pin as an input port (2) When not using P40/(VPP ) pin

Rev.2.02 Jun 19, 2007 page 62 of 73 REJ03B0146-0202 Fig. 67Strengthening measure example of LCD drive power supply

C o n n e c t b y t h e s h o r t e s t p o s s i b l e w i r i n g o n n e c t t h e b y p a s s c a p a c i t o r t o t h e VL 1 – VL p i n s a s s h o r t a s p o s s i b l e R e f e r e n t i a l v a l u e F NOTES ON USE Power Source Voltage When the power source voltage value of a microcomputer is less than the value which is indicated as the recommended operating conditions, the microcomputer does not operate normally and may perform unstable operation. In a system where the power source voltage drops slowly when the power source voltage drops or the power supply is turned off, reset a microcomputer when the power source voltage is less than the recommended operating conditions and design a system not to cause errors to the system by this unstable operation. LCD drive power supply Power supply capacitor may be insufficient with the division resis- tance for LCD power supply,and the characteristic of the LCD panel.In this case,there is the method of connecting the bypass capacitor about 0.1 –0.33µF to VL1 –V L3 pins.The example of a strengthening measure of the LCD drive power supply is shown in Figure 67. Product shipped in blank As for the product shipped in blank, Renesas does not perform the writing test to user ROM area after the assembly process though the QzROM writing test is performed enough before the assembly process. Therefore, a writing error of approx.0.1 % may occur. Moreover, please note the contact of cables and foreign bodies on a socket, etc. because a writing environment may cause some writing errors. Overvoltage Make sure that voltage exceeding the Vcc pin voltage is not ap- plied to other pins. In particular, ensure that the state indicated by bold lines in figure below does not occur for pin P40 (VPP power source pin for QzROM) during power-on or power-off. Otherwise the contents of QzROM could be rewritten. NOTES ON QzROM Notes On QzROM Writing Orders When ordering the QzROM product shipped after writing, submit the mask file (extension: .msk) which is made by the mask file converter MM. Be sure to set the ROM option ("MASK option" written in the mask file converter) setup when making the mask file by using the mask file converter MM. Notes On ROM Code Protect (QzROM product shipped after writing) As for the QzROM product shipped after writing, the ROM code protect is specified according to the ROM option setup data in the mask file which is submitted at ordering. The ROM option setup data in the mask file is “00 16” for protect enabled or “FF16” for protect disabled. Therefore, the contents of the ROM code protect address (other than the user ROM area) of the QzROM product shipped after writing is “00 16” or “FF16”. Note that the mask file which has nothing at the ROM option data or has the data other than “0016” and “FF16” can not be accepted. DATA REQUIRED FOR QzROM WRITING ORDERS The following are necessary when ordering a QzROM product shipped after writing: 1. QzROM Writing Confirmation Form* 2. Mark Specification Form* * For the QzROM writing confirmation form and the mark specifi- cation form, refer to the “Renesas Technology Corp.” Homepage (http://www.renesas.com). Note that we cannot deal with special font marking (customer's trademark etc.) in QzROM microcomputer. P40 pin voltage “H” input VCC pin voltage P40 pin voltage “L” input (1) Input voltage to other MCU pins rises before Vcc pin voltage. (2) Input voltage to other MCU pins falls after Vcc pin voltage. Note: The internal circuitry is unstable when Vcc is below the minimum voltage specification of 1.

8 V (shaded portion), so particular care should be exercised re

garding overvoltage. 1.8V 1.8V Fig. 68Timing Diagram (Applies to section indicated by bold line.)

Rev.2.02 Jun 19, 2007 page 63 of 73 REJ03B0146-0202 –0.3 to 6.5 VPower source voltage Input voltage P00–P0 7, P10–P1 7, P20–P2 7, P34–P3 7, P40–P4 7, P50–P5 7 P60–P6 7, P70, P71 VCC VI Symbol Parameter Conditions Ratings Unit All voltages are based on VSS . When an input voltage is mea- sured, output transistors are cut off. VI VI VI VI VO VO VO Input voltage VL1 Input voltage VL2 Input voltage VL3 Input voltage RESET, XIN Output voltage P00–P0 7, P10–P1 7 Output voltage P34–P3 7 Output voltage P20–P2 7, P41–P4 7,P50–P5 7, P60–P6 7, P70, P71 Output voltage SEG0–SEG 11 Output voltage XOUT Power dissipation Operating temperature Storage temperature At output port At segment output At segment output –0.3 to V CC +0.3 –0.3 to VL2 VL1 to VL3 VL2 to 6.5 –0.3 to VCC +0.3 –0.3 to VCC +0.3 –0.3 to VL3 –0.3 to VL3 –0.3 to VCC +0.3 –0.3 to VL3 –0.3 to VCC +0.3 300 –20 to 85 –40 to 150 V V V V V V V V V V V mW Ta = 25°C (VCC = 1.8 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted) 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 V CC VREF VCC Symbol Parameter Limits Min. V V V V V V V V V V V V V V V V Unit 4.5 4.0 2.0 1.8 2.5 2.0 1.8 2.5 2.0 1.8 1.8 2.5 1.8 AV SS 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 Typ. Max. Power source voltage (Note 1) Frequency/2 mode f(XIN) = 10 MHz f(XIN) = 8 MHz f(XIN) = 5 MHz f(XIN) = 2.5 MHz Frequency/4 mode f(XIN) = 10 MHz f(XIN) = 8 MHz f(XIN) = 5 MHz Frequency/8 mode f(XIN) = 10 MHz f(XIN) = 8 MHz f(XIN) = 5 MHz Low-speed mode (OCO included) Table 14 Absolute maximum ratings Table 15 Recommended operating conditions (1) Note : When the A/D converter is used, refer to the recommended operating condition for A/D converter. VSS VL 3 VREF AV SS VIA Power source voltage LCD power voltage A/D conversion reference voltage Analog power source voltage Analog input voltage AN 0–AN 7

ELECTRICAL CHARACTERISTICS

Rev.2.02 Jun 19, 2007 page 64 of 73 REJ03B0146-0202 (VCC = 1.8 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted) “H” input voltage P00–P07, P10–P17,P34–P3 7, P40, P41, P45, P47, P52, P53,P56,P60–P6 7,P70,P71 (CM4= 0) “H” input voltage P20–P27, P42–P44,P46,P50, P51, P54, P55, P57 “H” input voltage RESET “H” input voltage X IN “L” input voltage P00–P07, P10–P17,P34–P3 7, P40, P41, P45, P47, P52, P53, P56,P60–P6 7,P70,P71 (CM4= 0) “L” input voltage P20–P27, P42–P44,P46,P50, P51, P54, P55, P57 “L” input voltage RESET “L” input voltage X IN VCC VCC VCC VCC

0.3 VCC

0.2 VCC

Min. V V V V V V V V Unit 0.7VCC 0.8VCC 0.8VCC 0.8VCC Typ. Max. Table 16 Recommended operating conditions (2)

Rev.2.02 Jun 19, 2007 page 65 of 73 REJ03B0146-0202 P00–P0 7, P10–P1 7, P20–P2 7 (Note 1) P41–P4 7, P50–P5 7, P60–P6 7, P70, P71 (Note 1) P00–P0 7, P10–P1 7, P20–P2 7 (Note 1) P41–P4 7, P50–P5 7, P60–P6 7, P70, P71 (Note 1) P00–P0 7, P10–P1 7, P20–P2 7 (Note 1) P41–P4 7, P50–P5 7, P60–P6 7, P70, P71 (Note 1) P00–P0 7, P10–P1 7, P20–P2 7 (Note 1) P41–P4 7, P50–P5 7, P60–P6 7, P70, P71 (Note 1) P00–P0 7, P10–P1 7 (Note 2) P20–P2 7, P41–P4 7, P50–P5 7, P60–P6 7, P70, P71 (Note 2) 0–P0 7, P10–P1 7 (Note 2) P20–P2 7, P41–P4 7, P50–P5 7, P60–P6 7, P70, P71 (Note 2) 0–P0 7, P10–P1 7 (Note 3) P20–P2 7, P41–P4 7, P50–P5 7, P60–P6 7, P70, P71 (Note 3) 0–P0 7, P10–P1 7 (Note 3) P20–P2 7, P41–P4 7, P50–P5 7, P60–P6 7, P70, P71 (Note 3) –40 –40 –20 –20 CC = 1.8 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted) Notes 1: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured over 100 ms. The total peak current is the peak value of all the currents. 2: The peak output current is the peak current flowing in each port. 3: The average output current is an average value measured over 100 ms. 4: When the A/D converter is used, refer to the recommended operating condition for A/D converter. 5: When using the microcomputer in low-speed mode, make sure that the sub-clock input oscillation frequency on condition that f(XCIN) < f(XIN)/3. “H” total peak output current “H” total peak output current “L” total peak output current “L” total peak output current “H” total average output current “H” total average output current “L” total average output current “L” total average output current “H” peak output current “H” peak output current ΣIOH(peak) ΣIOH(peak) ΣIOL(peak) ΣIOL(peak) ΣIOH(avg) ΣIOH(avg) ΣIOL(avg) ΣIOL(avg) IOH(peak) IOH(peak) Symbol Parameter Limits Min. mA mA mA mA mA mA mA mA mA mA Unit Typ. Max. IOL(peak) IOL(peak) IOH(avg) IOH(avg) IOL(avg) –1.0 –2.5 mA mA mA mA mA mA “L” peak output current “L” peak output current “H” average output current “H” average output current “L” average output current “L” average output current Input frequency for timers X and Y (duty cycle 50%) IOL(avg) f(CNTR0) f(CNTR1) MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz kHz (VCC ≤ 2.0 V) Frequency/2 mode Frequency/2 mode Frequency/2 mode Frequency/2 mode Frequency/4 mode Frequency/4 mode Frequency/4 mode Frequency/8 mode Frequency/8 mode Frequency/8 mode 32.768 Main clock input oscillation frequency (duty cycle 50%) (Note 4) Sub-clock input oscillation frequency (duty cycle 50%) (Note 5) f(X IN) 2.5 5.0 5.0 2 ✕ VCC – 4 0.75 ✕ VCC + 1 6.25 ✕ VCC - 10 10.0 4 ✕ VCC – 8 1.5 ✕ VCC + 2 12.5 ✕ VCC - 20 10.0 4 ✕ VCC 15 ✕ VCC – 22 10.0 4 ✕ VCC 15 ✕ VCC – 22 Table 17 Recommended operating conditions (3) f(XCIN)

Rev.2.02 Jun 19, 2007 page 66 of 73 REJ03B0146-0202 IOL = 10 mA IOL = 2.5 mA IOL = 2.5 mA VCC = 2.5 V IOL = 5 mA IOL = 1.25 mA IOL = 1.25 mA VCC = 2.5 V VOL IOH = –2.5 mA IOH = –0.6 mA VCC = 2.5 V IOH = –5 mA IOH = –1.25 mA IOH = –1.25 mA VCC = 2.5 V VVCC –2.0“H” output voltage P00–P0 7, P10–P1 7 Symbol Parameter Limits Min. Unit 0.5 Typ. Max.Test conditions VOH 2.0 0.5 (VCC = 4.0 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted) RESET : VCC = 2.0 V to 5.5 V VI = VCC Pull-downs “off” VCC = 5 V, VI = VCC Pull-downs “on” V CC = 3 V, VI = VCC Pull-downs “on” VI = VCC “H” output voltage P20–P2 7, P41–P4 7, P50–P5 7, P60–P6 7, P70, P71 (Note) “L” output voltage P00–P0 7, P10–P7 “L” output voltage P20–P2 7, P41–P4 7, P50–P5 7, P60–P6 7, P70, P71 (Note) Hysteresis INT0–INT3, ADT, CNTR0, CNTR 1, P20–P2 7 Hysteresis S CLK , RXD Hysteresis RESET “H” input current P00–P0 7, P10–P1 7, P34–P3 7 “H” input current P20–P2 7, P40–P4 7, P50–P5 7, P60–P6 7, P70, P71 (Note) VOH VOL VT+ – VT– VT+ – VT– VT+ – VT– IIH IIH IIH VCC –2.0 VCC –0.5 6.0 –30 –6.0 0.5 0.5 2.0 0.5 140 5.0 5.0 –5.0 –5.0 –140 –45 V V V V V V V V V IIH IIL VCC –1.0 VCC –1.0 V V V1.0 V1.0 5.0 µA VI = VCC VI = VCC VI = VSS VI = VSS Pull-ups “off” VCC = 5 V, VI = VSS Pull-ups “on” V CC = 3 V, VI = VSS Pull-ups “on” V I = VSS VI = VSS When clock is stopped “H” input current RESET “H” input current X IN “L” input current P00–P0 7, P10–P1 7, P34–P3 7,P40 “L” input current P20–P2 7, P41–P4 7, P50–P5 7, P60–P6 7, P70, P71 (Note) “L” input current RESET “L” input current XIN RAM hold voltage 4.0 –5.0 –70 µA µA µA µA µA µA µA µA µA µA µA IIL IIL IIL VRAM –25 –4.0 No te: Whe n “1” is set to the port XC switch bit (bit 4 at address 003B16) of CPU mode register, the drive ability of port P70 is different from the value above mentioned. Table 18 Electrical characteristics (1) 1.8 5.5 V

Rev.2.02 Jun 19, 2007 page 67 of 73 REJ03B0146-0202 (VCC = 1.8 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted) Frequency/2 mode Frequency/4 mode Frequency/8 mode Frequency/2/4/8 mode In WIT state Low-speed mode f(XIN) = stopped Low-speed mode f(XIN) = stopped In WIT state Current increased at A/D converter operating All oscillation stopped Ta = 25 °C, Output transistors “off” (in STP state) All oscillation stopped Ta = 85 °C, Output transistors “off” (in STP state) VCC = 2.5 V, Ta = 25 °C Symbol Parameter Test conditions ICC Power source current Table 19 Electrical characteristics (2) VCC = 5.0 V VCC = 2.5 V VCC = 5.0 V VCC = 2.5 V VCC = 5.0 V VCC = 2.5 V VCC = 5.0 V VCC = 2.5 V VCC = 5.0 V VCC = 2.5 V VCC = 5.0 V VCC = 2.5 V f(XIN) = 10 MHz f(XIN) = 8 MHz f(XIN) = 4 MHz f(XIN) = 4 MHz f(XIN) = 2 MHz f(XIN) = 10 MHz f(XIN) = 8 MHz f(XIN) = 4 MHz f(XIN) = 10 MHz f(XIN) = 8 MHz f(XIN) = 4 MHz f(XIN) = 2 MHz f(XIN) = 10 MHz f(XIN) = 8 MHz f(XIN) = 4 MHz f(XIN) = 2 MHz f(XIN) = 10 MHz f(XIN) = 8 MHz f(XIN) = 4 MHz f(XIN) = 2 MHz f(XIN) = 10 MHz f(XIN) = 8 MHz f(XIN) = 4 MHz f(XIN) = 2 MHz f(XIN) = 10 MHz f(XIN) = 8 MHz f(XIN) = 4 MHz f(XIN) = 2 MHz f(XCIN) = 32 kHz On-chip oscillator f(XCIN) = 32 kHz On-chip oscillator f(X CIN) = 32 kHz On-chip oscillator f(XCIN) = 32 kHz On-chip oscillator VCC = 5 V, all modes VCC = 2.5 V, all modes R OCO On-chip oscillator oscillatoin Limits Min. UnitTyp. Max. 4.3 3.7 2.5 0.8 0.4 2.9 2.5 1.7 1.0 0.8 0.5 0.3 2.2 1.9 1.4 1.0 0.7 0.6 0.4 0.2 1.35 1.2 0.9 0.8 0.35 0.3 0.2 0.15 5.5 3.5 3.5 500 0.1 mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA µA µA µA µA µA µA µA µA µA µA µA µA kHz 8.6 7.4 5.0 1.6 0.8 5.8 5.0 3.4 2.0 1.6 1.0 0.6 4.4 3.8 2.8 2.0 1.4 1.2 0.8 0.4 2.7 2.4 1.8 1.6 0.7 0.6 0.4 0.3 240 1.0

Rev.2.02 Jun 19, 2007 page 68 of 73 REJ03B0146-0202 (VCC = 1.8 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol Parameter Limits Min. UnitTyp. Max.Test conditions ABS tCONV RLADDER IVREF IIA Resolution Absolute accuracy (excluding quantization error) Conversion time Ladder resistor Reference power source input current Analog port input current ADL2 = “0”, ADL1 = “0”, CPUM7 = “0” 2.2 V ≤ VCC = VREF ≤ 5.5 V f(XIN) = 2 ✕ VCC MHz ≤ 10 MHz ADL2 = “0”, ADL1 = “0”, CPUM7 = “0” 2.0 V ≤ VCC = VREF < 2.2 V f(XIN) = 4.4 MHz ADL2 = “0”, ADL1 = “1”, CPUM7 = “0” VCC = VREF = 4.0 to 5.5 V f(XIN) = 2 ✕ VCC MHz ≤ 10 MHz ADL2 = “1”, ADL1 = “0”, CPUM7 = “1” and EXPCM0 = “1” VCC = VREF = 1.8 to 2.2 V f(XIN) = 8 MHz (ADL2 = “0”, ADL1 = “0”, CPUM7 = “0”) VREF = 5 V Bits LSB LSB LSB LSB µs kΩ µA µA TC(X IN)✕ 100 100 200 5.0 Table 20 A/D converter characteristics (1) (in 8 bit A/D mode) 150 (VCC = 1.8 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol Parameter Limits Min. UnitTyp. Max.Test conditions ABS tCONV RLADDER IVREF IIA Resolution Absolute accuracy (excluding quantization error) Conversion time Ladder resistor Reference power source input current Analog port input current ADL2 = “0”, ADL1 = “0”, CPUM7 = “0” 2.2 V ≤ VCC = VREF ≤ 5.5 V f(XIN) = 2 ✕ VCC MHz ≤ 10 MHz ADL2 = “0”, ADL1 = “1”, CPUM7 = “0” VCC = VREF = 4.0 to 5.5 V f(XIN) = 2 ✕ VCC MHz ≤ 10 MHz ADL2 = “1”, ADL1 = “0”, CPUM7 = “1” and EXPCM0 = “1” VCC = VREF = 1.8 to 2.2 V f(XIN) = 8 MHz (ADL2 = “0”, ADL1 = “0”, CPUM7 = “0”) VREF = 5 V Bits LSB LSB LSB µs kΩ µA µA TC(X IN)✕ 100 100 200 5.0 Table 21 A/D converter characteristics (2) (in 10 bit A/D mode) 150

Rev.2.02 Jun 19, 2007 page 69 of 73 REJ03B0146-0202 (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Note:When bit 6 of address 001A16 is “1” (clock synchronous). Divide this limits value by four when bit 6 of address 001A16 is “0” (UART). Table 22 Timing requirements (1) Note:When bit 6 of address 001A16 is “1” (clock synchronous). Divide this limits value by four when bit 6 of address 001A16 is “0” (UART). (VCC = 1.8 to 4.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Table 23 Timing requirements (2) 1000/(4 ✕ VCC –8) 100 1000/(2 ✕ V CC –4) 200 105 105 800 370 370 220 100 Reset input “L” pulse width Main clock input cycle time (X IN input) Main clock input “H” pulse width Main clock input “L” pulse width CNTR 0, CNTR1 input cycle time CNTR 0, CNTR1 input “H” pulse width CNTR 0, CNTR1 input “L” pulse width INT0 to INT3 input “H” pulse width INT0 to INT3 input “L” pulse width Serial I/O clock input cycle time (Note) Serial I/O clock input “H” pulse width (Note) Serial I/O clock input “L” pulse width (Note) Serial I/O input set up time Serial I/O input hold time tw(RESET) tc(XIN) twH(X IN) twL(XIN) tc(CNTR) twH(CNTR) twL(CNTR) twH(INT) twL(INT) tc(SCLK ) twH(S CLK ) twL(SCLK ) tsu(RX D–S CLK ) th(SCLK –R XD) Symbol Parameter Limits Min. µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit Typ. Max. 4.0 ≤ Vcc < 4.5 V 4.5 ≤ Vcc ≤ 5.5 V 4.0 ≤ Vcc < 4.5 V 4.5 ≤ Vcc ≤ 5.5 V 4.0 ≤ Vcc < 4.5 V 4.5 ≤ Vcc ≤ 5.5 V 4.0 ≤ Vcc < 4.5 V 4.5 ≤ Vcc ≤ 5.5 V 4.0 ≤ Vcc < 4.5 V 4.5 ≤ Vcc ≤ 5.5 V 4.0 ≤ Vcc < 4.5 V 4.5 ≤ Vcc ≤ 5.5 V 125 1000/V CC 1000/(5 ✕ VCC –8) tc(CNTR)/2–20 tc(CNTR)/2–20 230 230 2000 950 950 400 200 Reset input “L” pulse width Main clock input cycle time (X IN input) Main clock input “H” pulse width Main clock input “L” pulse width CNTR 0, CNTR1 input cycle time CNTR 0, CNTR1 input “H” pulse width CNTR 0, CNTR1 input “L” pulse width INT0 to INT3 input “H” pulse width INT0 to INT3 input “L” pulse width Serial I/O clock input cycle time (Note) Serial I/O clock input “H” pulse width (Note) Serial I/O clock input “L” pulse width (Note) Serial I/O input set up time Serial I/O input hold time tw(RESET) tc(XIN) twH(X IN) twL(XIN) tc(CNTR) twH(CNTR) twL(CNTR) twH(INT) twL(INT) tc(SCLK ) twH(S CLK ) twL(SCLK ) tsu(RX D–S CLK ) th(SCLK –R XD) Symbol Parameter Limits Min. µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit Typ. Max. 2.0 ≤ Vcc ≤ 4.0 V Vcc < 2.0 V 2.0 ≤ Vcc ≤ 4.0 V Vcc < 2.0 V 2.0 ≤ Vcc ≤ 4.0 V Vcc < 2.0 V 2.0 ≤ Vcc ≤ 4.0 V Vcc < 2.0 V

Rev.2.02 Jun 19, 2007 page 70 of 73 REJ03B0146-0202 (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Note : When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”. Serial I/O clock output “H” pulse width Serial I/O clock output “L” pulse width Serial I/O output delay time (Note) Serial I/O output valid time (Note) Serial I/O clock output rising time Serial I/O clock output falling time 140 Symbol Parameter Limits Min. ns ns ns ns ns ns Unit tC (SCLK )/2–30 tC (SCLK )/2–30 –30 Typ. Max. twH(S CLK ) twL(SCLK ) td(SCLK –TXD) tv(SCLK –TXD) tr(SCLK ) tf(SCLK ) (VCC = 1.8 to 4.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) ns ns ns ns ns ns Unit Note : When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”. Serial I/O clock output “H” pulse width Serial I/O clock output “L” pulse width Serial I/O output delay time (Note) Serial I/O output valid time (Note) Serial I/O clock output rising time Serial I/O clock output falling time 350 100 100 Symbol Parameter Limits Min. tC (SCLK )/2–100 tC (SCLK )/2–100 –30 Max. twH(S CLK ) twL(SCLK ) td(SCLK –TXD) tv(SCLK –TXD) tr(SCLK ) tf(SCLK ) Typ. Fig. 69 Circuit for measuring output switching characteristics Table 24 Switching characteristics (1) Table 25 Switching characteristics (2) M e a s u r e m e n t o u t p u t p i n 1 0 0 p F C M O S o u t p u t N ote: Wh en bit 4 of the UART control register (address 001B16) is “1”. (N-channel open- drain output mode) N -channel open-drain output (Note) 1 kΩ 100 pF M easurement output pin

Rev.2.02 Jun 19, 2007 page 71 of 73 REJ03B0146-0202 Fig. 70 Timing diagram tW R E S E T 0.8VC C 0.2VCCR E S E T tC(XIN) tC C N T R tW H C N T R ) tW L C N T R 0 . 8 VC C 0.2VC C C N T R 0, C N T R 1 tW H I N T ) tW L I N T 0 . 8 VC C 0.2VC C I N T0– I N T3 tW H XI N ) tW L XI N ) 0.8VC C 0.2VC C XIN tC(SCLK ) tWL(S CLK ) tW H SC L 0 . 2 VC C 0.8VC CSCLK trtf td SC L TXD ) tv(SCLK -TXD) TXD R XD 0.2VCC 0.8VCC tsu(RXD-SCLK ) th(SCLK -RXD)

Rev.2.02 Jun 19, 2007 page 72 of 73 REJ03B0146-0202 y F 1 24 4164 Index mark c bp D E HE A e ZD ZE HD Detail F L A1 A2 INCLUDE TRIM OFFSET. DIMENSION "*3" DOES NOT NOTE) DO NOT INCLUDE MOLD FLASH. Previous CodeJEITA Package Code RENESAS Code PRQP0080GB-A 80P6N-A MASS[Typ.] 1.6gP-QFP80-14x20-0.80 0.20.150.13 0.450.350.3 MaxNomMin Dimension in Millimeters Symbol Reference 20.220.019.8D 14.214.013.8E 2.8A2 23.122.822.5 17.116.816.5 3.05A 0.20.10 0.80.60.4L 10°0° c 0.8e 0.10y HD HE bp ZD ZE 0.65 0.95 0.8 1.0 Diagrams showing the latest package dimensions and mounting information are available in the “Packages” section of the Renesas Technology website.

Rev.2.02 Jun 19, 2007 page 73 of 73 REJ03B0146-0202 c A L A1 A2 Index mark y F 60 41 201 x ZE ZD E HE D HD e bp DO NOT INCLUDE MOLD FLASH. NOTE) DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. Previous CodeJEITA Package Code RENESAS Code PLQP0080KB-A 80P6Q-A MASS[Typ.] 0.5gP-LQFP80-12x12-0.50 1.0 0.125 0.18 1.25 1.25 0.08 0.200.1450.09 0.250.200.15 MaxNomMin Dimension in Millimeters Symbol Reference 12.112.011.9D 12.112.011.9E 1.4A2 14.214.013.8 14.214.013.8 1.7A 0.20.10 0.70.50.3L x 10°0° c 0.5e 0.08y HD HE bp ZD ZE Terminal cross section c bp

REVISION HISTORY 3823 GROUP DATA SHEET Rev. Date Description Page Summary (1/2) 1.00 05/13/05 First edition 2.00 05/07/07 6 Table 3 is partly revised 8 Fig.5 is partly added

9 Table 4 is revised

14 “ROM Code Protect Address” is added Fig.10 is revised 40 “STP instruction Execution” is revised 49 “Oscillation Control” (1) Stop Mode is partly revised 52 “LCD drive Control Circuit” is revised 54 “(6) Wiring to P4 0/(VPP ) pin” is revised Fig.59 is revised 55 Fig.60 is partly deleted “NOTES ON QzROM” is added

60 Table 18 is partly added

2.01 05/11/08 6 Table 3 is partly revised

61 Table 19, 20 are partly revised

65-66 PACKAGE OUTLINE revised 2.02 07/06/19 − “RENESAS TECHNICAL UPDATE” reflected: TN-740-A111A/E 6T able 3: Function except a port function; •Serial I/O function pins → •Serial inter- face function pins 8 Fig. 5 M38234G4, M38235G6: Under development → Mass production Note deleted

9 Table 4: Under development deleted

10 FUNCTIONAL DESCRIPTION CENTRAL PROCESSING UNIT (CPU):

15 Fig. 11: Note added CPU mode extension register (002B16) → CPU mode expansion register Peripheral function extension register (003016) → Peripheral function expansion register

22 Table 8: AV SS added, Note revised

23-27 INTERRUPTS: Description revised, Fig. 18-20 added

46 ROM CORRECTION FUNCTION: Description added

48 Initial Value of Watchdog Timer: Description added

Standard Operation of Watchdog Timer: A part of description deleted Bit 6 and bit 7 of Watchdog Timer Control Register: added and revised Fig. 48 revised, Note added 51 Fig. 53: Port P0 direction register (000016) → (000116)

52 Frequency Control: Description revised

53 Fig. 56: revised 54 Fig. 57: revised 55-58 QzROM Writing Mode: added

58 Processor Status Register: added

59 Overvoltage: Description revised and Fig. 68 added

63 Table 15

V CC : Frequency/4 mode → Frequency/8 mode VREF : Limits Min. 2.0 → 1.8

66 Table 18: V RAM added

REVISION HISTORY 3823 GROUP DATA SHEET Rev. Date Description Page Summary (2/2) 2.02 07/06/19 67 Table 19 R OCO : Ta = 25 °C added

72 Note added

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Product Information

3823 specifications and overview.

Summary

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Description

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Source title 3823 Datasheet(PDF) - Renesas Technology Corp

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