3807

3807 RENESAS | Alldatasheet

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Technical content

Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp. The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices and power devices. Renesas Technology Corp. Customer Support Dept. April 1, 2003 To all our customers

DESCRIPTION

The 3807 group is a 8-bit microcomputer based on the 740 family core technology. The 3807 group has two serial I/Os, an A-D converter, a D-A converter, a real time output port function, a watchdog timer, and an analog comparator, which are available for a system controller which controls motors of office equipment and household appliances. The various microcomputers in the 3807 group include variations of internal memory size and packaging. For details, refer to the section on part numbering. For details on availability of microcomputers in the 3807 group, refer to the section on group expansion.

• 2 Clock generating circuit Main clock (X (connect to external ceramic resonator or quartz-crystal oscillator)
• Power source voltage (at 8 MHz oscillation frequency and high-speed selected) (at 8 MHz oscillation frequency and middle-speed selected) (at 32 kHz oscillation frequency and low-speed selected)
• Power dissipation (at 8 MHz oscillation frequency, at 5 V power source voltage) (at 32 kHz oscillation frequency, at 3 V power source voltage) APPLICATION LBP engine control, PPC, FAX, office equipment, household appli- ances, consumer electronics, etc.

FEATURES

(at 8 MHz oscillation frequency) Fig. 1. Pin configuration of M38073M4-XXXFP Package type : 80P6N-A 80-pin plastic-molded QFP PIN CONFIGURATION (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 414243444546474849505152535455565758596061626364 0/RTP 1/RTP 4/CK OUT 5/SYNC 0/AD 3/AD 4/AD 5/AD 6/AD 7/AD 1/AD 2/AD 3/AD 4/AD 5/AD 6/AD 7/AD 2/AN 1/AN 0/AN 7/AN M38073M4-XXXFP 6/AN 5/AN 4/AN 2/S CLK2 1/S OUT2 0/S IN2 7/DA 0/T OUT 6/S CLK1 5/T XD 4/R XD 3/INT P63/CMP IN /AN8 P64/CMP REF /AN9 P65/DAVREF /AN10 AV SS ADV REF VCC P80/DA3/AN11 P81/DA4/AN12 P82/RTP0 P83/RTP1 P84/RTP2 P85/RTP3 P86/RTP4 P87/RTP5 P42/INT0 CNV SS XIN XOUT VSS P27/DB7 P26/DB6 P25/DB5 P24/DB4 P23/DB3 P22/DB2 P21/DB1 P20/DB0 RESET 3/S RDY2 /ADT/AN 1/S CMP2 /INT 5/CNTR 4/CNTR 3/INT 2/INT 6/DA 0/AD 1/AD 2/AD 7/S RDY1 2/ONW 3/RESET OUT 6/WR 7/RD P40/XCOUT P41/XCIN CMP OUT CMPV CC MITSUBISHI MICROCOMPUTERS

3807 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Fig. 2. Functional block diagram FUNCTIONAL BLOCK DIAGRAM (Package : 80P6N) FUNCTIONAL BLOCK CNTR 0 CNTR 1 ADV REF AV SS INT4 INT2 INT1 INT0, TOUT RTP 5 RTP 0 INT4 R A M R O M C P U A X Y S PC H PC L PS SS V RESET CC V 73 26 CNV SS P0(8) 49 5051 5253 54 5556 P1(8) 41 43 45 4742 44 46 48 P2(8) 33 35 37 39 34 36 3840 P3(8) 57 59 61 6358 60 62 64 P4(8) 20 22 24 2821 23 25 29 P5(8) 12 14 16 1813 15 17 19 P7(8) 4 6 8 1057 9 11 P8(8) 65 67 69 71 66 68 70 72 P6(8) 76 78 2 77 1 374 75 RTP X IN OUT X SI/O1(8) SI/O2(8) D-A (8) D-A (8) D-A (8) D-A (8) Reset input Clock generating circuit Main clock input Main clock output A-D converter converter 2 converter 1 Timer Y (16)Timer X (16) Timer 1 (8) Timer 3 (8)Timer 2 (8) I/O port P 4 I/O port P 0 I/O port P 1 I/O port P 2 I/O port P 3 I/O port P 5 I/O port P 7 I/O port P 8 I/O port P 6 (8) INT0 TOUT RTP 5 RTP 0 converter 4 XCINXCOUT DAV REF INT1 Timer B (16)Timer A (16) XCIN XCOUT Analog comparator CMPV CC CMP OUT CMP REF CMP IN CMP REF CMP IN SCMP2 SCMP2 Sub –clock input Sub –clock output converter 3

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS VCC , VSS Power source • Apply voltage of 2.7–5.5 V to VCC , and 0 V to VSS . CMPV CC Analog comparator • Power source input pin for an analog comparator power source CNV SS CNV SS • This pin controls the operation mode of the chip.

• Normally connected to V SS .
• If this pin is connected to VCC , the internal ROM is inhibited and external memory is accessed. ADV REF Analog reference • Reference voltage input pin for A-D converter. voltage AV SS Analog power • Analog power source input pin for A-D and D-A converter and an analog comparator source • Connect to V SS . CMP OUT Analog comparator • Output pin for an analog comparator output RESET Reset input • Reset input pin for active “L” XIN Clock input • Input and output signals for the internal clock generating circuit.
• Connect a ceramic resonator or quartz-crystal oscillator between the XIN and XOUT pins to set the oscillation frequency. XOUT Clock output • If an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open.
• The clock is used as the oscillating source of system clock. P00–P0 7 I/O port P0 • 8-bit CMOS I/O port P10–P17 I/O port P1 • I/O direction register allows each pin to be individually programmed as either input or output. P20–P27 I/O port P2 • At reset this port is set to input mode.
• In modes other than single-chip, these pins are used as address, data bus I/O pins.
• CMOS compatible input level
• CMOS 3-state output structure
• Port P2 can be switched CMOS or TTL input level. P30/RTP6, I/O port P3 • 8-bit CMOS I/O port • Real time port function P31/RTP7 • I/O direction register allows each pin to be individually programmed as either input or output. pins P34/CKOUT , • At reset this port is set to input mode. • Clock output function pin P32, P33, • In modes other than single-chip, these pins are used as control bus I/O pins. P35–P37 • CMOS compatible input level
• CMOS 3-state output structure
• Port P3 2 can be switched CMOS or TTL input level. P40/XCOUT , I/O port P4 • 8-bit CMOS I/O port with the same function as port P0 • Sub-clock generating I/O P41/XCIN • CMOS compatible input level pins (connect a resonator) P42/INT0, • CMOS 3-state output structures • Interrupt input pins P43/INT1 • Timer X, Timer Y function pins (INT 0, INT1) P44/RXD, • Serial I/O1 function pins P45/TXD, P46/SCLK1 , P47/SRDY1 P50/TOUT I/O port P5 • 8-bit CMOS I/O port with the same function as port P0 • Timer 2 output pin P51/SCMP2 / • CMOS compatible input level • Interrupt input pin INT2 • CMOS 3-state output structure • Serial I/O2 function pin P52/INT3, • Interrupt input pin P53/INT4 • Real time port function pin(INT4) P54/CNTR 0, • Timer X, Timer Y function pins P55/CNTR 1 P56/DA1, • D-A conversion output P57/DA2 pins Function except a port function Table. 1. Pin description (1)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Table. 2. Pin description (2) Pin Name Function P60/AN5– I/O port P6 • 3-bit CMOS I/O port with the same function as port P0 • A-D conversion output P62/AN7 • CMOS compatible input level pins

• CMOS 3-state output structure P63/CMP IN/ Input port P6 • 2-bit CMOS input port • Analog comparator input pin AN 8 • CMOS compatible input level • A-D conversion input pin P64/CMP REF / • Reference voltage input pin AN 9 for analog comparator
• A-D conversion input pin P65/DAV REF / I/O port P6 • 1-bit CMOS I/O port with the same function as port P0 • D-A conversion power AN 10 • CMOS compatible input level source input pin
• CMOS 3-state output structure • A-D conversion input pin P70/SIN2, I/O port P7 • 8-bit CMOS I/O port with the same function as port P0 • Serial I/O2 function pins P71/SOUT2 , • CMOS compatible input level P72/SCLK2 • CMOS 3-state output structures P73/SRDY2 / • Serial I/O2 function pin ADT/AN 0 • A-D conversion input pin
• A-D trigger input pin P74/AN1– • A-D conversion input pin P77/AN4 P80/DA3/ I/O port P8 • 8-bit CMOS I/O port with the same function as port P0 • D-A conversion output AN 11, • CMOS compatible input level pin P81/DA4/ • CMOS 3-state output structures • A-D conversion input pin AN 12, P82/RTP0– • Realtime port function P87/RTP5 pins Function except a port function

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 3. Part numbering M3807 3 M 4 - XXX FPProduct Package type FP : 80P6N-A package FS : 80D0 package ROM number Omitted in some types. ROM/PROM size A B C D E F : 4096 bytes : 8192 bytes : 12288 bytes : 16384 bytes : 20480 bytes : 24576 bytes : 28672 bytes : 32768 bytes : 36864 bytes : 40960 bytes : 45056 bytes : 49152 bytes : 53248 bytes : 57344 bytes : 61440 bytes The first 128 bytes and the last 2 bytes of ROM are reserved areas ; they cannot be used. Memory type M E : Mask ROM version : EPROM or One Time PROM version RAM size : 192 bytes : 256 bytes : 384 bytes : 512 bytes : 640 bytes : 768 bytes : 896 bytes : 1024 bytes : 1536 bytes : 2048 bytes

Currently supported products are listed below. Table 3. List of supported products Note : Products under development or planning : the development schedule and specifications may be revised without notice. Support for Mask ROM, One Time PROM and EPROM versions.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER FUNCTIONAL DESCRIPTION Central Processing Unit (CPU) The 3807 group uses the standard 740 family instruction set. Refer to the table of 740 family addressing modes and machine instruc- tions or the SERIES 740 <Software> User´s Manual for details on the instruction set. Machine-resident 740 family instructions are as follows: The FST and SLW instructions cannot be used. The MUL, DIV, WIT and STP instruction can be used. The central processing unit (CPU) has the six registers. CPU Mode Register The CPU mode register contains the stack page selection bit and processor mode bits. The CPU mode register is allocated at address 003B 16. CPU mode register (CPUM : address 003B16) b7 b0 Stack page selection bit 0 : 0 page 1 : 1 page Main clock (X IN-XOUT ) stop bit 0 : oscillating 1 : stopped Main clock division ratio selection bits b7 b6 0 0 : φ = f(X IN)/2 (high-speed mode) 0 1 : φ = f(XIN)/8 (middle-speed mode) 1 0 : φ = f(XCIN)/2 (low-speed mode) 1 1 : Not available Processor mode bits b1 b0 0 0 : Single-chip mode 0 1 : Memory expansion mode 1 0 : Microprocessor mode 1 1 : Not available Port X C switch bit 0 : I/O port function (stop oscillating) 1 : X CIN-XCOUT oscillating function XCOUT drivability selection bit 0 : Low drive 1 : High drive Fig. 5. Structure of CPU mode register

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Memory Special function register (SFR) area The special function register (SFR) area in the zero page contains control registers such as I/O ports and timers. RAM RAM is used for data storage and for stack area of subroutine calls and interrupts. ROM The first 128 bytes and the last 2 bytes of ROM are reserved for device testing and the reset is user area for storing programs. Interrupt vector area The interrupt vector area contains reset and interrupt vectors. Zero page The 256 bytes from addresses 000016 to 00FF16 are called the zero page area. The internal RAM and the special function registers (SFR) are allocated to this area. The zero page addressing mode can be used to specify memory and register addresses in the zero page area. Access to this area with only 2 bytes is possible in the zero page addressing mode. Special page The 256 bytes from addresses FF0016 to FFFF16 are called the spe- cial page area. The special page addressing mode can be used to specify memory addresses in the special page area. Access to this area with only 2 bytes is possible in the special page addressing mode. Fig. 6. Memory map diagram 010016 000016 004016 084016 FF0016 FFDC 16 FFFE 16 FFFF 16 192 256 384 512 640 768 896 1024 1536 2048 XXXX 00FF16 013F16 01BF 16 023F16 02BF 16 033F16 03BF 16 043F16 063F16 083F16 4096 8192 12288 16384 20480 24576 28672 32768 36864 40960 45056 49152 53248 57344 61440 F000 E00016 D000 16 C000 16 B00016 A00016 900016 800016 700016 600016 500016 400016 300016 200016 100016 F08016 E08016 D080 16 C080 16 B08016 A08016 908016 808016 708016 608016 508016 408016 308016 208016 108016 YYYY 16 ZZZZ 16 RAM ROM Reserved area SFR area Not used Interrupt vector area ROM area Reserved ROM area (128 byte) Zero page Special page RAM area RAM capacity (byte) Address XXXX 16 ROM capacity (byte) Address YYYY 16 Reserved ROM area Address ZZZZ 16

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Fig. 7. Memory map of special function register (SFR) 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C 16 002D 16 002E16 002F16 003016 003116 003216 003316 003416 003516 003616 003716 003816 003916 003A16 003B16 003C 16 003D 16 003E16 003F16 000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C 16 000D 16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C 16 001D 16 001E16 001F16 Serial I/O2 register (SIO2) Port P0 (P0) Port P0 direction register (P0D) Port P1 (P1) Port P1 direction register (P1D) Port P2 (P2) Port P2 direction register (P2D) Port P3 (P3) Port P3 direction register (P3D) Port P4 (P4) Port P4 direction register (P4D) Port P5 (P5) Port P5 direction register (P5D) Port P6 (P6) Port P6 direction register (P6D) Port P7 (P7) Port P7 direction register (P7D) Port P8 (P8) Port P8 direction register (P8D) Timer XY control register (TXYCON) Port P2P3 control register (P2P3C) Pull-up control register (PULL) Watchdog timer control register (WDTCON) Transmit/Receive buffer register (TB/RB) Serial I/O1 status register (SIO1STS) Serial I/O1 control register (SIO1CON) UART control register (UARTCON) Baud rate generator (BRG) Serial I/O2 control register 1 (SIO2CON1) Serial I/O2 control register 2 (SIO2CON2) Real time port control register 3 (RTPCON3) Interrupt control register 2(ICON2) A-D conversion register (AD) Timer X (low-order) (TXL) Timer X (high-order) (TXH) Timer Y (low-order) (TYL) Timer Y (high-order) (TYH) Timer 1 (T1) Timer 2 (T2) Timer 3 (T3) Timer X mode register (TXM) Timer Y mode register (TYM) Timer 123 mode register (T123M) Real time port register (RTP) Real time port control register 0 (RTPCON0) Real time port control register 1 (RTPCON1) Real time port control register 2 (RTPCON2) Timer A (low-order) (TAL) Timer A (high-order) (TAH) Timer B (low-order) (TBL) Timer B (high-order) (TBH) D-A control register (DACON) A-D control register (ADCON) D-A1 conversion register (DA1) D-A2 conversion register (DA2) D-A3 conversion register (DA3) D-A4 conversion register (DA4) Interrupt edge selection register (INTEDGE) CPU mode register (CPUM) Interrupt request register 1(IREQ1) Interrupt request register 2(IREQ2) Interrupt control register 1(ICON1)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER I/O Ports [Direction Registers] PiD The 3807 group has 68 programmable I/O pins arranged in nine indi- vidual I/O ports (P0—P5, P6 0—P6 2, P65 and P7—P8). The I/O ports have direction registers which determine the input/output direction of each individual pin. Each bit in a direction register corresponds to one pin, each pin can be set to be input port or output port. When "0" is written to the bit corresponding to a pin, that pin becomes an input pin. When "1" is written to that pin, that pin becomes an output pin. If data is read from a pin set to output, the value of the port output latch is read, not the value of the pin itself. Pins set to input (the bit corre- sponding to that pin must be set to "0") are floating and the value of that pin can be written to. If a pin set to input is written to, only the port output latch is written to and the pin remains floating. [Pull-up Control Register] PULL Ports P0, P1 and P2 have built-in programmable pull-up resistors. The pull-up resistors are valid only in the case that the each control bit is set to "1" and the corresponding port direction registers are set to input mode. (1) CMOS/TTL input level selection Either CMOS input level or TTL input level can be selected as an input level for ports P2 0 to P27 and P32. The input level is selected by P2·P32 input level selection bit (b7) of the port P2P3 control register (address 001516). When the bit is set to "0", CMOS input level is selected. When the bit is set to "1", the TTL input level is selected. After this bit is re-set, its initial value depends on the state of the CNVss pin. When the CNVss pin is connected to Vss, the initial value becomes "0". When the CNVss pin is connected to Vcc, the initial value becomes "1". (2) Notes on STP instruction execution Make sure that the input level at each pin is either 0V or to Vcc during execution of the STP instruction. When an input level is at an inter- mediate potential, a current will flow from Vcc to Vss through the input-stage gate. Fig. 8. Structure of Port P2P3 control register Fig. 9. Structure of Pull-up control register Port P2P3 control register (P2P3C : address 0015 16) P34 Clock output control bit 0: I/O port 1: Clock output Output clock frequency selection bit 000: φ 001: f(X CIN) 010: “L” fixed output 011: “L” fixed output 100: f(X IN) (f(XCIN) in low-speed mode) 101: f(XIN)/2 (f(XCIN)/2 in low-speed mode) 110: f(XIN)/4 (f(XCIN)/4 in low-speed mode) 111: f(XIN)/16 (f(XCIN)/16 in low-speed mode) Not used (return "0" when read)

• P32 input level selection bit 0: CMOS level input 1: TTL level input 0: No pull-up 1: Pull-up Pull-up control register (PULL : address 0016 16) P00—P0 3 pull-up control bit P04,P05 pull-up control bit P06 pull-up control bit P07 pull-up control bit P10—P1 3 pull-up control bit P14—P1 7 pull-up control bit P20—P2 3 pull-up control bit P24—P2 7 pull-up control bit b7 b0

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Table. 4. List of I/O port functions (1) Pin Name Input/Output I/O Format Non-Port Function Related SFRs Ref.No. P00–P07 Port P0 Input/output, CMOS compatible input level Address low-order byte output CPU mode register (1) P10–P17 Port P1 individual bits CMOS 3-state output Address high-order byte output Pull-up control register P20–P27 Port P2 CMOS/TTL input level Data bus I/O CPU mode register CMOS 3-state output Pull-up control register Port P2P3 control register P30/RTP6, Port P3 CMOS compatible input level Real time port output CPU mode register (2) P31/RTP7 CMOS 3-state output Real time port control register P32 CMOS/TTL input level Control signal input CPU mode register (3) CMOS 3-state output Port P2P3 control register P33 CMOS compatible input level Control signal output CPU mode register CMOS 3-state output P34/CKOUT Clock output, φ output CPU mode register (4) Port P2P3 control register P35–P37 Control signal I/O CPU mode register (3) P40/XCOUT , Port P4 Sub-clock generating circuit CPU mode register (5) P41/XCIN (6) P42/INT0, External interrupt input Interrupt edge selection register(7) P43/INT1 Timer X, Timer Y function input P44/RXD, Serial I/O1 function I/O Serial I/O1 control register (8) P45/TXD, UART control register (9) P46/SCLK1 , (10) P47/SRDY1 (11) P50/TOUT Port P5 Timer 2 output Timer 123 mode register (12) P51/SCMP2 / External interrupt input Interrupt edge selection register(22) INT2 Serial I/O2 function I/O Serial I/O2 control register P52/INT3, External interrupt input Interrupt edge selection register(7) P53/INT4 Real time port trigger input (INT4) P54/CNTR 0 Timer X, Timer Y function I/O Timer X mode register (13) P55/CNTR 1 Timer Y mode register P56/DA1, D-A conversion output D-A control register (14) P57/DA2 P60/AN5— Port P6 A-D conversion input A-D control register (15) P62/AN7 P63/CMP IN/ Input CMOS compatible input level Analog comparator input pin A-D control register (16) AN 8 A-D conversion input P64/CMP REF / Analog comparator reference AN 9 voltage input pin A-D conversion input P65/DAV REF / Input/output, CMOS compatible input level D-A converter power source A-D control register (17) AN 10 individual bits CMOS 3-state output input A-D conversion input P70/SIN2, Port P7 Serial I/O2 function I/O Serial I/O2 control register (18) P71/SOUT2, (19) P72/SCLK2 (20) P73/SRDY2 / Serial I/O2 function I/O Serial I/O2 control register (21) ADT/AN 0 A-D trigger input A-D control register A-D conversion input P74/AN1— A-D conversion input A-D control register (15) P77/AN4

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Table. 5. List of I/O port functions (2) Pin Name Input/Output I/O Format Non-Port Function Related SFRs Ref.No. P80/DA3/ Port P8 Input/output, CMOS compatible input level D-A conversion output D-A control register (14) AN 11 individual bits CMOS 3-state output A-D conversion input A-D control register P81/DA4/ AN 12 P82/RTP0— Real time port output Real time port control (23) P87/RTP5 register Note1 : For details of the functions of ports P0 to P3 in modes other than single-chip mode, and how to use double-function ports as function I/O ports, refer to the applicable sections. 2 : Make sure that the input level at each pin is either 0 V or Vcc during execution of the STP instruction. When an input level is at an intermediate potential, a current will flow from Vcc to Vss through the input-stage gate.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Fig. 10. Port block diagram (1) (8) Port P44 Direction register Data bus Serial I/O1 enable bit Receive enable bit Port latch serial I/O1 input (3) Ports P32,P33,P35—P3 7 Direction register Data bus Port latch (6) Port P41 Direction register Data bus Port XC switch bit Port latch Sub-clock oscillating circuit input (5) Port P40 Direction register Data bus Port XC switch bit Port latch Oscillator Port P41 Port XC switch bit (7) Ports P42,P43,P52,P53 Data bus Direction register Port latch Interrupt input Timer X input (P42) Timer Y input (P43) RTP trigger input (P53) except P52 *1 Either CMOS input level or TTL input level can be selected as an input level for ports P20 to P27 and P32 by P2•P32 input level selection bit. (1) Ports P0—P2 Direction register Data bus Port latch Pull-up control (2) Ports P30,P31 Data bus Port latch Data for real time port Direction register Real time port output selection bit (4) Port P34 Data bus Port latch Clock output Direction register Clock output control

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER (9) Port P45 Data bus Serial I/O1 enable bit Transmit enable bit Serial I/O1 output P45/TXD P-channel output disable bit Port latch (11) Port P47 Data bus Serial I/O1 ready output Port latch Serial I/O1 mode selection bit Serial I/O1 enable bit SRDY1 output enable bit (10) Port P46 Serial I/O1 synchronous clock selection bit Serial I/O1 enable bit Data bus Serial I/O1 clock output Serial I/O1 external clock input Serial I/O1mode selection bit Serial I/O1enable bit Port latch Direction register (13) Ports P54,P55 Port latchData bus Timer output CNTR 0, CNTR1 interrupt input "001" "100" "101" "110" Timer X, Timer Y operating mode bits (14) Ports P56,P57,P80,P81 D-A conversion output Data bus Port latch DA 1 output enable bit (P56) DA 2 output enable bit (P57) DA 3 output enable bit (P80) DA 4 output enable bit (P81) A-D conversion input Analog input pin selection bit except P5 6,P57 (15) Ports P60—P6 2,P74—P7 7 Analog input pin selection bit A-D conversion input Data bus Port latch (16) Ports P63,P64 Analog input pin selection bit A-D conversion input Data bus Analog comparator input (12) Port P50 Port latchData bus TOUT output control bit Timer 2 output Direction register Direction register Direction register Direction register Direction register Direction register Fig. 11. Port block diagram (2)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Fig. 12. Port block diagram (3) (18) Port P70 Serial I/O2 input Data bus Direction register Port latch (19) Port P71 Data bus Port latch Direction register Serial I/O2 transmit completion signal Serial I/O2 port selection bit Serial I/O2 clock output P71/SOUT2 P-channel output disable bit (17) Port P65 Data bus Direction register Port latch D-A conversion power source input A-D conversion input Analog input pin selection bit (23) Ports P82—P8 7 Data bus Port latch Data for real time port Direction register Real time port output selection bit (22) Port P51 Data bus Serial I/O2 I/O comparison signal output Port latch Direction register Interrrupt input Serial I/O2 I/O comparison signal control bit (20) Port P72 Data bus Port latch Direction register Serial I/O2 synchronous clock selection bit Serial I/O2 port selection bit Serial I/O2 clock output Serial I/O2 external clock input P72/SCLK2 P-channel output disable bit (21) Port P73 Data bus Port latch Direction register Serial I/O2 ready output SRDY2 output enable bit A-D conversion input A-D trigger interrupt input Analog input pin selection bit AD external trigger valid bit

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Interrupts Interrupts occur by twenty sources: eight external, eleven internal, and one software. (1) Interrupt Control Each interrupt except the BRK instruction interrupt have both an interrupt request bit and an interrupt enable bit, and is controlled by the interrupt disable flag. An interrupt occurs if the corresponding interrupt request and enable bits are "1" and the interrupt disable flag is "0". Interrupt enable bits can be set or cleared by software. Inter- rupt request bits can be cleared by software, but cannot be set by software. The BRK instruction interrupt and reset cannot be disabled with any flag or bit. The I flag disables all interrupts except the BRK instruction interrupt and reset. If several interrupts requests occurs at the same time the interrupt with highest priority is accepted first. (2) Interrupt Operation Upon acceptance of an interrupt the following operations are auto- matically performed: 1. The processing being executed is stopped. 2. The contents of the program counter and processor status reg- ister are automatically pushed onto the stack 3. Concurrently with the push operation, the interrupt jump desti- nation address is read from the vector table into the program counter. 4. The interrupt disable flag is set and the corresponding inter- rupt request bit is cleared. n Notes on Use When the active edge of an external interrupt (INT 0—INT 4, CNTR0 or CNTR1) is set or the timer /INT interrupt source and the ADT/ A-D conversion interrupt source are changed, the corresponding interrupt request bit may also be set. Therefore, please take follow- ing sequence: (1) Disable the external interrupt which is selected. (2) Change the active edge in interrupt edge selection register (in case of CNTR 0: Timer X mode register ; in case of CNTR1: Timer Y mode register). (3) Clear the set interrupt request bit to "0." (4) Enable the external interrupt which is selected.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Table. 6. Interrupt vector addresses and priority Note1 : Vector addresses contain interrupt jump destination addresses. 2 : Reset function in the same way as an interrupt with the highest priority. Vector Addresses (Note 1) Interrupt RequestInterrupt Source Priority Remarks High Low Generating Conditions Reset (Note 2) 1 FFFD 16 FFFC 16 At reset Non-maskable INT0 2 FFFB 16 FFFA 16 At detection of either rising or falling edge of External interrupt INT 0 input (active edge selectable) INT1 3 FFF9 16 FFF8 16 At detection of either rising or falling edge of External interrupt INT 1 input (active edge selectable) Serial I/O1 4 FFF7 16 FFF6 16 At completion of serial I/O1 data receive Valid when serial I/O1 is selected receive Serial I/O1 5 FFF5 16 FFF4 16 At completion of serial I/O1 data transmit Valid when serial I/O1 is selected transmit shift or when transmit buffer is empty Timer X 6 FFF3 16 FFF2 16 At timer X underflow Timer Y 7 FFF1 16 FFF0 16 At timer Y underflow INT3 8 FFEF 16 FFEE 16 At detection of either rising or falling edge of External interrupt INT 3 input (active edge selectable) Valid when INT3 interrupt is selected Timer 2 At timer 2 underflow Valid when timer 2 interrupt is selected INT4 9 FFED 16 FFEC 16 At detection of either rising or falling edge of External interrupt INT 4 input (active edge selectable) Valid when INT4 interrupt is selected Timer 3 At timer 3 underflow Valid when timer 3 interrupt is selected CNTR 0 10 FFEB 16 FFEA 16 At detection of either rising or falling edge of External interrupt CNTR 0 input (active edge selectable) CNTR 1 11 FFE9 16 FFE8 16 At detection of either rising or falling edge of External interrupt CNTR 1 input (active edge selectable) Serial I/O2 12 FFE7 16 FFE6 16 At completion of serial I/O2 data transmit Valid when serial I/O2 is selected and receive INT2 13 FFE5 16 FFE4 16 At detection of either rising or falling edge of External interrupt INT 2 input (active edge selectable) Valid when INT2 interrupt is selected Timer 1 At timer 1 underflow Valid when timer 1 interrupt is selected Timer A 14 FFE3 16 FFE2 16 At timer A underflow Timer B 15 FFE1 16 FFE0 16 At timer B underflow A-D conversion 16 FFDF 16 FFDE 16 At completion of A-D conversion Valid when A-D interrupt is selected ADT At falling edge of ADT input External interrupt(valid at falling) Valid when ADT interrupt is selected and when A-D external trigger is selected. BRK instruction 17 FFDD 16 FFDC 16 At BRK instruction execution Non-maskable software interrupt

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Fig. 14. Structure of Interrupt-related registers b7 b0 b7 b0 b7 b0 b7 b0 b7 b0 Interrupt edge selection register INT0 interrupt edge selection bit INT1 interrupt edge selection bit INT2 interrupt edge selection bit INT3 interrupt edge selection bit INT4 interrupt edge selection bit Timer 1/INT2 interrupt source bit Timer 2/INT3 interrupt source bit Timer 3/INT4 interrupt source bit (INTEDGE : address 003A16) 0 : Falling edge active 1 : Rising edge activeInterrupt request register 1 INT0 interrupt request bit INT1 interrupt request bit Serial I/O1 receive interrupt request bit Serial I/O1 transmit interrupt request bit Timer X interrupt request bit Timer Y interrupt request bit Timer 2/INT 3 interrupt request bit Timer 3/INT4 interrupt request bit Interrupt control register 1 INT0 interrupt enable bit INT1 interrupt enable bit Serial I/O1 receive interrupt enable bit Serial I/O1 transmit interrupt enable bit Timer X interrupt enable bit Timer Y interrupt enable bit Timer 2/INT 3 interrupt enable bit Timer 3/INT4 interrupt enable bit 0 : No interrupt request issued 1 : Interrupt request issued (IREQ1 : address 003C 16) (ICON1 : address 003E16) Interrupt request register 2 CNTR 0 interrupt request bit CNTR 1 interrupt request bit Serial I/O2 interrupt request bit Timer 1/INT 2 interrupt request bit Timer A interrupt request bit Timer B interrupt request bit ADT/AD conversion interrupt request bit Not used (returns "0" when read) (IREQ2 : address 003D 16) Interrupt control register 2 CNTR 0 interrupt enable bit CNTR 1 interrupt enable bit Serial I/O2 interrupt enable bit Timer 1/INT 2 interrupt enable bit Timer A interrupt enable bit Timer B interrupt enable bit ADT/AD conversion interrupt enable bit Not used (returns "0" when read) (Do not write "1" to this bit) 0 : Interrupt disabled 1 : Interrupt enabled (ICON2 : address 003F 16) 0 : INT interrupt selected 1 : Timer interrupt selected Interrupt disable flag I Interrupt request Interrupt request bit Interrupt enable bit BRK instruction Reset Fig. 13. Interrupt control

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Timers The 3807 group has seven timers : four 16-bit timers (Timer X, Timer Y, Timer A, and Timer B) and three 8-bit timers (Timer 1, Timer 2, and Timer 3). All timers are down-counters. When the timer reaches either "00 16" or "000016", an underflow occurs with the next count pulse. Then the contents of the timer latch is reloaded into the timer and the timer continues down-counting. When a timer underflows, the interrupt request bit corresponding to that timer is set to "1." Read and write operation on 16-bit timer must be performed for both high- and low-order bytes. When reading a 16-bit timer, read from the high-order byte first. When writing to 16-bit timer, write to the low- order byte first. The 16-bit timer cannot perform the correct operation when reading during write operation, or when writing during read operation. Timers A and B are real time output port timers. For details, refer to the section "Real time output port". l Timer X, Timer Y Timer X and Y are independent 16-bit timers which can select enable seven different operation modes each by the setting of their mode registers. The related registers of timer X and Y are listed below. The following register abbreviations are used:

• Timer XY control register (TXYCON: address 0014 16)
• Port P4 direction register (P4D: address 000916)
• Port P5 direction register (P5D: address 000B16)
• Timer X (low-order) (TXL: address 002016)
• Timer X (high-order) (TXH: address 002116)
• Timer Y (low-order) (TYL: address 002216)
• Timer Y (high-order) (TYH: address 002316)
• Timer X mode register (TXM: address 002716)
• Timer Y mode register (TYM: address 002816)
• Interrupt edge selection register (INTEDGE: address 003A16)
• Interrupt request register 1 (IREQ1: address 003C16)
• Interrupt request register 2 (IREQ2: address 003D16)
• Interrupt control register 1 (ICON1: address 003E16)
• Interrupt control register 2 (ICON2: address 003F16) For details, refer to the structures of each register. The following is an explanation of the seven modes: (1) Timer • event counter mode À Timer mode
• Mode selection This mode can be selected by setting "000" to the following bits. Timer X operating mode bit (bits 2 to 0) of TXM Timer Y operating mode bit (bits 2 to 0) of TYM
• Count source selection In high- or middle-speed mode, f(X IN)/2, f(XIN)/16, or f(XCIN) can be selected as the count source. In low-speed mode the count source is f(X CIN). A count source is selected by the following bit. Timer X count source selection bit (bits 7 and 6) of TXM Timer Y count source selection bit (bits 7 and 6) of TYM
• Interrupt When an underflow is generated, the corresponding timer X interrupt request bit (b4) or timer Y interrupt request bit (b5) of IREQ1 is set to "1".
• Explanation of operation After reset release, timer X stop control bit (b0) and timer Y stop control bit (b1) of TXYCON are set to "1"and the timer stops. During timer stop, a timer value written to the timer X or timer Y is set by writing data to the corresponding timer latch and timer at the same time. The timer operation is started by setting the bits 0 or 1 of TXYCON to "0". When the timer reaches "0000 16", an underflow occurs with the next count pulse. Then the contents of the timer latch is reloaded into the timer and the timer continues down-counting. For changing a timer value during count operation, a latch value must be changed by writing data only to the corresponding latch first. Then the timer is reloaded with the new latch value at the next underflow. \` Event counter mode
• Mode selection This mode can be selected by the following sequence. 1. Set "000" to the timer X operating mode bit (bits 2 to 0) of TXM, or to the timer Y operating mode bit (bits 2 to 0) of TYM. 2. Select an input signal from the CNTR 0 pin (in case of timer X ; set "11" to bits 7 and 6 of TXM), or from the CNTR1 pin (in case of timer Y ; set "11" to bits 7 and 6 of TYM) as a count source. The valid edge for the count operation is selected by the CNTR0/ CNTR 1 active edge switch bit (b5) of TXM or TYM: if set to "0", counting starts with the rising edge or if set to "1", counting starts with the falling edge.
• Interrupt The interrupt generation at underflow is the same as already explained for the timer mode.
• Explanation of operation The operation is the same as already explained for the timer mode. In this mode, the double-function port of CNTR 0/CNTR 1 pin must be set to input. Figure 19 shows the timing chart for the timer • event counter mode. (2) Pulse output mode
• Mode selection This mode can be selected by setting "001" to the following bits. Timer X operating mode bit (bits 2 to 0) of TXM Timer Y operating mode bit (bits 2 to 0) of TYM
• Count source selection In high- or middle-speed mode, f(X IN)/2, f(XIN)/16, or f(XCIN) can be selected as the count source. In low-speed mode the count source is f(X CIN).
• Interrupt The interrupt generation at underflow is the same as already explained for the timer mode.
• Explanation of operation Counting operation is the same as in timer mode. Moreover the pulse which is inverted each time the timer underflows is output from CNTR 0/CNTR 1 pin. When the CNTR0/CNTR 1 active edge switch bit (b5) of TXM or TYM is "0", output starts with "H" level. When set to "1", output starts with "L" level.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Set the double-function port of CNTR0/CNTR 1 pin to output in this mode. [During timer operation stop] The output from CNTR 0/CNTR 1 pin is initialized to the level set through CNTR0/CNTR 1 active edge switch bit. [During timer operation enabled] When the value of the CNTR 0/CNTR 1 active edge switch bit is writ- ten over, the output level of CNTR0/CNTR 1 pin is inverted. Figure 20 shows the timing chart of the pulse output mode. (3) Pulse period measurement mode

• Mode selection This mode can be selected by setting "010" to the following bits. Timer X operating mode bit (bits 2 to 0) of TXM Timer Y operating mode bit (bits 2 to 0) of TYM
• Count source selection In high- or middle-speed mode, f(X IN)/2 or f(XIN)/16 can be selected as the count source. In low-speed mode the count source is f(X CIN).
• Interrupt The interrupt generation at underflow is the same as already explained for the timer mode. Bits 0 or 1 of IREQ2 is set to "1" synchronously to pulse period measurement completion.
• Explanation of operation [During timer operation stop] Select the count source. Next, select the interval of the pulse periods to be measured. When bit 5 of the TXM or TYM is set to "0", the timer counts during the interval of one falling edge of CNTR CNTR 1 pin input until the next falling edge of input. If bits 5 are set to "1", the timer counts during the interval of one rising edge until the next rising edge. [During timer operation enabled] The pulse period measurement starts by setting bit 0 or 1 of TXYCON to "0" and the timer counts down from the value that was set to the timer before the start of measurement. When a valid edge of measurement start/stop is detected, the 1's complement of the timer value is written to the timer latch and "FFFF 16" is set to the timer. Furthermore when the timer underflows, a timer X/Y interrupt request occurs and "FFFF 16" is set to the timer. The measured value is held until the next measurement completion. n Precautions Set the double-function port of CNTR0/CNTR 1 pin to input in this mode. A read-out of timer value is impossible in this mode. The timer is written to only during timer stop (no measurement of pulse periods). Since the timer latch in this mode is specialized for the read-out of measured values, do not perform any write operations during measurement. The timer is set to "FFFF 16" when the timer either underflows or a valid edge of pulse period measurement is detected. Due to that, the timer value at the start of measurement depends on the timer value before the start of measurement. Figure 19 shows the timing chart of the pulse period measurement mode. (4) Pulse width measurement mode
• Mode selection This mode can be selected by setting "011" to the following bits. Timer X operating mode bit (bits 2 to 0) of TXM Timer Y operating mode bit (bits 2 to 0) of TYM
• Count source selection In high- or middle-speed mode, f(X IN)/2 or f(XIN)/16 can be selected as the count source. In low-speed mode the count source is f(X CIN).
• Interrupt The interrupt generation at underflow is the same as already explained for the timer mode. Bit 0 or 1 of IREQ2 is set to "1" syn- chronously to pulse width measurement completion.
• Explanation of operation [During timer operation stop] Select the count source. Next, select the interval of the pulse widths to be measured. When bit 5 of TXM or TYM is set to "1", the timer counts during the interval of one falling edge of CNTR 0/CNTR 1 pin input until the next rising edge of input ("L" interval). If bit 5 is set to "0", the timer counts during the interval of one rising edge until the next falling edge ("H" interval). [During timer operation enabled] The pulse width measurement starts by setting bit 0 or 1 of TXYCON to "0" and the timer counts down from the value that was set to the timer before the start of measurement. When a valid edge of measurement completion is detected, the 1's complement of the timer value is written to the timer latch and "FFFF 16" is set to the timer. Furthermore when the timer underflows, a timer X/Y interrupt request occurs and "FFFF 16" is set to the timer. The measured value is held until the next measurement completion. n Precautions Set the double-function port of CNTR0/CNTR 1 pin to input in this mode. A read-out of timer value is impossible in this mode. The timer is written to only during timer stop (no measurement of pulse widths). Since the timer latch in this mode is specialized for the read-out of measured values, do not perform any write operations during mea- surement. The timer value is set to "FFFF 16" when the timer either underflows or a valid edge of pulse widths measurement is detected. Due to that, the timer value at the start of measurement depends on the timer value before the start of measurement. Figure 20 shows the timing chart of the pulse width measurement mode. (5) Programmable waveform generation mode
• Mode selection This mode can be selected by setting "100" to the following bits. Timer X operating mode bit (bits 2 to 0) of TXM Timer Y operating mode bit (bits 2 to 0) of TYM
• Count source selection In high- or middle-speed mode, f(X IN)/2, f(XIN)/16, or f(XCIN) can be selected as the count source. In low-speed mode the count source is f(X CIN).
• Interrupt The interrupt generation at underflow is the same as already

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS explained for the timer mode.

• Explanation of operation Counting operation is the same as in timer mode. Moreover the timer outputs the data set in the corresponding output level latch (bit 4 of TXM or TYM) to CNTR 0/CNTR 1 pin each time the timer underflows. After the timer underflows, the generation of optional waveform from CNTR 0/CNTR 1 pin is possible through a change of values in the output level latch and timer latch. n Precautions Set the double-function port of CNTR0/CNTR 1 pin to output in this mode. Figure 23 shows the timing chart of the programmable waveform generation mode. (6) Programmable one-shot generating mode
• Mode selection This mode can be selected by setting "101" to the following bits. Timer X operating mode bit (bits 2 to 0) of TXM Timer Y operating mode bit (bits 2 to 0) of TYM
• Count source selection In high- or middle-speed mode, f(X IN)/2 or f(XIN)/16 can be selected as the count source.
• Interrupt The interrupt generation at underflow is the same as already explained for the timer mode. The one-shot generating trigger condition must be set to the INT 0 interrupt edge selection bit (b0) and INT1 interrupt edge selection bit (b1) of INTEDGE. Setting these bits to "0" causes the interrupt request being triggered by a falling edge, setting them to "1" causes the interrupt request being triggered by a rising edge. The INT 0 interrupt request bit (b0) and INT1 interrupt request bit (b1) of IREQ1 are set to "1" by detecting the active edge of the INT pin.
• Explanation of operation For a "H" one-shot pulse, set bit 5 of TXM, TYM to "0". [During timer operation stop] The output level of CNTR 0/CNTR 1 pin is initialized to "L" at mode selection. Set the one-shot pulse width to TXH, TXL, TYH, TYL. A trigger generation during timer stop (input signal to INT 0/INT1 pin) is invalid. [During timer operation enabled] When a trigger generation is detected, "H" is output, and at underflow "L" is output from CNTR 0/CNTR 1 pin. For a "L" one-shot pulse set bit 5 of TXM, TYM to "1". [During timer operation stop] The output level of CNTR 0/CNTR 1 pin is initialized to "H" at mode selection. Set the one-shot pulse width to TXH, TXL, TYH, TYL. A trigger generation during timer stop (input signal to INT 0/INT1 pin) is invalid. [During timer operation enabled] When a trigger generation is detected, "L" is output, and at underflow "H" is output from CNTR 0/CNTR 1 pin. n Precautions
• Set the double-function port of CNTR0/CNTR 1 pin to output and the double-function port of INT0/INT1 pin to input in this mode.
• This mode is unused in low-speed mode.
• During one-shot generation permission or one-shot generation the output level from CNTR0/CNTR 1 pin changes if the value of the CNTR 0/CNTR 1 active edge switch bit is inverted. Figure 24 shows the timing chart of the programmable one-shot generating mode. (7) PWM mode
• Mode selection This mode can be selected by setting "110" to the following bits. Timer X operating mode bit (bits 2 to 0) of TXM Timer Y operating mode bit (bits 2 to 0) of TYM
• Count source selection In high- or middle-speed mode, f(X IN)/2 or f(XIN)/16 can be selected as the count source.
• Interrupt With a rising edge of CNTR0/CNTR 1 output, the timer X interrupt request bit (b4) and timer Y interrupt request bit (b5) of IREQ1 are set to "1".
• Explanation of operation PWM waveform is output from CNTR 0 pin (in case of timer X) or from CNTR1 pin (in case of timer Y). The "H" interval of PWM waveform is determined by the setting value m (m=0 to 255) of TXH and TYH and the "L" interval of PWM waveform is determined by the setting value n (n=0 to 255) of TXL and TYL. The PWM cycles are: PWM cycle time = (m+n)·ts PWM duty = m/(m+n) where: ts: period of timer X/timer Y count source [During count operation stop] When a timer value is set to TXL, TXH, TYL, TYH by writing data to timer and timer latch at the same time. When setting this value, the output of CNTR 0/CNTR 1 pin is initialized to the "H" level. [During count operation enabled] By setting the bit 0 or 1 of TXYCON to "0", an "H" interval of TXH or TYH is output first, and after that a "L" level interval of TXL or TYL are output next. These operations are repeated continuously. The PWM output is changed after the underflow by setting a timer value, which is set by writing data to the timer latch only, to TXL, TXH, TYL, TYH. n Precautions
• Set the double-function port of CNTR 0/CNTR 1 pin to output in this mode.
• This mode is unused in low-speed mode.
• When the PWM "H" interval is set to "00 16", PWM output is "L".
• When the PWM "L" interval is set to "0016", PWM output is "H".
• When the PWM "H" interval and "L" interval are set to "0016", PWM output is "L".
• When a PWM "H" interval or "L" interval is set to "0016" at least for a short time, timer X/timer Y interrupt request does not occur.
• When the value set to the timer latch is "0016", the value is unde- fined since the timer counts down by dummy count operation. Figure 23 shows the timing chart of the PWM mode.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER n Precautions regarding all modes

• Timer X, timer Y writing control One of the following operation is selected by bit 3 of TXM or TYM for timer X or timer Y. Writing data to the corresponding latch and timer at the same time Writing data to only corresponding latch When the operation "writing data to only corresponding latch" is selected, the value is set to the timer latch by writing a value to timer X/Y address and a timer is renewed at the next underflow. After releasing a reset, "writing the corresponding latch and timer at the same time" is selected. When a value is written to timer X/Y address, a value is set to a timer and a timer latch at the same time. When "writing data to only corresponding latch" is selected, if writ- ing to a reload latch and an underflow are performed at the same timing, the timer value is undefined.
• Timer X, timer Y read control In pulse period measurement mode and pulse width measurement mode the timer value cannot be read-out. In all other modes read- out operations without effect to count operations/stops are possible. However, the timer latch value cannot be read-out.
• Precautions regarding the CNTR 0/CNTR 1 active edge switch bit and the INT0/INT1 interrupt edge selection bit: The CNTR 0/CNTR 1 active edge switch bit and the INT0/INT1 interrupt edge selection bit settings have an effect also on each interrupt active edge.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 15. Block diagram of Timer X and Timer Y Data bus Programmable one-shot generating circuit Programmable one-shot generating mode CNTR 0 active edge switch bit "1" PWM generating circuit "0" PWM mode D T Q Programmable waveform generating mode S T Q Q pulse output mode CNTR 0 active edge switch bit "0" Pulse output mode"1" P42/INT0 Programmable one-shot generating mode PWM mode Pulse width measurement mode Pulse period measurement mode Output level latch INT0 interrupt request Timer X interrupt request CNTR 0 interrupt request f(XIN)/2 f(XIN)/16 f(XCIN) Timer X stop control bit Timer X count source selection bits P54/CNTR 0 CNTR 0 active edge switch bit "0" "1" P54 latch Timer X operating mode bits "001" "100" "101" "110" "1" "0" "0" "1" P43/INT1 INT1 interrupt request Timer Y interrupt request CNTR 1 interrupt request f(XIN)/2 f(XIN)/16 f(XCIN) P55/CNTR 1 CNTR 1 active edge switch bit "0" "1" P55 latch "001" "100" "101" "110" P55 direction register P54 direction register Edge detection circuit Edge detection circuit Timer Y (low-order) Timer Y (high-order) Timer Y latch (high-order) Programmable one-shot generating circuit PWM generating circuit Programmable one-shot generating mode PWM mode Output level latch Programmable waveform generating mode Pulse output mode Programmable one-shot generating mode CNTR 1 active edge switch bit PWM mode CNTR 1 active edge switch bit Pulse output mode D T Q S T Q Q Timer Y operating mode bits Timer Y count source selection bits Timer Y stop control bit Pulse width measurement mode Pulse period measurement mode Timer X (low-order) Timer X (high-order) Timer X latch (low-order)Timer X latch (high-order) Timer Y latch (low-order)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Fig. 16. Structure of Timer X mode register, Timer Y mode register, and Timer XY control register Timer Y mode register (TYM : address 0028 16) b7 b0 Timer X mode register (TXM : address 0027 16) Timer X operating mode bits b2 b1 b0 0 0 0 : Timer

• event counter mode 0 0 1 : Pulse output mode 0 1 0 : Pulse period measurement mode 0 1 1 : Pulse width measurement mode 1 0 0 : Programmable waveform generating mode 1 0 1 : Programmable one-shot generating mode 1 1 0 : PWM mode 1 1 1 : Not used b7 b0 Timer X count source selection bits b7 b6 0 0 : f(X IN)/2 0 1 : f(XIN)/16 1 0 : f(XCIN) 1 1 : Input signal from CNTR0 pin CNTR 0 active edge switch bit 0 : • Event counter mode ; counts rising edges
• Pulse output mode ; output starts with “H” level
• Pulse period measurement mode ; measures between two falling edges
• Pulse width measurement mode ; measures “H” periodes
• Programmable one-shot generating mode ; after start at “L” level, output a “H” pulse (interrupt request is triggered on falling edge) 1 : • Eevent counter mode ; counts falling edges
• Pulse output mode ; output starts with “L” level
• Pulse period measurement mode ; measures between two rising edges
• Pulse width measurement mode ; measures “L” periodes
• Programmable one-shot generating mode ; after start at “H” level, output a “L” pulse (interrupt request is triggered on rising edge) Timer X write control bit 0 : Write data to both timer latch and timer 1 : Write data to timer latch only Output level latch 0 : "L" output 1 : "H" output Timer Y operating mode bits b2 b1 b0 0 0 0 : Timer•event counter mode 0 0 1 : Pulse output mode 0 1 0 : Pulse period measurement mode 0 1 1 : Pulse width measurement mode 1 0 0 : Programmable waveform generating mode 1 0 1 : Programmable one-shot generating mode 1 1 0 : PWM mode 1 1 1 : Not used Timer Y count source selection bits b7 b6 0 0 : f(X IN)/2 0 1 : f(XIN)/16 1 0 : f(XCIN) 1 1 : Input signal from CNTR1 pin Timer Y write control bit 0 : Write data to both timer latch and timer 1 : Write data to timer latch only Output level latch 0 : "L" output 1 : "H" output CNTR 1 active edge switch bit 0 : • Event counter mode ; counts rising edges
• Pulse output mode ; output starts with “H” level
• Pulse period measurement mode ; measures between two falling edges
• Pulse width measurement mode ; measures “H” periodes
• Programmable one-shot generating mode ; after start at “L” level, output a “H” pulse (interrupt request is triggered on falling edge) 1 : • Eevent counter mode ; counts falling edges
• Pulse output mode ; output starts with “L” level
• Pulse period measurement mode ; measures between two rising edges
• Pulse width measurement mode ; measures “L” periodes
• Programmable one-shot generating mode ; after start at “H” level, output a “L” pulse (interrupt request is triggered on rising edge) Timer XY control register (TXYCON : address 0014 16) Not used (returns “0” when read) Timer X stop control bit 0 : start counting 1 : stop counting Timer Y stop control bit 0 : start counting 1 : stop counting b7 b0

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 18. Timing chart of Pulse output mode Fig. 17. Timing chart of Timer•Event counter mode FFFF 16 000016 TL TL: A value set to a timer latch TR: Timer interrupt request TR TR TR FFFF 16 000016 TL TL: A value set to a timer latch TR: Timer interrupt request CNTR: CNTR 0/CNTR 1 interrupt request TR TR TR TR Waveform output from CNTR 0/CNTR 1 pin CNTR CNTR This example’s condition: CNTR 0/CNTR 1 active edge switch bit “0”: ⇒ output starts with “H” level, interrupt at falling edge

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER TR: Timer interrupt request CNTR: CNTR 0/CNTR 1 interrupt request This example’s condition: CNTR 0/CNTR 1 active edge switch bit set to “1” ⇒ measure from rising edge to rising edge; interrupt at rising edge FFFF 16 000016 TR TR Signal input from CNTR 0/CNTR 1 pin CNTR CNTR CNTR FFFF 16+T2 T1T3 TR: Timer interrupt request CNTR: CNTR 0/CNTR 1 interrupt request This example’s condition: CNTR 0/CNTR 1 active edge switch bit set to “1” ⇒ measure “L” width; interrupt at rising edge Fig. 19 Timing chart of Pulse period measurement mode Fig. 20. Timing chart of Pulse width measurement mode

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 22. Timing chart of Programmable one-shot generating mode Fig. 21. Timing chart of Programmable waveform generating mode FFFF 16 000016 Signal output from CNTR 0/CNTR 1 pin T2T3 L: Initial value of timer TR: Timer interrupt request CNTR: CNTR 0/CNTR 1 interrupt request L L T1 TR TR TR TR This example’s condition: CNTR 0/CNTR 1 active edge switch bit set to “0” ⇒ output starts with “L” level; interrupt at falling edge CNTR CNTR FFFF 16 Signal output from CNTR 0/CNTR 1 pin L L TR TR TR LL Signal input from INT0/INT1 pin L: One-shot pulse width; timer latch value TR: timer interrupt request CNTR: CNTR 0/CNTR 1 interrupt request This example’s condition: CNTR 0/CNTR 1 active edge switch bit set to “0” ⇒ output a “H” pulse; interrupt at falling edge CNTR CNTR

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Fig. 23. Timing chart of PWM mode ts Timer X/Timer Y count source Timer X/Timer Y PWM output signal m 5 ts (m+n) 5 ts TR TR PWM waveform (duty : m/(m + n) and period: (m + n) 5 ts) is output m : the setting value of TXH/TYH (m = 0 to 255) n: the setting value of TXL/TYL (n = 0 to 255) ts: the period of timer X / timer Y count source CNTR CNTR: CNTR 0/CNTR 1 interrupt request TR: Timer interrupt request This example's condition: CNTR 0/CNTR 1 active edge switch bit set to “0” ⇒ output starts with “H” level; interrupt at falling edge n 5 ts

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS l Timer 1, Timer 2, Timer 3 Timer 1 to 3 are 8-bit timers for which the count source can be se- lected through timer 123 mode register. (1) Timer 2 write control Timer 2 write control bit (b2) of timer 123 mode register allows to select whether a value written to timer 2 is written to timer latch and timer synchronously or to the timer latch only. If only the timer latch is written to, the value is set only to the reload- latch by writing a value to the timer address at that time. The content of timer is reloaded with the next underflow. Usually writing operation to the timer latch and timer synchronously is selected. And a value is written to the timer latch and timer synchronously when a value is written to the timer address. If only the timer latch is written to, it may occur that the value set to the counter is not constant, when the timing with which the reload- latch is written to and the underflow timing is nearly the same. (2) Timer 2 output control When timer 2 output (T OUT ) is enabled, inverted signals are output from TOUT pin each time timer 2 has underflow. For this reason, set the double-function port of TOUT pin to output mode. n Precautions on timers 1 to 3 When the count source for timer 1 to 3 is switched, it may occur that short pulses are generated in count signals and that the timer count value shows big changes. When timer 1 output is selected as timer 2 or timer 3 count source, short pulses are generated to signals output from timer 1 through writing timer 1. Due to that, the count values for timer 2 and 3 may change very often. Therefore, when the count sources for timer 1 to 3 are set, set the values in order starting from timer 1. Fig. 25. Block diagram of Timer Fig. 24. Structure of Timer 123 mode register Timer 1 count source selection bits Timer 3 latch (8) Timer 3 (8) Q Q T S "00" P50 direction register P50 latch "0" "1" TOUT output active edge switch bit Timer 2 write control bit "0" "1" "10" P50/TOUT Timer 3 count source selection bit "0" "1" Timer 2 interrupt request Timer 3 interrupt request TOUT output control bit Timer 2 count source selection bit Timer 1 latch (8) Timer 1 (8) Timer 1 interrupt request f(XIN)/16 (f(XCIN)/16 in low-speed mode) f(XIN)/16 (f(XCIN)/16 in low-speed mode) f(XIN)/16 (f(XCIN)/16 in low-speed mode) "01" Data bus f(XCIN) f(XIN)/2 (f(XCIN)/2 in low-speed mode) Timer 2 latch (8) Timer 2 (8) TOUT output control bit TOUT output active edge switch bit 0 : start with "H" output 1 : start with "L" output Timer 123 mode register (T123M : address 0029 16) b7 b0 TOUT output control bit 0 : TOUT output disabled 1 : TOUT output enabled Timer 2 write control bit 0 : Write data to both timer latch and timer 1 : Write data to timer latch only Timer 2 count source selection bit 0 : Timer 1 output 1 : f(X IN)/16 (or f(XCIN)/16 in low-speed mode) Not used (returns “0” when read) Timer 1 count source selection bits 00 : f(X IN)/16 (or f(XCIN)/16 in low-speed mode) 01 : f(XIN)/2 (or f(XCIN)/2 in low-speed mode) 10 : f(XCIN) 11 : Not available Timer 3 count source selection bit 0 : Timer 1 output 1 : f(X IN)/16 (or f(XCIN)/16 in low-speed mode)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER The 3807 group has two on-chip sets of real time output ports (RTP). The two sets of real time output ports consist of two 16-bit timers A and B and eight 8-bit real time port registers. Synchronous to the reloading of timers A and B, the real time port register values are output from ports P8 2 to P87, P30 and P31. The real time port regis- ters consist of 8-bit register 0 to 7. Each port with its corresponding bits is shown in figure 26. Timer A and timer B have each two 16-bit timer latches. Figure 26 shows the real time port block diagram and figure 27 and 28 show the structure of the real time port control registers 0 to 3. There are four operating modes for real time ports which are: 8 repeated load mode, 6 repeated load mode, 5 repeated load mode and one-shot pulse generating mode. Each operating mode can be set for timer A and timer B separately. However, switch modes dur- ing timer count stop. (1) 8 repeated load mode The output operation for each value of the real time port registers 7 to 0 is performed repeatedly in association with an alternate underflow of the corresponding timer latch 1 or 0. The real time port output pointer changes in sequence as a cycle of 8 repeated load opera- The initial value at the generation of a start trigger can be specified by setting a value in the output pointer. Figure 29 shows a timing chart of 8 repeated load mode. (2) 6 repeated load mode The output operation for each value of real time port registers 5 to 0 is performed repeatedly in association with an alternate underflow of the corresponding timer latch 1 to 0. The real time port output pointer changes in sequence as a cycle of 6 repeated load operations as "5, The initial value at the generation of a start trigger can be specified by setting a value in the output pointer. Figure 30 shows a timing chart of the 6 repeated load mode. (3) 5 repeated load mode The output operation for each value of real time port registers 4 to 0 is performed repeatedly in association with an alternate underflow of the corresponding timer latch 1 or 0. The real time port output pointer changes in sequence as a cycle of 5 repeated load operations as "4, 3, 2, 1, 0, 4, 3, 2, 1, 0, 4, 3, 2, 1, ...." The initial value at the generation of a start trigger can be specified by setting a value in the output pointer. Figure 31 shows a timing chart of the 5 repeated load mode. (4) One-shot pulse generation mode The output operation for each value of real time port registers 2 to 0 is performed only once in association with trigger generation and an underflow of timer latch 1 or 0. After a trigger is generated, the value of real time port register 1 is output from the real time output port and the output pointer value becomes "000 2". At each underflow of the timer, the each value of real time port registers 0 and 2 is output in ascending sequence, then the operation is completed. After completion of the operation, the value of real time port register 2 is continuously output from the real time output port and the output pointer value continues to be "001 2" until the next start trigger is generated. In this condition, the real time port function is in the wait status. When this mode is selected, the pointer value is not changed by writing a value into the output pointer. If external trigger is specified as trigger selection when this mode is selected, a rising and falling double edge trigger is generated regardless of the contents of the INT 4 interrupt source bit (b7) of the interrupt edge selection register. Figure 32 shows a timing chart of the one-shot pulse generation mode. (5) Selection of timer interrupt mode The timer is a count-down system. The contents of the timer latch are reloaded by the count pulse subsequent to the moment when the contents of the counter becomes "0000 16". At the same time, the interrupt request bit corresponding to each timer is set to "1." The interrupt request corresponding to the value of the real time port output pointer can also be controlled. For controlling the interrupt request bit, refer to the item pertaining to the timer interrupt mode selection bit of the real time port control register 1,2 shown in figure 27 and 28. (6) Switch of timer count source The timer A and the timer B can select the system clock φ divided by 2 or 16 as a count source with the timer A, B count source selection bit (b0) of real time port control register 0. [Timer latches] Each of the timer A and the timer B has two 16-bit timer latches. Data is written into the 8 low-order bits and the 8 high-order bits in this order. When the high-order side has been written, the next latch is automatically specified. The writing pointer changes in sequence as "1, 0, 1, 0, 1, ...." The timer latch to be written first can be specified by setting the timer writing pointer. Data is not written directly into the timer A and the timer B. When reading the contents of the timer, the count value at that point of time is read. Read the high-order side first and then the low-order side. The low-order side value is read with the same timing as that for the high-order side value and held at the timer read latch. The data held state is released by reading the low- order side. At a reload operation of the timer A or the timer B. Timer latch 1 is reloaded as the initial value after a trigger is generated. After that, the timer latch is reloaded in sequence as "0, 1, 0, 1, ...." The timer latch value cannot be read out. [Start trigger] The operation of the real time port is started by a start trigger. When a start trigger is generated, the value of the real time port register specified by the output pointer (the value of real time port register 1 in the one-shot pulse generation mode) is output from the real time output port. The value of timer latch 1 is reloaded into the timer A or the timer B and the timer count A, B source stop bit is released, so that the timer count is started. After that, when the timer underflows, data is transferred from the real port register to the real time output port. As a start trigger, either internal trigger or external trigger can be selected by the timer A start trigger selection bit (b2) or timer B start trigger selection bit (b5) of real time port control register 0.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS When the internal trigger is selected, a start trigger is generated by an input signal of the INT 4 pin. The start trigger becomes a falling edge when the INT4 interrupt edge selection bit is "0" and a rising edge when this bit is "1". When the external trigger is selected in the one-shot pulse genera- tion mode, the start trigger becomes a rising/falling double edge trig- ger regardless of the contents of the INT 4 interrupt edge selection bit. [Real time port registers] RTP The data to be output to real time ports is written into 8 real time port registers 0 to 7. The correspondence between each bit of real time port registers and each port output is as follows : 1: bit 7 of real time port registers 7 to 0 P30: bit 6 of real time port registers 7 to 0 P87: bit 5 of real time port registers 7 to 0 P86: bit 4 of real time port registers 7 to 0 P85: bit 3 of real time port registers 7 to 0 P84: bit 2 of real time port registers 7 to 0 P83: bit 1 of real time port registers 7 to 0 P82: bit 0 of real time port registers 7 to 0 It can be selected for each bit by real time port control register 3 whether the output of each port is to be used as an ordinary I/O port or a real time port output. [Real time port data pointer] It can be optionally specified by the real time port data pointers A or B and the real time port data pointer A or B switching bit in which real time port register the output data is to be set or form which real time port register the data output is to be started. When writing output data into the real time port register, set the real time port data pointer A, B switch bit to "0" (select the R/W pointer) and also write a value into the 3 bits of the real time port data pointers A, B. With this, the real time port register for writing will be specified. After that, when a value is written into the real time port register (address 002A 16), the data is written into the specified real time port register and also the R/W pointer value is automatically decreased by 1. Then writing data is enabled into the next real time port register. A value of "000 2" to "1112" can be set int the R/W pointer regardless of the operating mode specified by the timer A, B operating mode selection bit, and the R/W pointer value is automatically decreased by 1 by writing data into the real time port register. However, when a value becomes "000 2", the R/W pointer value is decreased by 1 in the numeral range of stages to be used in each operating mode un- less the R/W pointer is set again at the subsequent write operation to the real time port register. When "111 2 (=7)" is set in the R/W pointer, the R/W pointer operation in each selected mode is as follows :

• During 8 repeated load mode 7Ý 6Ý 5Ý 4Ý 3Ý 2Ý 1Ý 0Ý 7Ý 6Ý 5...
• During 6 repeated load mode 7Ý 6Ý 5Ý 4Ý 3Ý 2Ý 1Ý 0Ý 5Ý 4Ý 3...
• During 5 repeated load mode 7Ý 6Ý 5Ý 4Ý 3Ý 2Ý 1Ý 0Ý 4Ý 3Ý 2....
• During one-shot pulse generation mode 7Ý 6Ý 5Ý 4Ý 3Ý 2Ý 1Ý 0Ý 2Ý 1Ý 0.... When reading the real time port register, set the real time port data pointer A, B switch bit to "0" (select the R/W pointer) and also writing a value into the 3 bits of the real time port data pointer A, B to specify the real time port register for reading. After that, the value of the specified real time port register can be read by reading the real time port register (address 002A 16). In this care, however, the R/W pointer value is not counted down automatically. Accordingly, to read an- other real time port register, rewrite the R/W pointer beforehand. To specify a read port register to be output to the real time output port, set the real time port data pointer A, B switch bit to "1" (select an output pointer) and also set a value in the 3 bits of the real time port data pointer A or B. When a start trigger is generated, data is output beginning with the real time port register set in the output pointer and the output pointer value is automatically decreased by 1. At each underflow of the timer A or timer B, the output pointer value is automatically decreased by 1. Regarding the case of the one-shot pulse generation mode, however, refer to the item pertaining to the one-shot pulse generation mode. When the real time port data pointer A to B has been read, only the output pointer can be read. n Notes regarding all modes
• When the trigger is generated again during timer count operation, the operation is started from the beginning. In this case, put an interval of 3 cycles or more between the generation of a trigger and the generation of the next trigger, If the generation of the next trig- ger occurs almost concurrently with the underflow timing of the timer, the next real time output may not be performed normally.
• To stop the timer count after generation of a start trigger, write "1" in the timer A, B count source stop bit of real time port control register 0 at an interval of 3 cycles or more of the timer count source.
• To change the contents of the real time port data pointer A, B switch bit, the real time port data pointer must be specified simultaneously. Therefore, use the LDM/STA instruction instead of the SEB/CLB instruction.
• If the timer A, B count source stop bit is changed ("1"Ý "0") by a start trigger between the read operation and the write operation of a read-modify-write instruction such as the SEB instruction which is used in real time port control register 0, the timer count will stop, having an effect on the real time output. An maximum interval of 2 cycles of the count source is required before the timer A, B count source stop bit is cleared to "0" which indicates the count operation state after a start trigger is generated regardless of whether the start trigger is an internal trigger or an external trigger. Accordingly, do not use the read-modify-write instruction for real time port control register 0 in this period. If a write operation for real time port control register 0 with any purpose other than stopping the timer count is performed concurrently with the generation of a start trigger, be sure to use such an instruction for writing "0" into the timer A, B count source stop bit as the LDM/STA instruction. Even if "0" is written into the timer A, B count source stop bit, the timer count remains in the stop state without change.
• When the timing for writing to the high-order side reload latch is almost equal to the underflow timing, an undesirable value may be set in the timer A or timer B.
• If the real time output port is selected by real time port control regis- ter 3 after resetting, "L" is output from this pin until a start trigger is generated.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER "10" "00" "01" Main clock division ratio selection bits "1" "0" Timer A, B count source selection bit Timer B interrupt request Timer A interrupt request P85/RTP3 Real time output Real time port output selection bit (P8 P85 latch P85 direction register P84/RTP2 P84 latch P84 direction register P83/RTP1 Real time output Real time port output selection bit (P8 P83 latch P83 direction register P82/RTP0 P82 latch PWM 0èoóÕ PWM 1èoóÕ 0 1 State transition of timer count source stop bit operation stop Timer count source stop bit is set to "1". at reset When an external start trigger is generated (external trigger is selected) When a start trigger bit is set to "1" (internal trigger is selected) A timer latch value is loaded into the timer P82 direction register Real time output Real time port output selection bit (P8 Real time output Real time port output selection bit (P8 Real time output Real time port output selection bit (P8 Real time output Real time port output selection bit (P8 Real time port register 4 (8) Real time port register 5 (8) Real time port register 6 (8) Real time port register 7 (8) Real time port register 0 (8) Real time port register 1 (8) Real time port register 2 (8) Real time port register 3 (8) "0" "1" Output latch (8) Timer B 0H latch (8) Timer B 1H latch (8) Timer B 0L latch (8) Timer B 1L latch (8) Timer B count source stop bit Timer A count source stop bit Timer A (16) Timer A 1H latch (8) Timer A 1L latch (8) "0" "1" Timer B (16) A timer latch value is loaded into the timer P50/RTP0 /PWM 0 P31/RTP7 P30/RTP6 Real time port R/W pointer A (3) Real time port output pointer A (3) Real time port output pointer B (3) Timer A write pointer (1) Timer B write pointer (1) Timer B read-out latch (8) Real time port R/W pointer B (3) Real time port • port allocation selection bit Timer A 0H latch (8)Timer A 0L latch (8) Timer A read-out latch (8) Real time port • port allocation selection bit Real time output Real time port output selection bit ( P31) Real time output Real time port output selection bit ( P30) Fig. 26. Block diagram of Real time output port

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Note: Rising or falling edge of external input can be switched by the INT4 interrupt edge selection bit of interrupt edge selection register (however, at one-shot pulse generating mode the timer is triggered at both rising and falling edge). Timer A interrupt mode selection bit 0: Interrupt request occurs with RTP output pointer value “000 1: Interrupt request occurs regardless of RTP output pointer value Timer A operation mode selection bit 00: 8 repeated load mode 01: 6 repeated load mode 10: 5 repeated load mode 11: One-shot pulse generating mode Real time port control register 1 (RTPCON1 : address 002C 16) Real time port data pointer A (output pointer value at read-out) 000: indicates real time port register 0 001: indicates real time port register 1 010: indicates real time port register 2 011: indicates real time port register 3 100: indicates real time port register 4 101: indicates real time port register 5 110: indicates real time port register 6 111: indicates real time port register 7 Timer A write pointer 0: indicates timer A0 latch 1: indicates timer A1 latch Real time port control register 0 (RTPCON0 : address 002B 16) Timer A, B count source selection bit 0: f(X IN)/2 or f(XCIN)/2 1: f(XIN)/16 or f(XCIN)/16 Timer B start trigger bit (“0” at read-out) 0: Not triggered 1: Timer B start (when bit 5=”0”) Timer A start trigger selection bit 0: Internal trigger (trigger is generated by setting bit 3 to “1”) 1: External trigger (trigger start by external input INT 4) (note) Timer A start trigger bit (“0” at read-out) 0: Not triggered 1: Timer A start (when bit 2=”0”) Real time port • port allocation selection bit 0: 4-4 port division (P8 2 to P85 correspond to timer A; P86, P87, P30, P31 correspond to timer B) 1: 2-6 port division (P8 2 to P87 correspond to timer A; P30, P31 correspond to timer B) Timer B count source stop bit 0: Count operation (when a start trigger is generated, “0” is set automatically) 1: Count stop Timer A count source stop bit 0: Count operation (when a start trigger is generated, “0” is set automatically) 1: Count stop Real time port data pointer A switch bit (“1” at read-out ) 0: R/W pointer 1: Output pointer Timer B start trigger selection bit 0: Internal trigger (trigger is generated by setting bit 6 to “1”) 1: External trigger (trigger start by external input INT 4) (note) Fig. 27. Structure of Real time output port related register (1)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Fig. 28 Structure of Real time output port related register (2) Timer B interrupt mode selection bit 0: Interrupt request occurs with RTP output pointer value “000 1: Interrupt request occurs regardless of RTP output pointer value Real time port control register 2 (RTPCON2 : address 002D 16) Real time port data pointer B (output pointer value at read-out) 000: indicates real time port register 0 001: indicates real time port register 1 010: indicates real time port register 2 011: indicates real time port register 3 100: indicates real time port register 4 101: indicates real time port register 5 110: indicates real time port register 6 111: indicates real time port register 7 Timer B write pointer 0: indicates timer B0 latch 1: indicates timer B1 latch Real time port control register 3 (RTPCON3 : address 002E 16) Real time port output selection bit (P82) 0: I/O port 1: Real time output port Real time port output selection bit (P8 0: I/O port 1: Real time output port Real time port output selection bit (P84) 0: I/O port 1: Real time output port Real time port output selection bit (P8 0: I/O port 1: Real time output port Real time port output selection bit (P86) 0: I/O port 1: Real time output port Real time port output selection bit (P8 0: I/O port 1: Real time output port Real time port output selection bit (P3 0: I/O port 1: Real time output port Real time port output selection bit (P3 0: I/O port 1: Real time output port Real time port data pointer B switch bit (“1” at read-out ) 0: R/W pointer 1: Output pointer Timer B operating mode selection bit 00: 8 repeated load mode 01: 6 repeated load mode 10: 5 repeated load mode 11: One-shot pulse generating mode

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 30. 6 repeated load mode operation Fig. 29. 8 repeated load mode operation Timer A count value Port P82 / RTP0 Port P83 / RTP1 Synchronous to the start trigger the timer latch value is loaded into the timer and timer count operation starts. Timer count source stop bit Timer A operating mode selection bit: in case of 8 repeated load mode Port P84 / RTP2 Port P85 / RTP3 7 6543210765 110 0 00 011 10 011 1 00 000 11 000 1 11 000 00 000 0 01 110 00 A 1 A 0 A 1 A 0 A 1 A 0 A 1 A 0 A 1 A 0 A 1 Real time port output pointer A #7—0: Data of real time port registers 7 to 0 4-4 port division Timer A operating mode selection bit: in case of 6 repeated load mode Timer A count value Port P82 / RTP0 Port P83 / RTP1 Synchronous to the start trigger the timer latch value is loaded into the timer and timer count operation starts. Timer count source stop bit Port P84 / RTP2 5 4321054321Real time port output pointer A 11 00 01 11 00 0 01 11 00 01 11 0 00 01 11 00 01 1 A 1 A 0 A 1 A 0 A 1 A 0 A 1 A 0 A 1 A 0 A 1 #5—0: Data of real time port registers 5 to 0 4-4 port division (3 ports out of P82/RTP0 to P85/RTP3 are used)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Fig. 31. 5 repeated load mode operation Timer A operating mode selection bit: in case of 5 repeated load mode Synchronous to the start trigger the timer latch value is loaded into the timer and timer count operation starts. 4 321043 2 1 0 10 00 11 00 01 11 00 01 1 00 0 01 10 00 11 00 00 11 0 00 1 10 A1 A0 A1 A0 A1 A0 A1 A0 A1 A0 Timer A count value Port P82 / RTP0 Port P83 / RTP1 Timer count source stop bit Port P84 / RTP2 Port P85 / RTP3 Real time port output pointer A Port P86 / RTP4 00 01 10 00 11 #4—0: Data of real time port registers 4 to 0 2-6 division (5 ports out of P82/RTP0 to P87/RTP5 are used) Timer A count value Synchronous to the start trigger the timer latch value is loaded into the timer and timer count operation starts. Timer count source stop bit Real time port output pointer A Timer A operating mode selection bit: in case of one-shot pulse generating mode Port P82 / RTP0 External start trigger input INT4 100 1 0 0 011 0 A1 A0 A1 A0 Counting stops when timer A0 latch has underflow 02 02 Port P83 / RTP1 #2—0: Data of real time port registers 2 to 0 Counting stops when timer A0 latch has underflow Fig. 32. One-shot pulse generating mode operation

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Serial I/O l Serial I/O1 Serial I/O1 can be used as either clock synchronous or asynchro- nous (UART) serial I/O. A dedicated timer (baud rate generator) is also provided for baud rate generation during Serial I/O1 opera- tion. (1) Clock Synchronous Serial I/O Mode Clock synchronous serial I/O1 mode can be selected by setting the serial I/O1 mode selection bit (b6) of the serial I/O1 control register to "1." For clock synchronous serial I/O, the transmitter and the receiver must use the same clock for serial I/O1 operation. If an internal clock is used, transmit/receive is started by a write signal to the Transmit/Receive buffer register (TB/RB) (address:0018 16). 1/4XIN F/F P46/SCLK1 Serial I/O1 status register Serial I/O 1 control register P47/SRDY1 P44/RXD P45/TXD f(XIN) (f(XCIN) in low-speed mode) Receive buffer register Address 001816 Receive shift register Receive buffer full flag (RBF) Receive interrupt request (RI) Clock control circuitShift clock Serial I/O1 synchronous clock selection bit Baud rate generator Division ratio 1/(n+1) Address 001C16 BRG count source selection bit Clock control circuitFalling edge detector Transmit buffer register Data bus Address 001816 Shift clock Transmit shift register shift completion flag (TSC) Transmit buffer empty flag (TBE) Transmit interrupt request (TI) Transmit interrupt source selection bit Address 0019 Data bus Address 001A16 Transmit shift register D 7 D 7 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 0 D 1 D 2 D 3 D 4 D 5 D 6 RBF = 1 TSC = 1TBE = 0 TBE = 1 TSC = 0 Transmit/Receive shift clock (1/2— 1/2048 of internal clock or external clock) Serial output TxD Serial input RxD Write-in signal to transmit/receive buffer register (address 0018 16) Overrun error (OE) detection Notes 1 : The transmit interrupt (TI) can be selected to occur either when the transmit buffer has emptied (TBE=1) or after the transmit shift operation has ended (TSC=1), by setting transmit interrupt source selection bit (TIC) of the serial I/O1 control register. 2 : If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data is output continuously from the TxD pin. 3 : The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” . Receive enable signal SRDY1 Fig. 34. Operation of clock synchronous serial I/O1 function Fig. 33. Block diagram of clock synchronous serial I/O1

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER (2) Asynchronous Serial I/O (UART) Mode Asynchronous serial I/O1 mode (UART) can be selected by clear- ing the Serial I/O1 mode selection bit (b6) of the Serial I/O1 control register to "0." Eight serial data transfer formats can be selected and the transfer formats used by a transmitter and receiver must be identical. The transmit and receive shift registers each have a buffer (the two buffers have the same address in memory). Since the shift register cannot be written to or read from directly, transmit data is written to the transmit buffer, and receive data is read from the receive buffer. The transmit buffer can also hold the next data to be transmitted, and the receive buffer can hold a character while the next charac- ter is being received. f(XIN) OE PE FE Data bus Receive buffer register Address 001816 Receive shift register Receive buffer full flag (RBF) Receive interrupt request (RI) Baud rate generator Division ratio 1/(n+1) Address 001C16 ST/SP/PA generator Transmit buffer register Data bus Transmit shift register Address 001816 Transmit shift register shift completion flag (TSC) Transmit buffer empty flag (TBE) Transmit interrupt request (TI) Address 001916 STdetector SP detector UART control register Address 001B16 Character length selection bit Address 001A16 BRG count source selection bit Transmit interrupt source selection bit Serial I/O1 synchronous clock selection bit Clock control circuit Character length selection bit 7 bit 8 bit (f(X CIN) in low-speed mode) Serial I/O1 control register P46/SCLK1 Serial I/O1 status register P44/RXD P45/TXD Fig. 35. Block diagram of UART serial I/O1 TSC=0 TBE=1 RBF=0 TBE=0 TBE=0 RBF=1 RBF=1 STD 0 D 1 SP D 0 D 1ST SP TBE=1 TSC=1* STD 0 D 1 SP D 0 D 1ST SP Transmit or receive clock Write-in signal to transmit buffer register Serial output TXD Read-out signal from receive buffer register Serial input RXD * Generated at 2nd bit in 2-stop bit mode 1 start bit 7 or 8 data bit 1 or 0 parity bit 1 or 2 stop bit 1: Error flag detection occurs at the same time that the RBF flag becomes "1" (at 1st stop bit, during reception). 2: The transmit interrupt (TI) can be selected to occur when either the TBE or TSC flag becomes "1", depending on the setting of the transmit interrupt source selection bit (TIC) of the serial I/O1 control register. 3: The receive interrupt (RI) is set when the RBF flag becomes "1". 4: After data is written to the transmit buffer register when TSC=1, 0.5 to 1,5 cycles of the data shift cycle is necessary until changing to TSC=0. Notes Fig. 36. Operation of UART serial I/O1 function

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER [Transmit Buffer Register/Receive Buffer Register] TB/RB (001816) The transmit buffer and the receive buffer are located in the same address. The transmit buffer is write-only and the receive buffer is read-only. If a character bit length is 7 bits, the MSB of data stored in the receive buffer is "0". [Serial I/O 1 Status Register] SIO1STS (0019 16) The read-only serial I/O1 status register consists of seven flags (b0 to b6) which indicate the operating status of the serial I/O1 function and various errors. Three of the flags (b4 to b6) are only valid in UART mode. The receive buffer full flag (b1) is cleared to "0" when the receive buffer is read. The error detection is performed at the same time data is transferred from the receive shift register to the receive buffer register, and the receive buffer full flag is set. A writing to the serial I/O1 status regis- ter clears all the error flags OE, PE, FE, and SE (b3 to b6, respec- tively). Writing "0" to the serial I/O1 enable bit (SIOE : b7 of the serial I/O1 control register) also clears all the status flags, including the error flags. All bits of the serial I/O1 status register are initialized to "0" at reset, but if the transmit enable bit (b4) of the serial I/O1 control register has been set to "1", the transmit shift register shift completion flag (b2) and the transmit buffer empty flag (b0) become "1." [Serial I/O1 Control Register] SIO1CON (001A 16) The serial I/O1 control register contains eight control bits for serial I/O1 functions. [UART Control Register] UARTCON (001B 16) The UART control register consists of four control bits (b0 to b3) which are valid when asynchronous serial I/O is selected and set the data format of an data transfer. One bit in this register (b4) is always valid and sets the output structure of the P4 5/TxD pin. [Baud Rate Generator] BRG (001C16) The baud rate generator determines the baud rate for serial transfer. With the 8-bit counter having a reload register the baud rate genera- tor divides the frequency of the count source by 1/(n+1), where n is the value written to the baud rate generator. b7b7 Transmit buffer empty flag (TBE) 0: Buffer full 1: Buffer empty Receive buffer full flag (RBF) 0: Buffer empty 1: Buffer full Transmit shift register shift completion flag (TSC) 0: Transmit shift in progress 1: Transmit shift completed Overrun error flag (OE) 0: No error 1: Overrun error Parity error flag (PE) 0: No error 1: Parity error Framing error flag (FE) 0: No error 1: Framing error Summing error flag (SE) 0: (OE) U (PE) U (FE)=0 1: (OE) U (PE) U (FE)=1 Not used (returns "1" when read) Serial I/O1 status register (SIO1STS : address 0019 16) Serial I/O1 control register (SIO1CON : address 001A 16) b0 b0 BRG count source selection bit (CSS) 0: f(X IN) (f(XCIN) in low-peed mode) 1: f(XIN)/4 ((XCIN)/4 in low-speed mode) Serial I/O1 synchronous clock selection bit (SCS) 0: BRG/ 4 (when clock synchronous serial I/O is selected) BRG/16 (UART is selected) 1: External clock input (when clock synchronous serial I/O is selected) External clock input/16 (UART is selected) S RDY1 output enable bit (SRDY) 0: P47 pin operates as ordinaly I/O pin 1: P47 pin operates as SRDY1 output pin Transmit interrupt source selection bit (TIC) 0: Interrupt when transmit buffer has emptied 1: Interrupt when transmit shift operation is completed Transmit enable bit (TE) 0: Transmit disabled 1: Transmit enabled Receive enable bit (RE) 0: Receive disabled 1: Receive enabled Serial I/O1 mode selection bit (SIOM) 0: Asynchronous serial I/O (UART) 1: Clock synchronous serial I/O Serial I/O1 enable bit (SIOE) 0: Serial I/O1 disabled (pins P4 4 to P47 operate as ordinary I/O pins) 1: Serial I/O1 enabled (pins P4 4 to P47 operate as serial I/O pins) b7 UART control register (UARTCON : address 001B 16) Character length selection bit (CHAS) 0: 8 bits 1: 7 bits Parity enable bit (PARE) 0: Parity cheching disabled 1: Parity checking enabled Parity selection bit (PARS) 0: Even parity 1: Odd parity Stop bit length selection bit (STPS) 0: 1 stop bit 1: 2 stop bits 5/TXD P-channel output disable bit (POFF) 0: CMOS output (in output mode) 1: N-channel open-drain output (in output mode) Not used (return "1" when read) Fig. 37. Structure of serial I/O1 related register

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER l Serial I/O2 The serial I/O2 can be operated only as the clock synchronous type. As a synchronous clock for serial transfer, either internal clock or external clock can be selected by the serial I/O2 synchronous clock selection bit (b6) of serial I/O2 control register 1. The internal clock incorporates a dedicated divider and permits selecting 6 types of clock by the internal synchronous clock selec- tion bit (b2, b1, b0) of serial I/O2 control register 1. Regarding S OUT2 and SCLK2 being output pins, either CMOS output format or N-channel open-drain output format can be selected by the P7 1/SOUT2 , P72/SCLK2 P-channel output disable bit (b7) of serial I/O2 control register 1. When the internal clock has been selected, a transfer starts by a write signal to the serial I/O2 register (address 001F 16). After comple- tion of data transfer, the level of the SOUT2 pin goes to high imped- ance automatically but bit 7 of the serial I/O2 control register 2 is not set to "1" automatically. When the external clock has been selected, the contents of the serial I/O2 register is continuously sifted while transfer clocks are input. Accordingly, control the clock externally. Note that the S OUT2 pin does not go to high impedance after completion of data trans- fer. To cause the S OUT2 pin to go to high impedance in the case where the external clock is selected, set bit 7 of the serial I/O2 control register 2 to "1" when S CLK2 is "H" after completion of data transfer. After the next data transfer is started (the transfer clock falls), bit 7 of the serial I/O2 control register 2 is set to "0" and the S OUT2 pin is put into the active state. Regardless of the internal clock to external clock, the interrupt re- quest bit is set after the number of bits (1 to 8 bits) selected by the optional transfer bit is transferred. In case of a fractional number of bits less than 8 bits as the last data, the received data to be stored in the serial I/O2 register becomes a fractional number of bits close to MSB if the transfer direction selection bit of serial I/O2 control register 1 is LSB first, or a fractional number of bits close to LSB if the said bit is MSB first. For the remaining bits, the previously re- ceived data is shifted. At transmit operation using the clock synchronous serial I/O, the S CMP2 signal can be output by comparing the state of the transmit pin SOUT2 with the state of the receive pin SIN2 in synchronization with a rise of the transfer clock. If the output level of the SOUT2 pin is equal to the input level to the SIN2 pin, "L" is output from the SCMP2 pin. If not, "H" is output. At this time, an INT2 interrupt request can also be generated. Select a valid edge by bit 2 of the interrupt edge selection register (address 003A 16). [Serial I/O2 Control Registers 1, 2] SIO2CON1 / SIO2CON2 The serial I/O2 control registers 1 and 2 are containing various se- lection bits for serial I/O2 control as shown in Figure 40. Fig. 38 Structure of Serial I/O2 control registers 1, 2 Serial I/O2 control register 1 (SIO2CON1 : address 001D 16) Serial I/O2 control register 2 (SIO2CON2 : address 001E 16) b7 b0 Optional transfer bits b2 b1 b0 0 0 0: 1 bit 0 0 1: 2 bit 0 1 0: 3 bit 0 1 1: 4 bit 1 0 0: 5 bit 1 0 1: 6 bit 1 1 0: 7 bit 1 1 1: 8 bit Not used ( returns "0" when read) Serial I/O2 I/O comparison signal control bit 0: P5

1 I/O

1: SCMP2 output SOUT2 pin control bit (P71) 0: Output active 1: Output high-impedance Internal synchronous clock selection bit b2 b1 b0 0 0 0: f(XIN)/8 (f(XCIN)/8 in low-speed mode) 0 0 1: f(XIN)/16 (f(XCIN)/16 in low-speed mode) 0 1 0: f(XIN)/32 (f(XCIN)/32 in low-speed mode) 0 1 1: f(XIN)/64 (f(XCIN)/64 in low-speed mode) 1 1 0: f(XIN)/128 f(XCIN)/128 in low-speed mode) 1 1 1: f(XIN)/256 (f(XCIN)/256 in low-speed mode) Serial I/O2 port selection bit 0: I/O port 1: S OUT2 ,SCLK2 output pin SRDY2 output enable bit 0: P73 pin is normal I/O pin 1: P73 pin is SRDY2 output pin Transfer direction selection bit 0: LSB first 1: MSB first Serial I/O2 synchronous clock selection bit 0: External clock 1: Internal clock 1/SOUT2 ,P72/SCLK2 P-channel output disable bit 0: CMOS output (in output mode) 1: N-channel open-drain output (in output mode )

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER XIN "1" "0" "0" "1" "0" "1" SRDY2 S CLK2 "0" "1" "1" "0" XCIN "10" "00" "01" Data bus Serial I/O2 interrupt requestSerial I/O2 port selection bit Serial I/O counter 2 (3) Serial I/O2 register (8) Synchronous circuit Serial I/O2 port selection bit Serial I/O2 synchronous clock selection bit S RDY2 output enable bit External clock Internal synchronous clock selection bitDivider Optional transfer bits (3) P72/SCLK2 P71/SOUT2 P70/SIN2 P72 latch P71 latch P73 latch P73/SRDY2 P51/SCMP2 /INT2 Serial I/O2 I/O comparison signal control bit P51 latch Q D Main clock division ratio selection bits (Note) Note: Either high-speed, middle-speed or low-speed mode is selected by bits 6 and 7 of CPU mode register. Fig. 40. Timing chart of Serial I/O2 D 7D 0 D 1 D 2 D 3 D 4 D 5 D 6 Transfer clock (Note 1) Serial I/O2 output SOUT2 Serial I/O2 input SIN2 Receive enable signal SRDY2 Write-in signal to serial I/O2 register (Note 2) Serial I/O2 interrupt request bit set 1: When the internal clock is selected as a transfer clock, the f(XIN) clock division (f(XCIN) in low-speed mode) can be selected by setting bits 0 to 2 of serial I/O2 control register 1. 2: When the internal clock is selected as a transfer clock, the S COUT2 pin has high impedance after transfer completion. Notes Fig. 39. Block diagram of Serial I/O2

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER SCLK2 SIN2 SOUT2 SCMP2 Judgement of I/O data comparison Fig. 41 SCMP2 output operation

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER A-D Converter [A-D Conversion Register] AD (address 003516) The A-D conversion register is a read-only register that contains the result of an A-D conversion. When reading this register during an A-D conversion, the previous conversion result is read. [A-D Control Register] ADCON The A-D control register controls the A-D conversion process. Bits 0 to 3 of this register select specific analog input pins. Bit 4 signals the completion of an A-D conversion. The value of this bit remains at "0" during an A-D conversion, then changes to "1" when the A-D conver- sion is completed. Writing "0" to this bit starts the A-D conversion. When bit 6, which is the AD external trigger valid bit, is set to "1", this bit enables A-D conversion at a falling edge of an ADT input. Set ports which is also used as ADT pins to input when using an A-D external trigger. Bit 5 is the ADV REF input switch bit. Writing "1" to this bit, this bit always causes ADVREF connection. Writing "0" to this bit causes ADVREF connection only during A-D conversion and cut off when A-D conversion is completed. [Comparison Voltage Generator] The comparison voltage generator divides the voltage between AV SS and ADVREF by 256, and outputs the divided voltages. [Channel Selector] The channel selector selects one of the input ports AN 12 to AN0 and inputs it to the comparator. [Comparator and Control Circuit] The comparator and control circuit compares an analog input voltage with the comparison voltage and stores the result in the A-D conversion register. When an A-D conversion is completed, the control circuit sets the AD conversion completion bit and the AD conversion interrupt request bit to "1." Note that the comparator is constructed linked to a capacitor, so set f(X IN) to at least 500kHz during A-D conversion. Use a CPU system clock dividing the main clock XIN as the internal clock φ. n Note When the A-D external trigger is invalidated by the AD external trigger valid bit, any interrupt request is not generated at a fall of the ADT input. When the AD external trigger valid bit is set to "1" before- hand, A-D conversion is not started by writing "0" into the AD conver- sion completion bit and "0" is not written into the AD conversion completion bit. Do not set "0" in the AD conversion completion bit concurrently with the timing at which the AD external trigger valid bit is rewritten. Put an interval of at least 50 cycles to more of the internal clock φ between a start of A-D conversion and the next start of A-D conversion. A-D control register (ADCON : address 0034 16) Analog input pin selection bit 0000: P7 3/SRDY2 /ADT/AN0 0001: P74/AN1 0010: P75/AN2 0011: P76/AN3 0100: P77/AN4 0101: P60/AN5 0110: P61/AN6 0111: P62/AN7 1000: P63/CMP IN/AN8 1001: P64/CMP REF /AN9 1010: P65/DAVREF /AN10 1011: P80/DA3/AN11 1100: P81/DA4/AN12 AD conversion completion bit 0: Conversion in progress 1: Conversion completed ADV REF input switch bit 0: OFF 1: ON AD external trigger valid bit 0: A-D external trigger invalid 1: A-D external trigger valid Interrupt source selection bit 0: Interrupt request at A-D conversion completed 1: Interrupt request at ADT input falling b7 b0 A-D control register Channel selector A-D control circuit A-D conversion register Resistor ladder AV SS ADV REF Comparator ADT/A-D interrupt request b7 b0 Data bus P73/SRDY2 /ADT/AN0 P74/AN1 P75/AN2 P76/AN3 P77/AN4 P60/AN5 P61/AN6 P62/AN7 P63/CMP IN/AN8 P64/CMP REF /AN9 P65/DAVREF /AN10 P80/DA3/AN11 P81/DA4/AN12 Fig. 42. Structure of A-D control register Fig. 43. Block diagram of A-D converter

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER D-A control register (DACON : address 0033 16) DA 1 output enable bit DA 2 output enable bit DA 3 output enable bit DA 4 output enable bit Not used (return "0" when read) 0 : Output disabled 1 : Output enabled b7 b0 AV SS P65/DAVREF /AN10 "0" "1" MSB "0" "1" R R R R R R R 2R 2R LSB P56/DA1 P57/DA2 P80/DA3/AN11 P81/DA4/AN12 D-A i conversion register (Note) DA i output enable bit (Note) Note: i=1 to 4 Fig. 46. Equivalent connection circuit of D-A converter D-A Converter The 3807 group has an on-chip D-A converter with 8-bit resolution and 4 channels (DAi (i=1—4)). The D-A converter is performed by setting the value in the D-A conversion register. The result of D-A converter is output from DAi pin by setting the DAi output enable bits to "1." When using the D-A converter, the corresponding port direc- tion register bit (P6 5/DAVREF /AN10, P56/DA1, P57/DA2, P80/DA3/AN11, P81/DA4/AN12) should be set to "0" (input status). The output analog voltage V is determined by the value n (base 10) in the D-A conversion register as follows: V=DAV REF x n/256 (n=0 to 255) Where DAV REF is the reference voltage. At reset, the D-A conversion registers are cleared to "0016", the DAi output enable bits are cleared to "0", and DAi pin is set to input (high impedance). The DA output is not buffered, so connect an external buffer when driving a low-impedance load. D-A1 conversion register (003616) D-A2 conversion register (003716) D-A3 conversion register (003816) D-A4 conversion register (003916) P56/DA1 P57/DA2 P80/DA3/AN11 P81/DA4/AN12 Data bus D-A i conversion register (8) R-2R resistor ladder DA i output enable bit Fig. 44. Structure of D-A control register Fig. 45. Block diagram of D-A converter

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Analog Comparator An analog comparator circuit which is independent of peripheral cir- cuits in the microcomputer is incorporated (Note). An analog comparator outputs the result of comparison with an input voltage of CMP REF pin which is specified as a reference voltage and an input voltage of CMPIN pin to CMPOUT pin. The result is "1" when the input voltage to port CMPIN is higher than the voltage applied to port CMPREF and "0" when the voltage is lower. Because the analog comparator consists of an analog MOS circuit, set the input voltage to the CMP IN pin and the CMPREF pin within the following range : VSS +1.2 V to CMPVCC –0.5V n Note The analog comparator circuit is separated from the MCU internal peripheral circuit in the microcomputer. Accordingly, even if the mi- crocomputer runs away, the analog comparator is still in operation. For this reason, the analog comparator can be used for safety circuit design. Fig. 47. Block diagram of Analog comparator P63/CMP IN /AN8 P64/CMP REF /AN9 CMP OUT CMPV CC AV SS

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER (2) Watchdog timer H count source selection bit operation Bit 7 of the watchdog timer control register (address 0017 16) permits selecting a watchdog timer H count source. When this bit is set to "0", the count source becomes the underflow signal of watchdog timer L. The detection time is set then to f(X IN)=131.072 ms at 8 MHz frequency and f(XCIN)=32.768 s at 32 kHz frequency. When this bit is set to "1", the count source becomes the signal divided by 16 for f(X IN) (or f(XCIN)). The detection time in this case is set to f(XIN)=512 µs at 8 MHz frequency and f(XCIN)=128 ms at 32 KHz frequency. This bit is cleared to "0" after resetting. (3) Operation of STP instruction disable bit Bit 6 of the watchdog timer control register (address 0017 16) permits disabling the STP instruction when the watchdog timer is in opera- tion. When this bit is "0", the STP instruction is enabled. When this bit is "1", the STP instruction is disabled. Once the STP instruction is executed, an internal resetting takes place. When this bit is set to "1", it cannot be rewritten to "0" by program. This bit is cleared to "0" after resetting. Watchdog Timer The watchdog timer gives a mean of returning to the reset status when a program cannot run on a normal loop (for example, because of a software run-away). The watchdog timer consists of an 8-bit watchdog timer L and a 8-bit watchdog timer H. l Standard operation of watchdog timer When any data is not written into the watchdog timer control register (address 0017 16) after resetting, the watchdog timer is in the stop state. The watchdog timer starts to count down by writing an optional value into the watchdog timer control register (address 0017 16) and an internal resetting takes place at an underflow of the watchdog timer H. Accordingly, programming is usually performed so that writing to the watchdog timer control register (address 0017 16) may be started before an underflow. When the watchdog timer control register (address 0017 16) is read, the values of the 6 high-order bits of the watchdog timer H, STP instruction disable bit, and watchdog timer H count source selection bit are read. (1) Initial value of watchdog timer At reset or writing to the watchdog timer control register (address 0017 16), each watchdog timer H and L is set to "FF16." XIN Data bus XCIN "10" "00" "01" Main clock division ratio selection bits (Note) "0" "1"1/16 Watchdog timer H count source selection bit Reset circuit STP instruction disable bit Watchdog timer H (8) “FF16” is set when watchdog timer control register is written to. Internal resetRESET Watchdog timer L (8) Note: Either high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of CPU mode register. STP instruction “FF16” is set when watchdog timer control register is written to. Fig. 48. Block diagram of Watchdog timer STP instruction disable bit 0: STP instruction enabled 1: STP instruction disabled Watchdog timer H count source selection bit 0: Watchdog timer L underflow 1: f(X IN)/16 or f(XCIN)/16 Watchdog timer H (for read-out of high-order 6 bit) Watchdog timer control register (WDTCON : address 0017 16) Fig. 49. Structure of Watchdog timer control register

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Port P2P3 control register (P2P3C : address 0015 16) P34 clock output control bit 0: I/O port 1: Clock output Output clock frequency selection bits 000: φ 001: f(X CIN) 010: "L" fixed for output 011: "L" fixed for output 100: f(X IN) (f(XCIN) in low-speed mode) 101: f(XIN)/2 (f(XCIN)/2 in low-speed mode) 110: f(XIN)/4 (f(XCIN)/4 in low-speed mode) 111: f(XIN)/16 (f(XCIN)/16 in low-speed mode) Not used (return "0" when read) P2•P3 2 input level selection bit 0: CMOS level input 1: TTL level input Clock output function The internal clock φ can be output from I/O port P34. Control of I/O ports and clock output function can be performed by port P2P3 control register (address 0015 16). (1) I/O ports or clock output function selection The P3 4 clock output control bit (b0) of port P2P3 control register selects the I/O port or clock output function. When clock output function is selected, the clock is output regardless of the port P3 direction register settings. Directly after bit 0 is written to, the port or clock output is switched synchronous to a falling edge of clock frequency selected by the output clock frequency selection bit. When memory expansion mode or microprocessor mode is selected in CPU mode register (b1, b0), clock output is selected on regardless of P3 4 clock output control bit settings or port P34 direction register settings. (2) Selection of output clock frequency The output clock frequency selection bits (b3, b2, b1) of port P2P3 control register select the output clock frequency. The output waveform when f(X IN) or f(XCIN) is selected, depends on X IN or XCIN input waveform however; all other output waveform settings have a duty cycle of 50%. Note: Either high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of CPU mode register. P34 port latch P34/CKOUT /ø "110" "100" Output clock frequency selection bits X IN "101" "111" "000" XCIN "001" Main clock division ratio selection bits (Note) Low-speed mode P34 direction register P34 clock output control bit Microprocessor mode/memory expansion mode "010" "011" High-speed or middle-speed mode Fig. 51. Block diagram of Clock output function Fig. 50. Structure of Port P2P3 control register

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Reset Circuit To reset the microcomputer, RESET pin should be held at an "L" level for 2 µs or more. Then the RESET pin is returned to an "H" level (the power source voltage should be between 2.7 V and 5.5 V, and the oscillation should be stable), reset is released. After the reset is completed, the program starts from the address contained in address FFFD 16 (high-order byte) and address FFFC16 (low-order byte). Make sure that the reset input voltage is less than 0.54 V for VCC of 2.7 V. (Note) 0.2VCC Poweron VCCRESET VCCRESET Power source voltage detection circuit Power source voltage Reset input voltage Note : Reset release voltage ; Vcc=2.7 V RESET Internal reset Data φ Address SYNC XIN: 10.5 to 18.5 clock cycles XIN ? ? ?? ? FFFC FFFD AD H ,L 1: The frequency relation of f(XIN) and f(φ) is f(XIN)=8 • f(φ). 2: The question marks (?) indicate an undefined state that depends on the previous state. Reset address from the vector table. Notes Fig. 52. Reset circuit example Fig. 53. Reset sequence

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 0016 0016 0016 0016 0016 FF16 FF16 FF16 FF16 0016 0016 0016 0016 0016 0016 FFFC 16 contents FF16002616 002716 002816 002916 002A16 002B16 002C 16 002D 16 002E16 002F16 003016 003116 003216 003316 003416 003616 003716 003816 003916 003A16 003B16 003C 16 003D 16 003E16 003F16 (PS) (PCH ) (PCL) * The initial values depend on level of port CNVSS. X: Not fixed Since the initial values for other than above mentioned registers and RAM contents are indefinite at reset, they must be set. Address Register contents Address Register contents 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 FF16 FF16 FF16 FF16 FF16 0116 0016000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C 16 000D 16 000E16 000F16 001016 001116 001416 001516 001616 001716 001916 001A16 001B16 001D 16 001E16 002016 002116 002216 002316 002416 002516 Timer X (low-order) Timer 2 Port P0 Port P0 direction register Port P1 Port P1 direction register Port P2 Port P2 direction register Port P3 Port P3 direction register Port P4 Port P4 direction register Port P5 Port P5 direction register Port P6 Port P6 direction register Port P7 Port P7 direction register Port P8 Port P8 direction register Timer XY control register Port P2P3 control register Pull-up control register Watchdog timer control register Serial I/O1 status register Serial I/O1 control register UART control register Serial I/O2 control register 1 Serial I/O2 control register 2 Timer X (high-order) Timer Y (low-order) Timer Y (high-order) Timer 1 (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) (15) (16) (17) (18) (19) (20) (21) (22) (23) (24) (25) (26) (27) (28) (29) (30) (31) (32) (33) (34) (35) (36) (37) (38) (39) (40) (41) (42) (43) (44) (45) (46) (47) (48) (49) (50) (51) (52) (53) (54) (55) (56) (57) (58) (59) (60)Program counter Timer 3 Interrupt edge selection register Timer X mode register Timer Y mode register Timer 123 mode register Real time port register 0—7 Real time port control register 0 Real time port control register 1 R/W pointer Output pointer Real time port control register 2 R/W pointer Output pointer Real time port control register 3 Timer A (low-order) Timer A (high-order) Timer B (low-order) Timer B (high-order) D-A control register A-D control register D-A1 conversion register D-A2 conversion register D-A3 conversion register D-A4 conversion register CPU mode register Interrupt request register 1 Interrupt request register 2 Interrupt control register 1 Interrupt control register 2 Processor status register 1 000 0 0016 111 0016 0016 0016 FFFD 16 contents 51 5 5 5 5 5 5 010010 0 * 000100 0 0 111 111 111 1 000 0 100100 0 0 000000 1 1 00000 0 0* 001111 1 1 100000 0 0 111000 0 0 000001 1 1 Fig. 54. Internal status at reset

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER ("0") before executing the STP instruction. Oscillator restarts when an external interrupt is received, but the internal clock φ is not sup- plied to the CPU (remains at "H") until timer 2 underflows. This al- lows time for the clock circuit oscillation to stabilize. The internal clock φ is supplied for the first time, when timer 2 underflows. Therefore make sure not to set the timer 2/INT3 interrupt request bit to "1" be- fore the STP instruction stops the oscillator. When the oscillator is restarted by reset apply "L" level to port RESET until the oscillation is stable since a wait time will not be generated. (2) Wait mode If the WIT instruction is executed, the internal clock φ stops at an "H" level. The states of XIN and XCIN are the same as the state before executing the WIT instruction. The internal clock restarts at reset or when an interrupt is received. Since the oscillator does not stop, nor- mal operation can be started immediately after the clock is restarted. Clock Generating Circuit The 3807 group has two built-in oscillation circuits. An oscillation circuit can be formed by connecting a resonator between X IN and XOUT (XCIN and XCOUT ). Use the circuit constants in accordance with the resonator manufacturer's recommended values. No external resistor is needed between X IN and XOUT since a feed-back resistor exists on-chip. However, an external feed-back resistor is needed between X CIN and XCOUT . Immediately after poweron, only the XIN oscillation circuit starts oscillating, and XCIN and XCOUT pins function as I/O ports. l Frequency control (1) Middle-speed mode The internal clock φ is the frequency of XIN divided by 8. After reset, this mode is selected. (2) High-speed mode The internal clock φ is half the frequency of XIN. (3) Low-speed mode The internal clock φ is half the frequency of XCIN. n Note If you switch the mode between middle/high-speed and low-speed, stabilize both X IN and XCIN oscillations. The sufficient time is required for the sub clock to stabilize, especially immediately after poweron and at returning from stop mode. When switching the mode between middle/high-speed and low-speed, set the frequency on condition that f(X IN) > 3f(XCIN). (4) Low power consumption mode The low power consumption operation can be realized by stopping the main clock X IN in low-speed mode. To stop the main clock, set bit 5 of the CPU mode register to "1." When the main clock XIN is re- started (by setting the main clock stop bit to "0"), set enough time for oscillation to stabilize. By clearing furthermore the X COUT drivability selection bit (b3) of CPU mode register to "0", low power consumption operation of less than 55 µ A (V CC =3 V, XCIN=32 kHz) can be realized by reducing the drivability between XCIN and XCOUT . At reset or during STP instruc- tion execution this bit is set to "1" and a reduced drivability that has an easy oscillation start is set. The sub-clock X CIN-XCOUT oscillating circuit can not directly input clocks that are generated externally. Ac- cordingly, make sure to cause an external resonator to oscillate. l Oscillation control (1) Stop mode If the STP instruction is executed, the internal clock φ stops at an "H" level, and XIN and XCIN oscillators stop. Timer 1 is set to "FF16" and timer 2 is set to "0116." Either XIN or XCIN divided by 16 is input to timer 1 as count source, and the output of timer 1 is connected to timer 2. The bits of the timer 123 mode register except timer 3 count source selection bit (b4) are cleared to "0". Set the timer 2/INT 3 interrupt source bit to "1" and timer 1/INT2 as well as timer 2/INT3 interrupt enable bit to disabled XCIN XCOUT XIN XOUT C IN C OUTC CIN C COUT Rf Rd XIN XOUT External oscillation circuit VCC VSS open C CIN C COUT Rf Rd XCIN XCOUT Fig. 56. External clock input circuit Fig. 55. Ceramic resonator circuit

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Fig. 57. System clock generating circuit block diagram (Single-chip mode) WIT instruction STP instruction Timing φ (internal clock) S R Q STP instruction S R Q Main clock stop bit S R Q 1/2 1/4 XIN XOUT XCOUTXCIN Interrupt request Reset Interrupt disable flag l Port XC switch bit "1" "0" "10" "01" Timer 1 count source selection bits Low-speed mode High-speed or middle-speed mode Middle-speed mode High-speed or low-speed mode Main clock division ratio selection bits (note) Note: Either high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of CPU mode register. When low-speed mode is selected, set port Xc switch bit (b4) to “1”. "1" "0" Timer 1 Timer 2 Timer 2 count source selection bit "00" Main clock division ratio selection bits (note)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER CM 4 : Port Xc switch bit 0 : I/O port function (stop oscillating) 1 : XCIN-XCOUT oscillating function CM 5 : Main clock (XIN- XOUT ) stop bit 0 : Operating 1 : Stopped CM 7,CM 6 : Main clock division ratio selection bit b7 b6 0 0 : f(XIN)/2 ( High-speed mode) 0 1 : f(XIN)/8 (Middle-speed mode) 1 0 : f(XCIN)/2 (Low-speed mode) 1 1 : Not available Note ResetCM 4 "1 " "0 " CM 4"0" "1 CM 6"1" "0 CM "1" "0 CM "1" "0 CM 7 "1 " "0 " CM 4 "1 " "0 " CM 5 "1 " "0 " CM 6 "1 " "0 " CM 6 "1 " "0 " CPU mode register (CPUM : address 003B16) b7 b4 CM 7"0" "1 CM 6"1" "0 CM 7=0 CM 6=1 CM 5=0(8MHz oscillating) CM 4=0(32kHz stopped) 1:Switch the mode by the allows shown between the mode blocks. (Do not switch between the mode directly without an allow . ) 2:The all modes can be switched to the stop mode or the wait mode and return to the source mode when the stop mode or the wait mode is ended. 3:Timer operates in the wait mode. 4:When the stop mode is ended, a delay of approximately 1 ms occurs by Timer 1 and Timer 2 in middle/high-speen mode. 5:When the stop mode is ended, a delay of approximately 0.25 s occurs by Timer 1 and Timer 2 in low-speed mode. 6:Wait until oscillation stabilizes after oscillating the main clock X IN before the switching from the low-speed mode to middle/high- speed mode. 7:The example assumes that 8 MHz is being applied to the X IN pin and 32 kHz to the XCIN pin. φ indicates the internal clock. Middle-speed mode (f( )=1 MHz) CM 7=0 CM 6=1 CM 5=0(8MHz oscillating) CM 4=1(32kHz oscillating) Middle-speed mode (f( )=1MHz) CM 7=0 CM 6=0 CM 5=0(8MHz oscillating) CM 4=0(32kHz stopped) High-speed mode (f( )=4MHz) CM 7=0 CM 6=0 CM 5=0(8MHz oscillating) CM 4=1(32kHz oscillating) High-speed mode (f( )=4MHz) CM 7=1 CM 6=0 CM 5=0(8MHz oscillating) CM 4=1(32kHz oscillating) Low-speed mode (f( )=16 kHz) CM 7=1 CM 6=0 CM 5=1(8MHz stopped) CM 4=1(32kHz oscillating) Low-speed mode (f( )=16 kHz) Fig. 58. State transitions of system clock

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Processor Mode Single-chip mode, memory expansion mode, and microprocessor mode can be selected by changing the contents of the processor mode bits (CM 0 and CM1 : b1 and b0 of address 003B16). In memory expansion mode and microprocessor mode, memory can be ex- panded externally through ports P0 to P3. In these modes, ports P0 to P3 lose their I/O port functions and become bus pins. Table. 7. Port functions in memory expansion mode and microprocessor mode Port Name Function Port P0 Outputs 8-bits low-order byte of address. Port P1 Outputs 8-bits high-order byte of address. Port P2 Operates as I/O pins for data D7 to D0 (including instruction code) Port P3 P3 0 and P31 function only as output pins (except that the port latch cannot be read). ____ P32 is the ONW input pin. P33 is the RESTOUT output pin. (Note) P34 is the φ output pin. P35 is the SYNC output pin. P36 is the WR output pin, and P37 is the RD output pin. Note : If CNVSS is connected to VSS , the microcomputer goes to single-chip mode after a reset, so this pin cannot be used as the RESET OUT output pin. (1) Single-chip mode Select this mode by resetting the microcomputer with CNV SS connected to VSS . (2) Memory expansion mode Select this mode by setting the processor mode bits (b1, b0) to "01" in software with CNV SS connected to VSS . This mode enables external memory expansion while maintaining the validity of the internal ROM. However, some I/O devices will not support the memory expansion mode. Internal ROM will take precedence over external memory if addresses conflict. (3) Microprocessor mode Select this mode by resetting the microcomputer with CNV SS con- nected to VCC , or by setting the processor mode bits to "10" in soft- ware with CNVSS connected to VSS . In microprocessor mode, the internal ROM is no longer valid and external memory must be used. Fig. 59. Memory maps in various processor modes Fig. 60. Structure of CPU mode register 000016 004016 084016 000816 000016 084016 YYYY 16 FFFF 16 000816 004016 FFFF 16 internal RAM reserved area internal ROM Memory expansion mode The shaded area are external memory area. SFR area YYYY 16 indicates the first address of internal ROM. SFR area Microprocessor mode internal RAM reserved area CPU mode register (CPUM : address 003B 16) Processor mode bits (CM1, CM0) b1 b0 0 0: Single-chip mode 0 1: Memory expansion mode 1 0: Microprocessor mode 1 1: Not available Stack page selection bit 0: 0 page 1: 1 page

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Bus control at memory expansion_____ The 3807 group has a built-in ONW function to facilitate access to external (expanded) memory and I/O devices in memory expansion mode or microprocessor mode. If an "L" level signal is input to port P32/ONW when the CPU is in a read or write state, the corresponding read or write cycle is extended___ ___ by one cycle of φ. During this extended period, the RD or WR signal remains at "L". This extension function is valid only for writing to and reading from addresses 0000 16 to 000716 and 084016 to FFFF16, and only read and write cycles are extended. Fig. 61. ONW function timing φ RD WR ONW * * Read cycle Write cycleDummy cycle Write cycle Read cycle Dummy cycle AD 15—AD 0 * Period during which ONW input signal is received During this period, the ONW signal must be fixed at either "H" or "L". At all other times, the input level of the ONW signal has no affect on operations. The bus cycles is not extended for an address in the area 0008 16 to 083F16, regardless of whether the ONW signal is received.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER NOTES ON PROGRAMMING Processor Status Register The contents of the processor status register (PS) after a reset are undefined, except for the interrupt disable flag (I) which is "1." After a reset, initialize flags which affect program execution. In particular, it is essential to initialize the index X mode (T) and the decimal mode (D) flags because of their effect on calculations. Interrupts The contents of the interrupt request bits do not change immediately after they have been written. After writing to an interrupt request reg- ister, execute at least one instruction before performing a BBC or BBS instruction. Decimal Calculations

• To calculate in decimal notation, set the decimal mode flag (D) to "1", then execute an ADC or SBC instruction. Only the ADC and SBC instructions yield proper decimal results. After executing an ADC or SBC instruction, execute at least one instruction before ex- ecuting a SEC, CLC, or CLD instruction.
• In decimal mode, the values of the negative (N), overflow (V), and zero (Z) flags are invalid. Timers If a value n (between 0 and 255) is written to a timer latch, the fre- quency division ratio is 1/(n+1). Multiplication and Division Instructions
• The index X mode (T) and the decimal mode (D) flags do not affect the MUL and DIV instruction.
• The execution of these instructions does not change the contents of the processor status register. Ports The contents of the port direction registers cannot be read. The following cannot be used:
• The data transfer instruction (LDA, etc.)
• The operation instruction when the index X mode flag (T) is "1"
• The addressing mode which uses the value of a direction register as an index
• The bit-test instruction (BBC or BBS, etc.) to a direction register
• The read-modify-write instructions (ROR, CLB, or SEB, etc.) to a direction register. Use instructions such as LDM and STA, etc., to set the port direction registers. Serial I/O In clock synchronous serial I/O, if the receive side is using an external clock and it is to output the S RDY1 signal, set the transmit enable bit, the receive enable bit, and the SRDY1 output enable bit to "1." Serial I/O1 continues to output the final bit from the T XD pin after transmission is completed. SOUT2 pin for serial I/O2 goes to high im- pedance after transfer is completed. When in serial I/O1 (clock-synchronous mode) or in serial I/O2 an external clock is used as synchronous clock, write transmission data to both the transmit buffer register and serial I/O2 register, during transfer clock is “H.” A-D Converter The comparator uses internal capacitors whose charge will be lost if the clock frequency is too low. Therefore, make sure that f(X IN) is at least on 500 kHz during an A-D conversion. (When the ONW pin has been set to "L", the A-D conver- sion will take twice as long to match the longer bus cycle, and so f(X IN) must be at least 1 MHz.) Do not execute the STP or WIT instruction during an A-D conver- sion. D-A Converter The accuracy of the D-A converter becomes rapidly poor under the V CC = 4.0 V or less condition; a supply voltage of VCC ≥ 4.0 V is recommended. When a D-A converter is not used, set all values of D-Ai conversion registers (i=1 to 4) to "00 16." Instruction Execution Time The instruction execution time is obtained by multiplying the frequency of the internal clock φ by the number of cycles needed to execute an instruction. The number of cycles required to execute an instruction is shown in the list of machine instructions. The frequency of the internal clock φ is half of the XIN frequency in high-speed mode. When the ONW function is used in modes other than single-chip mode, the frequency of the internal clock φ may be one fourth of the XIN frequency.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER NOTES ON USAGE Handling of Source Pins In order to avoid a latch-up occurrence, connect a capacitor suitable for high frequencies as bypass capacitor between power source pin CC pin) and GND pin (Vss pin) and between power source pin (VCC pin) and analog power source input pin (AVSS pin). Besides, connect the capacitor to as close as possible. For bypass capacitor which should not be located too far from the pins to be connected, a ce- ramic capacitor of 0.01 µF—0.1 µ F is recommended. P34 clock output function In the case of using an I/O port P34 as a clock output function, note the following : when an output clock frequency is changed during outputting a clock, the port may feed a noise having a shorter pulse width than the standard at the switch timing. Besides, it also may happen at the timing for switching the low-speed mode to the middle/ high-speed mode. Timer X and timer Y In the pulse period measurement mode or the pulse width measure- ment mode for timers X and Y, set the "L" or "H" pulse width of input signal from CNTR 0/CNTR 1 pin to 2 cycles or more of a timer count source. EPROM version/One Time PROM version The CNV SS pin is connected to the internal memory circuit block by a low-ohmic resistance, since it has the multiplexed function to be a programmable power source pin (V PP pin) as well. To improve the noise reduction, connect a track between CNVSS pin and VSS pin or VCC pin with 1 to 10 kΩ resistance. The mask ROM version track of port CNVSS has no operational inter- ference even if it is connected via a resistor.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER DATA REQUIRED FOR MASK ORDERS The following are necessary when ordering a mask ROM produc- tion: (1) Mask ROM Order Confirmation Form (2) Mark Specification Form (3) Data to be written to ROM, in EPROM form (three identical cop- ies) ROM PROGRAMMING METHOD The built-in PROM of the blank One Time PROM version and built-in EPROM version can be read or programmed with a general purpose PROM programmer using a special programming adapter. Set the address of PROM programmer in the user ROM area. Table. 8. Special programming adapter Package Name of Programming Adapter 80P6N-A PCA4738F-80A 80D0 PCA4738L-80A The PROM of the blank One Time PROM version is not tested or screened in the assembly process and following processes. To en- sure proper operation after programming, the procedure shown in Figure 64 is recommended to verify programming. Fig. 62. Programming and testing of One Time PROM version Programming with PROM programmer Screening (Caution) (150°C for 40 hours) Verification with PROM programmer Functional check in target device The screening temperature is far higher than the storage temperature. Never expose to 150 °C exceeding 100 hours. Caution :

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

ELECTRICAL CHARACTERISTICS

Table 9 Absolute maximum ratings ABSOLUTE MAXIMUM RATINGS ConditionsSymbol Ratings UnitParameter VCC CMPV CC VI VI VI VI VI VID VO VO Pd Topr Tstg Power source voltage Analog comparator power source voltage Input voltage P0 0–P07, P10–P17, P20–P2 7, P30–P37, P40–P47, P50–P57, P60–P65, P70–P77, P80–P87, ADV REF Input voltage RESET, XIN Input voltage CNV SS (ROM version) Input voltage CNV SS (PROM version) In-phase input voltage CMP IN, CMPREF Differential input voltage |CMPIN–CMP REF | Output voltage P0 0–P07, P10–P17, P20–P2 7, P30–P37, P40–P47, P50–P57, P60–P62, P65, P70–P7 7, P80–P87, XOUT Output voltage CMP OUT Power dissipation Operating temperature Storage temperature –0.3 to 7.0 –0.3 to 7.0 –0.3 to V CC +0.3 –0.3 to VCC +0.3 –0.3 to 7 –0.3 to 13 –0.3 to CMPVCC +0.3 CMPV CC –0.3 to VCC +0.3 –0.3 to CMPVCC +0.3 500 –20 to 85 –40 to 125 V V V V V V V V V V mW Ta = 25°C All voltages are based on V SS . Output transistors are cut off.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Table 10 Recommended operating conditions (1) (Vcc = 2.7 to 5.5 V, Ta = – 20 to 85 °C, unless otherwise noted) RECOMMENDED OPERATING CONDITIONS V V V V V V V V V V V V V V V V V 5.5 5.5 V CC VCC VCC VCC VCC VCC VCC 0.2VCC 0.2VCC 0.8 0.2VCC 0.16VCC 2.7 4.0 2.0 2.7 AV SS 0.8VCC 0.8VCC 2.0 0.8VCC Min. Typ. Max. Symbol Parameter Unit VCC VSS ADV REF DAV REF CMPV CC AV SS VIA VIH VIH VIH VIH VIL VIL VIL VIL VIL Power source voltage Power source voltage A-D comparator reference voltage D-A comparator reference voltage Analog comparator power source voltage Analog power source voltage A-D comparator input voltage AN 0—AN 12 “H” input voltage P0 0—P0 7, P10—P1 7, P30, P31, P33—P3 7, P40—P4 7, P50—P5 7, P60—P6 5, P70—P7 7, P80—P8 7 “H” input voltage (CMOS input level selected) P20—P2 7, P32 “H” input voltage (TTL input level selected) P20—P2 7, P32 (Note) “H” input voltage RESET, XIN, CNVSS “L” input voltage P0 0—P0 7, P10—P1 7, P30, P31, P33—P3 7, P40—P4 7, P50—P5 7, P60—P6 5, P70—P7 7, P80—P8 7 “L” input voltage (CMOS input level selected) P20—P2 7, P32 “L” input voltage (TTL input level selected) P20—P2 7, P32 (Note) “L” input voltage RESET, CNV SS “L” input voltage X IN f(XIN) 4.1MHz f(XIN) = 8MHz 5.0 5.0 V CC Limits Note:When Vcc is 4.0 to 5.5 V. “H” total peak output current (Note) P00–P07, P10–P17, P20–P2 7, P30–P37, P80–P87 “H” total peak output current (Note) P40–P47, P50–P57, P60–P6 2, P65, CMP OUT , P70–P7 7 “L” total peak output current (Note) P00–P07, P10–P17, P20–P2 3, P30–P37, P80–P87 “L” total peak output current (Note) 4–P27 “L” total peak output current (Note) P40–P47, P50–P57, P60–P6 2, P65, CMP OUT , P70–P7 7 “H” total average output current (Note) P00–P07, P10–P17, P20–P2 7, P30–P37, P80–P87 “H” total average output current (Note) P40–P47, P50–P57, P60–P6 2, P65, CMP OUT , P70–P7 7 “L” total average output current (Note) P00–P07, P10–P17, P20–P2 3, P30–P37, P80–P87 “L” total average output current (Note) 4–P27 “L” total average output current (Note) P40–P47, P50–P57, P60–P6 2, P65, CMP OUT , P70–P7 7 Min. Typ. Max. Symbol Parameter Limits Unit ∑ IOH(peak) ∑ IOH(peak) ∑ IOL(peak) ∑ IOL(peak) ∑ IOL(peak) ∑ IOH(avg) ∑ IOH(avg) ∑ IOL(avg) ∑ IOL(avg) ∑ IOL(avg) in single chip mode in memory expansion mode and microprocessor mode –80 –80 –40 –40 mA mA mA mA mA mA mA mA mA mA mA mA in single chip mode in memory expansion mode and microprocessor mode Table 11 Recommended operating conditions (2) (Vcc = 2.7 to 5.5 V, Ta = – 20 to 85 °C, unless otherwise noted) Note:The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured over 100ms. The total peak current is the peak value of all the currents.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Table 12 Recommended operating conditions (3) (Vcc = 2.7 to 5.5 V, Ta = – 20 to 85 °C, unless otherwise noted) “H” peak output current (Note 1) P00–P07, P10–P17, P20–P27, P30–P3 7, P40–P47, P50–P57, P60–P6 2, P65, CMPOUT , P70–P77, P80–P8 7 “L” peak output current (Note 1) P00–P07, P10–P17, P20–P23, P30–P3 7, P40–P47, P50–P57, P60–P6 2, P65, CMPOUT , P70–P77, P80–P8 7 “L” peak output current (Note 1) 4–P27 “H” average output current (Note 2) P00–P07, P10–P17, P20–P27, P30–P3 7, P40–P47, P50–P57, P60–P6 2, P65, CMPOUT , P70–P77, P80–P8 7 “L” average output current (Note 2) P00–P07, P10–P17, P20–P23, P30–P3 7, P40–P47, P50–P57, P60–P6 2, P65, CMPOUT , P70–P77, P80–P8 7 “L” average output current (Note 2) 4–P27 Main clock input oscillation frequency (Note 3) Symbol Parameter Limits Unit IOH(peak) IOL(peak) IOL(peak) IOH(avg) IOL(avg) IOL(avg) f(XIN) f(XCIN) in single chip mode in memory expansion mode and microprocessor mode 32.768 mA mA mA mA mA mA mA mA MHz MHz MHz MHz MHz kHz –10 CC –4 CC –4 5032.768Sub-clock input oscillation frequency (Note 3, 4) in single chip mode in memory expansion mode and microprocessor mode High-speed mode 4.0V V CC 5.5V High-speed mode 2.7V V CC 4.0V Middle-speed mode 4.0V V CC 5.5V Middle-speed mode (Note 5) 2.7V V CC 4.0V Middle-speed mode (Note 5) 2.7V V CC 4.0V Max.Typ.Min. Note1: The peak output current is the peak current flowing in each port. 2:The average output current IOL (avg), IOH (avg) in an average value measured over 100ms. 3:When the oscillation frequency has a duty cyde of 50%. 4:When using the microcomputer in low-speed mode, set the sub-clock input oscillation frequency on condition that f(XCIN) f(XIN)/ 5:When using the timer X/Y, timer A/B (real time output port), timer 1/2/3, serial I/O1, serial I/O2, and A-D converter, set the main clock input oscillation frequency to the max. 3 Vcc–4 (MHz).

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER V V V V V V V µA µA µA µA µA µA mA V 2.0 0.4 5.0 5.0 –5.0 –5.0 5.5 Min. Typ. Max. Symbol Parameter Limits Unit “H” output voltage P00–P07, P10–P17, P20–P27, P30–P37, P40–P47, P50–P57, P60–P62, P65, P70–P7 7, P80–P87, CMPOUT (Note 1) “L” output voltage P00–P07, P10–P17, P20–P27, P30–P37, P40–P47, P50–P57, P60–P62, P65, P70–P7 7, P80–P87, CMPOUT Hysteresis P4 2, P43, P51–P55, P73 (Note 2), CNTR 0, CNTR1, INT0–INT4, ADT Hysteresis R XD, SCLK1 , SIN2, SCLK2 Hysteresis RESET “H” input current P00–P07, P10–P17, P20–P27, P30–P37, P40–P47, P50–P57, P60–P65, P70–P77, P80–P8 7 “H” input current RESET, CNV SS “H” input current XIN “L” input current P00–P07, P10–P17, P20–P27, P30–P37, P40–P47, P50–P57, P60–P65, P70–P77, P80–P8 7 “L” input current RESET, CNV SS “L” input current XIN “L” input current P00–P07, P10–P17, P20–P2 7 RAM hold voltage VOH VOL VT+–VT– VT+–VT– VT+–VT– IIH IIH IIH IIL IIL IIL IIL VRAM IOH = –10mA VCC = 4.0 to 5.5V IOH = –1.0mA VCC = 2.7 to 5.5V IOL = 10mA VCC = 4.0 to 5.5V IOL = 1.6mA VCC = 2.7 to 5.5V VI = VCC (Pin floating. Pull-up transistors “off”) V I = VCC VI = VCC VI = VSS (Pin floating. Pull-up transistors “off”) V I = VSS VI = VSS Pull-up transistors “on” V I = VSS When clock stopped Test conditions 0.4 0.5 0.5 –0.2 V CC –2.0 VCC –1.0 2.0 Note1: P45 is measured when the P45/TX D P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”. P71, and P12 are measured when the P71/SOUT2 and P72/SCLK2 P-channel output disable bit of the serial I/O2 control register 1 (bit 7 of address 001D16). 2:P73 is measured when the AD external trigger valid bit of the A–D control register (bit 6 of address 003416) is “1”. Table 13 Electrical characteristics (1) (Vcc = 2.7 to 5.5 V, Vss = 0 V, Ta = – 20 to 85 °C, unless otherwise noted)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Min. Typ. Max. Symbol Parameter Limits UnitTest conditions ICC High-speed mode f(X IN) = 8MHz f(XCIN) = 32.768kHz Output transistors “off” High-speed mode f(X IN) = 8MHz (in WIT state) f(XCIN) = 32.768kHz Output transistors “off” Low-speed mode f(X IN) = stopped f(XCIN) = 32.768kHz Low-power dissipation mode (CM3 = 0) Output transistors “off” Low-speed mode f(X IN) = stopped f(XCIN) = 32.768kHz (in WIT state) Low-power dissipation mode (CM3 = 0) Output transistors “off” Low-speed mode (V CC = 3V) f(XIN) = stopped f(XCIN) = 32.768kHz Low-power dissipation mode (CM3 = 0) Output transistors “off” Low-speed mode (V CC = 3V) f(XIN) = stopped f(XCIN) = 32.768kHz (in WIT state) Low-power dissipation mode (CM3 = 0) Output transistors “off” Middle-speed mode f(X IN) = 8MHz f(XCIN) = stopped Output transistors “off” Middle-speed mode f(X IN) = 8MHz (in WIT state) f(XCIN) = stopped Output transistors “off” Increment when A-D conversion is executed f(X IN) = 8MHz All oscillation stopped (in STP state) Output transistors “off” Power source current CMPI CC Analog comparator Power source current Ta = 25°C Ta = 85°C 6.8 1.6 5.0 4.0 1.5 800 0.1 200 200 10.0 7.0 1.0 500 mA mA µA µA µ A µA mA mA µA µA µA µA Table 14 Electrical characteristics (2) (Vcc = 2.7 to 5.5 V, Vss = 0 V, Ta = – 20 to 85 °C, unless otherwise noted)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER mV µ A µ A V ns CMPV CC = 5.0V CMP REF = 2.5V, Rs = 0Ω CMPV CC = 5.0V CMP REF = 2.5V Min. Typ. Max. Symbol Parameter Limits UnitTest conditions t CONV RLADDER IADVREF II(AD) Resolution Absolute accuracy (excluding quantization error) Conversion time Ladder resistor Reference power source input current A-D port input current VCC = ADVREF = 5.0V ADV REF = 5.0V ADVREF “ on” ADV REF “ off” 150 100 200 5.0 Bits LSB tc( kΩ µ A µ A µ A Min. Typ. Max.Symbol Parameter Limits UnitTest conditions t su Ro IDAVREF Resolution Absolute accuracy Setting time Output resistor Reference power source input current (Note) V CC = 4.0 to 5.5V VCC = 2.7 to 4.0V 1.0 2.5 3.2 Bits µs kΩ mA 1 2.5 Note: Using one D-A converter, with the value in the D-A conversion register of the other D-A converter being “0016”. Min. Typ. Max. Symbol Parameter Limits UnitTest conditions VIO IB IIO VICM AV tPD Input offset voltage Input bias current Input offset current In-phase input voltage range Voltage gain Response time 1.2 CMPV CC –0.5 2500 Table 15 A-D converter characteristics (Vcc = 2.7 to 5.5 V, Vss = AVss = 0 V, ADVREF = 2.0 V to Vcc, Ta = – 20 to 85 °C, unless otherwise noted) Table 16 D-A converter characteristics (Vcc = 2.7 to 5.5 V, Vss = AVss = 0 V, DAVREF = 2.7 V to Vcc, Ta = – 20 to 85 °C, unless otherwise noted) Table 17 Analog comparator characteristics (Vcc = 2.7 to 5.5 V, Vss = AVss = 0 V, CMPVcc = 2.7 V to Vcc, Ta = – 20 to 85 °C, unless otherwise noted) A-D CONVERTER CHARACTERISTICS D-A CONVERTER CHARACTERISTICS ANALOG COMPARATOR CHARACTERISTICS

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER TIMING REQUIREMENTS Table 18 Timing requirements (1) (Vcc = 4.0 to 5.5 V, Vss = 0 V, Ta = – 20 to 85 °C, unless otherwise noted) Min. Typ. Max. Symbol Parameter Limits Unit tW (RESET) tC (XIN) tWH (XIN) tWL (XIN) tC (CNTR) tWH (CNTR) tWL (CNTR) tWH (INT) tWL (INT) tC (SCLK1 ) tWH (SCLK1 ) tWL (SCLK1 ) tsu(RX D–S CLK1 ) th(SCLK1 –R XD) tC (SCLK2 ) tWH (SCLK2 ) tWL (SCLK2 ) tsu(SIN2–SCLK2 ) th(SCLK2 –SIN2) 125 200 800 370 370 220 100 1000 400 400 200 200 s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Reset input “L” pulse width External clock input cycle time External clock input “H” pulse width External clock input “L” pulse width CNTR 0, CNTR1 input cycle time CNTR 0, CNTR1 input “H” pulse width CNTR 0, CNTR1 input “L” pulse width INT0 to INT4 input “H” pulse width INT0 to INT4 input “L” pulse width Serial I/O1 clock input cycle time (Note) Serial I/O1 clock input “H” pulse width (Note) Serial I/O1 clock input “L” pulse width (Note) Serial I/O1 clock input set up time Serial I/O1 clock input hold time Serial I/O2 clock input cycle time Serial I/O2 clock input “H” pulse width Serial I/O2 clock input “L” pulse width Serial I/O2 clock input set up time Serial I/O2 clock input hold time Note: When bit 6 of address 001A 16 is “1” (clock synchronous). Divide this value by four when bit 6 of address 001A16 is “0” (UART). Max. Symbol Parameter Unit Min. Typ. tW (RESET) tC (XIN) tWH (XIN) tWL (XIN) tC (CNTR) tWH (CNTR) tWL (CNTR) tWH (INT) tWL (INT) tC (SCLK1 ) tWH (SCLK1 ) tWL (SCLK1 ) tsu(RX D–S CLK1 ) th(SCLK1 –R XD) tC (SCLK2 ) tWH (SCLK2 ) tWL (SCLK2 ) tsu(SIN2–SCLK2 ) th(SCLK2 –SIN2) 243 100 100 500 230 230 230 230 2000 950 950 400 200 2000 950 950 400 300 µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Reset input “L” pulse width External clock input cycle time External clock input “H” pulse width External clock input “L” pulse width CNTR 0, CNTR1 input cycle time CNTR 0, CNTR1 input “H” pulse width CNTR 0, CNTR1 input “L” pulse width INT0 to INT4 input “H” pulse width INT0 to INT4 input “L” pulse width Serial I/O1 clock input cycle time (Note) Serial I/O1 clock input “H” pulse width (Note) Serial I/O1 clock input “L” pulse width (Note) Serial I/O1 clock input set up time Serial I/O1 clock input hold time Serial I/O2 clock input cycle time Serial I/O2 clock input “H” pulse width Serial I/O2 clock input “L” pulse width Serial I/O2 clock input set up time Serial I/O2 clock input hold time Note: When bit 6 of address 001A 16 is “1” (clock synchronous). Divide this value by four when bit 6 of address 001A16 is “0” (UART). Table 19 Timing requirements (2) (Vcc = 2.7 to 5.5 V, Vss = 0 V, Ta = – 20 to 85 °C, unless otherwise noted) Limits

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER SWITCHING CHARACTERISTICS Min. Typ. Max. Symbol Parameter Limits Unit ns ns ns ns ns ns ns ns ns ns ns ns ns t WH (SCLK1 ) tWL (SCLK1 ) td(SCLK1 –TX D) tv(SCLK1 –TX D) tr(SCLK1 ) tf(SCLK1 ) tWH (SCLK2 ) tWL (SCLK2 ) td(SCLK2 –SOUT2 ) tv(SCLK2 –SOUT2 ) tf(SCLK2 ) tr(CMOS) tf(CMOS) Serial I/O1 clock output “H” pulse width Serial I/O1 clock output “L” pulse width Serial I/O1 output delay time (Note 1) Serial I/O1 output valid time (Note 1) Serial I/O1 clock output rising time Serial I/O1 clock output falling time Serial I/O2 clock output “H” pulse width Serial I/O2 clock output “L” pulse width Serial I/O2 output delay time (Note 2) Serial I/O2 output valid time (Note 2) Serial I/O2 clock output falling time CMOS output rising time (Note 3) CMOS output falling time (Note 3) 140 200 t C (SCLK1 )/2–30 tC (SCLK1 )/2–30 –30 tC (SCLK2 )/2–160 tC (SCLK2 )/2–160 Test conditions Fig. 3.1.1 Fig. 3.1.1 Fig. 3.1.1 Note 1:When the P4 5/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”. 2: When the P71/SOUT2 , P72/SCLK2 P-channel output disable bit of the serial I/O2 control register1 (bit 7 of address 001D16) is “0”. 3: XOUT pin is excluded. Table 20 Switching characteristics (1) (Vcc = 4.0 to 5.5 V, Vss = 0 V, Ta = – 20 to 85 °C, unless otherwise noted) Serial I/O1 clock output “H” pulse width Serial I/O1 clock output “L” pulse width Serial I/O1 output delay time (Note 1) Serial I/O1 output valid time (Note 1) Serial I/O1 clock output rising time Serial I/O1 clock output falling time Serial I/O2 clock output “H” pulse width Serial I/O2 clock output “L” pulse width Serial I/O2 output delay time (Note 2) Serial I/O2 output valid time (Note 2) Serial I/O2 clock output falling time CMOS output rising time (Note 3) CMOS output falling time (Note 3) Min. Typ. Max.Symbol Parameter Limits UnitTest conditions tWH (SCLK1 ) tWL (SCLK1 ) td(SCLK1 –TX D) tv(SCLK1 –TX D) tr(SCLK1 ) tf(SCLK1 ) tWH (SCLK2 ) tWL (SCLK2 ) td(SCLK2 –SOUT2 ) tv(SCLK2 –SOUT2 ) tf(SCLK2 ) tr(CMOS) tf(CMOS) Fig. 3.1.1 Fig. 3.1.1 Fig. 3.1.1 t C (SCLK1 )/2–50 tC (SCLK1 )/2–50 –30 tC (SCLK2 )/2–240 tC (SCLK2 )/2–240 350 400 ns ns ns ns ns ns ns ns ns ns ns ns ns Note 1:When the P4 5/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”. 2:When the P71/SOUT2 , P72/SCLK2 P-channel output disable bit of the serial I/O2 control register1 (bit 7 of address 001D16) is “0”. 3:XOUT pin is excluded. Table 21 Switching characteristics (2) (Vcc = 2.7 to 5.5 V, Vss = 0 V, Ta = – 20 to 85 °C, unless otherwise noted)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns φ clock cycle time φ clock “H” pulse width φ clock “L” pulse width AD 15–AD 8 delay time AD 7–AD 0 delay time AD 15–AD 8 valid time AD 7–AD 0 valid time SYNC delay time SYNC valid time Data bus delay time Data bus valid time RD pulse width, WR pulse width RD pulse width, WR pulse width (When one-wait is valid) AD 15–AD 8 delay time AD 7–AD 0 delay time AD 15–AD 8 valid time AD 7–AD 0 valid time Data bus delay time Data bus valid time RESET OUT output delay time RESET OUT output valid time (Note) Min.Symbol Limits Test conditions tc(φ) tWH (φ) tWL (φ) td(φ–AH) td(φ–AL) tv(φ–AH) tv(φ–AL) td(φ–SYNC) tv(φ–SYNC) td(φ–DB) tv(φ–DB) __ __ tWL (RD), tWL (WR) __ __ td(AH–RD) , td(AH–WR) __ __ td(AL–RD), td(AL–WR) __ __ tv(RD–AH), tv(WR–AH) __ __ tv(RD–AL), tv(WR–AL) td(WR–DB) tv(WR–DB) td(RESET–RESET OUT ) tv(φ–RESET OUT ) Typ. Max. 2tC (XIN) t C (XIN)–16 tC (XIN)–20 t C (XIN)–10 tC (XIN)–10 t C (XIN)–10 3tC (XIN)–10 tC (XIN)–35 tC (XIN)–40 200 100 Note:The RESET OUT output goes “H” in sync with the fall of the φ clock that is anywhere between about 8 cycle and 13 cycles after the____________ RESET input goes “H”. Parameter Fig. 3.1.1 TIMING REQUIREMENTS IN MEMORY EXPANSION MODE AND MICROPROCESSOR MODE SWITCHING CHARACTERISTICS IN MEMORY EXPANSION MODE AND MICROPROCESSOR MODE ____ tsu(ONW– φ) ____ th(φ–ONW) tsu(DB–φ) th(φ–DB) tsu(ONW–RD), tsu(ONW–WR) th(RD–ONW) , th(WR–ONW) tsu(DB–RD) th(RD–DB) ONW input set up time ONW input hold time Data bus set up time Data bus hold time ONW input set up time ONW input hold time Data bus set up time Data bus hold time Min. Typ. Max. Symbol Parameter Limits Unit –20 –20 –20 –20 ns ns ns ns ns ns ns ns Table 22 Timing requirements in memory expansion and microprocessor mode(1) (Vcc = 4.0 to 5.5 V, Vss = 0 V, Ta = – 20 to 85 °C, in high-speed mode, unless otherwise noted) Table 23 Switching characteristics in memory expansion and microprocessor mode(1) (Vcc = 4.0 to 5.5 V, Vss = 0 V, Ta = – 20 to 85 °C, in high-speed mode, unless otherwise noted)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Measurement output pin 100pF CMOS output 100pF N-channel open-drain output Measurement output pin Fig. 63 Circuit for measuring output switching Fig. 64 Circuit for measuring output switching characteristics (2)characteristics(1)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Fig. 65 Timing diagram (1) (in single-chip mode) 0.2VCC tWL(INT) 0.8VCC tWH(INT) 0.2VCC 0.2VCC 0.8VCC 0.8VCC 0.2VCC tWL(X IN) 0.8VCC tWH(X IN) tC(XIN) XIN 0.2VCC 0.8VCC tW(RESET) RESET tf tr 0.2VCC tWL(CNTR) 0.8VCC tWH(CNTR) tC(CNTR) td(SCLK1 -TXD),td(SCLK2-SOUT2 ) tv(SCLK1 -TXD), tv(SCLK2-SOUT2 ) tC(SCLK1 ), tC(SCLK2 ) tWL(S CLK1 ), tWL(S CLK2 ) tWH(S CLK1 ), tWH(S CLK2 ) th(SCLK1-R XD), th(SCLK2-SIN2) tsu(RXD -SCLK1 ), tsu(SIN2-SCLK2 ) TXD SOUT2 R XD SIN2 SCLK1 SCLK2 INT0 INT4 CNTR 0, CNTR1 Timing Diagram

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Fig. 66 Timing diagram (2) (in memory expansion mode and microprocessor mode) tWL( ) 0.5VCC tWH( ) tC( ) td( - AH) td( - AL) td( - SYNC) tv( - AH) tv( - AL) tv( - SYNC) td( - WR) tv( - WR) 0.5VCC 0.5VCC 0.5VCC 0.5VCC tSU(ONW - ) th( - ONW ) 0.8VCC 0.2VCC 0.8VCC 0.2VCC tSU(DB- ) th( - DB) 0.5VCC td( -DB) tv( -DB) 0.2VCC 0.8VCC 0.5VCC td(RESET- RESET OUT ) 0.5VCC AD 15 AD 8 AD 7 AD 0 SYNC RD,WR ONW DB 0 DB 7 DB 0 DB 7 RESET RESET OUT tv( RESET OUT ) (At CPU reading) (At CPU writing) Timing Diagram in Memory Expansion Mode and Microprocessor Mode (CMOS level input) Timing Diagram in Microprocessor Mode

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Fig. 67 Timing diagram (3) (in memory expansion mode and microprocessor mode) 0.5VCCRD,WR 0.5VCCAD 15 AD 8 td(AH-WR) tv(WR-AH) 0.5VCCAD 7 AD 0 td(AL-WR) tv(WR-AL) 0.8VCC 0.2VCCDB 0 DB 7 0.5VCCRD tSU(DB-RD) th(RD-DB) 0.5VCCDB 0 DB 7 0.5VCCWR td(WR-DB) tv(WR-DB) th(WR-ONW) 0.8VCC 0.2VCCONW tsu(ONW-WR) tv(RD-AH)td(AH-RD) td(AL-RD) tv(RD-AL) th(RD-ONW)tsu(ONW-RD) tWL(RD) tWL(WR) (At CPU reading) Timing Diagram in Memory Expansion Mode and Microprocessor Mode (CMOS level input) (At CPU writing)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Fig. 68 Timing diagram (4) (in memory expansion mode and microprocessor mode) tWL( )tWH( ) tC( ) td( - AH) td( - AL) td( - SYNC) tv( - AH) tv( - AL) tv( - SYNC) td( - WR) tv( - WR) tSU(ONW - ) th( - ONW ) tSU(DB- ) th( - DB) td( - DB) tv( - DB) td(RESET- RESET OUT ) AD 15 AD 8 AD 7 AD 0 SYNC RD,WR ONW DB 0 DB 7 DB 0 DB 7 RESET RESET OUT tv( - RESETOUT ) 2.0V 0.8V 2.0V 0.8V 2.0V 0.8V 2.0V 0.8V 2.0V 0.8V 2.4V 0.45V 2.4V 0.45V 2.0V 0.8V 2.0V 0.8V 2.0V 0.8V 0.8V CC 0.2VCC (At CPU reading) (At CPU writing) Timing Diagram in Memory Expansion Mode and Microprocessor Mode (TTL level input) Timing Diagram in Microprocessor Mode

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Fig. 69 Timing diagram (5) (in memory expansion mode and microprocessor mode) RD,WR AD 15 AD 8 td(AH-WR) tv(WR-AH) AD 7 AD 0 td(AL-WR) tv(WR-AL) DB 0 DB 7 2.0V RD tSU(DB-RD) th(RD-DB) DB 0 DB 7 WR td(WR-DB) tv(WR-DB) th(WR-ONW ) ONW tsu(ONW-WR) tv(RD-AH)td(AH-RD) td(AL-RD) tv(RD-AL) th(RD-ONW )tsu(ONW-RD) tWL(WR) 0.8V 2.0V 0.8V 2.0V 0.8V 2.4V 0.45V 2.4V 0.45V 2.0V 0.8V 2.0V 0.8V 2.0V 0.8V tWL(RD) (At CPU reading) (At CPU writing) Timing Diagram in Memory Expansion Mode and Microprocessor Mode (TTL level input)

© 1996 MITSUBISHI ELECTRIC CORP. H-DF047-A KI-9609 New publication, effective Sep. 1996. Specifications subject to change without notice. Notes regarding these materials

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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Rev. Rev. No. date 1.0 First Edition 9711.30 REVISION DESCRIPTION LIST 3807 GROUP DATA SHEET (1/1) Revision Description