3804H

3804H RENESAS | Alldatasheet

Document overview

• Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 116

Technical content

Rev.1.01 Jan 25, 2005 page 1 of 114 REJ03B0131-0101Z 3804 Group (Spec.H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER REJ03B0131-0101Z Rev.1.01 Jan 25, 2005

DESCRIPTION

The 3804 group (Spec. H) is the 8-bit microcomputer based on the 740 family core technology. The 3804 group (Spec. H) is designed for household products, of- fice automation equipment, and controlling systems that require analog signal processing, including the A/D converter and D/A converters.

FEATURES

(at 16.8 MHz oscillation frequency) G Memory size G Interrupts (external 8, internal 12, software 1) 8-bit ✕ 4 (with 8-bit prescaler) G Serial interface G Multi-master I (8-bit reading enabled) (connect to external ceramic resonator or quartz-crystal oscillator) G Power source voltage In high-speed mode In middle-speed mode In low-speed mode G Power dissipation (at 16.8 MHz oscillation frequency, at 5 V power source voltage) (at 32 kHz oscillation frequency, at 3 V power source voltage) G Packages <Flash memory mode> G Program/Erase control by software command I Notes Cannot be used for application embedded in the MCU card. Currently support products are listed below. RAM size (bytes) RemarksPackage Table 1 Support products Product name Flash memory size (bytes) M38049FFHSP M38049FFHFP M38049FFHHP M38049FFHKP 64P4B 64P6N-A 64P6Q-A 64P6U-A Vcc = 2.7 to 5.5 V 61440 2048

Rev.1.01 Jan 25, 2005 page 2 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) PIN CONFIGURATION (TOP VIEW) Fig. 1 3804 group (Spec. H) pin configuration Package type : 64P6N-A/64P6Q-A/64P6U-A 48 47 46 45 43 42 41 40 39 38 37 36 35 34 3344 0/AN 1/AN 2/AN 3/AN 4/AN 5/AN 6/AN 7/AN 0/INT 1/INT P27(LED 7) P20(LED 0) P21(LED 1) P22(LED 2) P23(LED 3) P24(LED 4) P25(LED 5) P26(LED 6) VSS XOUT XIN P42/INT1 RESET CNV SS P40/INT40/XCOUT P41/INT00/XCIN P35/TXD 3 P34/RXD 3 P31/DA2 P30/DA1 VCC VREF AV SS P67/AN7 P66/AN6 P65/AN5 P64/AN4 P63/AN3 P37/SRDY3 P36/SCLK3 P33/SCL P32/SDA 1/AN 0/AN 7/INT 6/PWM 5/CNTR 4/CNTR 2/S CLK2 1/S OUT2 0/S IN2 6/S CLK1 5/T XD 4/R XD 3/INT 2/AN 7/S RDY1 /CNTR 3/S RDY2 M38049FFHFP/HP/KP 1 2 3 4 6 7 8 9 10 11 12 13 14 15 165 Fig. 2 3804 group (Spec. H) pin configuration Package type : 64P4B VCC VREF AV SS P67/AN7 P66/AN6 P64/AN4 P63/AN3 P62/AN2 P61/AN1 P60/AN0 P57/INT3 P56/PWM P55/CNTR 1 P54/CNTR 0 P52/SCLK2 P51/SOUT2 P50/SIN2 P46/SCLK1 P45/TXD 1 P44/RXD 1 P43/INT2 P42/INT1 CNV SS P40/INT40/XCOUT XIN XOUT VSS RESET P30/DA1 P31/DA2 P34/RXD 3 P35/TXD 3 P00/AN8 P20(LED0) P53/SRDY2 P65/AN5 P41/INT00/XCIN P01/AN9 P02/AN10 P03/AN11 P04/AN12 P05/AN13 P06/AN14 P07/AN15 P10/INT41 P11/INT01 P12 P13 P14 P15 P16 P17 P21(LED1) P22(LED2) P23(LED3) P24(LED4) P25(LED5) P26(LED6) P27(LED7) P32/SDA P33/SCL P36/SCLK3 P37/SRDY3 P47/SRDY1 /CNTR 2 M38049FFHSP PIN CONFIGURATION (TOP VIEW)

Rev.1.01 Jan 25, 2005 page 3 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) FUNCTIONAL BLOCK DIAGRAM (Package: 64P4B) Fig. 3 Functional block diagram FUNCTIONAL BLOCK I C2 I N I N I N X I N O U T X R A M R O M C P U A X Y S P C H P C L P S S S V 3 2 R E S E T 2 7 C C V 2 6 C N V S S C N T R P 4 9 5 0 5 15 2 5 35 45 55 6 P 4 1 4 3 4 5 4 7 4 2 4 4 4 6 4 8 P 3 3 3 5 3 7 3 9 3 4 3 6 3 8 4 0 P 5 7 5 9 6 1 6 3 5 8 6 0 6 2 6 4 P 2 0 2 2 2 4 2 8 2 1 2 3 2 5 2 9 1 0 1 1 P 6 I / O p o r t P I / O p o r t P I / O p o r t P I / O p o r t P ( L E D d r i v e I / O p o r t P I / O p o r t P C l o c k g e n e r a t i n g c i r c u i t C l o c k i n p u t P r e s c a l e r T i m e r D a t a b u s C N T R T i m e r Z A D c o n v e r t e r V R E F A V S S I N 1 2 1 4 1 6 1 8 1 3 1 5 1 7 1 9 I / O p o r t P P W M P S I O S I O D A c o n v e r t e r X C I N C O U T X 3 0 3 1 2 8 2 9 C N T R S I O I N I N I N C l o c k o u t p u t S u b c l o c k i n p u t S u b c l o c k o u t p u t R e s e t i n p u t T i m e r T i m e r X T i m e r Y P r e s c a l e r X P r e s c a l e r Y D A c o n v e r t e r

Rev.1.01 Jan 25, 2005 page 4 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) PIN DESCRIPTION FunctionsNamePin

• Apply voltage of 2.7 V–5.5 V to Vcc, and 0 V to Vss.
• This pin controls the operation mode of the chip.
• Normally connected to VSS .
• Reference voltage input pin for A/D and D/A converters.
• Analog power source input pin for A/D and D/A converters.
• Connect to VSS .
• Reset input pin for active “L”.
• Input and output pins for the clock generating circuit.
• Connect a ceramic resonator or quartz-crystal oscillator between the XIN and XOUT pins to set the oscillation frequency.
• When an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open.
• 8-bit CMOS I/O port.
• I/O direction register allows each pin to be individually programmed as either input or output.
• CMOS compatible input level.
• CMOS 3-state output structure.
• Pull-up control is enabled in a bit unit.
• P20–P27 are enabled to output large current for LED drive.
• 8-bit CMOS I/O port.
• I/O direction register allows each pin to be individually programmed as either input or output.
• CMOS compatible input level.
• P3 2 to P33 can be switched between CMOS compat- ible input level or SMBUS input level in the I2C-BUS interface function.
• P30, P31, P34–P37 are CMOS 3-state output structure.
• P32, P33 are N-channel open-drain output structure.
• Pull-up control of P30, P31, P34–P37 is enabled in a bit unit.
• 8-bit CMOS I/O port.
• I/O direction register allows each pin to be individually programmed as either input or output.
• CMOS compatible input level.
• CMOS 3-state output structure.
• Pull-up control is enabled in a bit unit. Power source CNV SS input Reference voltage Analog power source Table 2 Pin description Function except a port function
• A/D converter input pin
• Interrupt input pin
• D/A converter input pin
• Serial I/O3 function pin I/O port P4 •Interrupt input pin
• Sub-clock generating I/O pin (resonator connected)
• Interrupt input pin VCC , VSS CNV SS VREF AV SS RESET Reset input Clock inputXIN XOUT Clock output P00/AN8– P07/AN15 I/O port P0 P10/INT41 P11/INT01 P12–P17 I/O port P1 P20–P27 I/O port P2 P30/DA1 P31/DA2 P32/SDA P33/SCL P34/RxD3 P35/TxD3 P36/SCLK3 P37/SRDY3 P40/INT40/ XCOUT P41/INT00/ XCIN P42/INT1 P43/INT2 P44/RxD1 P45/TxD1 P46/SCLK1 P47/SRDY1 /CNTR 2 P50/SIN2 P51/SOUT2 P52/SCLK2 P53/SRDY2 P54/CNTR 0 P55/CNTR 1 P56/PWM P57/INT3 P60/AN0– P67/AN7
• 8-bit CMOS I/O port.
• I/O direction register allows each pin to be individually programmed as either input or output.
• CMOS compatible input level.
• CMOS 3-state output structure.
• Pull-up control is enabled in a bit unit.
• Serial I/O1 function pin
• Serial I/O1, timer Z function pin I/O port P5 I/O port P6
• Serial I/O2 function pin
• Timer X function pin
• Timer Y function pin
• PWM output pin
• Interrupt input pin
• A/D converter input pin
• I2C-BUS interface function pins I/O port P3

Rev.1.01 Jan 25, 2005 page 5 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) PART NUMBERING Fig. 4 Part numbering M3804 9 F F H SPProduct name Package type SP : 64P4B FP : 64P6N-A HP : 64P6Q-A KP : 64P6U-A ROM/PROM size : 4096 bytes : 8192 bytes : 12288 bytes : 16384 bytes : 20480 bytes : 24576 bytes : 28672 bytes : 32768 bytes Memory type F : Flash memory version RAM size : 192 bytes : 256 bytes : 384 bytes : 512 bytes : 640 bytes : standard H : Minner spec. change product : 36864 bytes : 40960 bytes : 45056 bytes : 49152 bytes : 53248 bytes : 57344 bytes : 61440 bytes A B C D E F : 768 bytes : 896 bytes : 1024 bytes : 1536 bytes : 2048 bytes

Rev.1.01 Jan 25, 2005 page 6 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) GROUP EXPANSION Renesas plans to expand the 3804 group (Spec. H) as follows. Memory Size Packages Fig. 5 Memory expansion plan Memory Expansion Plan 48K 32K 28K 24K 20K 16K 12K 384 512 640 768 896 1024 60K 1152 1280 1408 1536 2048 3072 4032 ROM size (bytes) RAM size (bytes) M38049FFH M38049FF As of Jan. 2005: Under development : Mass production

Rev.1.01 Jan 25, 2005 page 7 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) FUNCTIONAL DESCRIPTION CENTRAL PROCESSING UNIT (CPU) The 3804 group (Spec. H) uses the standard 740 Family instruc- tion set. Refer to the table of 740 Family addressing modes and machine instructions or the 740 Family Software Manual for de- tails on the instruction set. Machine-resident 740 Family instructions are as follows: The FST and SLW instructions cannot be used. The STP, WIT, MUL, and DIV instructions can be used. [Accumulator (A)] The accumulator is an 8-bit register. Data operations such as data transfer, etc. are executed mainly through the accumulator. [Index Register X (X)] The index register X is an 8-bit register. In the index addressing modes, the value of the OPERAND is added to the contents of register X and specifies the real address. [Index Register Y (Y)] The index register Y is an 8-bit register. In partial instruction, the value of the OPERAND is added to the contents of register Y and specifies the real address. Fig. 6 740 Family CPU register structure [Stack Pointer (S)] The stack pointer is an 8-bit register used during subroutine calls and interrupts. This register indicates start address of stored area (stack) for storing registers during subroutine calls and interrupts. The low-order 8 bits of the stack address are determined by the contents of the stack pointer. The high-order 8 bits of the stack ad- dress are determined by the stack page selection bit. If the stack page selection bit is “0” , the high-order 8 bits becomes “00 16”. If the stack page selection bit is “1”, the high-order 8 bits becomes “0116”. The operations of pushing register contents onto the stack and popping them from the stack are shown in Figure 7. Store registers other than those described in Figure 6 with pro- gram when the user needs them during interrupts or subroutine calls (see Table 3). [Program Counter (PC)] The program counter is a 16-bit counter consisting of two 8-bit registers PC H and PCL. It is used to indicate the address of the next instruction to be executed. A Accumulator b7 b0 b7b15 b0 b7 b0 X Index register X Y Index register Y S Stack pointer PC L Program counterPC H N V T B D I Z C Processor status register (PS) Carry flag Zero flag Interrupt disable flag Decimal mode flag Break flag Index X mode flag Overflow flag Negative flag

Rev.1.01 Jan 25, 2005 page 8 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) Table 3 Push and pop instructions of accumulator or processor status register Accumulator Processor status register Push instruction to stack PHA PHP Pop instruction from stack PLA PLP Fig. 7 Register push and pop at interrupt generation and subroutine call N o t e: C o n d i t i o n f o r a c c e p t a n c e o f a n i n t e r r u p t I n t e r r u p t e n a b l e f l a g i s “ 1 ” E x e c u t e J S R O n g o i n g R o u t i n e M S P C H ) S S M S P C L) E x e c u t e R T S P C L)M S S S S S S S P C H )M S S u b r o u t i n e P O P re t u r n a d d r e s s f r o m s t a c k P u s h r e t u r n a d d r e s s o n s t a c k M S P S E x e c u t e R T I P S S S S S S I n t e r r u p t S e r v i c e R o u t i n e P O P c o n t e n t s o f p r o c e s s o r s t a t u s r e g i s t e r f r o m s t a c k M S P C H ) S S M S P C L) S S P C L)M S S S S S P C H )M S P O P r e t u r n a d d r e s s f r o m s t a c k I F l a g i s s e t f r o m t o F e t c h t h e j u m p v e c t o r P u s h r e t u r n a d d r e s s o n s t a c k P u s h c o n t e n t s o f p r o c e s s o r s t a t u s r e g i s t e r o n s t a c k I n t e r r u p t r e q u e s t N o t e I n t e r r u p t d i s a b l e f l a g i s “ 0 ”

Rev.1.01 Jan 25, 2005 page 9 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) [Processor status register (PS)] The processor status register is an 8-bit register consisting of 5 flags which indicate the status of the processor after an arithmetic operation and 3 flags which decide MCU operation. Branch opera- tions can be performed by testing the Carry (C) flag , Zero (Z) flag, Overflow (V) flag, or the Negative (N) flag. In decimal mode, the Z, V, N flags are not valid.

• Bit 0: Carry flag (C) The C flag contains a carry or borrow generated by the arithmetic logic unit (ALU) immediately after an arithmetic operation. It can also be changed by a shift or rotate instruction.
• Bit 1: Zero flag (Z) The Z flag is set if the result of an immediate arithmetic operation or a data transfer is “0”, and cleared if the result is anything other than “0”.
• Bit 2: Interrupt disable flag (I) The I flag disables all interrupts except for the interrupt generated by the BRK instruction. Interrupts are disabled when the I flag is “1”.
• Bit 3: Decimal mode flag (D) The D flag determines whether additions and subtractions are executed in binary or decimal. Binary arithmetic is executed when this flag is “0”; decimal arithmetic is executed when it is “1”. Decimal correction is automatic in decimal mode. Only the ADC and SBC instructions can execute decimal arithmetic.
• Bit 4: Break flag (B) The B flag is used to indicate that the current interrupt was generated by the BRK instruction. The BRK flag in the processor status register is always “0”. When the BRK instruction is used to generate an interrupt, the processor status register is pushed onto the stack with the break flag set to “1”.
• Bit 5: Index X mode flag (T) When the T flag is “0”, arithmetic operations are performed between accumulator and memory. When the T flag is “1”, direct arithmetic operations and direct data transfers are enabled between memory locations.
• Bit 6: Overflow flag (V) The V flag is used during the addition or subtraction of one byte of signed data. It is set if the result exceeds +127 to -128. When the BIT instruction is executed, bit 6 of the memory location operated on by the BIT instruction is stored in the overflow flag.
• Bit 7: Negative flag (N) The N flag is set if the result of an arithmetic operation or data transfer is negative. When the BIT instruction is executed, bit 7 of the memory location operated on by the BIT instruction is stored in the negative flag. Table 4 Set and clear instructions of each bit of processor status register Set instruction Clear instruction C flag SEC CLC Z flag I flag SEI CLI D flag SED CLD B flag T flag SET CLT V flag CLV N flag

Rev.1.01 Jan 25, 2005 page 10 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) Fig. 8 Structure of CPU mode register [CPU Mode Register (CPUM)] 003B16 The CPU mode register contains the stack page selection bit, etc. The CPU mode register is allocated at address 003B16. C P U m o d e r e g i s t e r P U M a d d r e s s 0 0 3 B1 b 7 b 0 Fix this bit to “1”. Stack page selection bit 0 : 0 page 1 : 1 page Processor mode bits b1 b0 0 0 : Single-chip mode 0 1 : 1 0 : Not available 1 1 : Port X C switch bit 0 : I/O port function (stop oscillating) 1 : X CIN–XCOUT oscillating function Main clock (XIN–XOUT ) stop bit 0 : Oscillating 1 : Stopped Main clock division ratio selection bits b7 b6 0 0 : φ = f(X IN)/2 (high-speed mode) 0 1 : φ = f(XIN)/8 (middle-speed mode) 1 0 : φ = f(XCIN)/2 (low-speed mode) 1 1 : Not available

Rev.1.01 Jan 25, 2005 page 11 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) MISRG (1) Bit 0 of address 001016: Oscillation stabilizing time set af- ter STP instruction released bit When the MCU stops the clock oscillation by the STP instruction and the STP instruction has been released by an external interrupt source, usually, the fixed values of Timer 1 and Prescaler 12 (Timer 1 = 01 16, Prescaler 12 = FF16) are automatically reloaded in order for the oscillation to stabilize. The user can inhibit the au- tomatic setting by setting “1” to bit 0 of MISRG (address 0010 16). However, by setting this bit to “1”, the previous values, set just be- fore the STP instruction was executed, will remain in Timer 1 and Prescaler 12. Therefore, you will need to set an appropriate value to each register, in accordance with the oscillation stabilizing time, before executing the STP instruction. Figure 9 shows the structure of MISRG. (2) Bits 1, 2, 3 of address 0010 16: Middle-speed Mode Auto- matic Switch Function In order to switch the clock mode of an MCU which has a sub- clock, the following procedure is necessary: set CPU mode register (003B 16) --> start main clock oscillation --> wait for oscillation stabilization --> switch to middle-speed mode (or high-speed mode). However, the 3804 group (Spec. H) has the built-in function which automatically switches from low to middle-speed mode either by the SCL/SDA interrupt or by program. G Middle-speed mode automatic switch by SCL/SDA Interrupt The SCL/SDA interrupt source enables an automatic switch when the middle-speed mode automatic switch set bit (bit 1) of MISRG (address 0010 16) is set to “1”. The conditions for an automatic switch execution depend on the settings of bits 5 and 6 of the I2C START/STOP condition control register (address 001616). Bit 5 is the SCL/SDA interrupt pin polarity selection bit and bit 6 is the SCL/SDA interrupt pin selection bit. The main clock oscillation sta- bilizing time can also be selected by middle-speed mode automatic switch wait time set bit (bit 2) of the MISRG. G Middle-speed mode automatic switch by program The middle-speed mode can also be automatically switched by program while operating in low-speed mode. By setting the middle-speed automatic switch start bit (bit 3) of MISRG (address 0010 16) to “1” in the condition that the middle-speed mode auto- matic switch set bit is “1” while operating in low-speed mode, the MCU will automatically switch to middle-speed mode. In this case, the oscillation stabilizing time of the main clock can be selected by the middle-speed automatic switch wait time set bit (bit 2) of MISRG (address 0010 16). Fig. 9 Structure of MISRG M I S R G M I S R G a d d r e s s b7 b0 N o t e1 : D u r i n g o p e r a t i o n i n l o w - s p e e d m o d e , i t i s p o s s i b l e a u t o m a t i c a l l y t o s w i t c h t o m i d d l e s p e e d m o d e o w i n g t o S C L S D A i n t e r r u p t : W h e n a u t o m a t i c s w i t c h t o m i d d l e s p e e d m o d e f r o m l o w s p e e d m o d e o c c u r s t h e v a l u e s o f C P U m o d e r e g i s t e r c h a n g e Not used (return “0” when read) (Do not write “1” to this bit) M i d d l e - s p e e d m o d e a u t o m a t i c s w i t c h s t a r t b i t D e p e n d i n g o n p r o g r a m I n v a l i d A u t o m a t i c s w i t c h s t a r t N o t e Middle-speed mode automatic switch wait time set bit 0: 4.5 to 5.5 machine cycles 1: 6.5 to 7.5 machine cycles M i d d l e - s p e e d m o d e a u t o m a t i c s w i t c h s e t b i t N o t s e t a u t o m a t i c a l l y A u t o m a t i c s w i t c h i n g e n a b l e d N o t e O s c i l l a t i o n s t a b i l i z i n g t i m e s e t a f t e r S T P i n s t r u c t i o n r e l e a s e d b i t A u t o m a t i c a l l y s e t t o T i m e r F t o P r e s c a l e r A u t o m a t i c a l l y s e t d i s a b l e d

Rev.1.01 Jan 25, 2005 page 12 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) MEMORY Special Function Register (SFR) Area The Special Function Register area in the zero page contains con- trol registers such as I/O ports and timers. RAM The RAM is used for data storage and for stack area of subroutine calls and interrupts. ROM The ROM area can program/erase. Interrupt Vector Area The interrupt vector area contains reset and interrupt vectors. Zero Page Access to this area with only 2 bytes is possible in the zero page addressing mode. Special Page Access to this area with only 2 bytes is possible in the special page addressing mode. Fig. 10 Memory map diagram 010016 000016 004016 FF0016 FFDC 16 FFFE 16 FFFF 16 192 256 384 512 640 768 896 1024 1536 2048 XXXX 00FF16 013F16 01BF 16 023F16 02BF 16 033F16 03BF 16 043F16 063F16 083F16 4096 8192 12288 16384 20480 24576 28672 32768 36864 40960 45056 49152 53248 57344 61440 F000 E00016 D000 16 C000 16 B00016 A00016 900016 800016 700016 600016 500016 400016 300016 200016 100016 YYYY 16 RAM ROM 0FF016 0FFF 16 SFR area Not used Interrupt vector area ROM area Zero page Special page RAM area RAM size (bytes) Address XXXX 16 ROM size (bytes) Address YYYY 16 SFR area Not used

Rev.1.01 Jan 25, 2005 page 13 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) Fig. 11 Memory map of special function register (SFR) 0 0 2 01 0 0 2 11 0 0 2 21 0 0 2 31 0 0 2 41 0 0 2 51 0 0 2 61 002716 002816 0 0 2 91 0 0 2 A1 0 0 2 B1 0 0 2 C 1 0 0 2 D 1 0 0 2 E1 0 0 2 F1 0 0 3 01 0 0 3 11 0 0 3 21 0 0 3 31 003416 003516 003616 0 0 3 71 0 0 3 81 0 0 3 91 0 0 3 A1 0 0 3 B1 0 0 3 C 1 0 0 3 D 1 0 0 3 E1 0 0 3 F1 0 0 0 01 0 0 0 11 0 0 0 21 0 0 0 31 0 0 0 41 0 0 0 51 0 0 0 61 000716 000816 0 0 0 91 0 0 0 A1 0 0 0 B1 0 0 0 C 1 0 0 0 D 1 0 0 0 E1 0 0 0 F1 0 0 1 01 0 0 1 11 0 0 1 21 0 0 1 31 001416 001516 001616 0 0 1 71 0 0 1 81 0 0 1 91 0 0 1 A1 0 0 1 B1 0 0 1 C 1 0 0 1 D 1 0 0 1 E1 0 0 1 F1

6 Serial I/O2 register (SIO2)

P o r t P 0 ( P 0 ) P o r t P 0 d i r e c t i o n r e g i s t e r ( P 0 D ) P o r t P 1 ( P 1 ) P o r t P 1 d i r e c t i o n r e g i s t e r ( P 1 D ) P o r t P 2 ( P 2 ) P o r t P 2 d i r e c t i o n r e g i s t e r ( P 2 D ) P o r t P 3 ( P 3 ) P o r t P 3 d i r e c t i o n r e g i s t e r ( P 3 D ) P o r t P 4 ( P 4 ) P o r t P 4 d i r e c t i o n r e g i s t e r ( P 4 D ) P o r t P 5 ( P 5 ) P o r t P 5 d i r e c t i o n r e g i s t e r ( P 5 D ) P o r t P 6 ( P 6 ) P o r t P 6 d i r e c t i o n r e g i s t e r ( P 6 D ) T i m e r 1 2 , X c o u n t s o u r c e s e l e c t i o n r e g i s t e r ( T 1 2 X C S S ) T i m e r Y, Z c o u n t s o u r c e s e l e c t i o n r e g i s t e r ( T Y Z C S S ) M I S R G T r a n s m i t / R e c e i v e b u f f e r r e g i s t e r 1 ( T B 1 / R B 1 ) S e r i a l I / O 1 s t a t u s r e g i s t e r ( S I O 1 S T S ) S e r i a l I / O 1 c o n t r o l r e g i s t e r ( S I O 1 C O N ) UART1 control register (UART1CON) B a u d r a t e g e n e r a t o r 1 ( B R G 1 ) S e r i a l I / O 2 c o n t r o l r e g i s t e r ( S I O 2 C O N ) I n t e r r u p t c o n t r o l r e g i s t e r 2 ( I C O N 2 ) A D c o n v e r s i o n r e g i s t e r 1 ( A D 1 ) P r e s c a l e r Y ( P R E Y ) Timer Y (TY) A D / D A c o n t r o l r e g i s t e r ( A D C O N ) DA1 conversion register (DA1) D A 2 c o n v e r s i o n r e g i s t e r ( D A 2 ) I n t e r r u p t e d g e s e l e c t i o n r e g i s t e r ( I N T E D G E ) CPU mode register (CPUM) I n t e r r u p t r e q u e s t r e g i s t e r 1 ( I R E Q 1 ) Interrupt request register 2 (IREQ2) I n t e r r u p t c o n t r o l r e g i s t e r 1 ( I C O N 1 ) P r e s c a l e r 1 2 ( P R E 1 2 ) T i m e r 2 ( T 2 ) P r e s c a l e r X ( P R E X ) T i m e r X ( T X ) T i m e r 1 ( T 1 ) T i m e r X Y m o d e r e g i s t e r ( T M ) AD conversion register 2 (AD2) I n t e r r u p t s o u r c e s e l e c t i o n r e g i s t e r ( I N T S E L ) W a t c h d o g t i m e r c o n t r o l r e g i s t e r ( W D T C O N )

0 F F 01

0 F F 11

Port P0 pull-up control register (PULL0) T i m e r Z l o w - o r d e r ( T Z L ) T i m e r Z h i g h - o r d e r ( T Z H ) P W M c o n t r o l r e g i s t e r ( P W M C O N ) P W M p r e s c a l e r ( P R E P W M ) T i m e r Z m o d e r e g i s t e r ( T Z M ) P W M r e g i s t e r ( P W M ) B a u d r a t e g e n e r a t o r 3 ( B R G 3 ) T r a n s m i t / R e c e i v e b u f f e r r e g i s t e r 3 ( T B 3 / R B 3 ) Serial I/O3 status register (SIO3STS) S e r i a l I / O 3 c o n t r o l r e g i s t e r ( S I O 3 C O N ) U A R T 3 c o n t r o l r e g i s t e r ( U A R T 3 C O N ) Port P1 pull-up control register (PULL1)

0 F F 21

0 F F 31

P o r t P 2 p u l l - u p c o n t r o l r e g i s t e r ( P U L L 2 ) P o r t P 3 p u l l - u p c o n t r o l r e g i s t e r ( P U L L 3 )

0 F F 41

6 P o r t P 4 p u l l - u p c o n t r o l r e g i s t e r ( P U L L 4 )

0 F F 51

0 F F 61

P o r t P 5 p u l l - u p c o n t r o l r e g i s t e r ( P U L L 5 ) P o r t P 6 p u l l - u p c o n t r o l r e g i s t e r ( P U L L 6 ) ✽ Reserved area: Do not write any data to these addresses, because these areas are reserved.

0 F E 01

0 F E 11

Flash memory control register 0 (FMCR0) Flash memory control register 1 (FMCR1)

0 F E 21

0 F E 31

Flash memory control register 2 (FMCR2) Reserved ✽

0 F E 41

6 Reserved ✽

0 F E 51

0 F E 61

Reserved ✽ Reserved ✽

0 F E 71

0 F E 81

Reserved ✽ Reserved ✽

0 F E 91

0FEA 16 Reserved ✽

0 F E B1

Reserved ✽ Reserved ✽

0 F E D 1

Reserved ✽ Reserved ✽

0 F E F1

d a t a s h i f t r e g i s t e r S I2C s t a t u s r e g i s t e r S I2C c o n t r o l r e g i s t e r S D I2C c l o c k c o n t r o l r e g i s t e r S I2C S T A R T S T O P c o n d i t i o n c o n t r o l r e g i s t e r S D I2C s p e c i a l m o d e s t a t u s r e g i s t e r S I2C s p e c i a l m o d e c o n t r o l r e g i s t e r S D

0 F F 71

6 I2C

s l a v e a d d r e s s r e g i s t e r S D

0 F F 81

6 I2C slave address register 1 (S0D1)

s l a v e a d d r e s s r e g i s t e r S D

Rev.1.01 Jan 25, 2005 page 14 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) I/O PORTS The I/O ports have direction registers which determine the input/ output direction of each individual pin. Each bit in a direction reg- ister corresponds to one pin, and each pin can be set to be input port or output port. When “0” is written to the bit corresponding to a pin, that pin be- 0/AN8–P07/AN15 P10/INT41 P11/INT01 P12–P17 P20/LED0– P27/LED7 P30/DA1 P31/DA2 P32/SDA P33/SCL P34/RxD3 P35/TxD3 P36/SCLK3 P37/SRDY3 P40/INT40/XCIN P41/INT00/XCOUT P42/INT1 P43/INT2 P44/RxD1 P45/TxD1 P46/SCLK1 P47/SRDY1 /CNTR 2 Pin Name I/O Structure CMOS compatible input level CMOS 3-state output Non-Port Function Ref.No. Table 5 I/O port function Related SFRs Port P0 Port P1 Port P3 (1) (2) Port P2 A/D converter input External interrupt input D/A converter output AD/DA control register Interrupt edge selection register AD/DA control register (3) (4) (5) CMOS compatible input level CMOS 3-state output CMOS compatible input level N-channel open-drain output CMOS/SMBUS input level (when selecting I 2C-BUS interface function) CMOS compatible input level CMOS 3-state output Port P4 Serial I/O3 function I/O Serial I/O3 control register UART3 control register (6) (7) (8) (9) External interrupt input Sub-clock generating circuit External interrupt input Serial I/O1 function I/O Interrupt edge selection register CPU mode register Interrupt edge selection register Serial I/O1 control register UART1 control register (10) (11) (2) (6) (7) (8) (12) Serial I/O1 function I/O Timer Z function I/O Serial I/O1 control register Timer Z mode register Serial I/O2 control register Serial I/O2 function I/OPort P5 Port P6 (13) (14) (15) (16) (17) (18) (2) (1) Timer X, Y function I/O PWM output External interrupt input A/D converter input Timer XY mode register PWM control register Interrupt edge selection register AD/DA control register Notes 1: Refer to the applicable sections how to use double-function ports as function I/O ports. 2: Make sure that the input level at each pin is either 0 V or VCC during execution of the STP instruction. When an input level is at an intermediate potential, a current will flow from VCC to VSS through the input-stage gate. comes an input pin. When “1” is written to that bit, that pin be- comes an output pin. If data is read from a pin which is set to output, the value of the port output latch is read, not the value of the pin itself. Pins set to input are floating. If a pin set to input is written to, only the port output latch is written to and the pin remains floating. P50/SIN2 P51/SOUT2 P52/SCLK2 P53/SRDY2 P54/CNTR 0 P55/CNTR 1 P56/PWM P57/INT3 P60/AN0–P67/AN7 CMOS compatible input level CMOS 3-state output CMOS compatible input level CMOS 3-state output CMOS compatible input level CMOS 3-state output I2C-BUS interface func- tion I/O I2C control register

Rev.1.01 Jan 25, 2005 page 15 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) Fig. 12 Port block diagram (1) (6) Ports P34, P44 S e r i a l I / O i n p u t ( 1 ) P o r t s P 0 , P 6 A / D c o n v e r t e r i n p u t Analog input pin selection bit Direction register D a t a b u s P o r t l a t c h P u l l - u p c o n t r o l b i t ( 2 ) P o r t s P 10, P 11, P 42, P 43, P 57 Interrupt input ( 3 ) P o r t s P 12 t o P 17, P 2 ( 4 ) P o r t s P 30, P 31 D A1 o u t p u t e n a b l e ( P 30) D o u t p u t e n a b l e P 31) ( 8 ) P o r t s P 36, P 46( 7 ) P o r t s P 35, P 45 ( 5 ) P o r t s P 32, P 33 D a t a b u s D i r e c t i o n r e g i s t e r P o r t l a t c h Pull-up control bit P u l l - u p c o n t r o l b i t Direction register P o r t l a t c hD a t a b u s D a t a b u s D i r e c t i o n r e g i s t e r P o r t l a t c h Pull-up control bit D/A converter output D a t a b u s D i r e c t i o n r e g i s t e r P o r t l a t c h P u l l - u p c o n t r o l b i t Serial I/O enable bit Receive enable bit D i r e c t i o n r e g i s t e r Port latchD a t a b u s P u l l - u p c o n t r o l b i t S e r i a l I / O e n a b l e b i t T r a n s m i t e n a b l e b i t P - c h a n n e l o u t p u t d i s a b l e b i t S e r i a l I / O e n a b l e b i t Serial I/O mode selection bit S e r i a l I / O e n a b l e b i t S e r i a l I / O s y n c h r o n o u s c l o c k s e l e c t i o n b i t Data bus Direction register P o r t l a t c h Pull-up control bit S e r i a l I / O e x t e r n a l c l o c k i n p u t S e r i a l I / O c l o c k o u t p u t S e r i a l I / O o u t p u t Direction register P o r t l a t c hD a t a b u s S D A o u t p u t S C L o u t p u t SDA input SCL input I2C B U S i n t e r f a c e e n a b l e b i t

Rev.1.01 Jan 25, 2005 page 16 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) Fig. 13 Port block diagram (2) (10) Port P40 (11) Port P41 (13) Port P50 Port XC switch bit INT40 interrupt input Port P41 Serial I/O2 input (12) Port P47 (9) Port P37 SRDY3 output enable bit (14) Port P51 INT00 interrupt input Serial I/O3 enable bit Serial I/O3 mode selection bit Data bus Direction register Port latch Pull-up control bit Serial I/O3 ready output Pull-up control bit Data bus Direction register Port latch Port XC switch bit Oscillator CNTR 2 interrupt input SRDY1 output enable bit Serial I/O1 enable bit Serial I/O1 mode selection bit Data bus Serial I/O1 ready output Timer output Data bus Direction register Port latch Pull-up control bit Sub-clock generating circuit input Port XC switch bit Pull-up control bit Data bus Direction register Port latch Pull-up control bit Data bus Direction register Port latch Serial I/O2 output Serial I/O2 transmit completion signal Serial I/O2 port selection bit P-channel output disable bit Bit 2 Timer Z operating mode bits Bit 1 Bit 0 Port latch Direction register Pull-up control bit

Rev.1.01 Jan 25, 2005 page 17 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) Fig. 14 Port block diagram (3) ( 1 6 ) P o r t P 53( 1 5 ) P o r t P 52 ( 1 7 ) P o r t s P 54, P 55 ( 1 8 ) P o r t P 56 PWM output S e r i a l I / O 2 s y n c h r o n o u s c l o c k s e l e c t i o n b i t Serial I/O2 port selection bit D a t a b u s D i r e c t i o n r e g i s t e r Port latch P u l l - u p c o n t r o l b i t S e r i a l I / O 2 e x t e r n a l c l o c k i n p u t S e r i a l I / O 2 c l o c k o u t p u t SR D Y 2 e n a b l e b i t Serial I/O2 ready output D a t a b u s D i r e c t i o n r e g i s t e r P o r t l a t c h Data bus Direction register Port latch P u l l - u p c o n t r o l b i t C N T R i n t e r r u p t i n p u t P u l s e o u t p u t m o d e Timer output D a t a b u s D i r e c t i o n r e g i s t e r Port latch P W M o u t p u t e n a b l e b i t Pull-up control bit P u l l - u p c o n t r o l b i t

Rev.1.01 Jan 25, 2005 page 18 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) Fig. 15 Structure of port pull-up control register (1) Port P0 pull-up control register b 7b 0 P 00 p u l l - u p c o n t r o l b i t N o p u l l u p P u l l u p P p u l l u p c o n t r o l b i t N o p u l l u p P u l l u p P p u l l u p c o n t r o l b i t N o p u l l u p P u l l u p P p u l l u p c o n t r o l b i t N o p u l l u p P u l l u p P p u l l u p c o n t r o l b i t N o p u l l u p P u l l u p P p u l l u p c o n t r o l b i t N o p u l l u p P u l l u p P p u l l u p c o n t r o l b i t N o p u l l u p P u l l u p P p u l l u p c o n t r o l b i t N o p u l l u p P u l l u p b7 b0 Port P1 pull-up control register P10 pull-up control bit 0: No pull-up 1: Pull-up 1 pull-up control bit 0: No pull-up 1: Pull-up 2 pull-up control bit 0: No pull-up 1: Pull-up 3 pull-up control bit 0: No pull-up 1: Pull-up 4 pull-up control bit 0: No pull-up 1: Pull-up 5 pull-up control bit 0: No pull-up 1: Pull-up 6 pull-up control bit 0: No pull-up 1: Pull-up 7 pull-up control bit 0: No pull-up 1: Pull-up (PULL1: address 0FF1 16) ( P U L L 0 : a d d r e s s 0 F F 01 Note: Pull-up control is valid when the corresponding bit of the port direction register is “0” (input). When that bit is “1” (output), pull-up cannot be set to the port of which pull-up is selected. Note: Pull-up control is valid when the corresponding bit of the port direction register is “0” (input). When that bit is “1” (output), pull-up cannot be set to the port of which pull-up is selected.

Rev.1.01 Jan 25, 2005 page 19 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) Fig. 16 Structure of port pull-up control register (2) Port P2 pull-up control register b 7b 0 P 20 p u l l - u p c o n t r o l b i t N o p u l l u p P u l l u p P p u l l u p c o n t r o l b i t N o p u l l u p P u l l u p P p u l l u p c o n t r o l b i t N o p u l l u p P u l l u p P p u l l u p c o n t r o l b i t N o p u l l u p P u l l u p P p u l l u p c o n t r o l b i t N o p u l l u p P u l l u p P p u l l u p c o n t r o l b i t N o p u l l u p P u l l u p P p u l l u p c o n t r o l b i t N o p u l l u p P u l l u p P p u l l u p c o n t r o l b i t N o p u l l u p P u l l u p b7 b0 P o r t P 3 p u l l - u p c o n t r o l r e g i s t e r P30 pull-up control bit 0: No pull-up 1: Pull-up 1 pull-up control bit 0: No pull-up 1: Pull-up Not used (return “0” when read) 4 pull-up control bit 0: No pull-up 1: Pull-up 5 pull-up control bit 0: No pull-up 1: Pull-up 6 pull-up control bit 0: No pull-up 1: Pull-up 7 pull-up control bit 0: No pull-up 1: Pull-up (PULL3: address 0FF3 16) ( P U L L 2 : a d d r e s s 0 F F 21 N o t P u l l u p c o n t r o l i s v a l i d w h e n t h e c o r r e s p o n d i n g b i t o f t h e p o r t d i r e c t i o n r e g i s t e r i s i n p u t W h e n t h a t b i t i s o u t p u t p u l l u p c a n n o t b e s e t t o t h e p o r t o f w h i c h p u l l u p i s s e l e c t e d N o t e: P u l l - u p c o n t r o l i s v a l i d w h e n t h e c o r r e s p o n d i n g b i t o f t h e p o r t d i r e c t i o n r e g i s t e r i s i n p u t W h e n t h a t b i t i s o u t p u t p u l l u p c a n n o t b e s e t t o t h e p o r t o f w h i c h p u l l u p i s s e l e c t e d

Rev.1.01 Jan 25, 2005 page 20 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) Fig. 17 Structure of port pull-up control register (3) Port P4 pull-up control register b 7b 0 P 40 p u l l - u p c o n t r o l b i t N o p u l l u p P u l l u p P p u l l u p c o n t r o l b i t N o p u l l u p P u l l u p P p u l l u p c o n t r o l b i t N o p u l l u p P u l l u p P p u l l u p c o n t r o l b i t N o p u l l u p P u l l u p P p u l l u p c o n t r o l b i t N o p u l l u p P u l l u p P p u l l u p c o n t r o l b i t N o p u l l u p P u l l u p P p u l l u p c o n t r o l b i t N o p u l l u p P u l l u p P p u l l u p c o n t r o l b i t N o p u l l u p P u l l u p b 7b 0 P o r t P 5 p u l l - u p c o n t r o l r e g i s t e r P 50 p u l l - u p c o n t r o l b i t N o p u l l u p P u l l u p P p u l l u p c o n t r o l b i t N o p u l l u p P u l l u p P p u l l u p c o n t r o l b i t N o p u l l u p P u l l u p P p u l l u p c o n t r o l b i t N o p u l l u p P u l l u p P p u l l u p c o n t r o l b i t N o p u l l u p P u l l u p P p u l l u p c o n t r o l b i t N o p u l l u p P u l l u p P p u l l u p c o n t r o l b i t N o p u l l u p P u l l u p P p u l l u p c o n t r o l b i t N o p u l l u p P u l l u p (PULL5: address 0FF516) ( P U L L 4 : a d d r e s s 0 F F 41 Note: Pull-up control is valid when the corresponding bit of the port direction register is “0” (input). When that bit is “1” (output), pull-up cannot be set to the port of which pull-up is selected. Note: Pull-up control is valid when the corresponding bit of the port direction register is “0” (input). When that bit is “1” (output), pull-up cannot be set to the port of which pull-up is selected.

Rev.1.01 Jan 25, 2005 page 21 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) Fig. 18 Structure of port pull-up control register (4) P o r t P 6 p u l l - u p c o n t r o l r e g i s t e r b 7b 0 P 60 p u l l - u p c o n t r o l b i t N o p u l l u p P u l l u p P p u l l u p c o n t r o l b i t N o p u l l u p P u l l u p P p u l l u p c o n t r o l b i t N o p u l l u p P u l l u p P p u l l u p c o n t r o l b i t N o p u l l u p P u l l u p P p u l l u p c o n t r o l b i t N o p u l l u p P u l l u p P p u l l u p c o n t r o l b i t N o p u l l u p P u l l u p P p u l l u p c o n t r o l b i t N o p u l l u p P u l l u p P p u l l u p c o n t r o l b i t N o p u l l u p P u l l u p ( P U L L 6 : a d d r e s s 0 F F 61 Note: Pull-up control is valid when the corresponding bit of the port direction register is “0” (input). When that bit is “1” (output), pull-up cannot be set to the port of which pull-up is selected.

Rev.1.01 Jan 25, 2005 page 22 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) INTERRUPTS The 3804 group (Spaec. H)’s interrupts are a type of vector and occur by 16 sources among 23 sources: nine external, thirteen in- ternal, and one software. Interrupt Control Each interrupt is controlled by an interrupt request bit, an interrupt enable bit, and the interrupt disable flag except for the software in- terrupt set by the BRK instruction. An interrupt occurs if the corresponding interrupt request and enable bits are “1” and the in- terrupt disable flag is “0”. Interrupt enable bits can be set or cleared by software. Interrupt request bits can be cleared by software, but cannot be set by software. The reset and the BRK instruction cannot be disabled with any flag or bit. The I (interrupt disable) flag disables all interrupts ex- cept the reset and the BRK instruction interrupt. When several interrupt requests occur at the same time, the inter- rupts are received according to priority. Interrupt Operation By acceptance of an interrupt, the following operations are auto- matically performed: 1. The contents of the program counter and the processor status register are automatically pushed onto the stack. 2. The interrupt disable flag is set and the corresponding interrupt request bit is cleared. 3. The interrupt jump destination address is read from the vector table into the program counter. Interrupt Source Selection Which of each combination of the following interrupt sources can be selected by the interrupt source selection register (address 0039 16). 1. INT0 or Timer Z 2. Serial I/O1 transmission or SCL, SDA 3. CNTR 0 or SCL, SDA 4. CNTR1 or Serial I/O3 reception 5. Serial I/O2 or Timer Z 6. INT 2 or I2C 7. INT4 or CNTR2 8. A/D converter or serial I/O3 transmission External Interrupt Pin Selection The occurrence sources of the external interrupt INT0 and INT4 can be selected from either input from INT00 and INT40 pin, or in- put from INT01 and INT41 pin by the INT0, INT4 interrupt switch bit of interrupt edge selection register (bit 6 of address 003A16). I Notes When setting the followings, the interrupt request bit may be set to “1”.

• When setting external interrupt active edge Related register: Interrupt edge selection register (address 003A16) Timer XY mode register (address 002316) Timer Z mode register (address 002A16) I2C START/STOP condition control register (address 001616)
• When switching interrupt sources of an interrupt vector address where two or more interrupt sources are allocated Related register: Interrupt source selection register (address 003916) When not requiring for the interrupt occurrence synchronized with these setting, take the following sequence. ➀ Set the corresponding interrupt enable bit to “0” (disabled). ➁ Set the interrupt edge select bit or the interrupt source select bit to “1”. ➂ Set the corresponding interrupt request bit to “0” after 1 or more instructions have been executed. { Set the corresponding interrupt enable bit to “1” (enabled).

Rev.1.01 Jan 25, 2005 page 23 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) Interrupt Request Generating Conditions RemarksInterrupt Source Low FFFC 16 FFFA 16 High FFFD 16 FFFB 16 Priority Table 6 Interrupt vector addresses and priority Notes 1: Vector addresses contain interrupt jump destination addresses. 2: Reset function in the same way as an interrupt with the highest priority. Vector Addresses (Note 1) Reset (Note 2) INT0 Timer Z INT Serial I/O1 reception Serial I/O1 transmission At reset At detection of either rising or falling edge of INT0 input At timer Z underflow At detection of either rising or falling edge of INT1 input At completion of serial I/O1 data reception At completion of serial I/O1 transmission shift or when transmission buffer is empty At detection of either rising or falling edge of SCL or SDA At timer X underflow At timer Y underflow At timer 1 underflow At timer 2 underflow At detection of either rising or falling edge of CNTR 0 input At detection of either rising or falling edge of SCL or SDA At detection of either rising or falling edge of CNTR1 input At completion of serial I/O3 data reception At completion of serial I/O2 data transmission or reception At timer Z underflow At detection of either rising or falling edge of INT 2 input At completion of data transfer At detection of either rising or falling edge of INT3 input At detection of either rising or falling edge of INT4 input At detection of either rising or falling edge of CNTR2 input At completion of A/D conversion At completion of serial I/O3 transmission shift or when transmission buffer is empty At BRK instruction execution Non-maskable External interrupt (active edge selectable) External interrupt (active edge selectable) Valid when serial I/O1 is selected Valid when serial I/O1 is selected FFF8 FFF6 16 FFF4 16 FFF2 16 FFF0 16 FFEE 16 FFEC 16 FFEA 16 FFF9 16 FFF7 16 FFF5 16 FFF3 16 FFF1 16 FFEF 16 FFED 16 FFEB 16 Timer X Timer Y Timer 1 Timer 2 CNTR SCL, SDA CNTR 1 Serial I/O3 reception Serial I/O2 Timer Z INT2 I2C INT3 STP release timer underflow External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) Valid when serial I/O3 is selected Valid when serial I/O2 is selected External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) Valid when serial I/O3 is selected Non-maskable software interrupt

11 FFE9 16 FFE8 16

(active edge selectable) SCL, SDA

Rev.1.01 Jan 25, 2005 page 24 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) Fig. 19 Interrupt control Interrupt disable flag (I) Interrupt request Interrupt request bit Interrupt enable bit BRK instruction Reset

Rev.1.01 Jan 25, 2005 page 25 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) Fig. 20 Structure of interrupt-related registers I n t e r r u p t e d g e s e l e c t i o n r e g i s t e r I N T0 a c t i v e e d g e s e l e c t i o n b i t I N a c t i v e e d g e s e l e c t i o n b i t N o t u s e d r e t u r n s w h e n r e a d I N a c t i v e e d g e s e l e c t i o n b i t I N a c t i v e e d g e s e l e c t i o n b i t I N a c t i v e e d g e s e l e c t i o n b i t I N T0, I N i n t e r r u p t s w i t c h b i t I N I N i n t e r r u p t I N I N i n t e r r u p t N o t u s e d r e t u r n s w h e n r e a d ( I N T E D G E : a d d r e s s 0 0 3 A1 I n t e r r u p t r e q u e s t r e g i s t e r 1 I N T0/ T i m e r Z i n t e r r u p t r e q u e s t b i t I N i n t e r r u p t r e q u e s t b i t S e r i a l I O r e c e i v e i n t e r r u p t r e q u e s t b i t S e r i a l I O t r a n s m i t S C L S D A i n t e r r u p t r e q u e s t b i t T i m e r X i n t e r r u p t r e q u e s t b i t T i m e r Y i n t e r r u p t r e q u e s t b i t T i m e r i n t e r r u p t r e q u e s t b i t T i m e r i n t e r r u p t r e q u e s t b i t I n t e r r u p t c o n t r o l r e g i s t e r 1 0 : N o i n t e r r u p t r e q u e s t i s s u e d I n t e r r u p t r e q u e s t i s s u e d ( I R E Q 1 : a d d r e s s 0 0 3 C 1 ( I C O N 1 : a d d r e s s 0 0 3 E1 I n t e r r u p t r e q u e s t r e g i s t e r 2 C N T R 0/ S C L , S D A i n t e r r u p t r e q u e s t b i t C N T R 1/ S e r i a l I O r e c e i v e i n t e r r u p t r e q u e s t b i t S e r i a l I O T i m e r Z i n t e r r u p t r e q u e s t b i t I N T2/ I2C i n t e r r u p t r e q u e s t b i t I N i n t e r r u p t r e q u e s t b i t I N T4/C N T R 2 i n t e r r u p t r e q u e s t b i t A D c o n v e r t e r S e r i a l I O t r a n s m i t i n t e r r u p t r e q u e s t b i t N o t u s e d r e t u r n s w h e n r e a d ( I R E Q 2 : a d d r e s s 0 0 3 D 1 I n t e r r u p t c o n t r o l r e g i s t e r 2 0 : I n t e r r u p t s d i s a b l e d I n t e r r u p t s e n a b l e d ( I C O N 2 : a d d r e s s 0 0 3 F1 0 : F a l l i n g e d g e a c t i v e R i s i n g e d g e a c t i v e 0 : F a l l i n g e d g e a c t i v e R i s i n g e d g e a c t i v e C N T R 0/ S C L , S D A i n t e r r u p t e n a b l e b i t C N T R 1/ S e r i a l I O r e c e i v e i n t e r r u p t e n a b l e b i t S e r i a l I O T i m e r Z i n t e r r u p t e n a b l e b i t I N T2/ I2C i n t e r r u p t e n a b l e b i t I N i n t e r r u p t e n a b l e b i t I N T4/C N T R 2 i n t e r r u p t e n a b l e b i t A D c o n v e r t e r S e r i a l I O t r a n s m i t i n t e r r u p t e n a b l e b i t N o t u s e d r e t u r n s w h e n r e a d I N T0/ T i m e r Z i n t e r r u p t e n a b l e b i t I N i n t e r r u p t e n a b l e b i t S e r i a l I O r e c e i v e i n t e r r u p t e n a b l e b i t S e r i a l I O t r a n s m i t S C L S D A i n t e r r u p t e n a b l e b i t T i m e r X i n t e r r u p t e n a b l e b i t T i m e r Y i n t e r r u p t e n a b l e b i t T i m e r i n t e r r u p t e n a b l e b i t T i m e r i n t e r r u p t e n a b l e b i t b 7 I n t e r r u p t s o u r c e s e l e c t i o n r e g i s t e rb b 7 b 0 b 7 b 0 b 7 b 0 b 7 b 0 b 7 b 0 I N T0/ T i m e r Z i n t e r r u p t s o u r c e s e l e c t i o n b i t I N T0 i n t e r r u p t T i m e r Z i n t e r r u p t S e r i a l I O T i m e r Z i n t e r r u p t s o u r c e s e l e c t i o n b i t S e r i a l I O 2 i n t e r r u p t T i m e r Z i n t e r r u p t S e r i a l I O t r a n s m i t S C L S D A i n t e r r u p t s o u r c e s e l e c t i o n b i t S e r i a l I O t r a n s m i t i n t e r r u p t S C L S D A i n t e r r u p t C N T R 0/ S C L S D A i n t e r r u p t s o u r c e s e l e c t i o n b i t C N T R 0 i n t e r r u p t S C L S D A i n t e r r u p t I N T4/ C N T R 2 i n t e r r u p t s o u r c e s e l e c t i o n b i t I N T4 i n t e r r u p t C N T R 2 i n t e r r u p t I N T2/ I2C i n t e r r u p t s o u r c e s e l e c t i o n b i t I N i n t e r r u p t I2C i n t e r r u p t C N T R 1/ S e r i a l I O r e c e i v e i n t e r r u p t s o u r c e s e l e c t i o n b i t C N T R 1 i n t e r r u p t S e r i a l I O r e c e i v e i n t e r r u p t A D c o n v e r t e r S e r i a l I O t r a n s m i t i n t e r r u p t s o u r c e s e l e c t i o n b i t A D c o n v e r t e r i n t e r r u p t S e r i a l I O t r a n s m i t i n t e r r u p t ( D o n o t w r i t e “ 1 ” t o t h e s e b i t s s i m u l t a n e o u s l y . ) ( I N T S E L : a d d r e s s 0 0 3 91 ( D o n o t w r i t e “ 1 ” t o t h e s e b i t s s i m u l t a n e o u s l y . )

Rev.1.01 Jan 25, 2005 page 26 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) TIMERS G 8-bit Timers The 3804 group (Spec. H) has four 8-bit timers: timer 1, timer 2, timer X, and timer Y . The timer 1 and timer 2 use one prescaler in common, and the timer X and timer Y use each prescaler. Those are 8-bit prescalers. Each of the timers and prescalers has a timer latch or a prescaler latch. The division ratio of each timer or prescaler is given by 1/(n + 1), where n is the value in the corresponding timer or prescaler latch. All timers are down-counters. When the timer reaches “00 16”, an underflow occurs at the next count pulse and the contents of the corresponding timer latch are reloaded into the timer and the count is continued. When the timer underflows, the interrupt re- quest bit corresponding to that timer is set to “1”. G Timer divider The divider count source is switched by the main clock division ratio selection bits of CPU mode register (bits 7 and 6 at address 003B 16). When these bits are “00” (high-speed mode) or “01” (middle-speed mode), XIN is selected. When these bits are“10” (low-speed mode), XCIN is selected. G Prescaler 12 The prescaler 12 counts the output of the timer divider. The count source is selected by the timer 12, X count source selection 1/1024 of f(X IN) or f(XCIN). Timer 1 and Timer 2 The timer 1 and timer 2 counts the output of prescaler 12 and pe- riodically set the interrupt request bit. G Prescaler X and prescaler Y The prescaler X and prescaler Y count the output of the timer divider or f(X CIN). The count source is selected by the timer 12, X count source selection register (address 000E16) and the timer Y, Z count source selection register (address 000F16) among 1/2, or f(XCIN); and f(XCIN). Timer X and Timer Y The timer X and timer Y can each select one of four operating modes by setting the timer XY mode register (address 002316). (1) Timer mode G Mode selection This mode can be selected by setting “00” to the timer X operating mode bits (bits 1 and 0) and the timer Y operating mode bits (bits 5 and 4) of the timer XY mode register (address 002316). G Explanation of operation The timer count operation is started by setting “0” to the timer X count stop bit (bit 3) and the timer Y count stop bit (bit 7) of the timer XY mode register (address 0023 16). When the timer reaches “0016”, an underflow occurs at the next count pulse and the contents of timer latch are reloaded into the timer and the count is continued. (2) Pulse output mode G Mode selection This mode can be selected by setting “01” to the timer X operating mode bits (bits 1 and 0) and the timer Y operating mode bits (bits 5 and 4) of the timer XY mode register (address 0023 16). G Explanation of operation The operation is the same as the timer mode’s. Moreover the pulse which is inverted each time the timer underflows is output from CNTR 0/CNTR 1 pin. Regardless of the timer counting or not the output of CNTR0/CNTR 1 pin is initialized to the level of speci- fied by their active edge switch bits when writing to the timer. When the CNTR 0 active edge switch bit (bit 2) and the CNTR1 ac- tive edge switch bit (bit 6) of the timer XY mode register (address 0023 16) is “0”, the output starts with “H ” level. When it is “1”, the output starts with “L” level. Switching the CNTR0 or CNTR1 active edge switch bit will reverse the output level of the corresponding CNTR0 or CNTR1 pin. I Precautions Set the double-function port of CNTR0/CNTR 1 pin and port P54/ P55 to output in this mode.

Rev.1.01 Jan 25, 2005 page 27 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) (3) Event counter mode G Mode selection This mode can be selected by setting “10” to the timer X operating mode bits (bits 1 and 0) and the timer Y operating mode bits (bits 5 and 4) of the timer XY mode register (address 0023 16). G Explanation of operation The operation is the same as the timer mode’s except that the timer counts signals input from the CNTR0 or CNTR 1 pin. The valid edge for the count operation depends on the CNTR0 active edge switch bit (bit 2) or the CNTR1 active edge switch bit (bit 6) of the timer XY mode register (address 002316). When it is “0”, the rising edge is valid. When it is “1”, the falling edge is valid. I Precautions Set the double-function port of CNTR0/CNTR 1 pin and port P54/ P55 to input in this mode. (4) Pulse width measurement mode G Mode selection This mode can be selected by setting “11” to the timer X operating mode bits (bits 1 and 0) and the timer Y operating mode bits (bits 5 and 4) of the timer XY mode register (address 0023 16). G Explanation of operation When the CNTR 0 active edge switch bit (bit 2) or the CNTR1 ac- tive edge switch bit (bit 6) of the timer XY mode register (address 002316) is “1”, the timer counts during the term of one falling edge of CNTR 0/CNTR 1 pin input until the next rising edge of input (“L” term). When it is “0”, the timer counts during the term of one rising edge input until the next falling edge input (“H ” term). I Precautions Set the double-function port of CNTR0/CNTR 1 pin and port P54/ P55 to input in this mode. The count operation can be stopped by setting “1” to the timer X count stop bit (bit 3) and the timer Y count stop bit (bit 7) of the timer XY mode register (address 0023 16). The interrupt request bit is set to “1” each time the timer underflows.

• Precautions when switching count source When switching the count source by the timer 12, X and Y count source selection bits, the value of timer count is altered in incon- siderable amount owing to generating of thin pulses on the count input signals. Therefore, select the timer count source before setting the value to the prescaler and the timer.

Rev.1.01 Jan 25, 2005 page 28 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) Fig. 21 Block diagram of timer X, timer Y, timer 1, and timer 2 Q Q “1” “0” P 54/ C N T R 0 Q Q P 55/ C N T R 1 “0 ” “ 1 ” R R T T f(XCIN) f ( XC I N ) C l o c k f o r t i m e r 1 2 XI N XC I N ( 1 / 2 , 1 / 4 , 1 / 8 , 1 / 1 6 , 1 / 3 2 , 1 / 6 4 , 1 / 1 2 8 , 1 / 2 5 6 , 1 / 5 1 2 , 1 / 1 0 2 4 ) D i v i d e rC l o c k f o r t i m e r Y C l o c k f o r t i m e r X Count source selection bit C N T R 0 a c t i v e e d g e s w i t c h b i t Port P54 direction register P u l s e o u t p u t m o d e Port P54 latch C N T R 0 a c t i v e e d g e s w i t c h b i t T o g g l e f l i p - f l o p P u l s e w i d t h m e a s u r e m e n t m o d e T i m e r m o d e P u l s e o u t p u t m o d e Timer X count stop bit P r e s c a l e r X ( 8 ) Prescaler X latch (8) Data bus Timer X latch (8) T i m e r X ( 8 ) T o t i m e r X i n t e r r u p t r e q u e s t b i t T o C N T R 0 i n t e r r u p t r e q u e s t b i t T i m e r X l a t c h w r i t e p u l s e P u l s e o u t p u t m o d e Clock for timer Y C o u n t s o u r c e s e l e c t i o n b i t E v e n t c o u n t e r m o d e P u l s e w i d t h m e a s u r e m e n t m o d e T i m e r m o d e P u l s e o u t p u t m o d e Timer Y count stop bitEvent counter mode“0 ” “1” CNTR 1 active edge switch bit Prescaler Y (8) P r e s c a l e r Y l a t c h ( 8 ) D a t a b u s Timer Y latch (8) T i m e r Y ( 8 ) T o t i m e r Y i n t e r r u p t r e q u e s t b i t T o C N T R 1 i n t e r r u p t r e q u e s t b i t Port P55 direction register Pulse output mode Port P55 latch “1” “0” CNTR 1 active edge switch bit T o g g l e f l i p - f l o p Timer Y latch write pulse Pulse output mode T i m e r 2 l a t c h ( 8 ) Timer 2 (8) T o t i m e r 2 i n t e r r u p t r e q u e s t b i t T o t i m e r 1 i n t e r r u p t r e q u e s t b i t Clock for timer 12 P r e s c a l e r 1 2 ( 8 ) P r e s c a l e r 1 2 l a t c h ( 8 ) Data bus T i m e r 1 l a t c h ( 8 ) Timer 1 (8) “ 0 0 ” “ 1 0 ” M a i n c l o c k d i v i s i o n r a t i o s e l e c t i o n b i t s

Rev.1.01 Jan 25, 2005 page 29 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) Fig. 22 Structure of timer XY mode register T i m e r X Y m o d e r e g i s t e r T M a d d r e s s T i m e r X o p e r a t i n g m o d e b i t s b T i m e r m o d e P u l s e o u t p u t m o d e E v e n t c o u n t e r m o d e P u l s e w i d t h m e a s u r e m e n t m o d e C N T R 0 a c t i v e e d g e s w i t c h b i t I n t e r r u p t a t f a l l i n g e d g e C o u n t a t r i s i n g e d g e i n e v e n t c o u n t e r m o d e I n t e r r u p t a t r i s i n g e d g e C o u n t a t f a l l i n g e d g e i n e v e n t c o u n t e r m o d e T i m e r X c o u n t s t o p b i t C o u n t s t a r t C o u n t s t o p T i m e r Y o p e r a t i n g m o d e b i t s b T i m e r m o d e P u l s e o u t p u t m o d e E v e n t c o u n t e r m o d e P u l s e w i d t h m e a s u r e m e n t m o d e C N T R 1 a c t i v e e d g e s w i t c h b i t I n t e r r u p t a t f a l l i n g e d g e C o u n t a t r i s i n g e d g e i n e v e n t c o u n t e r m o d e I n t e r r u p t a t r i s i n g e d g e C o u n t a t f a l l i n g e d g e i n e v e n t c o u n t e r m o d e T i m e r Y c o u n t s t o p b i t C o u n t s t a r t C o u n t s t o p b 7 b 0

Rev.1.01 Jan 25, 2005 page 30 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) Fig. 23 Structure of timer 12, X and timer Y, Z count source selection registers Timer 12 count source selection bits b3b2b1b0 0000 : f ( XIN)/2 or f(XCIN)/2 0001 : f ( XIN)/4 or f(XCIN)/4 0010 : f ( XIN)/8 or f(XCIN)/8 0011 : f ( XIN)/16 or f(XCIN)/16 0100 : f ( XIN)/32 or f(XCIN)/32 0101 : f ( XIN)/64 or f(XCIN)/64 0110 : f ( XIN)/128 or f(XCIN)/128 0111 : f ( XIN)/256 or f(XCIN)/256 1000 : f ( XIN)/512 or f(XCIN)/512 1001 : f(XIN)/1024 or f(XCIN)/1024 Timer 12, X count source selection register (T12XCSS : address 000E16) b 7 b 0 Timer X count source selection bits b7b6b5b4 0000 : f ( XIN)/2 or f(XCIN)/2 1011 : 0001 : f ( XIN)/4 or f(XCIN)/4 1100 : 0010 : f ( XIN)/8 or f(XCIN)/8 1101 : Not used 0011 : f ( XIN)/16 or f(XCIN)/16 1110 : 0100 : f ( XIN)/32 or f(XCIN)/32 1111 : 0101 : f ( XIN)/64 or f(XCIN)/64 0110 : f ( XIN)/128 or f(XCIN)/128 0111 : f ( XIN)/256 or f(XCIN)/256 1000 : f ( XIN)/512 or f(XCIN)/512 1001 : f ( XIN)/1024 or f(XCIN)/1024 1010 : f(XCIN) Timer Y, Z count source selection register (TYZCSS : address 000F16) Timer Y count source selection bits b3b2b1b0 0000 : f ( XIN)/2 or f(XCIN)/2 0001 : f ( XIN)/4 or f(XCIN)/4 0010 : f ( XIN)/8 or f(XCIN)/8 0011 : f ( XIN)/16 or f(XCIN)/16 0100 : f ( XIN)/32 or f(XCIN)/32 0101 : f ( XIN)/64 or f(XCIN)/64 0110 : f ( XIN)/128 or f(XCIN)/128 0111 : f ( XIN)/256 or f(XCIN)/256 1000 : f ( XIN)/512 or f(XCIN)/512 1001 : f ( XIN)/1024 or f(XCIN)/1024 1010 : f(XCIN) b 7 b0 Timer Z count source selection bits b7b6b5b4 0000 : f ( XIN)/2 or f(XCIN)/2 1011 : 0001 : f ( XIN)/4 or f(XCIN)/4 1100 : 0010 : f ( XIN)/8 or f(XCIN)/8 1101 : Not used 0011 : f ( XIN)/16 or f(XCIN)/16 1110 : 0100 : f ( XIN)/32 or f(XCIN)/32 1111 : 0101 : f ( XIN)/64 or f(XCIN)/64 0110 : f ( XIN)/128 or f(XCIN)/128 0111 : f ( XIN)/256 or f(XCIN)/256 1000 : f ( XIN)/512 or f(XCIN)/512 1001 : f ( XIN)/1024 or f(XCIN)/1024 1010 : f(XCIN) 1 0 1 1 : N o t u s e d 1010 : 1011 : 1100 : 1101 : 1110 : 1111 : N o t u s e d

Rev.1.01 Jan 25, 2005 page 34 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) Fig. 24 Block diagram of timer Z “1” “0” P42/INT1 P47/CNTR 2 “0” “1” “001” “100” “101” f(XCIN) XIN XCIN Output level latch Programmable one-shot generating mode Programmable one-shot generating circuit CNTR 2 active edge switch bit Programmable one-shot generating mode Data bus To timer Z interrupt request bit To CNTR 2 interrupt request bit To INT1 interrupt request bitProgrammable waveform generating mode Pulse output mode CNTR 2 active edge switch bit Pulse output mode Timer Z low-order latch Timer Z low-order Timer Z high-order latch Timer Z high-order Timer Z operating mode bits Port P47 direction register Port P47 latch Pulse period measurement mode Pulse width measurement mode Edge detection circuit Timer Z count stop bit Count source selection bit Divider Clock for timer Z CNTR 2 active edge switch bit D Q T TQ Q S “1” “0” “0” “1” Timer/Event counter mode switch bit

Rev.1.01 Jan 25, 2005 page 35 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) Fig. 25 Structure of timer Z mode register T i m e r Z m o d e r e g i s t e r T Z M a d d r e s s T i m e r Z o p e r a t i n g m o d e b i t s b b b 000 : T i m e r E v e n t c o u n t e r m o d e 001 : P u l s e o u t p u t m o d e 010 : P u l s e p e r i o d m e a s u r e m e n t m o d e 011 : P u l s e w i d t h m e a s u r e m e n t m o d e 100 : P r o g r a m m a b l e w a v e f o r m g e n e r a t i n g m o d e 101 : P r o g r a m m a b l e o n e s h o t g e n e r a t i n g m o d e 110 : N o t a v a i l a b l e 111 : N o t a v a i l a b l e T i m e r Z w r i t e c o n t r o l b i t W r i t i n g d a t a t o b o t h l a t c h a n d t i m e r s i m u l t a n e o u s l y W r i t i n g d a t a o n l y t o l a t c h O u t p u t l e v e l l a t c h L o u t p u t H o u t p u t C N T R 2 a c t i v e e d g e s w i t c h b i t E v e n t c o u n t e r m o d e C o u n t a t r i s i n g e d g e P u l s e o u t p u t m o d e S t a r t o u t p u t t i n g H P u l s e p e r i o d m e a s u r e m e n t m o d e M e a s u r e m e n t b e t w e e n t w o f a l l i n g e d g e s P u l s e w i d t h m e a s u r e m e n t m o d e M e a s u r e m e n t o f H t e r m P r o g r a m m a b l e o n e s h o t g e n e r a t i n g m o d e A f t e r s t a r t o u t p u t t i n g L H o n e s h o t p u l s e g e n e r a t e d I n t e r r u p t a t f a l l i n g e d g e E v e n t c o u n t e r m o d e C o u n t a t f a l l i n g e d g e P u l s e o u t p u t m o d e S t a r t o u t p u t t i n g L P u l s e p e r i o d m e a s u r e m e n t m o d e M e a s u r e m e n t b e t w e e n t w o r i s i n g e d g e s P u l s e w i d t h m e a s u r e m e n t m o d e M e a s u r e m e n t o f L t e r m P r o g r a m m a b l e o n e s h o t g e n e r a t i n g m o d e A f t e r s t a r t o u t p u t t i n g H L o n e s h o t p u l s e g e n e r a t e d I n t e r r u p t a t r i s i n g e d g e T i m e r Z c o u n t s t o p b i t C o u n t s t a r t C o u n t s t o p T i m e r E v e n t c o u n t e r m o d e s w i t c h b i t N o t e T i m e r m o d e E v e n t c o u n t e r m o d e b 7 b0 Note: When selecting the modes except the timer/event counter mode, set “0” to this bit.

Rev.1.01 Jan 25, 2005 page 36 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) Fig. 26 Timing chart of timer/event counter mode Fig. 27 Timing chart of pulse output mode F F F T L TR TR TR TL : Value set to timer latch TR : Timer interrupt request F F F T L T L V a l u e s e t t o t i m e r l a t c h T R T i m e r i n t e r r u p t r e q u e s t C N T R 2 C N T R 2 i n t e r r u p t r e q u e s t C N T R 2 a c t i v e e d g e s w i t c h b i t F a l l i n g e d g e a c t i v e TR T RT RT R W a v e f o r m o u t p u t f r o m C N T R 2 p i n CNTR 2 CNTR 2

Rev.1.01 Jan 25, 2005 page 37 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) Fig. 28 Timing chart of pulse period measurement mode (Measuring term between two rising edges) Fig. 29 Timing chart of pulse width measurement mode (Measuring “L” term) FFFF 16 T T RT R T T C N T R 2 C N T R 2 C N T R 2 CNTR 2 F F F 6 + T 1 T 2 T

3 FFFF 16

S i g n a l in p u t f r o m C N T R 2 p i n C N T R 2 o f r i s i n g e d g e a c t i v e T R T i m e r i n t e r r u p t r e q u e s t C N T R 2 C N T R 2 i n t e r r u p t r e q u e s t F F F T R T C N T R 2 C N T R 2 C N T R 2 F F F 6 + T

2 T1T3

CNTR 2 interrupt of rising edge active; Measurement of “L” width TR : Timer interrupt request CNTR 2 : CNTR2 interrupt request Signal input from CNTR 2 pin

Rev.1.01 Jan 25, 2005 page 38 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) Fig. 30 Timing chart of programmable waveform generating mode Fig. 31 Timing chart of programmable one-shot generating mode (“H ” one-shot pulse generating) F F F T T T2T L L T1 TR TR TR TR CNTR 2 C N T R 2 S i g n a l o u t p u t f r o m C N T R 2 p i n L : Timer initial value TR : Timer interrupt request CNTR 2 : CNTR2 interrupt request (CNTR 2 active edge switch bit = “0”; Falling edge active) F F F L L T RT RT R LL CNTR 2 CNTR 2 S i g n a l o u t p u t f r o m C N T R 2 p i n L : One-shot pulse width TR : Timer interrupt request CNTR 2 : CNTR2 interrupt request (CNTR 2 active edge switch bit = “0”; Falling edge active) Signal input from INT1 pin

Rev.1.01 Jan 25, 2005 page 39 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) SERIAL INTERFACE Serial I/O1 Serial I/O1 can be used as either clock synchronous or asynchro- nous (UART) serial I/O1. A dedicated timer is also provided for baud rate generation. (1) Clock Synchronous Serial I/O Mode Clock synchronous serial I/O1 mode can be selected by setting the serial I/O1 mode selection bit of the serial I/O1 control register (bit 6 of address 001A 16) to “1”. For clock synchronous serial I/O, the transmitter and the receiver must use the same clock. If an internal clock is used, transfer is started by a write signal to the transmit/receive buffer register. Fig. 32 Block diagram of clock synchronous serial I/O1 Fig. 33 Operation of clock synchronous serial I/O1 F / F P 46/ SC L K Serial I/O1 status register Serial I/O1 control register P47/SRDY1 P44/RXD 1 P45/TXD 1 Receive buffer register 1 Address 001816 R e c e i v e s h i f t r e g i s t e r 1 Receive buffer full flag (RBF) Receive interrupt request (RI) Clock control circuitShift clock S e r i a l I / O 1 s y n c h r o n o u s c l o c k s e l e c t i o n b i t F r e q u e n c y d i v i s i o n r a t i o n Baud rate generator 1 Address 001C16 B R G c o u n t s o u r c e s e l e c t i o n b i t Clock control circuitF a l l i n g - e d g e d e t e c t o r Transmit buffer register 1 Data bus Address 001816 Shift clock Transmit shift completion flag (TSC) Transmit buffer empty flag (TBE) Transmit interrupt request (TI) Transmit interrupt source selection bit Address 001916 D a t a b u s A d d r e s s 0 0 1 A1 T r a n s m i t s h i f t r e g i s t e r 1 f(XIN) ( f ( XC I N ) i n l o w - s p e e d m o d e ) D 7 D 7 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 0 D 1 D 2 D 3 D 4 D 5 D 6 RBF = 1 TSC = 1T B E = 0 T B E = 1 T S C T r a n s f e r s h i f t c l o c k t o o f t h e i n t e r n a l c l o c k o r a n e x t e r n a l c l o c k S e r i a l o u t p u t T x D 1 Serial input RxD1 W r i t e p u l s e t o r e c e i v e / t r a n s m i t b u f f e r r e g i s t e r a d d r e s s Overrun error (OE) detection Notes 1: As the transmit interrupt (TI), which can be selected, either when the transmit buffer has emptied (TBE=1) or after the transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O1 control register. 2: If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data is output continuously from the TxD pin. 3: The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” . R e c e i v e e n a b l e s i g n a l SR D Y

Rev.1.01 Jan 25, 2005 page 40 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) (2) Asynchronous Serial I/O (UART) Mode Clock asynchronous serial I/O mode (UART) can be selected by clearing the serial I/O1 mode selection bit of the serial I/O1 control register to “0”. Eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. The transmit and receive shift registers each have a buffer, but the two buffers have the same address in a memory. Since the shift register cannot be written to or read from directly, transmit data is written to the transmit buffer register, and receive data is read from the receive buffer register. The transmit buffer register can also hold the next data to be transmitted, and the receive buffer register can hold a character while the next character is being received.Fig. 34 Block diagram of UART serial I/O1 Fig. 35 Operation of UART serial I/O1 f(XIN) OE PE FE Data bus Receive buffer register 1 Address 001816 Receive shift register 1 Receive buffer full flag (RBF) Receive interrupt request (RI) Baud rate generator Frequency division ratio 1/(n+1) Address 001C16 ST/SP/PA generator Transmit buffer register 1 Data bus Transmit shift register 1 Address 001816 Transmit shift completion flag (TSC) Transmit buffer empty flag (TBE) Transmit interrupt request (TI) Address 001916 ST detector SP detector UART1 control register Address 001B16 Character length selection bit Address 001A16 BRG count source selection bit Transmit interrupt source selection bit Serial I/O1 synchronous clock selection bit Clock control circuit Character length selection bit 7 bits 8 bits Serial I/O1 control register P46/SCLK1 Serial I/O1 status register P44/RXD 1 P45/TXD 1 (f(XCIN) in low-speed mode) TSC=0 TBE=1 RBF=0 TBE=0 TBE=0 RBF=1 RBF=1 STD 0 D 1 SP D 0 D 1ST SP TBE=1 TSC=1 STD 0 D 1 SP D 0 D 1ST SP Transmit or receive clock Transmit buffer write signal Generated at 2nd bit in 2-stop-bit mode 1 start bit 7 or 8 data bit 1 or 0 parity bit 1 or 2 stop bit (s) 1: Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception). 2: As the transmit interrupt (TI), when either the TBE or TSC flag becomes “1,” can be selected to occur depending on the setting of the transmit interrupt source selection bit (TIC) of the serial I/O1 control register. 3: The receive interrupt (RI) is set when the RBF flag becomes “1.” 4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle are necessary until changing to TSC=0. Notes Serial output TXD 1 Serial input RXD 1 Receive buffer read signal

Rev.1.01 Jan 25, 2005 page 41 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) [Serial I/O1 Control Register (SIO1CON)] 001A 16 The serial I/O1 control register consists of eight control bits for the serial I/O1 function. [UART1 Control Register (UART1CON)] 001B 16 The UART control register consists of four control bits (bits 0 to 3) which are valid when asynchronous serial I/O is selected and set the data format of an data transfer, and one bit (bit 4) which is al- ways valid and sets the output structure of the P4 5/TXD 1 pin. [Serial I/O1 Status Register (SIO1STS)] 001916 The read-only serial I/O1 status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial I/O1 function and various errors. Three of the flags (bits 4 to 6) are valid only in UART mode. The receive buffer full flag (bit 1) is cleared to “0” when the receive buffer register is read. If there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer reg- ister, and the receive buffer full flag is set. A write to the serial I/O1 status register clears all the error flags OE, PE, FE, and SE (bit 3 to bit 6, respectively). Writing “0” to the serial I/O1 enable bit SIOE (bit 7 of the serial I/O1 control register) also clears all the status flags, including the error flags. Bits 0 to 6 of the serial I/O1 status register are initialized to “0” at reset, but if the transmit enable bit (bit 4) of the serial I/O1 control register has been set to “1”, the transmit shift completion flag (bit 2) and the transmit buffer empty flag (bit 0) become “1”. [Transmit Buffer Register 1/Receive Buffer Register 1 (TB1/RB1)] 001816 The transmit buffer register 1 and the receive buffer register 1 are located at the same address. The transmit buffer is write-only and the receive buffer is read-only. If a character bit length is 7 bits, the MSB of data stored in the receive buffer is “0”. [Baud Rate Generator 1 (BRG1)] 001C16 The baud rate generator determines the baud rate for serial trans- fer. The baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate genera- tor.

Rev.1.01 Jan 25, 2005 page 42 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) Fig. 36 Structure of serial I/O1 control registers b 7b 7 T r a n s m i t b u f f e r e m p t y f l a g T B E B u f f e r f u l l B u f f e r e m p t y R e c e i v e b u f f e r f u l l f l a g R B F B u f f e r e m p t y B u f f e r f u l l T r a n s m i t s h i f t c o m p l e t i o n f l a g T S C T r a n s m i t s h i f t i n p r o g r e s s T r a n s m i t s h i f t c o m p l e t e d O v e r r u n e r r o r f l a g O E N o e r r o r O v e r r u n e r r o r P a r i t y e r r o r f l a g P E N o e r r o r P a r i t y e r r o r F r a m i n g e r r o r f l a g F E N o e r r o r F r a m i n g e r r o r S u m m i n g e r r o r f l a g S E O E U P E U F E O E U P E U F E N o t u s e d r e t u r n s w h e n r e a d S e r i a l I O s t a t u s r e g i s t e r Serial I/O1 control register b 0 b 0 BRG count source selection bit (CSS) 0: f(XIN) (f(XCIN) in low-speed mode) 1: f(XIN)/4 (f(XCIN)/4 in low-speed mode) Serial I/O1 synchronous clock selection bit (SCS) 0: BRG output divided by 4 when clock synchronous serial I/O is selected, BRG output divided by 16 when UART is selected. 1: External clock input when clock synchronous serial I/O is selected, external clock input divided by 16 when UART is selected. S RDY1 output enable bit (SRDY) 0: P47 pin operates as normal I/O pin 1: P47 pin operates as SRDY1 output pin Transmit interrupt source selection bit (TIC) 0: Interrupt when transmit buffer has emptied 1: Interrupt when transmit shift operation is completed Transmit enable bit (TE) 0: Transmit disabled 1: Transmit enabled Receive enable bit (RE) 0: Receive disabled 1: Receive enabled Serial I/O1 mode selection bit (SIOM) 0: Clock asynchronous (UART) serial I/O 1: Clock synchronous serial I/O Serial I/O1 enable bit (SIOE) 0: Serial I/O1 disabled (pins P4 4 to P47 operate as normal I/O pins) 1: Serial I/O1 enabled (pins P44 to P47 operate as serial I/O pins) b 7 U A R T c o n t r o l r e g i s t e r C h a r a c t e r l e n g t h s e l e c t i o n b i t C H A S b i t s b i t s P a r i t y e n a b l e b i t P A R E P a r i t y c h e c k i n g d i s a b l e d P a r i t y c h e c k i n g e n a b l e d P a r i t y s e l e c t i o n b i t P A R S E v e n p a r i t y O d d p a r i t y S t o p b i t l e n g t h s e l e c t i o n b i t S T P S s t o p b i t s t o p b i t s P 45/ TXD 1 P c h a n n e l o u t p u t d i s a b l e b i t P O F F C M O S o u t p u t i n o u t p u t m o d e N c h a n n e l o p e n d r a i n o u t p u t i n o u t p u t m o d e N o t u s e d r e t u r n w h e n r e a d b 0 S I O S T S a d d r e s s (SIO1CON : address 001A16) (UART1CON : address 001B16)

Rev.1.01 Jan 25, 2005 page 43 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) 2. Notes when selecting clock asynchronous serial I/O

2.1 Stop of transmission operation

Clear the transmit enable bit to “0” (transmit disabled). The trans- mission operation does not stop by clearing the serial I/O1 enable bit to “0”. G Reason Since transmission is not stopped and the transmission circuit is not initialized even if only the serial I/O1 enable bit is cleared to “0” (serial I/O disabled), the internal transmission is running (in this case, since pins TxD1, RxD1, S CLK1 , and SRDY1 function as I/O ports, the transmission data is not output). When data is written to the transmit buffer register in this state, data starts to be shifted to the transmit shift register. When the serial I/O1 enable bit is set to “1” at this time, the data during internally shifting is output to the TxD1 pin and an operation failure occurs.

2.2 Stop of receive operation

Clear the receive enable bit to “0” (receive disabled).

2.3 Stop of transmit/receive operation

G Note 1 (only transmission operation is stopped) Clear the transmit enable bit to “0” (transmit disabled). The trans- mission operation does not stop by clearing the serial I/O1 enable bit to “0”. G Reason Since transmission is not stopped and the transmission circuit is not initialized even if only the serial I/O1 enable bit is cleared to “0” (serial I/O disabled), the internal transmission is running (in this case, since pins TxD 1, RxD1, SCLK1 , and SRDY1 function as I/O ports, the transmission data is not output). When data is written to the transmit buffer register in this state, data starts to be shifted to the transmit shift register. When the serial I/O1 enable bit is set to “1” at this time, the data during internally shifting is output to the TxD 1 pin and an operation failure occurs. G Note 2 (only receive operation is stopped) Clear the receive enable bit to “0” (receive disabled). I Notes concerning serial I/O1 1. Notes when selecting clock synchronous serial I/O

1.1 Stop of transmission operation

Clear the serial I/O1 enable bit and the transmit enable bit to “0” (serial I/O and transmit disabled). G Reason Since transmission is not stopped and the transmission circuit is not initialized even if only the serial I/O1 enable bit is cleared to “0” (serial I/O disabled), the internal transmission is running (in this case, since pins TxD1, RxD1, S CLK1 , and SRDY1 function as I/O ports, the transmission data is not output). When data is written to the transmit buffer register in this state, data starts to be shifted to the transmit shift register. When the serial I/O1 enable bit is set to “1” at this time, the data during internally shifting is output to the TxD1 pin and an operation failure occurs.

1.2 Stop of receive operation

Clear the receive enable bit to “0” (receive disabled), or clear the serial I/O1 enable bit to “0” (serial I/O disabled).

1.3 Stop of transmit/receive operation

Clear both the transmit enable bit and receive enable bit to “0” (transmit and receive disabled). (when data is transmitted and received in the clock synchronous serial I/O mode, any one of data transmission and reception can- not be stopped.) G Reason In the clock synchronous serial I/O mode, the same clock is used for transmission and reception. If any one of transmission and re- ception is disabled, a bit error occurs because transmission and reception cannot be synchronized. In this mode, the clock circuit of the transmission circuit also oper- ates for data reception. Accordingly, the transmission circuit does not stop by clearing only the transmit enable bit to “0” (transmit disabled). Also, the transmission circuit is not initialized by clear- ing the serial I/O1 enable bit to “0” (serial I/O disabled) (refer to 1.1).

Rev.1.01 Jan 25, 2005 page 44 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) 3. SRDY1 output of reception side G Note When signals are output from the SRDY1 pin on the reception side by using an external clock in the clock synchronous serial I/O mode, set all of the receive enable bit, the S RDY1 output enable bit, and the transmit enable bit to “1” (transmit enabled). 4. Setting serial I/O1 control register again G Note Set the serial I/O1 control register again after the transmission and the reception circuits are reset by clearing both the transmit en- able bit and the receive enable bit to “0.” 5. Data transmission control with referring to transmit shift register completion flag G Note After the transmit data is written to the transmit buffer register, the transmit shift register completion flag changes from “1” to “0” with a delay of 0.5 to 1.5 shift clocks. When data transmission is con- trolled with referring to the flag after writing the data to the transmit buffer register, note the delay. 6. Transmission control when external clock is selected G Note When an external clock is used as the synchronous clock for data transmission, set the transmit enable bit to “1” at “H ” of the S CLK1 input level. Also, write data to the transmit buffer register at “H ” of the SCLK1 input level. 7. Transmit interrupt request when transmit enable bit is set G Note When using the transmit interrupt, take the following sequence. ➀ Set the serial I/O1 transmit interrupt enable bit to “0” (disabled). ➁ Set the transmit enable bit to “1”. ➂ Set the serial I/O1 transmit interrupt request bit to “0” after 1 or more instruction has executed. ➃ Set the serial I/O1 transmit interrupt enable bit to “1” (enabled). G Reason When the transmit enable bit is set to “1”, the transmit buffer empty flag and the transmit shift register shift completion flag are also set to “1”. Therefore, regardless of selecting which timing for the generating of transmit interrupts, the interrupt request is gener- ated and the transmit interrupt request bit is set at this point. Clear both the transmit enable bit (TE) and the receive enable bit (RE) to “0” Set the bits 0 to 3 and bit 6 of the serial I/O control register Set both the transmit enable bit (TE) and the receive enable bit (RE), or one of them to “1” Can be set with the LDM instruction at the same time

Rev.1.01 Jan 25, 2005 page 45 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) Serial I/O2 The serial I/O2 function can be used only for clock synchronous serial I/O2. For clock synchronous serial I/O2, the transmitter and the receiver must use the same clock. If the internal clock is used, transfer is started by a write signal to the serial I/O2 register. [Serial I/O2 Control Register (SIO2CON)] 001D 16 The serial I/O2 control register contains eight bits which control various serial I/O2 functions. Fig. 37 Structure of serial I/O2 control register Fig. 38 Block diagram of serial I/O2 S e r i a l I / O 2 c o n t r o l r e g i s t e r S I O C O N a d d r e s s D 1 b 7 I n t e r n a l s y n c h r o n o u s c l o c k s e l e c t i o n b i t s f XI N ) f XC I N ) i n l o w s p e e d m o d e f XI N ) f XC I N ) i n l o w s p e e d m o d e f XI N ) f XC I N ) i n l o w s p e e d m o d e f XI N ) f XC I N ) i n l o w s p e e d m o d e f XI N ) f XC I N ) i n l o w s p e e d m o d e f XI N ) f XC I N ) i n l o w s p e e d m o d e S e r i a l I O p o r t s e l e c t i o n b i t I O p o r t SO U T SC L K s i g n a l o u t p u t SR D Y o u t p u t e n a b l e b i t I O p o r t SR D Y s i g n a l o u t p u t T r a n s f e r d i r e c t i o n s e l e c t i o n b i t L S B f i r s t M S B f i r s t S e r i a l I O s y n c h r o n o u s c l o c k s e l e c t i o n b i t E x t e r n a l c l o c k I n t e r n a l c l o c k P 51/ SO U T P c h a n n e l o u t p u t d i s a b l e b i t C M O S o u t p u t i n o u t p u t m o d e N c h a n n e l o p e n d r a i n o u t p u t i n o u t p u t m o d e b 0 b 2 b 1 b 0 “1” “0” “ 0 ” “ 1 ” “ 0 ” “ 1 ” SR D Y SC L K “ 0 ” “ 1 ” D a t a b u s S e r i a l I / O 2 i n t e r r u p t r e q u e s t S e r i a l I / O 2 p o r t s e l e c t i o n b i t S e r i a l I / O c o u n t e r 2 ( 3 ) Serial I/O2 register (8) S y n c h r o n i z a t i o n c i r c u i t S e r i a l I / O 2 p o r t s e l e c t i o n b i t S e r i a l I / O 2 s y n c h r o n o u s c l o c k s e l e c t i o n b i t SR D Y o u t p u t e n a b l e b i t E x t e r n a l c l o c k Internal synchronous clock selection bits D i v i d e r P52/SCLK2 P51/SOUT2 P 50/ SI N P52 latch P51 latch P53 latch P53/SRDY2 f(XIN) ( f ( XC I N ) i n l o w - s p e e d m o d e ) Address 001F16

Rev.1.01 Jan 25, 2005 page 46 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) Fig. 39 Timing of serial I/O2 D 7D 0 D 1 D 2 D 3 D 4 D 5 D 6 T r a n s f e r c l o c k ( N o t e 1 ) S e r i a l I / O 2 o u t p u t SO U T S e r i a l I / O 2 i n p u t SI N R e c e i v e e n a b l e s i g n a l SR D Y S e r i a l I / O 2 r e g i s t e r w r i t e s i g n a l (Note 2) S e r i a l I / O 2 i n t e r r u p t r e q u e s t b i t s e t 1 : W h e n t h e i n t e r n a l c l o c k i s s e l e c t e d a s t h e t r a n s f e r c l o c k , t h e d i v i d e r a t i o o f f ( XI N ) , o r f ( XC I N ) i n l o w - s p e e d m o d e , c a n b e s e l e c t e d b y s e t t i n g b i t s t o o f t h e s e r i a l I O c o n t r o l r e g i s t e r W h e n t h e i n t e r n a l c l o c k i s s e l e c t e d a s t h e t r a n s f e r c l o c k t h e SO U T p i n g o e s t o h i g h i m p e d a n c e a f t e r t r a n s f e r c o m p l e t i o n N o t e s

Rev.1.01 Jan 25, 2005 page 47 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) Serial I/O3 Serial I/O3 can be used as either clock synchronous or asynchro- nous (UART) serial I/O3. A dedicated timer is also provided for baud rate generation. (1) Clock Synchronous Serial I/O Mode Clock synchronous serial I/O3 mode can be selected by setting the serial I/O3 mode selection bit of the serial I/O3 control register (bit 6 of address 0032 16) to “1”. For clock synchronous serial I/O, the transmitter and the receiver must use the same clock. If an internal clock is used, transfer is started by a write signal to the transmit/receive buffer register. Fig. 40 Block diagram of clock synchronous serial I/O3 Fig. 41 Operation of clock synchronous serial I/O3 F / F P 36/ SC L K Serial I/O3 status register Serial I/O3 control register P37/SRDY3 P34/RXD 3 P35/TXD 3 Receive buffer register 3 Address 003016 R e c e i v e s h i f t r e g i s t e r 3 Receive buffer full flag (RBF) Receive interrupt request (RI) C l o c k c o n t r o l c i r c u i tShift clock S e r i a l I / O 3 s y n c h r o n o u s c l o c k s e l e c t i o n b i t F r e q u e n c y d i v i s i o n r a t i o n Baud rate generator 3 Address 002F16 B R G c o u n t s o u r c e s e l e c t i o n b i t Clock control circuitF a l l i n g - e d g e d e t e c t o r Transmit buffer register 3 Data bus Address 003016 Shift clock Transmit shift completion flag (TSC) T r a n s m i t b u f f e r e m p t y f l a g ( T B E ) Transmit interrupt request (TI) Transmit interrupt source selection bit Address 003116 D a t a b u s A d d r e s s 0 0 3 21 T r a n s m i t s h i f t r e g i s t e r 3 f(XIN) ( f ( XC I N ) i n l o w - s p e e d m o d e ) D 7 D 7 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 0 D 1 D 2 D 3 D 4 D 5 D 6 R B F = 1 T S C 1T B E = 0 TBE = 1 TSC = 0 T r a n s f e r s h i f t c l o c k t o o f t h e i n t e r n a l c l o c k o r a n e x t e r n a l c l o c k S e r i a l o u t p u t T x D 3 S e r i a l i n p u t R x D 3 W r i t e p u l s e t o r e c e i v e / t r a n s m i t b u f f e r r e g i s t e r a d d r e s s O v e r r u n e r r o r ( O E ) d e t e c t i o n Notes 1 : A s t h e t r a n s m i t i n t e r r u p t ( T I ) , w h i c h c a n b e s e l e c t e d , e i t h e r w h e n t h e t r a n s m i t b u f f e r h a s e m p t i e d ( T B E = 1 ) o r a f t e r t h e t r a n s m i t s h i f t o p e r a t i o n h a s e n d e d T S C b y s e t t i n g t h e t r a n s m i t i n t e r r u p t s o u r c e s e l e c t i o n b i t T I C o f t h e s e r i a l I O c o n t r o l r e g i s t e r I f d a t a i s w r i t t e n t o t h e t r a n s m i t b u f f e r r e g i s t e r w h e n T S C t h e t r a n s m i t c l o c k i s g e n e r a t e d c o n t i n u o u s l y a n d s e r i a l d a t a i s o u t p u t c o n t i n u o u s l y f r o m t h e T x D p i n T h e r e c e i v e i n t e r r u p t R I i s s e t w h e n t h e r e c e i v e b u f f e r f u l l f l a g R B F b e c o m e s R e c e i v e e n a b l e s i g n a l SR D Y

Rev.1.01 Jan 25, 2005 page 48 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) (2) Asynchronous Serial I/O (UART) Mode Clock asynchronous serial I/O mode (UART) can be selected by clearing the serial I/O3 mode selection bit of the serial I/O3 control register to “0”. Eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. The transmit and receive shift registers each have a buffer, but the two buffers have the same address in a memory. Since the shift register cannot be written to or read from directly, transmit data is written to the transmit buffer register, and receive data is read from the receive buffer register. The transmit buffer register can also hold the next data to be transmitted, and the receive buffer register can hold a character while the next character is being received. Fig. 42 Block diagram of UART serial I/O3 Fig. 43 Operation of UART serial I/O3 f ( XI N ) O E P EF E 1 / 1 6 1 / 1 6 D a t a b u s R e c e i v e b u f f e r r e g i s t e r 3 A d d r e s s 0 0 3 01 R e c e i v e s h i f t r e g i s t e r 3 R e c e i v e b u f f e r f u l l f l a g ( R B F ) R e c e i v e i n t e r r u p t r e q u e s t ( R I ) B a u d r a t e g e n e r a t o r 3 F r e q u e n c y d i v i s i o n r a t i o 1 / ( n + 1 ) A d d r e s s 0 0 2 F1 S T / S P / P A g e n e r a t o r T r a n s m i t b u f f e r r e g i s t e r 3 D a t a b u s T r a n s m i t s h i f t r e g i s t e r 3 A d d r e s s 0 T r a n s m i t s h i f t c o m p l e t i o n f l a g ( T S C ) T r a n s m i t b u f f e r e m p t y f l a g ( T B E ) T r a n s m i t i n t e r r u p t r e q u e s t ( T I ) A d d r e s s 0 S T d e t e c t o r S P d e t e c t o r U A R T 3 c o n t r o l r e g i s t e r A d d r e s s 0 0 3 31 C h a r a c t e r l e n g t h s e l e c t i o n b i t A d d r e s s 0 0 3 21 B R G c o u n t s o u r c e s e l e c t i o n b i t T r a n s m i t i n t e r r u p t s o u r c e s e l e c t i o n b i t S e r i a l I / O 3 s y n c h r o n o u s c l o c k s e l e c t i o n b i t C l o c k c o n t r o l c i r c u i t C h a r a c t e r l e n g t h s e l e c t i o n b i t 7 b i t s 8 b i t s S e r i a l I / O 3 c o n t r o l r e g i s t e r P 36/ SC L K S e r i a l I / O 3 s t a t u s r e g i s t e r P 34/ R XD 3 P 35/ TXD 3 ( f ( XC I N ) i n l o w - s p e e d m o d e ) TSC=0 TBE=1 RBF=0 TBE=0 TBE=0 RBF=1 RBF=1 STD 0 D 1 SP D 0 D 1ST SP TBE=1 TSC=1 STD 0 D 1 SP D 0 D 1ST SP Transmit or receive clock Transmit buffer write signal Generated at 2nd bit in 2-stop-bit mode 1 start bit 7 or 8 data bit 1 or 0 parity bit 1 or 2 stop bit (s) 1: Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception). 2: As the transmit interrupt (TI), when either the TBE or TSC flag becomes “1,” can be selected to occur depending on the setting of the transmit interrupt source selection bit (TIC) of the serial I/O3 control register. 3: The receive interrupt (RI) is set when the RBF flag becomes “1.” 4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle are necessary until changing to TSC=0. Notes Serial output TXD 3 Serial input RXD 3 Receive buffer read signal

Rev.1.01 Jan 25, 2005 page 49 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) [Serial I/O3 Control Register (SIO3CON)] 003216 The serial I/O3 control register consists of eight control bits for the serial I/O3 function. [UART3 Control Register (UART3CON)] 003316 The UART control register consists of four control bits (bits 0 to 3) which are valid when asynchronous serial I/O is selected and set the data format of an data transfer, and one bit (bit 4) which is al- ways valid and sets the output structure of the P3 5/TXD 3 pin. [Serial I/O3 Status Register (SIO3STS)] 003116 The read-only serial I/O3 status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial I/O3 function and various errors. Three of the flags (bits 4 to 6) are valid only in UART mode. The receive buffer full flag (bit 1) is cleared to “0” when the receive buffer register is read. If there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer reg- ister, and the receive buffer full flag is set. A write to the serial I/O3 status register clears all the error flags OE, PE, FE, and SE (bit 3 to bit 6, respectively). Writing “0” to the serial I/O3 enable bit SIOE (bit 7 of the serial I/O3 control register) also clears all the status flags, including the error flags. Bits 0 to 6 of the serial I/O3 status register are initialized to “0” at reset, but if the transmit enable bit (bit 4) of the serial I/O3 control register has been set to “1”, the transmit shift completion flag (bit 2) and the transmit buffer empty flag (bit 0) become “1”. [Transmit Buffer Register 3/Receive Buffer Register 3 (TB3/RB3)] 003016 The transmit buffer register 3 and the receive buffer register 3 are located at the same address. The transmit buffer is write-only and the receive buffer is read-only. If a character bit length is 7 bits, the MSB of data stored in the receive buffer is “0”. [Baud Rate Generator 3 (BRG3)] 002F16 The baud rate generator determines the baud rate for serial trans- fer. The baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate genera- tor.

Rev.1.01 Jan 25, 2005 page 50 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) Fig. 44 Structure of serial I/O3 control registers b 7b 7 T r a n s m i t b u f f e r e m p t y f l a g T B E B u f f e r f u l l B u f f e r e m p t y R e c e i v e b u f f e r f u l l f l a g R B F B u f f e r e m p t y B u f f e r f u l l T r a n s m i t s h i f t c o m p l e t i o n f l a g T S C T r a n s m i t s h i f t i n p r o g r e s s T r a n s m i t s h i f t c o m p l e t e d O v e r r u n e r r o r f l a g O E N o e r r o r O v e r r u n e r r o r P a r i t y e r r o r f l a g P E N o e r r o r P a r i t y e r r o r F r a m i n g e r r o r f l a g F E N o e r r o r F r a m i n g e r r o r S u m m i n g e r r o r f l a g S E O E U P E U F E O E U P E U F E N o t u s e d r e t u r n s w h e n r e a d S e r i a l I O s t a t u s r e g i s t e r S e r i a l I O c o n t r o l r e g i s t e r b0 b 0 B R G c o u n t s o u r c e s e l e c t i o n b i t C S S f XI N ) f XC I N ) i n l o w s p e e d m o d e f XI N ) f XC I N ) i n l o w s p e e d m o d e S e r i a l I O s y n c h r o n o u s c l o c k s e l e c t i o n b i t S C S B R G o u t p u t d i v i d e d b y w h e n c l o c k s y n c h r o n o u s s e r i a l I O i s s e l e c t e d B R G o u t p u t d i v i d e d b y w h e n U A R T i s s e l e c t e d E x t e r n a l c l o c k i n p u t w h e n c l o c k s y n c h r o n o u s s e r i a l I O i s s e l e c t e d e x t e r n a l c l o c k i n p u t d i v i d e d b y w h e n U A R T i s s e l e c t e d SR D Y o u t p u t e n a b l e b i t S R D Y P p i n o p e r a t e s a s n o r m a l I O p i n P p i n o p e r a t e s a s SR D Y o u t p u t p i n T r a n s m i t i n t e r r u p t s o u r c e s e l e c t i o n b i t T I C I n t e r r u p t w h e n t r a n s m i t b u f f e r h a s e m p t i e d I n t e r r u p t w h e n t r a n s m i t s h i f t o p e r a t i o n i s c o m p l e t e d T r a n s m i t e n a b l e b i t T E T r a n s m i t d i s a b l e d T r a n s m i t e n a b l e d R e c e i v e e n a b l e b i t R E R e c e i v e d i s a b l e d R e c e i v e e n a b l e d S e r i a l I O m o d e s e l e c t i o n b i t S I O M C l o c k a s y n c h r o n o u s U A R T s e r i a l I O C l o c k s y n c h r o n o u s s e r i a l I O S e r i a l I O e n a b l e b i t S I O E S e r i a l I O d i s a b l e d p i n s P t o P o p e r a t e a s n o r m a l I O p i n s S e r i a l I O e n a b l e d p i n s P t o P o p e r a t e a s s e r i a l I O p i n s b 7 U A R T c o n t r o l r e g i s t e r C h a r a c t e r l e n g t h s e l e c t i o n b i t C H A S b i t s b i t s P a r i t y e n a b l e b i t P A R E P a r i t y c h e c k i n g d i s a b l e d P a r i t y c h e c k i n g e n a b l e d P a r i t y s e l e c t i o n b i t P A R S E v e n p a r i t y O d d p a r i t y S t o p b i t l e n g t h s e l e c t i o n b i t S T P S s t o p b i t s t o p b i t s P 35/ TXD 3 P c h a n n e l o u t p u t d i s a b l e b i t P O F F C M O S o u t p u t i n o u t p u t m o d e N c h a n n e l o p e n d r a i n o u t p u t i n o u t p u t m o d e N o t u s e d r e t u r n w h e n r e a d b 0 S I O S T S a d d r e s s S I O C O N a d d r e s s (UART3CON : address 003316)

Rev.1.01 Jan 25, 2005 page 51 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) 2. Notes when selecting clock asynchronous serial I/O Clear the transmit enable bit to “0” (transmit disabled). The trans- mission operation does not stop by clearing the serial I/O3 enable bit to “0”. G Reason Since transmission is not stopped and the transmission circuit is not initialized even if only the serial I/O3 enable bit is cleared to “0” (serial I/O disabled), the internal transmission is running (in this case, since pins TxD 3, RxD3, SCLK3 , and SRDY3 function as I/O ports, the transmission data is not output). When data is written to the transmit buffer register in this state, data starts to be shifted to the transmit shift register. When the serial I/O3 enable bit is set to “1” at this time, the data during internally shifting is output to the TxD 3 pin and an operation failure occurs. Clear the receive enable bit to “0” (receive disabled). G Note 1 (only transmission operation is stopped) Clear the transmit enable bit to “0” (transmit disabled). The trans- mission operation does not stop by clearing the serial I/O3 enable bit to “0”. G Reason Since transmission is not stopped and the transmission circuit is not initialized even if only the serial I/O3 enable bit is cleared to “0” (serial I/O disabled), the internal transmission is running (in this case, since pins TxD 3, RxD3, SCLK3 , and SRDY3 function as I/O ports, the transmission data is not output). When data is written to the transmit buffer register in this state, data starts to be shifted to the transmit shift register. When the serial I/O3 enable bit is set to “1” at this time, the data during internally shifting is output to the TxD 3 pin and an operation failure occurs. G Note 2 (only receive operation is stopped) Clear the receive enable bit to “0” (receive disabled). I Notes concerning serial I/O3 1. Notes when selecting clock synchronous serial I/O Clear the serial I/O3 enable bit and the transmit enable bit to “0” (serial I/O and transmit disabled). G Reason Since transmission is not stopped and the transmission circuit is not initialized even if only the serial I/O3 enable bit is cleared to “0” (serial I/O disabled), the internal transmission is running (in this case, since pins TxD 3, RxD3, SCLK3 , and SRDY3 function as I/O ports, the transmission data is not output). When data is written to the transmit buffer register in this state, data starts to be shifted to the transmit shift register. When the serial I/O enable bit is set to “1” at this time, the data during internally shifting is output to the TxD 3 pin and an operation failure occurs. Clear the receive enable bit to “0” (receive disabled), or clear the serial I/O3 enable bit to “0” (serial I/O disabled). Clear both the transmit enable bit and receive enable bit to “0” (transmit and receive disabled). (when data is transmitted and received in the clock synchronous serial I/O mode, any one of data transmission and reception can- not be stopped.) G Reason In the clock synchronous serial I/O mode, the same clock is used for transmission and reception. If any one of transmission and re- ception is disabled, a bit error occurs because transmission and reception cannot be synchronized. In this mode, the clock circuit of the transmission circuit also oper- ates for data reception. Accordingly, the transmission circuit does not stop by clearing only the transmit enable bit to “0” (transmit disabled). Also, the transmission circuit is not initialized by clear- ing the serial I/O3 enable bit to “0” (serial I/O disabled) (refer to 1.1).

Rev.1.01 Jan 25, 2005 page 52 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) 3. SRDY3 output of reception side G Note When signals are output from the SRDY3 pin on the reception side by using an external clock in the clock synchronous serial I/O mode, set all of the receive enable bit, the S RDY3 output enable bit, and the transmit enable bit to “1” (transmit enabled). 4. Setting serial I/O3 control register again G Note Set the serial I/O3 control register again after the transmission and the reception circuits are reset by clearing both the transmit en- able bit and the receive enable bit to “0.” 5. Data transmission control with referring to transmit shift register completion flag G Note After the transmit data is written to the transmit buffer register, the transmit shift register completion flag changes from “1” to “0” with a delay of 0.5 to 1.5 shift clocks. When data transmission is con- trolled with referring to the flag after writing the data to the transmit buffer register, note the delay. 6. Transmission control when external clock is selected G Note When an external clock is used as the synchronous clock for data transmission, set the transmit enable bit to “1” at “H ” of the S CLK3 input level. Also, write data to the transmit buffer register at “H ” of the SCLK input level. 7. Transmit interrupt request when transmit enable bit is set G Note When using the transmit interrupt, take the following sequence. ➀ Set the serial I/O3 transmit interrupt enable bit to “0” (disabled). ➁ Set the transmit enable bit to “1”. ➂ Set the serial I/O3 transmit interrupt request bit to “0” after 1 or more instruction has executed. ➃ Set the serial I/O3 transmit interrupt enable bit to “1” (enabled). G Reason When the transmit enable bit is set to “1”, the transmit buffer empty flag and the transmit shift register shift completion flag are also set to “1”. Therefore, regardless of selecting which timing for the generating of transmit interrupts, the interrupt request is gener- ated and the transmit interrupt request bit is set at this point. Clear both the transmit enable bit (TE) and the receive enable bit (RE) to “0” Set the bits 0 to 3 and bit 6 of the serial I/O3 control register Set both the transmit enable bit (TE) and the receive enable bit (RE), or one of them to “1” Can be set with the LDM instruction at the same time

Rev.1.01 Jan 25, 2005 page 53 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) PULSE WIDTH MODULATION (PWM) The 3804 group (Spec. H) has PWM functions with an 8-bit reso- lution, based on a signal that is the clock input XIN or that clock input divided by 2 or the clock input XCIN or that clock input di- vided by 2 in low-speed mode. Data Setting The PWM output pin also functions as port P56. Set the PWM pe- riod by the PWM prescaler, and set the “H ” term of output pulse by the PWM register. If the value in the PWM prescaler is n and the value in the PWM register is m (where n = 0 to 255 and m = 0 to 255) : PWM period = 255 ✕ (n+1) / f(X IN) = 31.875 ✕ (n+1) µs (when f(XIN) = 8 MHz) Output pulse “H ” term = PWM period ✕ m / 255 (when f(XIN) = 8 MHz) Fig. 45 Timing of PWM period Fig. 46 Block diagram of PWM function PWM Operation When bit 0 (PWM enable bit) of the PWM control register is set to “1”, operation starts by initializing the PWM output circuit, and pulses are output starting at an “H ”. If the PWM register or PWM prescaler is updated during PWM output, the pulses will change in the cycle after the one in which the change was made. 31.875 ✕ m ✕ (n+1) 255 µs PWM output m: Contents of PWM register n : Contents of PWM prescaler T : PWM period (when f(X IN) = 8 MHz Data bus Count source selection bit “0” “ 1 ” P W M p r e s c a l e r p r e l a t c h PWM register pre-latch PWM prescaler latch PWM register latch T r a n s f e r c o n t r o l c i r c u i t PWM register XIN or XCIN Port P56 latch PWM enable bit P o r t P 56 P W M p r e s c a l e r

Rev.1.01 Jan 25, 2005 page 54 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) Fig. 47 Structure of PWM control register Fig. 48 PWM output timing when PWM register or PWM prescaler is changed P W M c o n t r o l r e g i s t e r P W M C O N a d d r e s s 2B1 P W M f u n c t i o n e n a b l e b i t C o u n t s o u r c e s e l e c t i o n b i t N o t u s e d r e t u r n w h e n r e a d b 7 b 0 0 : P W M d i s a b l e d P W M e n a b l e d 0 : f ( XI N ) f XI N ) A B C B T C PWM output PWM register write signal PWM prescaler write signal (Changes “H ” term from “A” to “B”.) (Changes PWM period from “T” to “T2”.) When the contents of the PWM register or PWM prescaler have changed, the PWM output will change from the next period after the change. T T T2

Rev.1.01 Jan 25, 2005 page 55 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) A/D CONVERTER [AD Conversion Register 1, 2 (AD1, AD2)] 0035 16, 003816 The AD conversion register is a read-only register that stores the result of an A/D conversion. When reading this register during an A/D conversion, the previous conversion result is read. Bit 7 of the AD conversion register 2 is the conversion mode se- lection bit. When this bit is set to “0,” the A/D converter becomes the 10-bit A/D mode. When this bit is set to “1,” that becomes the 8-bit A/D mode. The conversion result of the 8-bit A/D mode is stored in the AD conversion register 1. As for 10-bit A/D mode, not only 10-bit reading but also only high-order 8-bit reading of con- version result can be performed by selecting the reading procedure of the AD conversion registers 1, 2 after A/D conversion is completed (in Figure 50). As for 10-bit A/D mode, the 8-bit reading inclined to MSB is per- formed when reading the AD converter register 1 after A/D conversion is started; and when the AD converter register 1 is read after reading the AD converter register 2, the 8-bit reading in- clined to LSB is performed. [AD/DA Control Register (ADCON)] 003416 The AD/DA control register controls the A/D conversion process. Bits 0 to 2 and bit 4 select a specific analog input pin. Bit 3 signals the completion of an A/D conversion. The value of this bit remains at “0” during an A/D conversion, and changes to “1” when an A/D conversion ends. Writing “0” to this bit starts the A/D conversion. Comparison Voltage Generator The comparison voltage generator divides the voltage between VREF and AVSS into 1024, and that outputs the comparison voltage in the 10-bit A/D mode (256 division in 8-bit A/D mode). The A/D converter successively compares the comparison voltage V ref in each mode, dividing the VREF voltage (see below), with the input voltage.

• 10-bit A/D mode (10-bit reading) Vref = ✕ n (n = 0–1023)
• 10-bit A/D mode (8-bit reading) Vref = ✕ n (n = 0–255)
• 8-bit A/D mode =0 (n = 0) Fig. 49 Structure of AD/DA control register Channel Selector The channel selector selects one of ports P67/AN7 to P60/AN0 or P07/AN15 to P00/AN8, and inputs the voltage to the comparator. Comparator and Control Circuit The comparator and control circuit compares an analog input volt- age with the comparison voltage, and then stores the result in the AD conversion registers 1, 2. When an A/D conversion is com- pleted, the control circuit sets the AD conversion completion bit and the AD interrupt request bit to “1”. Note that because the comparator consists of a capacitor cou- pling, set f(X IN) to 500 kHz or more during an A/D conversion. VREF 256 VREF 256 Fig. 50 Structure of 10-bit A/D mode reading VREF 1024 A D / D A c o n t r o l r e g i s t e r A D C O N a d d r e s s A n a l o g i n p u t p i n s e l e c t i o n b i t s 1 P 60/ A N 0 o r P 00/ A N 8 P 61/ A N 1 o r P 01/ A N 9 P 62/ A N 2 o r P 02/ A N 1 P 63/ A N 3 o r P 03/ A N 1 P 64/ A N 4 o r P 04/ A N 1 P 65/ A N 5 o r P 05/ A N 1 P 66/ A N 6 o r P 06/ A N 1 P 67/ A N 7 o r P 07/ A N 1 A D c o n v e r s i o n c o m p l e t i o n b i t C o n v e r s i o n i n p r o g r e s s C o n v e r s i o n c o m p l e t e d A n a l o g i n p u t p i n s e l e c t i o n b i t A N 0 t o A N 7 s i d e A N 8 t o A N 1 s i d e N o t u s e d r e t u r n s w h e n r e a d D o u t p u t e n a b l e b i t D o u t p u t d i s a b l e d D o u t p u t e n a b l e d D o u t p u t e n a b l e b i t D o u t p u t d i s a b l e d D o u t p u t e n a b l e d b7 b 0 b2 b1 b0 10-bit reading (Read address 003816 before 003516) AD conversion register 2 (AD2: address 003816) AD conversion register 1 (AD1: address 003516) 8-bit reading (Read only address 003516) AD conversion register 1 (AD1: address 0035 16) N o t e : Bi t s 2 t o 6 o f a d d r e s s 0 0 3 81 6 b e c o m e “ 0 ” a t r e a d i n g b7 b6 b5 b4 b3 b2 b1 b0 b7 b b7 b0 b9 b8 b7 b6 b5 b4 b3 b2 b 7 b0

Rev.1.01 Jan 25, 2005 page 56 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) Fig. 51 Block diagram of A/D converter C h a n n e l s e l e c t o r A / D c o n t r o l c i r c u i t A D c o n v e r s i o n r e g i s t e r 1 Resistor ladder VREF AV SS C o m p a r a t o r A D c o n v e r t e r i n t e r r u p t r e q u e s t b 7b 0 P 60/ A N 0 P 61/ A N 1 P62/AN2 P63/AN3 P 64/ A N 4 D a t a b u s A D / D A c o n t r o l r e g i s t e r A D c o n v e r s i o n r e g i s t e r 2 ( A d d r e s s 0 0 3 41 (Address 003816) (Address 003516) P 65/ A N 5 P 66/ A N 6 P 67/ A N 7 P 00/ A N 8 P 01/ A N 9 P 02/ A N 1 P03/AN11 P 04/ A N 1 P05/AN13 P 06/ A N 1 P07/AN15

Rev.1.01 Jan 25, 2005 page 57 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) D/A CONVERTER The 3804 group (Spec. H) has two internal D/A converters (DA1 and DA2) with 8-bit resolution. The D/A conversion is performed by setting the value in each DA conversion register. The result of D/A conversion is output from the DA 1 or DA2 pin by setting the DA output enable bit to “1”. When using the D/A converter, the corresponding port direction register bit (P3 0/DA1 or P31/DA2) must be set to “0” (input status). The output analog voltage V is determined by the value n (decimal notation) in the DA conversion register as follows: V = VREF ✕ n/256 (n = 0 to 255) Where VREF is the reference voltage. At reset, the DA conversion registers are cleared to “0016”, and the DA output enable bits are cleared to “0”, and the P30/DA1 and P31/DA2 pins become high impedance. The DA output does not have buffers. Accordingly, connect an ex- ternal buffer when driving a low-impedance load. Fig. 52 Block diagram of D/A converter Fig. 53 Equivalent connection circuit of D/A converter (DA1) P 30/ D A1 D A 1 c o n v e r s i o n r e g i s t e r ( 8 ) R - 2 R r e s i s t o r l a d d e r D A1 o u t p u t e n a b l e b i t P 31/ D A2 D A 2 c o n v e r s i o n r e g i s t e r ( 8 ) R - 2 R r e s i s t o r l a d d e r D A2 o u t p u t e n a b l e b i t D a t a b u s AV SS VREF “ 0 ” “1” M S B “ 0 ” “1” R 2 R R R R 2 R R 2 R R R

2 R2 R

D A1 o u t p u t e n a b l e b i t

Rev.1.01 Jan 25, 2005 page 58 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) XIN Data bus XCIN “10” “00” “01” Main clock division ratio selection bits (Note) “0” “1”1/16 Watchdog timer H count source selection bit Reset circuit STP instruction disable bit Watchdog timer H (8) “FF16” is set when watchdog timer control register is written to. Internal resetRESET Watchdog timer L (8) Note: Either high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the CPU mode register. STP instruction “FF16” is set when watchdog timer control register is written to. Reset release time waiting WATCHDOG TIMER The watchdog timer gives a mean of returning to the reset status when a program cannot run on a normal loop (for example, be- cause of a software run-away). The watchdog timer consists of an 8-bit watchdog timer L and an 8-bit watchdog timer H. Watchdog Timer Initial Value Watchdog timer L is set to “FF 16” and watchdog timer H is set to “FF 16” by writing to the watchdog timer control register (address 001E 16) or at a reset. Any write instruction that causes a write sig- nal can be used, such as the STA, LDM, CLB, etc. Data can only be written to bits 6 and 7 of the watchdog timer control register. Regardless of the value written to bits 0 to 5, the above-mentioned value will be set to each timer. Watchdog Timer Operations The watchdog timer stops at reset and a countdown is started by the writing to the watchdog timer control register. An internal reset occurs when watchdog timer H underflows. The reset is released after its release time. After the release, the program is restarted from the reset vector address. Usually, write to the watchdog timer control register by software before an underflow of the watchdog timer H. The watchdog timer does not function if the watchdog timer control register is not written to at least once. Fig. 55 Structure of Watchdog timer control register When bit 6 of the watchdog timer control register is kept at “0”, the STP instruction is enabled. When that is executed, both the clock and the watchdog timer stop. Count re-starts at the same time as the release of stop mode (Note). The watchdog timer does not stop while a WIT instruction is executed. In addition, the STP in- struction is disabled by writing “1” to this bit again. When the STP instruction is executed at this time, it is processed as an undefined instruction, and an internal reset occurs. Once a “1” is written to this bit, it cannot be programmed to “0” again. The following shows the period between the write execution to the watchdog timer control register and the underflow of watchdog timer H. Bit 7 of the watchdog timer control register is “0”: when X CIN = 32.768 kHz; 32 s when XIN = 16 MHz; 65.536 ms Bit 7 of the watchdog timer control register is “1”: when XCIN = 32.768 kHz; 125 ms when XIN = 16 MHz; 256 µs Note: The watchdog timer continues to count even while waiting for a stop release. Therefore, make sure that watchdog timer H does not un- derflow during this period. Fig. 54 Block diagram of Watchdog timer Watchdog timer H (for read-out of high-order 6 bit) STP instruction disable bit 0: STP instruction enabled 1: STP instruction disabled Watchdog timer H count source selection bit 0: Watchdog timer L underflow 1: f(X IN)/16 or f(XCIN)/16 W a t c h d o g t i m e r c o n t r o l r e g i s t e r W D T C O N a d d r e s s b 0

Rev.1.01 Jan 25, 2005 page 59 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) Function In conformity with Philips I2C-BUS standard: 10-bit addressing format 7-bit addressing format High-speed clock mode Standard clock mode In conformity with Philips I 2C-BUS standard: Master transmission Master reception Slave transmission Slave reception 16.1 kHz to 400 kHz (at φ= 4 MHz) Table 7 Multi-master I 2C-BUS interface functions Item Format Communication mode System clock φ = f(XIN)/2 (high-speed mode) φ = f(XIN)/8 (middle-speed mode) MULTI-MASTER I 2C-BUS INTERFACE The 3804 group (Spec. H) has the multi-master I2C-BUS interface. The multi-master I2C-BUS interface is a serial communications cir- cuit, conforming to the Philips I2C-BUS data transfer format. This interface, offering both arbitration lost detection and a synchro- nous functions, is useful for the multi-master serial communications. Figure 56 shows a block diagram of the multi-master I 2C-BUS in- terface and Table 7 lists the multi-master I2C-BUS interface functions. This multi-master I 2C-BUS interface consists of the I2C slave ad- dress registers 0 to 2, the I2C data shift register, the I2C clock control register, the I2C control register, the I2C status register, the I2C START/STOP condition control register, the I2C special mode control register, the I2C special mode status register, and other control circuits. When using the multi-master I 2C-BUS interface, set 1 MHz or more to the internal clock φ. Fig. 56 Block diagram of multi-master I2C-BUS interface ✽ : Purchase of MITSUBISHI ELECTRIC CORPORATIONS I2C components conveys a license under the Philips I2C Patent Rights to use these components an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. SCL clock frequency I2C status register b7 b0 S A D A D

5 SAD4 SAD3 SAD2 SAD1 SAD0 RWB

c i r c u i t b7 b0 AC K A C K B I T FAST MODE CCR 4 C C R

3 CCR 2 CCR1 CCR 0

S0D0 –2 SIS I2C S T A R T S T O P c o n d i t i o n c o n t r o l r e g i s t e r SIP SSC 4 S S C 3 S S C 2 S S C S C b 7b 0 T I S S TSE L 10BIT SAD A L S B C C

1 BC0

E S b 7b 0 S P C F S 3 PIN2 A A S A S A S b 7b 0 S P C F L S 3 D P I N 2 H D P I N 2 I N H S L A D A C K I C O N I2 C special mode control register I2C special mode status register I2C slave address registers 0 to 2 Noise elimination circuit Address comparator D a t a c o n t r o l c i r c u i t S y s t e m c l o c k (φ) I n t e r r u p t g e n e r a t i n g c i r c u i t I n t e r r u p t r e q u e s t s i g n a l I2C I R Q B i t c o u n t e r Clock control circuit Internal data bus Clock division A L c i r c u i t I2C c l o c k c o n t r o l r e g i s t e r I2C c o n t r o l r e g i s t e r Serial clock (SCL) I2C data shift register I n t e r r u p t r e q u e s t s i g n a l C L S D A I R Q ) I n t e r r u p t g e n e r a t i n g c i r c u i t S e r i a l d a t a S D A N o i s e e l i m i n a t i o n c i r c u i t S D

Rev.1.01 Jan 25, 2005 page 60 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) [I2C Data Shift Register (S0)] 001116 The I2C data shift register (S0: address 001116) is an 8-bit shift register to store receive data and write transmit data. When transmit data is written into this register, it is transferred to the outside from bit 7 in synchronization with the SCL, and each time one-bit data is output, the data of this register are shifted by one bit to the left. When data is received, it is input to this register from bit 0 in synchronization with the SCL, and each time one-bit data is input, the data of this register are shifted by one bit to the left. The minimum 2 cycles of the internal clock φ are required from the rising of the SCL until input to this register. The I 2C data shift register is in a write enable status only when the I2C-BUS interface enable bit (ES0 bit) of the I2C control register (S1D: address 001416) is “1”. The bit counter is reset by a write in- struction to the I2C data shift register. When both the ES0 bit and the MST bit of the I2C status register (S1: address 001316) are “1,” the SCL is output by a write instruction to the I2C data shift regis- ter. Reading data from the I2C data shift register is always enabled regardless of the ES0 bit value. [I2C Slave Address Registers 0 to 2 (S0D0 to S0D2)] 0FF716 to 0FF916 The I2C slave address registers 0 to 2 (S0D0 to S0D2: addresses 0FF7 16 to 0FF916) consists of a 7-bit slave address and a read/ write bit. In the addressing mode, the slave address written in this register is compared with the address data to be received immedi- ately after the START condition is detected.

• Bit 0: Read/write bit (RWB) This is not used in the 7-bit addressing mode. In the 10-bit ad- dressing mode, set RWB to “0” because the first address data to be received is compared with the contents (SAD6 to SAD0 + RWB) of the I 2C slave address registers 0 to 2. When 2-byte address data match slave address, a 7-bit slave ad- dress which is received after restart condition has detected and R/W data can be matched by setting “1” to RWB with software. The RWB is cleared to “0” automatically when the stop condition is detected.
• Bits 1 to 7: Slave address (SAD0–SAD6) These bits store slave addresses. Regardless of the 7-bit address- ing mode or the 10-bit addressing mode, the address data transmitted from the master is compared with these bits’ contents. Fig. 57 Structure of I 2C slave address registers 0 to 2 SAD6 S A D A D A D A D A D A D W B S l a v e a d d r e s s I2C s l a v e a d d r e s s r e g i s t e r S D a d d r e s s F F I2C s l a v e a d d r e s s r e g i s t e r S D a d d r e s s F F I2C s l a v e a d d r e s s r e g i s t e r S D a d d r e s s F F Read/write bit b7 b0

Rev.1.01 Jan 25, 2005 page 61 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) Table 8 Set values of I2C clock control register and SCL frequency Fig. 58 Structure of I2C clock control register SCL frequency (at φ = 4 MHz, unit : kHz) (Note 1) Setting value of CCR4 –CCR0 Standard clock mode Setting disabled Setting disabled Setting disabled High-speed clock modeCCR4 CCR3 CCR2 CCR1 CCR0 Setting disabled Setting disabled Setting disabled 34.5 33.3 32.3 100 83.3 333 250 400 (Note 3) 166 – (Note 2) – (Note 2) [I2C Clock Control Register (S2)] 001516 The I2C clock control register (S2: address 001516) is used to set ACK control, SCL mode and SCL frequency.

• Bits 0 to 4: SCL frequency control bits (CCR0–CCR4) These bits control the SCL frequency. Refer to Table 8.
• Bit 5: SCL mode specification bit (FAST MODE) This bit specifies the SCL mode. When this bit is set to “0,” the standard clock mode is selected. When the bit is set to “1,” the high-speed clock mode is selected. When connecting the bus of the high-speed mode I 2C bus stan- dard (maximum 400 kbits/s), use 8 MHz or more oscillation frequency f(X IN) in the high-speed mode (2 division clock).
• Bit 6: ACK bit (ACK BIT) This bit sets the SDA status when an ACK clock✽ is generated. When this bit is set to “0,” the ACK return mode is selected and SDA goes to “L” at the occurrence of an ACK clock. When the bit is set to “1,” the ACK non-return mode is selected. The SDA is held in the “H ” status at the occurrence of an ACK clock. However, when the slave address agree with the address data in the reception of address data at ACK BIT = “0,” the SDA is auto- matically made “L” (ACK is returned). If there is a disagreement between the slave address and the address data, the SDA is auto- matically made “H ” (ACK is not returned). ✽ ACK clock: Clock for acknowledgment
• Bit 7: ACK clock bit (ACK) This bit specifies the mode of acknowledgment which is an ac- knowledgment response of data transfer. When this bit is set to “0,” the no ACK clock mode is selected. In this case, no ACK clock occurs after data transmission. When the bit is set to “1,” the ACK clock mode is selected and the master generates an ACK clock each completion of each 1-byte data transfer. The device for transmitting address data and control data releases the SDA at the occurrence of an ACK clock (makes SDA “H ”) and receives the ACK bit generated by the data receiving device. Note:Do not write data into the I2C clock control register during transfer. If data is written during transfer, the I2C clock generator is reset, so that data cannot be transferred normally. 500/CCR value (Note 3) 1000/CCR value (Note 3) 17.2 16.6 16.1 Notes 1:Duty of SCL output is 50 %. The duty becomes 35 to 45 % only when the high-speed clock mode is selected and CCR value = 5 (400 kHz, at φ = 4 MHz). “H ” duration of the clock fluctuates from –4 to +2 machine cycles in the standard clock mode, and fluctu- ates from –2 to +2 machine cycles in the high-speed clock mode. In the case of negative fluctuation, the frequency does not in- crease because “L” duration is extended instead of “H ” duration reduction. These are values when SCL synchronization by the synchronous function is not performed. CCR value is the decimal notation value of the SCL frequency control bits CCR4 to CCR0. 2: Each value of SCL frequency exceeds the limit at φ = 4 MHz or more. When using these setting value, use φ of 4 MHz or less. 3: The data formula of SCL frequency is described below: φ/(8 ✕ CCR value) Standard clock mode φ/(4 ✕ CCR value) High-speed clock mode (CCR value ≠ 5) φ/(2 ✕ CCR value) High-speed clock mode (CCR value = 5) Do not set 0 to 2 as CCR value regardless of φ frequency. Set 100 kHz (max.) in the standard clock mode and 400 kHz (max.) in the high-speed clock mode to the SCL frequency by setting the SCL frequency control bits CCR4 to CCR0. ACK ACK BIT FAST MODE CCR4 CCR 3 CCR2 CCR1 CCR 0 I2C c l o c k c o n t r o l r e g i s t e r S a d d r e s s b 7b 0 S C L f r e q u e n c y c o n t r o l b i t s R e f e r t o T a b l e S C L m o d e s p e c i f i c a t i o n b i t S t a n d a r d c l o c k m o d e H i g h s p e e d c l o c k m o d e A C K b i t A C K i s r e t u r n e d A C K i s n o t r e t u r n e d A C K c l o c k b i t N o A C K c l o c k A C K c l o c k

Rev.1.01 Jan 25, 2005 page 62 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) Fig. 59 Structure of I2C control register [I2C Control Register (S1D)] 001416 The I2C control register (S1D: address 001416) controls data com- munication format.

• Bits 0 to 2: Bit counter (BC0–BC2) These bits decide the number of bits for the next 1-byte data to be transmitted. The I 2C interrupt request signal occurs immediately after the number of count specified with these bits (ACK clock is added to the number of count when ACK clock is selected by ACK clock bit (bit 7 of S2, address 0015 16) have been transferred, and BC0 to BC2 are returned to “0002”. Also when a START condition is received, these bits become “0002” and the address data is always transmitted and received in 8 bits.
• Bit 3: I 2C interface enable bit (ES0) This bit enables to use the multi-master I2C-BUS interface. When this bit is set to “0,” the use disable status is provided, so that the SDA and the SCL become high-impedance. When the bit is set to “1,” use of the interface is enabled. When ES0 = “0,” the following is performed.
• PIN = “1,” BB = “0” and AL = “0” are set (which are bits of the I2C status register, S1, at address 001316 ).
• Writing data to the I2C data shift register (S0: address 001116) is disabled.
• Bit 4: Data format selection bit (ALS) This bit decides whether or not to recognize slave addresses. When this bit is set to “0,” the addressing format is selected, so that address data is recognized. When a match is found between a slave address and address data as a result of comparison or when a general call (refer to “I 2C Status Register,” bit 1) is re- ceived, transfer processing can be performed. When this bit is set to “1,” the free data format is selected, so that slave addresses are not recognized.
• Bit 5: Addressing format selection bit (10BIT SAD) This bit selects a slave address specification format. When this bit is set to “0,” the 7-bit addressing format is selected. In this case, only the high-order 7 bits (slave address) of the I 2C slave address registers 0 to 2 are compared with address data. When this bit is set to “1,” the 10-bit addressing format is selected, and all the bits of the I 2C slave address registers 0 to 2 are compared with ad- dress data.
• Bit 7: I2C-BUS interface pin input level selection bit (TISS) This bit selects the input level of the SCL and SDA pins of the multi-master I 2C-BUS interface. b 7 T I S S 1 B I T S A D ALS E S 0 B C 2 BC 1 BC 0 b 0 N o t u s e d r e t u r n w h e n r e a d I2C c o n t r o l r e g i s t e r S D a d d r e s s B i t c o u n t e r ( N u m b e r o f t r a n s m i t r e c e i v e b i t s b 000 : 001 : 010 : 011 : 100 : 101 : 110 : 111 : I2C-BUS interface enable bit 0 : Disabled 1 : Enabled D a t a f o r m a t s e l e c t i o n b i t A d d r e s s i n g f o r m a t F r e e d a t a f o r m a t A d d r e s s i n g f o r m a t s e l e c t i o n b i t b i t a d d r e s s i n g f o r m a t b i t a d d r e s s i n g f o r m a t I2C-BUS interface pin input level selection bit 0 : CMOS input 1 : SMBUS input

Rev.1.01 Jan 25, 2005 page 63 of 114 REJ03B0131-0101Z 3804 Group (Spec. H)

• Bit 4: SCL pin low hold bit (PIN) This bit generates an interrupt request signal. Each time 1-byte data is transmitted, the PIN bit changes from “1” to “0.” At the same time, an interrupt request signal occurs to the CPU. The PIN bit is set to “0” in synchronization with a falling of the last clock (in- cluding the ACK clock) of an internal clock and an interrupt request signal occurs in synchronization with a falling of the PIN bit. When the PIN bit is “0,” the SCL is kept in the “0” state and clock generation is disabled. Figure 61 shows an interrupt request signal generating timing chart. The PIN bit is set to “1” in one of the following conditions:
• Executing a write instruction to the I 2C data shift register (S0: address 001116). (This is the only condition which the prohibition of the internal clock is released and data can be communicated except for the start condition detection.)
• When the ES0 bit is “0”
• At reset
• When writing “1” to the PIN bit by software The PIN bit is set to “0” in one of the following conditions:
• Immediately after completion of 1-byte data transmission (includ- ing when arbitration lost is detected)
• Immediately after completion of 1-byte data reception
• In the slave reception mode, with ALS = “0” and immediately af- ter completion of slave address agreement or general call address reception
• In the slave reception mode, with ALS = “1” and immediately af- ter completion of address data reception
• Bit 5: Bus busy flag (BB) This bit indicates the status of use of the bus system. When this bit is set to “0,” this bus system is not busy and a START condition can be generated. The BB flag is set/reset by the SCL, SDA pins input signal regardless of master/slave. This flag is set to “1” by detecting the START condition, and is set to “0” by detecting the STOP condition. The condition of these detecting is set by the START/STOP condition setting bits (SSC4–SSC0) of the I START/STOP condition control register (S2D: address 001616). When the ES0 bit of the I2C control register (bit 3 of S1D, address 001416) is “0” or reset, the BB flag is set to “0.” For the writing function to the BB flag, refer to the sections “START Condition Generating Method” and “STOP Condition Gen- erating Method” described later. [I2C Status Register (S1)] 001316 The I2C status register (S1: address 001316) controls the I2C-BUS interface status. The low-order 4 bits are read-only bits and the high-order 4 bits can be read out and written to. Set “0000 2” to the low-order 4 bits, because these bits become the reserved bits at writing.
• Bit 0: Last receive bit (LRB) This bit stores the last bit value of received data and can also be used for ACK receive confirmation. If ACK is returned when an ACK clock occurs, the LRB bit is set to “0.” If ACK is not returned, this bit is set to “1.” Except in the ACK mode, the last bit value of received data is input. The state of this bit is changed from “1” to “0” by executing a write instruction to the I 2C data shift register (S0: address 001116).
• Bit 1: General call detecting flag (AD0) When the ALS bit is “0”, this bit is set to “1” when a general call✽ whose address data is all “0” is received in the slave mode. By a general call of the master device, every slave device receives con- trol data after the general call. The AD0 bit is set to “0” by detecting the STOP condition or START condition, or reset. ✽ General call:The master transmits the general call address “0016” to all slaves.
• Bit 2: Slave address comparison flag (AAS) This flag indicates a comparison result of address data when the ALS bit is “0”. ➀ In the slave receive mode, when the 7-bit addressing format is selected, this bit is set to “1” in one of the following conditions:
• The address data immediately after occurrence of a START condition agrees with the slave address stored in the high-or- der 7 bits of the I 2C slave address register.
• A general call is received. ➁ In the slave receive mode, when the 10-bit addressing format is selected, this bit is set to “1” with the following condition:
• When the address data is compared with the I2C slave ad- dress register (8 bits consisting of slave address and RWB bit), the first bytes agree. ➂ This bit is set to “0” by executing a write instruction to the I 2C data shift register (S0: address 001116) when ES0 is set to “1” or reset.
• Bit 3: Arbitration lost✽ detecting flag (AL) In the master transmission mode, when the SDA is made “L” by any other device, arbitration is judged to have been lost, so that this bit is set to “1.” At the same time, the TRX bit is set to “0,” so that immediately after transmission of the byte whose arbitration was lost is completed, the MST bit is set to “0.” The arbitration lost can be detected only in the master transmission mode. When ar- bitration is lost during slave address transmission, the TRX bit is set to “0” and the reception mode is set. Consequently, it becomes possible to detect the agreement of its own slave address and ad- dress data transmitted by another master device. The AL bit is set to “0” in one of the following conditions:
• Executing a write instruction to the I 2C data shift register (S0: ad- dress 001116)
• When the ES0 bit is “0”
• At reset ✽ Arbitration lost :The status in which communication as a master is dis- abled.

Rev.1.01 Jan 25, 2005 page 64 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) Fig. 61 Interrupt request signal generating timing Fig. 60 Structure of I2C status register

• Bit 6: Communication mode specification bit (transfer direc- tion specification bit: TRX) This bit decides a direction of transfer for data communication. When this bit is “0,” the reception mode is selected and the data of a transmitting device is received. When the bit is “1,” the transmis- sion mode is selected and address data and control data are output onto the SDA in synchronization with the clock generated on the SCL. This bit is set/reset by software and hardware. About set/reset by hardware is described below. This bit is set to “1” by hardware when all the following conditions are satisfied:
• When ALS is “0”
• In the slave reception mode or the slave transmission mode
• When the R/W bit reception is “1” This bit is set to “0” in one of the following conditions:
• When arbitration lost is detected.
• When a STOP condition is detected.
• When writing “1” to this bit by software is invalid by the START condition duplication preventing function (Note).
• With MST = “0” and when a START condition is detected.
• With MST = “0” and when ACK non-return is detected.
• At reset
• Bit 7: Communication mode specification bit (master/slave specification bit: MST) This bit is used for master/slave specification for data communica- tion. When this bit is “0,” the slave is specified, so that a START condition and a STOP condition generated by the master are re- ceived, and data communication is performed in synchronization with the clock generated by the master. When this bit is “1,” the master is specified and a START condition and a STOP condition are generated. Additionally, the clocks required for data communi- cation are generated on the SCL. This bit is set to “0” in one of the following conditions.
• Immediately after completion of the byte which has lost arbitra- tion when arbitration lost is detected
• When a STOP condition is detected.
• Writing “1” to this bit by software is invalid by the START condi- tion duplication preventing function (Note).
• At reset Note: START condition duplication preventing function The MST, TRX, and BB bits is set to “1” at the same time after con- firming that the BB flag is “0” in the procedure of a START condition occurrence. However, when a START condition by another master device occurs and the BB flag is set to “1” immediately after the con- tents of the BB flag is confirmed, the START condition duplication preventing function makes the writing to the MST and TRX bits in- valid. The duplication preventing function becomes valid from the rising of the BB flag to reception completion of slave address. b 7 MS T b 0 I2C s t a t u s r e g i s t e r S a d d r e s s L a s t r e c e i v e b i t ( N o t e ) a s t b i t a s t b i t G e n e r a l c a l l d e t e c t i n g f l a g N o t e o g e n e r a l c a l l d e t e c t e d e n e r a l c a l l d e t e c t e d S l a v e a d d r e s s c o m p a r i s o n f l a g N o t e A d d r e s s d i s a g r e e m e n t A d d r e s s a g r e e m e n t Arbitration lost detecting flag (Note) 0 : Not detected 1 : Detected S C L p i n l o w h o l d b i t S C L p i n l o w h o l d S C L p i n l o w r e l e a s e Bus busy flag 0 : Bus free 1 : Bus busy Communication mode specification bits 00 : Slave receive mode 01 : Slave transmit mode 10 : Master receive mode 11 : Master transmit mode TRX BB PIN AL AAS AD0 LRB N o t e : T h e s e b i t s a n d f l a g s c a n b e r e a d o u t , b u t c a n n o t b e w r i t t e n . W r i t e t o t h e s e b i t s a t w r i t i n g SCL PIN I2CIRQ

Rev.1.01 Jan 25, 2005 page 65 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) START Condition Generating Method When writing “1” to the MST, TRX, and BB bits of the I2C status register (S1: address 001316) at the same time after writing the slave address to the I2C data shift register (S0: address 001116) with the condition in which the ES0 bit of the I2C control register (S1D: address 001416) is “1” and the BB flag is “0”, a START con- dition occurs. After that, the bit counter becomes “0002” and an SCL for 1 byte is output. The START condition generating timing is different in the standard clock mode and the high-speed clock mode. Refer to Figure 62, the START condition generating timing diagram, and Table 9, the START condition generating timing table. STOP Condition Generating Method When the ES0 bit of the I2C control register (S1D: address 001416) is “1,” write “1” to the MST and TRX bits, and write “0” to the BB bit of the I2C status register (S1: address 001316) simulta- neously. Then a STOP condition occurs. The STOP condition generating timing is different in the standard clock mode and the high-speed clock mode. Refer to Figure 63, the STOP condition generating timing diagram, and Table 10, the STOP condition gen- erating timing table. Fig. 62 START condition generating timing diagram Fig. 63 STOP condition generating timing diagram Table 10 STOP condition generating timing table Item Setup time Hold time Standard clock mode 5.0 µs (20 cycles) 4.5 µs (18 cycles) Note:Absolute time at φ = 4 MHz. The value in parentheses denotes the number of φ cycles. High-speed clock mode 3.0 µs (12 cycles) 2.5 µs (10 cycles) Table 9 START condition generating timing table Item Setup time Hold time Standard clock mode 5.0 µs (20 cycles) 5.0 µs (20 cycles) Note:Absolute time at φ = 4 MHz. The value in parentheses denotes the number of φ cycles. High-speed clock mode 2.5 µs (10 cycles) 2.5 µs (10 cycles) I2C s t a t u s r e g i s t e r w r i t e s i g n a l Hold timeS e t u p t i m e S C L SDA I2C status register write signal H o l d t i m eS e t u p t i m e SCL SDA

Rev.1.01 Jan 25, 2005 page 66 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) Fig. 64 START/STOP condition detecting timing diagram START/STOP Condition Detecting Operation The START/STOP condition detection operations are shown in Figures 64, 65, and Table 11. The START/STOP condition is set by the START/STOP condition set bit. The START/STOP condition can be detected only when the input signal of the SCL and SDA pins satisfy three conditions: SCL re- lease time, setup time, and hold time (see Table 11). The BB flag is set to “1” by detecting the START condition and is reset to “0” by detecting the STOP condition. The BB flag set/reset timing is different in the standard clock mode and the high-speed clock mode. Refer to Table 11, the BB flag set/ reset time. Note:When a STOP condition is detected in the slave mode (MST = 0), an interrupt request signal “I2CIRQ ” occurs to the CPU. Table 11 START condition/STOP condition detecting conditions Note:Unit : Cycle number of internal clock φ SSC value is the decimal notation value of the START/STOP condi- tion set bits SSC4 to SSC0. Do not set “0” or an odd number to SSC value. The value in parentheses is an example when the I 2C START/ STOP condition control register is set to “1816” at φ = 4 MHz. Fig. 65 STOP condition detecting timing diagram SCL release time Standard clock mode High-speed clock mode 4 cycles (1.0 µs) 2 cycles (0.5 µs) 2 cycles (0.5 µs) 3.5 cycles (0.875 µs) SSC value + 1 SSC value + 1 SSC value –1 Setup time Hold time BB flag set/ reset time SSC value + 1 cycle (6.25 µs) cycle < 4.0 µs (3.125 µs) cycle < 4.0 µs (3.125 µs) + 2 cycles (3.375 µs) H o l d t i m eS e t u p t i m e SCL SDA BB flag S C L r e l e a s e t i m e B B f l a g s e t t i m e H o l d t i m eS e t u p t i m e SCL SDA BB flag S C L r e l e a s e t i m e B B f l a g r e s e t t i m e

Rev.1.01 Jan 25, 2005 page 67 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) [I2C START/STOP Condition Control Register (S2D)] 001616 The I2C START/STOP condition control register (S2D: address 001616) controls START/STOP condition detection.

• Bits 0 to 4: START/STOP condition set bits (SSC4–SSC0) SCL release time, setup time, and hold time change the detection condition by value of the main clock divide ratio selection bit and the oscillation frequency f(X IN) because these time are measured by the internal system clock. Accordingly, set the proper value to the START/STOP condition set bits (SSC4 to SSC0) in considered of the system clock frequency. Refer to Table 11. Do not set “00000 2” or an odd number to the START/STOP condi- tion set bits (SSC4 to SSC0). Refer to Table 12, the recommended set value to START/STOP condition set bits (SSC4–SSC0) for each oscillation frequency.
• Bit 5: SCL/SDA interrupt pin polarity selection bit (SIP) An interrupt can occur when detecting the falling or rising edge of the SCL or SDA pin. This bit selects the polarity of the SCL or SDA pin interrupt pin.
• Bit 6: SCL/SDA interrupt pin selection bit (SIS) This bit selects the pin of which interrupt becomes valid between the SCL pin and the SDA pin. Note: When changing the setting of the SCL/SDA interrupt pin polarity se- lection bit, the SCL/SDA interrupt pin selection bit, or the I2C-BUS interface enable bit ES0, the SCL/SDA interrupt request bit may be set. When selecting the SCL/SDA interrupt source, disable the inter- rupt before the SCL/SDA interrupt pin polarity selection bit, the SCL/ SDA interrupt pin selection bit, or the I 2C-BUS interface enable bit ES0 is set. Reset the request bit to “0” after setting these bits, and enable the interrupt. START/STOP condition control register Oscillation frequency f(XIN) (MHz) Fig. 66 Structure of I2C START/STOP condition control register Note:Do not set an odd number to the START/STOP condition set bits (SSC4 to SSC0) and “000002”. Table 12 Recommended set value to START/STOP condition set bits (SSC4–SSC0) for each oscillation frequency Main clock divide ratio Internal clock φ (MHz) SCL release time (µs) Setup time (µs) Hold time (µs) XXX11010 XXX11000 XXX00100 XXX01100 XXX01010 XXX00100 3.5 µs (14 cycles) 3.25 µs (13 cycles) 3.0 µs (3 cycles) 3.5 µs (7 cycles) 3.0 µs (6 cycles) 3.0 µs (3 cycles) 6.75 µs (27 cycles) 6.25 µs (25 cycles) 5.0 µs (5 cycles) 6.5 µs (13 cycles) 5.5 µs (11 cycles) 5.0 µs (5 cycles) 3.25 µs (13 cycles) 3.0 µs (12 cycles) 2.0 µs (2 cycles) 3.0 µs (6 cycles) 2.5 µs (5 cycles) 2.0 µs (2 cycles) b 7b 0 I2C START/STOP condition control register S T A R T / S T O P c o n d i t i o n s e t b i t s S C L S D A i n t e r r u p t p i n p o l a r i t y s e l e c t i o n b i t a l l i n g e d g e a c t i v e i s i n g e d g e a c t i v e S C L S D A i n t e r r u p t p i n s e l e c t i o n b i t D A v a l i d C L v a l i d N o t u s e d F i x t h i s b i t t o SIS S I P S S C S C S C S C S C ( S 2 D : a d d r e s s 0 0 1 61

Rev.1.01 Jan 25, 2005 page 68 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) [I2C Special Mode Status Register (S3)] 001216 The I2C special mode status register (S3: address 001216) con- sists of the flags indicating I2C operating state in the I2C special mode, which is set by the I2C special mode control register (S3D: address 001716). The stop condition flag is valid in all operating modes.

• Bit 0: Slave address 0 comparison flag (AAS0) Bit 1: Slave address 1 comparison flag (AAS1) Bit 2: Slave address 2 comparison flag (AAS2) These flags indicate a comparison result of address data. These flags are valid only when the slave address control bit (MSLAD) is “1”. In the 7-bit addressing format of the slave reception mode, the re- spective slave address i (i = 0, 1, 2) comparison flags corresponding to the I 2C slave address registers 0 to 2 are set to “1” when an address data immediately after an occurrence of a START condition agrees with the high-order 7-bit slave address stored in the I 2C slave address registers 0 to 2 (addresses 0FF716 to 0FF916). In the 10-bit addressing format of the slave mode, the respective slave address i (i = 0, 1, 2) comparison flags corresponding to the I 2C slave address registers are set to “1” when an address data is compared with the 8 bits consisting of the slave address stored in the I 2C slave address registers 0 to 2 and the RWB bit, and the first byte agrees. These flags are initialized to “0” at reset, when the slave address control bit (MSLAD) is “0”, or when writing data to the I2C data shift register (S0: address 001116).
• Bit 5: SCL pin low hold 2 flag (PIN2) When the ACK interrupt control bit (ACKICON) and the ACK clock bit (ACK) are “1”, this flag is set to “0” in synchronization with the falling of the data’s last SCL clock, just before the ACK clock. The SCL pin is simultaneously held low, and the I2C interrupt request occurs. This flag is initialized to “1” at reset, when the ACK interrupt con- trol bit (ACKICON) is “0”, or when writing “1” to the SCL pin low hold 2 flag set bit (PIN2IN). The SCL pin is held low when either the SCL pin low hold bit (PIN) or the SCL pin low hold 2 flag (PIN2) becomes “0”. The low hold state of the SCL pin is released when both the SCL pin low hold bit (PIN) and the SCL pin low hold 2 flag (PIN2) are “1”.
• Bit 7: Stop condition flag (SPCF) This flag is set to “1” when a STOP condition occurs. This flag is initialized to “0” at reset, when the I 2C-BUS interface enable bit (ES0) is “0”, or when writing “1” to the STOP condition flag clear bit (SPFCL). Fig. 67 Structure of I2C special mode status register b7 b0 I2C special mode status register (S3 : address 001216) Slave address 0 comparison flag 0 : Address disagreement 1 : Address agreement STOP condition flag 0 : No detection 1 : Detection A A S 0AAS1AAS2P I N 2S P C F Slave address 1 comparison flag 0 : Address disagreement 1 : Address agreement Slave address 2 comparison flag 0 : Address disagreement 1 : Address agreement Not used (return “0” when read) Not used (return “0” when read) SCL pin low hold 2 flag 0 : SCL pin low hold 1 : SCL pin low release (Note) N o t e : I n o r d e r t h a t t h e l o w h o l d s t a t e o f t h e S C L p i n m a y r e l e a s e , i t i s n e c e s s a r y t h a t t h e S C L p i n l o w h o l d f l a g a n d t h e S C L p i n l o w h o l d b i t P I N a r e s i m u l t a n e o u s l y Not used (return “0” when read)

Rev.1.01 Jan 25, 2005 page 69 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) [I2C Special Mode Control Register (S3D)] 001716 The I2C special mode control register (S3D: address 001716) con- trols special functions such as occurrence timing of reception interrupt request and extending slave address comparison to 3 bytes.

• Bit 1: ACK interrupt control bit (ACKICON) This bit controls the timing of I 2C interrupt request occurrence at completion of data receiving due to master reception or slave re- ception. When this bit is “0”, the SCL pin low hold bit (PIN) is set to “0” in synchronization with the falling of the last SCL clock, including the ACK clock. The SCL pin is simultaneously held low, and the I interrupt request occurs. When this bit is “1” and the ACK clock bit (ACK) is “1”, the SCL pin low hold 2 flag (PIN2) is set to “0” in synchronization with the fall- ing of the data’s last SCL clock, just before the ACK clock. The SCL pin is simultaneously held low, and the I2C interrupt request occurs again. The ACK bit can be changed after the contents of data are confirmed by using this function.
• Bit 2: I 2C slave address control bit (MSLAD) This bit controls a slave address. When this bit is “0”, only the I2C slave address register 0 (address 0FF716) becomes valid as a slave address and a read/write bit. When this bit is “1”, all of the I 2C slave address registers 0 to 2 (addresses 0FF716 to 0FF916) become valid as a slave address and a read/write bit. In this case, when an address data agrees with any one of the I2C slave address registers 0 to 2, the slave address comparison flag (AAS) is set to “1” and the I2C slave ad- dress comparison flag corresponding to the agreed I2C slave address registers 0 to 2 is also set to “1”.
• Bit 5: SCL pin low hold 2 flag set bit (PIN2IN) Writing “1” to this bit initializes the SCL pin low hold 2 flag (PIN2) to “1”. When writing “0”, nothing is generated.
• Bit 6: SCL pin low hold set bit (PIN2HD) When the SCL pin low hold bit (PIN) becomes “0”, the SCL pin is held low. However, the SCL pin low hold bit (PIN) cannot be set to “0” by software. The SCL pin low hold set bit (PIN2HD) is used to , hold the SCL pin in the low state by software. When writing “1” to this bit, the SCL pin low hold 2 flag (PIN2) becomes “0”, and the SCL pin is held low. When writing “0”, nothing occurs.
• Bit 7: STOP condition flag clear bit (SPFCL) Writing “1” to this bit initializes the STOP condition flag (SPCF) to “0”. When writing “0”, nothing is generated. Fig. 68 Structure of I2C special mode control register b 7b 0 I2C s p e c i a l m o d e c o n t r o l r e g i s t e r S D a d d r e s s S T O P c o n d i t i o n f l a g c l e a r b i t ( N o t e 2 ) W r i t i n g t o t h i s b i t i n i t i a l i z e s t h e S T O P c o n d i t i o n f l a g t o ACKI CON MS L A DPIN2INS P F C L A C K i n t e r r u p t c o n t r o l b i t t c o m m u n i c a t i o n c o m p l e t i o n t f a l l i n g o f A C K c l o c k a n d c o m m u n i c a t i o n c o m p l e t i o n S l a v e a d d r e s s c o n t r o l b i t n e b y t e s l a v e a d d r e s s c o m p a r e m o d e h r e e b y t e s l a v e a d d r e s s c o m p a r e m o d e N o t u s e d r e t u r n w h e n r e a d N o t u s e d F i x t h i s b i t t o S C L p i n l o w h o l d 2 f l a g s e t b i t ( N o t e s 1 , 2 ) W r i t i n g t o t h i s b i t i n i t i a l i z e s t h e S C L p i n l o w h o l d f l a g t o PIN2- HD SCL pin low hold set bit (Notes 1, 2) When writing “1” to this bit, the SCL pin low hold 2 flag becomes “0” and the SCL pin is held low. N o t e s 1 : D o n o t w r i t e “ 1 ” t o t h e s e b i t s s i m u l t a n e o u s l y . r e t u r n w h e n r e a d N o t u s e d F i x t h i s b i t t o

Rev.1.01 Jan 25, 2005 page 70 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) Fig. 69 Address data communication format Address Data Communication There are two address data communication formats, namely, 7-bit addressing format and 10-bit addressing format. The respective address communication formats are described below. ➀ 7-bit addressing format To adapt the 7-bit addressing format, set the 10BIT SAD bit of the I 2C control register (S1D: address 001416) to “0”. The first 7- bit address data transmitted from the master is compared with the high-order 7-bit slave address stored in the I2C slave ad- dress register. At the time of this comparison, address comparison of the RWB bit of the I 2C slave address register is not performed. For the data transmission format when the 7-bit addressing format is selected, refer to Figure 69, (1) and (2). ➁ 10-bit addressing format To adapt the 10-bit addressing format, set the 10BIT SAD bit of the I 2C control register (S1D: address 001416) to “1.” An ad- dress comparison is performed between the first-byte address data transmitted from the master and the 8-bit slave address stored in the I 2C slave address register. At the time of this com- parison, an address comparison between the RWB bit of the I2C slave address register and the R/W bit which is the last bit of the address data transmitted from the master is made. In the 10-bit addressing mode, the RWB bit which is the last bit of the address data not only specifies the direction of communication for control data, but also is processed as an address data bit. When the first-byte address data agree with the slave address, the AAS bit of the I 2C status register (S1: address 001316) is set to “1.” After the second-byte address data is stored into the I2C data shift register (S0: address 001116), perform an ad- dress comparison between the second-byte data and the slave address by software. When the address data of the 2 bytes agree with the slave address, set the RWB bit of the I 2C slave address register to “1” by software. This processing can make the 7-bit slave address and R/W data agree, which are re- ceived after a RESTART condition is detected, with the value of the I 2C slave address register. For the data transmission for- mat when the 10-bit addressing format is selected, refer to Figure 69, (3) and (4). S S l a v e a d d r e s sR / W A D a t a A / A PA D a t a b i t s “ 0 ” 1 t o 8 b i t s1 t o 8 b i t s ( 1 ) A m a s t e r - t r a n s m i t t e r t r a n s m i t s d a t a t o a s l a v e - r e c e i v e r S Slave address R/W A Data A PA Data 7 bits “1” 1 to 8 bits 1 to 8 bits ( 2 ) A m a s t e r - r e c e i v e r r e c e i v e s d a t a f r o m a s l a v e - t r a n s m i t t e r 7 b i t s “ 0 ” 8 b i t s ( 3 ) A m a s t e r - t r a n s m i t t e r t r a n s m i t s d a t a t o a s l a v e - r e c e i v e r w i t h a 1 0 - b i t a d d r e s s 1 to 8 bits 1 t o 8 b i t s S R / W AS l a v e a d d r e s s s t b i t s Slave address 2nd bytes AAD a t a Data PA / A 7 b i t s “ 0 ” 8 b i t s (4) A master-receiver receives data from a slave-transmitter with a 10-bit address S : START condition A : ACK bit Sr : Restart condition P : STOP condition R/W : Read/Write bit 7 b i t s “1” 1 t o 8 b i t s1 t o 8 b i t s S R / W ASlave address 1st 7 bits S l a v e a d d r e s s n d b y t e s A Sr Slave address 1st 7 bits R / W AD a t a D a t a PA : M a s t e r t o s l a v e : S l a v e t o m a s t e r A

Rev.1.01 Jan 25, 2005 page 71 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) Example of Master Transmission An example of master transmission in the standard clock mode, at the SCL frequency of 100 kHz and in the ACK return mode is shown below. ➀ Set a slave address in the high-order 7 bits of the I 2C slave ad- dress register and “0” into the RWB bit. ➁ Set the ACK return mode and SCL = 100 kHz by setting “8516” in the I2C clock control register (S2: address 001516). ➂ Set “0016” in the I2C status register (S1: address 001316) so that transmission/reception mode can become initializing condi- tion. ➃ Set a communication enable status by setting “08 16” in the I2C control register (S1D: address 001416). ➄ Confirm the bus free condition by the BB flag of the I2C status register (S1: address 001316). ➅ Set the address data of the destination of transmission in the high-order 7 bits of the I2C data shift register (S0: address 001116) and set “0” in the least significant bit. ➆ Set “F016” in the I2C status register (S1: address 001316) to generate a START condition. At this time, an SCL for 1 byte and an ACK clock automatically occur. ➇ Set transmit data in the I2C data shift register (S0: address 001116). At this time, an SCL and an ACK clock automatically occur. ➈ When transmitting control data of more than 1 byte, repeat step ➇ . ➉ Set “D0 16” in the I2C status register (S1: address 001316) to generate a STOP condition if ACK is not returned from slave re- ception side or transmission ends. Example of Slave Reception An example of slave reception in the high-speed clock mode, at the SCL frequency of 400 kHz, in the ACK non-return mode and using the addressing format is shown below. ➀ Set a slave address in the high-order 7 bits of the I 2C slave ad- dress register and “0” in the RWB bit. ➁ Set the no ACK clock mode and SCL = 400 kHz by setting “2516” in the I2C clock control register (S2: address 001516). ➂ Set “0016” in the I2C status register (S1: address 001316) so that transmission/reception mode can become initializing condi- tion. ➃ Set a communication enable status by setting “08 16” in the I2C control register (S1D: address 001416). ➄ When a START condition is received, an address comparison is performed. ➅ •When all transmitted addresses are “0” (general call): AD0 of the I2C status register (S1: address 001316) is set to “1” and an interrupt request signal occurs.

• When the transmitted addresses agree with the address set in ➀ : AAS of the I2C status register (S1: address 001316) is set to “1” and an interrupt request signal occurs.
• In the cases other than the above AD0 and AAS of the I2C sta- tus register (S1: address 001316) are set to “0” and no interrupt request signal occurs. ➆ Set dummy data in the I2C data shift register (S0: address 001116). ➇ When receiving control data of more than 1 byte, repeat step ➆ . ➈ When a STOP condition is detected, the communication ends.

Rev.1.01 Jan 25, 2005 page 72 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) (2) START condition generating procedure using multi-master 1. Procedure example (The necessary conditions of the generat- ing procedure are described as the following 2 to 5. LDA — (Taking out of slave address value) SEI (Interrupt disabled) BBS 5, S1, BUSBUSY (BB flag confirming and branch process) BUSFREE: STA S0 (Writing of slave address value) LDM #$F0, S1 (Trigger of START condition generating) CLI (Interrupt enabled) BUSBUSY: CLI (Interrupt enabled) 2. Use “Branch on Bit Set” of “BBS 5, S1, –” for the BB flag con- firming and branch process. 3. Use “STA $12, STX $12” or “STY $12 ” of the zero page ad- dressing instruction for writing the slave address value to the I 2C data shift register. 4. Execute the branch instruction of above 2 and the store instruc- tion of above 3 continuously shown the above procedure example. 5. Disable interrupts during the following three process steps:

• BB flag confirming
• Writing of slave address value
• Trigger of START condition generating When the condition of the BB flag is bus busy, enable interrupts immediately. (3) RESTART condition generating procedure 1. Procedure example (The necessary conditions of the generat- ing procedure are described as the following 2 to 4.) Execute the following procedure when the PIN bit is “0.” LDM #$00, S1 (Select slave receive mode) LDA — (Taking out of slave address value) SEI (Interrupt disabled) STA S0 (Writing of slave address value) LDM #$F0, S1 ( Trigger of RESTART condition generating) CLI (Interrupt enabled) 2. Select the slave receive mode when the PIN bit is “0.” Do not write “1” to the PIN bit. Neither “0” nor “1” is specified for the writing to the BB bit. The TRX bit becomes “0” and the SDA pin is released. 3. The SCL pin is released by writing the slave address value to the I 2C data shift register. 4. Disable interrupts during the following two process steps:
• Writing of slave address value
• Trigger of RESTART condition generating (4) Writing to I2C status register Do not execute an instruction to set the PIN bit to “1” from “0” and an instruction to set the MST and TRX bits to “0” from “1” simulta- neously. It is because it may enter the state that the SCL pin is released and the SDA pin is released after about one machine cycle. Do not execute an instruction to set the MST and TRX bits to “0” from “1” simultaneously when the PIN bit is “1.” It is because it may become the same as above. (5) Process of after STOP condition generating Do not write data in the I 2C data shift register S0 and the I2C sta- tus register S1 until the bus busy flag BB becomes “0” after generating the STOP condition in the master mode. It is because the STOP condition waveform might not be normally generated. Reading to the above registers does not have the problem. I Precautions when using multi-master I2C- BUS interface (1) Read-modify-write instruction The precautions when the read-modify-write instruction such as SEB, CLB etc. is executed for each register of the multi-master I 2C-BUS interface are described below.
• I2C data shift register (S0: address 001116) When executing the read-modify-write instruction for this regis- ter during transfer, data may become a value not intended.
• I 2C slave address registers 0 to 2 (S0D0 to S0D2: addresses 0FF7 16 to0FF916) When the read-modify-write instruction is executed for this regis- ter at detecting the STOP condition, data may become a value not intended. It is because H/W changes the read/write bit (RWB) at the above timing.
• I 2C status register (S1: address 001316) Do not execute the read-modify-write instruction for this register because all bits of this register are changed by H/W.
• I 2C control register (S1D: address 001416) When the read-modify-write instruction is executed for this regis- ter at detecting the START condition or at completing the byte transfer, data may become a value not intended. Because H/W changes the bit counter (BC0-BC2) at the above timing.
• I 2C clock control register (S2: address 001516) The read-modify-write instruction can be executed for this regis- ter.
• I 2C START/STOP condition control register (S2D: address 001616) The read-modify-write instruction can be executed for this regis- ter.

Rev.1.01 Jan 25, 2005 page 73 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) RESET CIRCUIT To reset the microcomputer, RESET pin should be held at an “L” level for 16 cycles or more of XIN. Then the RESET pin is returned to an “H ” level (the power source voltage should be between 2.7 V to 5.5 V, and the oscillation should be stable), reset is released. After the reset is completed, the program starts from the address contained in address FFFD16 (high-order byte) and address FFFC 16 (low-order byte). Input to the RESET pin in the following procedure. G When power source is stabilized (1) Input “L” level to RESET pin. (2) Input “L” level for 16 cycles or more to X IN pin. (3) Input “H ” level to RESET pin. G At power-on (1) Input “L” level to RESET pin. (2) Increase the power source voltage to 2.7 V. (3) Wait for td(P-R) until internal power source has stabilized. (4) Input “L” level for 16 cycles or more to XIN pin. (5) Input “H ” level to RESET pin. Fig. 71 Reset sequence Fig. 70 Reset circuit example RESET Internal reset Data φ Address SYNC XIN: 10.5 to 18.5 clock cycles XIN ? ? ?? ? FFFC FFFD AD H ,L 1: The frequency relation of f(XIN) and f(φ) is f(XIN)=8 • f(φ). 2: The question marks (?) indicate an undefined state that depends on the previous state. Reset address from the vector table. Notes VCCRESET VCCRESET Exam ple at VCC = 5V td(P-R)+XIN 16 cycles or more 2.7 V 0.2VCC or less VCC RESET VCC RESET td(P-R)+XIN 16 cycles or more 2.7 V Power source voltage detection circuit

Rev.1.01 Jan 25, 2005 page 74 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) Fig. 72 Internal status at reset Timer Z (low-order) (TZL) Timer Z (high-order) (TZH) Timer Z mode register (TZM) PWM control register (PWMCON) PWM prescaler (PREPWM) PWM register (PWM) Baud rate generator 3 (BRG3) Transmit/Receive buffer register 3 (TB3/RB3) Serial I/O3 status register (SIO3STS) Serial I/O3 control register (SIO3CON) UART3 control register (UART3CON) AD/DA control register (ADCON) AD conversion register 1 (AD1) DA1 conversion register (DA1) DA2 conversion register (DA2) AD conversion register 2 (AD2) Interrupt source selection register (INTSEL) Interrupt edge selection register (INTEDGE) CPU mode register (CPUM) Interrupt request register 1 (IREQ1) Interrupt request register 2 (IREQ2) Interrupt control register 1 (ICON1) Interrupt control register 2 (ICON2) Flash memory control register 0 (FMCR0) Flash memory control register 1 (FMCR1) Flash memory control register 2 (FMCR2) Port P0 pull-up control register (PULL0) Port P1 pull-up control register (PULL1) Port P2 pull-up control register (PULL2) Port P3 pull-up control register (PULL3) Port P4 pull-up control register (PULL4) Port P5 pull-up control register (PULL5) Port P6 pull-up control register (PULL6) I2C slave address register 0 (S0D0) I2C slave address register 1 (S0D1) I2C slave address register 2 (S0D3) Processor status register Program counter XXXXXXXX 1110 0 000 Note :X : Not fixed Since the initial values for other than above mentioned registers and RAM contents are indefinite at reset, they must be set. (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) (15) (16) (17) (18) (19) (20) (21) (22) (23) (24) (25) (26) (27) (28) (29) (30) (31) (32) (33) (34) (35) (36) (37) (38) (39) (40) (41) (42) (43) (44) (45) (46) (47) (48) (49) (50) (51) (52) (53) (54) (55) (56) (57) (58) (59) (60) (61) (62) (63) (64) (65) (66) (67) (68) (69) (70) (71) (72) (73) (74) (75) (76) (77) Register contents 002816 002916 002A16 002B16 002C 16 002D 16 002F16 003016 003116 003216 003316 003416 003516 003616 003716 003816 003916 003A16 003B16 003C 16 003D 16 003E16 003F16 0FE0 16 0FE1 16 0FE2 16 0FF016 0FF116 0FF216 0FF316 0FF416 0FF516 0FF616 0FF716 0FF816 0FF916 (PS) (PCH ) (PCL) Address FF16 FF16 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0116 4016 4516 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 Address Register contents 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 FF16 0116 FF16 0016 FF16 FF16 FF16 FF16 XXXXXXXX 00111111 XXXXXXXX FFFD 16 contents FFFC 16 contents XXXXXXX Port P0 (P0) Port P0 direction register (P0D) Port P1 (P1) Port P1 direction register (P1D) Port P2 (P2) Port P2 direction register (P2D) Port P3 (P3) Port P3 direction register (P3D) Port P4 (P4) Port P4 direction register (P4D) Port P5 (P5) Port P5 direction register (P5D) Port P6 (P6) Port P6 direction register (P6D) Timer 12, X count source selection register (T12XCSS) Timer Y, Z count source selection register (TYZCSS) MISRG I2C data shift register (S0) I2C special mode status register (S3) I2C status register (S1) I2C control register (S1D) I2C clock control register (S2) I2C START/STOP condition control register (S2D) I2C special mode control register (S3D) Transmit/Receive buffer register 1 (TB1/RB1) Serial I/O1 status register (SIO1STS) Serial I/O1 control register (SIO1CON) UART1 control register (UART1CON) Baud rate generator 1 (BRG1) Serial I/O2 control register (SIO2CON) Watchdog timer control register (WDTCON) Serial I/O2 register (SIO2) Prescaler 12 (PRE12) Timer 1 (T1) Timer 2 (T2) Timer XY mode register (TM) Prescaler X (PREX) Timer X (TX) Prescaler Y (PREY) Timer Y (TY) 00110011 00110011 XXXXXXXX 10000000 000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C 16 000D 16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C 16 001D 16 001E16 001F16 002016 002116 002216 002316 002416 002516 002616 002716 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 10000000 11 100000 00 001000 XX000000 01 00 1000 XXXXXXXX 00100000 0001000X 00011010

Rev.1.01 Jan 25, 2005 page 75 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) CLOCK GENERATING CIRCUIT The 3804 group (Spec. H) has two built-in oscillation circuits: main clock XIN-XOUT oscillation circuit and sub clock XCIN-XCOUT oscil- lation circuit. An oscillation circuit can be formed by connecting a resonator between X IN and XOUT (XCIN and XCOUT ). Use the cir- cuit constants in accordance with the resonator manufacturer’s recommended values. No external resistor is needed between XIN and XOUT since a feed-back resistor exists on-chip.(An external feed-back resistor may be needed depending on conditions.) However, an external feed-back resistor is needed between X CIN and XCOUT . Immediately after power on, only the XIN oscillation circuit starts oscillating, and XCIN and XCOUT pins function as I/O ports. Frequency Control (1) Middle-speed mode The internal clock φ is the frequency of XIN divided by 8. After re- set is released, this mode is selected. (2) High-speed mode The internal clock φ is half the frequency of XIN. (3) Low-speed mode The internal clock φ is half the frequency of XCIN. (4) Low power dissipation mode The low power consumption operation can be realized by stopping the main clock XIN in low-speed mode. To stop the main clock, set bit 5 of the CPU mode register to “1.” When the main clock XIN is restarted (by setting the main clock stop bit to “0”), set sufficient time for oscillation to stabilize. Oscillation Control (1) Stop mode If the STP instruction is executed, the internal clock φ stops at an “H ” level, and XIN and XCIN oscillators stop. When the oscillation stabilizing time set after STP instruction released bit is “0,” the prescaler 12 is set to “FF16” and timer 1 is set to “0116.” When the oscillation stabilizing time set after STP instruction released bit is “1,” set the sufficient time for oscillation of used oscillator to stabi- lize since nothing is set to the prescaler 12 and timer 1. After STP instruction is released, the input of the prescaler 12 is connected to count source which had set at executing the STP in- struction, and the output of the prescaler 12 is connected to timer 1. Set the timer 1 interrupt enable bit to disabled (“0”) before ex- ecuting the STP instruction. Oscillator restarts when an external interrupt is received, but the internal clock φ is not supplied to the CPU (remains at “H ”) until timer 1 underflows. The internal clock φ is supplied for the first time, when timer 1 underflows. Therefore make sure not to set the timer 1 interrupt request bit to “1” before the STP instruction stops the oscillator. When the oscillator is re- started by reset, apply “L” level to the RESET pin until the oscillation is stable since a wait time will not be generated. The internal power supply circuit is changed to low power con- sumption mode for consumption current reduction at the time of STP instruction execution. Although an internal power supply circuit is usually changed to the normal operation mode at the time of the return from an STP in- struction, since a certain time is required to start the power supply to the flash memory and operation of flash memory to be enabled, set wait time 100 µs or more by the oscillation stabilization time set function after release of the STP instruction which used the timer 1. (2) Wait mode If the WIT instruction is executed, the internal clock φ stops at an “H ” level, but the oscillator does not stop. The internal clock φ re- starts when an interrupt is received. Since the oscillator does not stop, normal operation can be started immediately after the clock is restarted. I Note

• If you switch the mode between middle/high-speed and low- speed, stabilize both X IN and XCIN oscillations. The sufficient time is required for the sub clock to stabilize, especially immediately after power on and at returning from stop mode. When switching the mode between middle/high-speed and low-speed, set the fre- quency on condition that f(X IN) > 3f(XCIN).
• When using the quartz-crystal oscillator of high frequency, such as 16 MHz etc., it may be necessary to select a specific oscillator with the specification demanded.

Rev.1.01 Jan 25, 2005 page 76 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) Fig. 73 Ceramic resonator circuit Fig. 74 External clock input circuit VCC VSS XCIN XCOUT XIN XOUT Open Open External oscillation circuit External oscillation circuit VCC VSS XC I N XC O U T XI N XO U T C I N C O U TC C I N C C O U T Rf Rd Rd (Note) N o t e s : I n s e r t a d a m p i n g r e s i s t o r i f r e q u i r e d . T h e r e s i s t a n c e w i l l v a r y d e p e n d i n g o n t h e o s c i l l a t o r a n d t h e o s c i l l a t i o n d r i v e c a p a c i t y s e t t i n g U s e t h e v a l u e r e c o m m e n d e d b y t h e m a k e r o f t h e o s c i l l a t o r A l s o i f t h e o s c i l l a t o r m a n u f a c t u r e r s d a t a s h e e t s p e c i f i e s t h a t a f e e d b a c k r e s i s t o r b e a d d e d e x t e r n a l t o t h e c h i p t h o u g h a f e e d b a c k r e s i s t o r e x i s t s o n c h i p i n s e r t a f e e d b a c k r e s i s t o r b e t w e e n XI N a n d XO U T f o l l o w i n g t h e i n s t r u c t i o n

Rev.1.01 Jan 25, 2005 page 77 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) WIT instruction STP instruction Timing φ (internal clock) S R Q STP instruction S R Q Main clock stop bit S R Q 1/2 1/4 XIN XOUT XCOUTXCIN Interrupt request Reset Interrupt disable flag l Port XC switch bit “1” “0” Low-speed mode High-speed or middle-speed mode Middle-speed mode High-speed or low-speed mode Main clock division ratio selection bits (Note 1) Notes 1: Either high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the CPU mode register. When low-speed mode is selected, set port Xc switch bit (b4) to “1”. 2: f(XIN)/16 is supplied as the count source to the prescaler 12 at reset. The count source before executing the STP instruction is supplied as the count source at executing STP instruction. 3: When bit 0 of MISRG is “0”, timer 1 is set “0116” and prescaler 12 is set “FF16” automatically. When bit 0 of MISRG is “1”, set the appropriate value to them in accordance with oscillation stablizing time required by the using oscillator because nothing is automatically set into timer 1 and prescaler 12. 4: Although a feed-back resistor exists on-chip, an external feed-back resistor may be needed depending on conditions. Main clock division ratio selection bits (Note 1) Prescaler 12 Timer 1 Reset or STP instruction (Note 2) Divider (Note 3) Reset (Note 4) Fig. 75 System clock generating circuit block diagram

Rev.1.01 Jan 25, 2005 page 78 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) Fig. 76 State transitions of system clock C M 4 : P o r t X c s w i t c h b i t I O p o r t f u n c t i o n s t o p o s c i l l a t i n g XC I N - XC O U T o s c i l l a t i n g f u n c t i o n C M 5 M a i n c l o c k XI N - XO U s t o p b i t O p e r a t i n g S t o p p e d C M 7, C M 6: M a i n c l o c k d i v i s i o n r a t i o s e l e c t i o n b i t b b φ f XI N ) H i g h s p e e d m o d e φ f XI N ) M i d d l e s p e e d m o d e φ f XC I N ) L o w s p e e d m o d e N o t a v a i l a b l e Notes R e s e t C M → “ ” C M4“ → “ C M6“ → “ C M4 ”← → “ C → “ C M 7 → “ C M 4 → “ C M 5 → “ CM 6 C M 6 → “ C P U m o d e r e g i s t e r b7 b4 C M7“ → “ C M6“ → “ ( C P U M : a d d r e s s 0 0 3 B1 C M 7= 0 C M 6= C M 5= M H z o s c i l l a t i n g C M 4= k H z s t o p p e d M i d d l e - s p e e d m o d e f (φ) M H z C M 7= 0 C M 6= C M 5= M H z o s c i l l a t i n g C M 4= k H z o s c i l l a t i n g M i d d l e - s p e e d m o d e f (φ) M H z CM 7=0 CM 6=0 CM 5=0(8 MHz oscillating) CM 4=0(32 kHz stopped) High-speed mode (f(φ)=4 MHz) C M 7= 1 C M 6= C M 5= M H z o s c i l l a t i n g C M 4= k H z o s c i l l a t i n g Low-speed mode (f(φ)=16 kHz) C M 7= 1 C M 6= C M 5= M H z s t o p p e d C M 4= k H z o s c i l l a t i n g L o w - s p e e d m o d e f (φ) k H z CM 7=0 CM 6=0 CM 5=0(8 MHz oscillating) CM 4=1(32 kHz oscillating) High-speed mode (f(φ)=4 MHz) 1 : S w i t c h t h e m o d e b y t h e a l l o w s s h o w n b e t w e e n t h e m o d e b l o c k s . ( D o n o t s w i t c h b e t w e e n t h e m o d e s d i r e c t l y w i t h o u t a n a l l o w . ) T h e a l l m o d e s c a n b e s w i t c h e d t o t h e s t o p m o d e o r t h e w a i t m o d e a n d r e t u r n t o t h e s o u r c e m o d e w h e n t h e s t o p m o d e o r t h e w a i t m o d e i s e n d e d T i m e r o p e r a t e s i n t h e w a i t m o d e W h e n t h e s t o p m o d e i s e n d e d a d e l a y o f a p p r o x i m a t e l y m s o c c u r s b y c o n n e c t i n g p r e s c a l e r a n d T i m e r i n m i d d l e h i g h s p e e d m o d e W h e n t h e s t o p m o d e i s e n d e d a d e l a y o f a p p r o x i m a t e l y s o c c u r s b y T i m e r a n d T i m e r i n l o w s p e e d m o d e : W a i t u n t i l o s c i l l a t i o n s t a b i l i z e s a f t e r o s c i l l a t i n g t h e m a i n c l o c k XI N b e f o r e t h e s w i t c h i n g f r o m t h e l o w s p e e d m o d e t o m i d d l e h i g h s p e e d m o d e T h e e x a m p l e a s s u m e s t h a t M H z i s b e i n g a p p l i e d t o t h e XI N p i n a n d k H z t o t h e XC I N p i n φ i n d i c a t e s t h e i n t e r n a l c l o c k

Rev.1.01 Jan 25, 2005 page 79 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) Table 13 Summary of 3804 group (spec. H) FLASH MEMORY MODE The 3804 group (spec. H) has the flash memory that can be re- written with a single power source. For this flash memory, three flash memory modes are available in which to read, program, and erase: the parallel I/O and standard serial I/O modes in which the flash memory can be manipulated using a programmer and the CPU rewrite mode in which the flash memory can be manipulated by the Central Processing Unit (CPU). This flash memory has some blocks on it as shown in Figure 77 and each block can be erased. In addition to the ordinary User ROM area to store the MCU op- eration control program, the flash memory has a Boot ROM area that is used to store a program to control rewriting in CPU rewrite and standard serial I/O modes. This Boot ROM area has had a standard serial I/O mode control program stored in it when shipped from the factory. However, the user can write a rewrite control program in this area that suits the user’s application sys- tem. This Boot ROM area can be rewritten in only parallel I/O mode. G Summary Table 13 lists the summary of the 3804 Group (spec. H). Item Power source voltage (Vcc) Program/Erase V PP voltage (VPP ) Flash memory mode Erase block division User ROM area/Data ROM area Boot ROM area (Note) Program method Erase method Program/Erase control method Number of commands Number of program/Erase times ROM code protection Specifications V CC = 2.7 to 5.5 V VCC = 2.7 to 5.5 V 3 modes; Parallel I/O mode, Standard serial I/O mode, CPU rewrite mode Refer to Fig. 77. Not divided (4K bytes) In units of bytes Block erase Program/Erase control by software command 5 commands 100 Available in parallel I/O mode and standard serial I/O mode Note: The Boot ROM area has had a standard serial I/O mode control program stored in it when shipped from the factory. This Boot ROM area can be erased and written in only parallel I/O mode.

Rev.1.01 Jan 25, 2005 page 80 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) Fig. 77 Block diagram of built-in flash memory G Boot Mode The control program for CPU rewrite mode must be written into the User ROM or Boot ROM area in parallel I/O mode beforehand. (If the control program is written into the Boot ROM area, the stan- dard serial I/O mode becomes unusable.) See Figure 77 for details about the Boot ROM area. Normal microcomputer mode is entered when the microcomputer is reset with pulling CNV SS pin low. In this case, the CPU starts operating using the control program in the User ROM area. When the microcomputer is reset and the CNV SS pin high after pulling the P45/TxD1 pin and CNVss pin high, the CPU starts op- erating (start address of program is stored into addresses FFFC16 and FFFD 16) using the control program in the Boot ROM area. This mode is called the “Boot mode”. Also, User ROM area can be rewritten using the control program in the Boot ROM area. G Block Address Block addresses refer to the maximum address of each block. These addresses are used in the block erase command. G CPU Rewrite Mode In CPU rewrite mode, the internal flash memory can be operated on (read, program, or erase) under control of the Central Process- ing Unit (CPU). In CPU rewrite mode, only the User ROM area shown in Figure 77 can be rewritten; the Boot ROM area cannot be rewritten. Make sure the program and block erase commands are issued for only the User ROM area and each block area. The control program for CPU rewrite mode can be stored in either User ROM or Boot ROM area. In the CPU rewrite mode, because the flash memory cannot be read from the CPU, the rewrite con- trol program must be transferred to internal RAM area before it can be executed. SFR area Internal RAM area (2K bytes) 000016 004016 083F16 SFR area Internal flash memory area (60K bytes) 0FE0 16 RAM FFFF 16 0FFF 16 100016 User ROM area Data block B: 2K bytes 100016 180016 E00016 C000 16 FFFF 16 F00016 FFFF 16 Boot ROM area 4K bytes Notes 1: The boot ROM area can be rewritten in a paral- lel I/O mode. (Access to except boot ROM area is disablrd.) 2: To specify a block, use the maximum address in the block. Block 3: 24K bytes 2000 800016 Data block A: 2K bytes Block 2: 16K bytes Block 1: 8 K bytes Block 0: 8 K bytes

Rev.1.01 Jan 25, 2005 page 82 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) Fig. 81 CPU rewrite mode set/release flowchart Figure 81 shows a flowchart for setting/releasing CPU rewrite mode. Fig. 80 Structure of flash memory control register 2 Table 14 State of E/W inhibition function All user block E/W enable bit

8 KB user block E/W

8 KB ✕ 2 block

16 KB + 24 KB block

Notes 1: For this bit to be set to “1”, the user needs to write a “0” and then a “1” to it in succession. For this bit to be set to “0”, write “0” only to this bit. 2: Effective only when the CPU rewrite mode select bit = “1”. b7 b0 Not used Not used (do not write “1” to this bit.) All user block E/W enable bit (Notes 1, 2) 0 : E/W disabled 1 : E/W enabled Flash memory control register 2 (FMCR2: address : 0FE216: initial value: 4516) Not used Not used End Start Execute read array command (Note 2) Single-chip mode or Boot mode Set CPU mode register (Note 1) Using software command executes erase, program, or other operation J u m p t o c o n t r o l p r o g r a m t r a n s f e r r e d t o i n t e r n a l R A M S u b s e q u e n t o p e r a t i o n s a r e e x e c u t e d b y c o n t r o l p r o g r a m i n t h i s R A M Transfer CPU rewrite mode control program to internal RAM Notes 1: Set the main clock as follows depending on the clock division ratio selection bits of CPU mode register (bits 6, 7 of address 003B16). 2: Before exiting the CPU rewrite mode after completing erase or program operation, always be sure to execute the read array command. W r i t e t o C P U r e w r i t e m o d e s e l e c t b i t S e t C P U r e w r i t e m o d e s e l e c t b i t t o “ 1 ” ( b y w r i t i n g a n d t h e n i n s u c c e s s i o n S e t a l l u s e r b l o c k E / W e n a b l e b i t t o “ 1 ” b y w r i t i n g a n d t h e n i n s u c c e s s i o n S e t K B u s e r b l o c k E W e n a b l e b i t A t E W d i s a b l e d w r i t i n g a t E W e n a b l e d w r i t i n g a n d t h e n i n s u c c e s s i o n Set all user block E/W enable bit to “0” Set 8 KB user block E/W enable bit to “0”

Rev.1.01 Jan 25, 2005 page 83 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) I Notes on CPU Rewrite Mode Take the notes described below when rewriting the flash memory in CPU rewrite mode. G Operation speed During CPU rewrite mode, set the system clock φ to 4.0 MHz or less using the clock division ratio selection bits (bits 6 and 7 of ad- dress 003B 16). G Instructions inhibited against use The instructions which refer to the internal data of the flash memory cannot be used during CPU rewrite mode. G Interrupts The interrupts cannot be used during CPU rewrite mode because they refer to the internal data of the flash memory. G Watchdog timer If the watchdog timer has been already activated, internal reset due to an underflow will not occur because the watchdog timer is surely cleared during program or erase. G Reset Reset is always valid. The MCU is activated using the boot mode at release of reset in the condition of CNVss = “H ”, so that the pro- gram will begin at the address which is stored in addresses FFFC 16 and FFFD16 of the boot ROM area.

Rev.1.01 Jan 25, 2005 page 84 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) G Software Commands Table 15 lists the software commands. After setting the CPU rewrite mode select bit to “1”, execute a soft- ware command to specify an erase or program operation. Each software command is explained below.

• Read Array Command (FF 16) The read array mode is entered by writing the command code “FF 16” in the first bus cycle. When an address to be read is input in one of the bus cycles that follow, the contents of the specified address are read out at the data bus (D 0 to D7). The read array mode is retained until another command is written.
• Read Status Register Command (7016) When the command code “7016” is written in the first bus cycle, the contents of the status register are read out at the data bus (D0 to D7) by a read in the second bus cycle. The status register is explained in the next section.
• Clear Status Register Command (5016) This command is used to clear the bits SR4 and SR5 of the status register after they have been set. These bits indicate that opera- tion has ended in an error. To use this command, write the command code “50 16” in the first bus cycle.
• Program Command (40 16) Program operation starts when the command code “4016” is writ- ten in the first bus cycle. Then, if the address and data to program are written in the 2nd bus cycle, program operation (data program- ming and verification) will start. Whether the write operation is completed can be confirmed by read status register or the RY/BY status flag. When the program starts, the read status register mode is entered automatically and the contents of the status register is read at the data bus (D 0 to D 7). The status register bit 7 (SR7) is set to “0” at the same time the write operation starts and is returned to “1” upon completion of the write operation. In this case, the read status register mode re- mains active until the read array command (FF16) is written. Table 15 List of software commands (CPU rewrite mode) The RY/BY status flag of the flash memory control register is “0” during write operation and “1” when the write operation is com- pleted as is the status register bit 7. At program end, program results can be checked by reading the status register. Fig. 82 Program flowchart C o m m a n d Program Clear status register Read array Read status register X X F i r s t b u s c y c l eS e c o n d b u s c y c l e F F1 7 01 5 01 4 01 Write Write Write Write XS R DRead W r i t e (Note 1) W A ( N o t e ) WD (Note 2) Block erase 2 01 6Write D0 16W r i t eB A (Note 3) M o d eA d d r e s s M o d eA d d r e s s D a t a ( D 0 t o D 7)(D0 to D7) N o t e N o t e s 1 : S R D = S t a t u s R e g i s t e r D a t a W A W r i t e A d d r e s s W D W r i t e D a t a B A B l o c k A d d r e s s t o b e e r a s e d I n p u t t h e m a x i m u m a d d r e s s o f e a c h b l o c k X d e n o t e s a g i v e n a d d r e s s i n t h e U s e r R O M a r e a Cycle number X X X D a t a S t a r t W r i t e “ 4 01 R e a d s t a t u s r e g i s t e r P r o g r a m c o m p l e t e d N O Y E S W r i t e a d d r e s s W r i t e d a t a SR4 = “0”? P r o g r a m e r r o r N O Y E S S R 7 = “ 1 ” ? o r R Y B Y W r i t e

Rev.1.01 Jan 25, 2005 page 85 of 114 REJ03B0131-0101Z 3804 Group (Spec. H)

• Block Erase Command (2016/D016) By writing the command code “2016” in the first bus cycle and the confirmation command code “D0 16” and the block address in the second bus cycle that follows, the block erase (erase and erase verify) operation starts for the block address of the flash memory to be specified. Whether the block erase operation is completed can be confirmed by read status register or the RY/BY status flag of flash memory control register. At the same time the block erase operation starts, the read status register mode is automatically entered, so that the contents of the status register can be read out. The status register bit 7 (SR7) is set to “0” at the same time the block erase operation starts and is returned to “1” upon completion of the block erase operation. In this case, the read status register mode remains ac- tive until the read array command (FF 16) is written. The RY/BY status flag is “0” during block erase operation and “1” when the block erase operation is completed as is the status reg- ister bit 7. After the block erase ends, erase results can be checked by read- ing the status register. For details, refer to the section where the status register is detailed. Fig. 83 Erase flowchart Write “2016” “ D 01 B l o c k a d d r e s s Erase completed (write read command “FF16”) NO YES Start W r i t e S R 5 = “ 0 ” ? E r a s e e r r o r YES N O S R 7 = “ 1 ” ? o r R Y B Y R e a d s t a t u s r e g i s t e r

Rev.1.01 Jan 25, 2005 page 86 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) Table 16 Definition of each bit in status register G Status Register The status register shows the operating status of the flash memory and whether erase operations and programs ended suc- cessfully or in error. It can be read in the following ways: (1) By reading an arbitrary address from the User ROM area after writing the read status register command (70 16) (2) By reading an arbitrary address from the User ROM area in the period from when the program starts or erase operation starts to when the read array command (FF 16) is input. Also, the status register can be cleared by writing the clear status register command (5016). After reset, the status register is set to “8016”. Table 16 shows the status register. Each bit in this register is ex- plained below.

• Sequencer status (SR7) The sequencer status indicates the operating status of the flash memory. This bit is set to “0” (busy) during write or erase operation and is set to “1” when these operations ends. After power-on, the sequencer status is set to “1” (ready).
• Erase status (SR5) The erase status indicates the operating status of erase operation. If an erase error occurs, it is set to “1”. When the erase status is cleared, it is reset to “0”.
• Program status (SR4) The program status indicates the operating status of write opera- tion. When a write error occurs, it is set to “1”. The program status is reset to “0” when it is cleared. If “1” is written for any of the SR5 and SR4 bits, the read array, program, and block erase commands are not accepted. Before ex- ecuting these commands, execute the clear status register command (50 16) and clear the status register. Also, if any commands are not correct, both SR5 and SR4 are set to “1”. Each bit of SRD bits SR7 (bit7) SR6 (bit6) SR5 (bit5) SR4 (bit4) SR3 (bit3) SR2 (bit2) SR1 (bit1) SR0 (bit0) Sequencer status Reserved Erase status Program status Reserved Reserved Reserved Reserved Status name “1” Ready Terminated in error Terminated in error “0” Busy Terminated normally Terminated normally Definition

Rev.1.01 Jan 25, 2005 page 87 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) G Full Status Check By performing full status check, it is possible to know the execu- tion results of erase and program operations. Figure 84 shows a full status check flowchart and the action to be taken when each error occurs. Fig. 84 Full status check flowchart and remedial procedure for errors R e a d s t a t u s r e g i s t e r S R 4 = “ 1 ” a n d S N O Y E S SR5 = “0” ? Y E S Er a s e e r r o rN O S R 4 = “ 0 ” ? YES NO Command sequence error P r o g r a m e r r o r E n d ( b l o c k e r a s e , p r o g r a m ) E x e c u t e t h e c l e a r s t a t u s r e g i s t e r c o m m a n d ( 5 01 t o c l e a r t h e s t a t u s r e g i s t e r T r y p e r f o r m i n g t h e o p e r a t i o n o n e m o r e t i m e a f t e r c o n f i r m i n g t h a t t h e c o m m a n d i s e n t e r e d c o r r e c t l y S h o u l d a n e r a s e e r r o r o c c u r , t h e b l o c k i n e r r o r c a n n o t b e u s e d Note: When one of SR5 and SR4 is set to “1”, none of the read array, program, and block erase commands is accepted. Execute the clear status register command (50 16) before executing these commands. S h o u l d a p r o g r a m e r r o r o c c u r , t h e b l o c k i n e r r o r c a n n o t b e u s e d

Rev.1.01 Jan 25, 2005 page 88 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) G Functions To Inhibit Rewriting Flash Memory Version To prevent the contents of internal flash memory from being read out or rewritten easily, this MCU incorporates a ROM code protect function for use in parallel I/O mode and an ID code check func- tion for use in standard serial I/O mode. (1) ROM Code Protect Function The ROM code protect function is the function to inhibit reading out or modifying the contents of internal flash memory by using the ROM code protect control address (address FFDB 16) in paral- lel I/O mode. Figure 85 shows the ROM code protect control address (address FFDB16). (This address exists in the User ROM area.) If one or both of the pair of ROM code protect bits is set to “0”, the ROM code protect is turned on, so that the contents of internal flash memory are protected against readout and modification. The ROM code protect is implemented in two levels. If level 2 is se- lected, the flash memory is protected even against readout by a shipment inspection LSI tester, etc. When an attempt is made to select both level 1 and level 2, level 2 is selected by default. If both of the two ROM code protect reset bits are set to “00”, the ROM code protect is turned off, so that the contents of internal flash memory can be readout or modified. Once the ROM code protect is turned on, the contents of the ROM code protect reset bits cannot be modified in parallel I/O mode. Use the serial I/O or CPU rewrite mode to rewrite the contents of the ROM code protect reset bits. Rewriting of only the ROM code protect control address (address FFDB 16) cannot be performed. When rewriting the ROM code pro- tect reset bit, rewrite the whole user ROM area (block 0) containing the ROM code protect control address. Fig. 85 Structure of ROM code protect control address R O M c o d e p r o t e c t c o n t r o l a d d r e s s a d d r e s s F F D R O M C P F w h e n s h i p p e d Reserved bits (“1” at read/write) ROM code protect level 2 set bits (ROMCP2) (Notes 1, 2) b3b2 0 0: Protect enabled 0 1: Protect enabled 1 0: Protect enabled 1 1: Protect disabled ROM code protect reset bits (ROMCR) (Note 3) b5b4 0 0: Protect removed 0 1: Protect set bits effective 1 0: Protect set bits effective 1 1: Protect set bits effective ROM code protect level 1 set bits (ROMCP1) (Note 1) b7b6 0 0: Protect enabled 0 1: Protect enabled 1 0: Protect enabled 1 1: Protect disabled b0b Notes 1: When ROM code protect is turned on, the internal flash memory is protected against readout or modification in parallel I/O mode. 2: When ROM code protect level 2 is turned on, ROM code readout by a shipment inspection LSI tester, etc. also is inhibited. 3: The ROM code protect reset bits can be used to turn off ROM code protect level 1 and ROM code protect level 2. However, since these bits cannot be modified in parallel I/O mode, they need to be rewritten in serial I/O mode or CPU rewrite mode.

Rev.1.01 Jan 25, 2005 page 89 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) (2) ID Code Check Function Use this function in standard serial I/O mode. When the contents of the flash memory are not blank, the ID code sent from the pro- grammer is compared with the ID code written in the flash memory to see if they match. If the ID codes do not match, the commands sent from the programmer are not accepted. The ID code consists of 8-bit data, and its areas are FFD4 16 to FFDA16. Write a pro- gram which has had the ID code preset at these addresses to the flash memory. Fig. 86 ID code store addresses ROM code protect control ID7 ID6 ID5 ID4 ID3 ID2 ID1 FFDB 16 FFDA 16 FFD9 16 FFD8 16 FFD7 16 FFD6 16 FFD5 16 FFD4 16 Address Interrupt vector area

Rev.1.01 Jan 25, 2005 page 90 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) G Parallel I/O Mode The parallel I/O mode is used to input/output software commands, address and data in parallel for operation (read, program and erase) to internal flash memory. Use the external device (writer) only for 3804 Group (spec. H). For details, refer to the user’s manual of each writer manufacturer.

• User ROM and Boot ROM Areas In parallel I/O mode, the User ROM and Boot ROM areas shown in Figure 77 can be rewritten. Both areas of flash memory can be operated on in the same way. The Boot ROM area is 4 Kbytes in size and located at addresses F000 16 through FFFF16. Make sure program and block erase op- erations are always performed within this address range. (Access to any location outside this address range is prohibited.) In the Boot ROM area, an erase block operation is applied to only one 4 Kbyte block. The boot ROM area has had a standard serial I/O mode control program stored in it when shipped from the fac-tory. Therefore, using the MCU in standard serial I/O mode, do not rewrite to the Boot ROM area.

Rev.1.01 Jan 25, 2005 page 91 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) G Standard serial I/O Mode The standard serial I/O mode inputs and outputs the software commands, addresses and data needed to operate (read, pro- gram, erase, etc.) the internal flash memory. This I/O is clock synchronized serial. This mode requires a purpose-specific pe- ripheral unit. The standard serial I/O mode is different from the parallel I/O mode in that the CPU controls flash memory rewrite (uses the CPU rewrite mode), rewrite data input and so forth. The standard serial I/O mode is started by connecting “H ” to the CNVss pin and “H ” to the P4 5 (BOOTENT) pin, and releasing the reset operation. (In the ordinary microcomputer mode, set CNVss pin to “L” level.) This control program is written in the Boot ROM area when the product is shipped from Renesas. Accordingly, make note of the fact that the standard serial I/O mode cannot be used if the Boot ROM area is rewritten in parallel I/O mode. The standard serial I/ O mode has standard serial I/O mode 1 of the clock synchronous serial and standard serial I/O mode 2 of the clock asynchronous serial. Tables 17 and 18 show description of pin function (standard serial I/O mode). Figures 87 to 90 show the pin connections for the standard serial I/O mode. In standard serial I/O mode, only the User ROM area shown in Figure 77 can be rewritten. The Boot ROM area cannot be written. In standard serial I/O mode, a 7-byte ID code is used. When there is data in the flash memory, this function determines whether the ID code sent from the peripheral unit (programmer) and those writ- ten in the flash memory match. The commands sent from the peripheral unit (programmer) are not accepted unless the ID code matches.

Rev.1.01 Jan 25, 2005 page 92 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) Pin name Signal name I/O VCC ,VSS Power supply I CNV SS CNV SS I RESET Reset input I XIN Clock input I XOUT Clock output O AV SS Analog power supply input VREF Reference voltage input I P00–P07,P10–P17, I/O port I/O P20–P27,P30–P37, P40–P43,P50–P57, P60–P67 P44 RxD input I P45 TxD output O P46 SCLK input I P47 BUSY output O Table 17 Description of pin function (Flash Memory Serial I/O Mode 1) Function Apply 2.7 to 5.5 V to the Vcc pin and 0 V to the Vss pin. After input of port is set, input “H ” level. Reset input pin. To reset the microcomputer, RESET pin should be held at an “L” level for 16 cycles or more of X IN. Connect an oscillation circuit between the XIN and XOUT pins. As for the connection method, refer to the “clock generating circuit”. Connect AVss to Vss. Apply reference voltage of A/D to this pin. Input “L” or “H ” level, or keep open. Serial data input pin. Serial data output pin. Serial clock input pin. BUSY signal output pin. Pin name Signal name I/O VCC ,VSS Power supply I CNV SS CNV SS I RESET Reset input I XIN Clock input I XOUT Clock output O AVss Analog power supply input VREF Reference voltage input I P00–P07,P10–P17, I/O port I/O P20–P27,P30–P37, P40–P43,P50–P57, P60–P67 P44 RxD input I P45 TxD output O P46 SCLK input I P47 BUSY output O Table 18 Description of pin function (Flash Memory Serial I/O Mode 2) Function Apply 2.7 to 5.5 V to the Vcc pin and 0 V to the Vss pin. After input of port is set, input “H ” level. Reset input pin. To reset the microcomputer, RESET pin should be held at an “L” level for 16 cycles or more of X IN. Connect an oscillation circuit between the XIN and XOUT pins. As for the connection method, refer to the “clock generating circuit”. Connect AVss to Vss. Apply reference voltage of A/D to this pin. Input “L” or “H ” level, or keep open. Serial data input pin. Serial data output pin. Input “L” level. BUSY signal output pin.

Rev.1.01 Jan 25, 2005 page 93 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) Fig. 87 Connection for standard serial I/O mode 1 (M38049FFHFP/HP/KP) 48 47 46 45 43 42 41 40 39 38 37 36 35 34 3344 0/AN 1/AN 2/AN 3/AN 4/AN 5/AN 6/AN 7/AN 0/INT 1/INT P27(LED 7) P20(LED 0) P21(LED 1) P22(LED 2) P23(LED 3) P24(LED 4) P25(LED 5) P26(LED 6) VSS XOUT XIN P42/INT1 RESET CNV SS P40/INT40/XCOUT P41/INT00/XCIN P35/TXD 3 P34/RXD 3 P31/DA2 P30/DA1 VCC VREF AV SS P67/AN7 P66/AN6 P65/AN5 P64/AN4 P63/AN3 P37/SRDY3 P36/SCLK3 P33/SCL P32/SDA 1/AN 0/AN 7/INT 6/PWM 5/CNTR 4/CNTR 2/S CLK2 1/S OUT2 0/S IN2 6/S CLK1 5/T XD 4/R XD 3/INT 2/AN 7/S RDY1 /CNTR 3/S RDY2 M38049FFHFP/HP/KP 1 2 3 4 6 7 8 9 10 11 12 13 14 15 165 VSS RESET CNVss VCC RxD TxD SCLK BUSY ✽ Connect oscillation circuit. indicates flash memory pin. Package type: 64P6N-A/64P6Q-A/64P6U-A

Rev.1.01 Jan 25, 2005 page 94 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) Fig. 88 Connection for standard serial I/O mode 2 (M38049FFHFP/HP/KP) 48 47 46 45 43 42 41 40 39 38 37 36 35 34 3344 0/AN 1/AN 2/AN 3/AN 4/AN 5/AN 6/AN 7/AN 0/INT 1/INT P27(LED 7) P20(LED 0) P21(LED 1) P22(LED 2) P23(LED 3) P24(LED 4) P25(LED 5) P26(LED 6) VSS XOUT XIN P42/INT1 RESET CNV SS P40/INT40/XCOUT P41/INT00/XCIN P35/TXD 3 P34/RXD 3 P31/DA2 P30/DA1 VCC VREF AV SS P67/AN7 P66/AN6 P65/AN5 P64/AN4 P63/AN3 P37/SRDY3 P36/SCLK3 P33/SCL P32/SDA 1/AN 0/AN 7/INT 6/PWM 5/CNTR 4/CNTR 2/S CLK2 1/S OUT2 0/S IN2 6/S CLK1 5/T XD 4/R XD 3/INT 2/AN 7/S RDY1 /CNTR 3/S RDY2 M38049FFHFP/HP/KP 1 2 3 4 6 7 8 9 10 11 12 13 14 15 165 VSS CNVss VCC RxD TxD “L” input BUSY RESET ✽ Connect oscillation circuit. Package type: 64P6N-A/64P6Q-A/64P6U-A indicates flash memory pin.

Rev.1.01 Jan 25, 2005 page 95 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) Fig. 89 Connection for standard serial I/O mode 1 (M38049FFHSP) VCC VREF A VS S P67/AN7 P66/AN6 P64/AN4 P63/AN3 P62/AN2 P61/AN1 P60/AN0 P 57/ I N T3 P 56/ P W M P 55/ C N T R 1 P 54/ C N T R 0 P 52/ SC L K P51/SOUT2 P50/SIN2 P46/SCLK1 P 45/ TXD 1 P44/RXD 1 P 43/ I N T2 P 42/ I N T1 CNV SS P 40/ I N T4 0/ XC O U T XIN XOUT VSS RESET P30/DA1 P 31/ D A2 P 34/ R XD 3 P 35/ TXD 3 P 00/ A N 8 P 20( L E D 0) P53/SRDY2 P65/AN5 P41/INT00/XCIN P 01/ A N 9 P 02/ A N 1 P 03/ A N 1 P 04/ A N 1 P 05/ A N 1 P 06/ A N 1 P 07/ A N 1 P 10/ I N P 11/ I N P 12 P 13 P14 P 15 P16 P 17 P21(LED1) P 22( L E D 2) P23(LED3) P 24( L E D 4) P25(LED5) P 26( L E D 6) P 27( L E D 7) P 32/ S D A P 33/ S C L P 36/SC L K P 37/SR D Y P47/SRDY1 /CNTR 2 M 3 8 0 4 9 F F H S P 5 5 5 4 5 3 5 2 5 1 5 0 4 9 4 8 4 7 4 6 4 5 4 4 4 2 4 1 4 0 3 9 3 5 3 4 6 3 6 2 6 1 6 0 5 9 5 8 5 7 5 6 6 4 VS S R E S E T CNV SS R XD TXD SCLK BUSY VC C ✽ Connect oscillation circuit. P a c k a g e t y p e : 6 4 P 4B indicates flash memory pin.

Rev.1.01 Jan 25, 2005 page 96 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) Fig. 90 Connection for standard serial I/O mode 2 (M38049FFHSP) VC C VREF AV SS P 67/ A N 7 P 66/ A N 6 P 64/ A N 4 P 63/ A N 3 P 62/ A N 2 P 61/ A N 1 P 60/ A N 0 P 57/ I N T3 P 56/ P W M P 55/ C N T R 1 P54/CNTR 0 P 52/ SC L K P51/SOUT2 P 50/ SI N P 46/ SC L K P 45/ TXD 1 P 44/ R XD 1 P 43/ I N T2 P 42/ I N T1 CNV SS P 40/ I N T4 0/ XC O U T XIN XOUT VSS R E S E T P 30/ D A1 P 31/ D A2 P 34/ R XD 3 P 35/ TXD 3 P 00/ A N 8 P 20( L E D 0) P 53/ SR D Y P 65/ A N 5 P41/INT00/XCIN P 01/ A N 9 P 02/ A N 1 P 03/ A N 1 P 04/ A N 1 P 05/ A N 1 P 06/ A N 1 P 07/ A N 1 P10/INT41 P11/INT01 P 12 P 13 P14 P 15 P 16 P17 P 21( L E D 1) P22(LED2) P23(LED3) P 24( L E D 4) P25(LED5) P26(LED6) P 27( L E D 7) P 32/ S D A P 33/ S C L P 36/SC L K P 37/SR D Y P47/SRDY1 /CNTR 2 M 3 8 0 4 9 F F H S P 5 5 5 4 5 3 5 2 5 1 4 9 4 2 4 1 3 9 3 8 3 7 3 6 3 5 3 4 3 3 6 3 VSS C N VS S R XD TXD “L” input BUSY VC C RESET C o n n e c t o s c i l l a t i o n c i r c u i t Package type: 64P4Bindicates flash memory pin.

Rev.1.01 Jan 25, 2005 page 97 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) Fig. 91 Operating waveform for standard serial I/O mode 1 Fig. 92 Operating waveform for standard serial I/O mode 2 Power source RESET CNV SS P45(TXD) P46(SCLK ) P47(BUSY) P44(RXD) td(CNVSS -RESET) td(P45-RESET) Symbol td(CNVss-RESET) td(P45-RESET) Limits Min. Typ. Max. Unit 0 – – ms ms Notes: In the standard serial I/O mode 1, input “H ” to the P46 pin. Be sure to set the CNVss pin to “H ” before rising RESET. Be sure to set the P45 pin to “H ” before rising RESET. Power source RESET CNV SS P45(TXD) P47(BUSY) P44(RXD) P46(SCLK ) td(CNVSS -RESET) td(P45-RESET) Symbol td(CNVss-RESET) td(P45-RESET) Limits Min.Typ. Max. Unit 0 – – ms ms Notes: In the standard serial I/O mode 2, input “H ” to the P46 pin. Be sure to set the CNVss pin to “H ” before rising RESET. Be sure to set the P45 pin to “H ” before rising RESET.

Rev.1.01 Jan 25, 2005 page 98 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) NOTES ON PROGRAMMING Processor Status Register The contents of the processor status register (PS) after a reset are undefined, except for the interrupt disable flag (I) which is “1.” Af- ter a reset, initialize flags which affect program execution. In particular, it is essential to initialize the index X mode (T) and the decimal mode (D) flags because of their effect on calculations. Interrupts The contents of the interrupt request bits do not change immedi- ately after they have been written. After writing to an interrupt request register, execute at least one instruction before perform- ing a BBC or BBS instruction. Decimal Calculations

• To calculate in decimal notation, set the decimal mode flag (D) to “1”, then execute an ADC or SBC instruction. After executing an ADC or SBC instruction, execute at least one instruction be- fore executing a SEC, CLC, or CLD instruction.
• In decimal mode, the values of the negative (N), overflow (V), and zero (Z) flags are invalid. Timers If a value n (between 0 and 255) is written to a timer latch, the fre- quency division ratio is 1/(n+1). Multiplication and Division Instructions
• The index X mode (T) and the decimal mode (D) flags do not af- fect the MUL and DIV instruction.
• The execution of these instructions does not change the con- tents of the processor status register. Ports The contents of the port direction registers cannot be read. The following cannot be used:
• The data transfer instruction (LDA, etc.)
• The operation instruction when the index X mode flag (T) is “1”
• The instruction with the addressing mode which uses the value of a direction register as an index
• The bit-test instruction (BBC or BBS, etc.) to a direction register
• The read-modify-write instructions (ROR, CLB, or SEB, etc.) to a direction register. Use instructions such as LDM and STA, etc., to set the port direc- tion registers. Serial Interface In clock synchronous serial I/O, if the receive side is using an ex- ternal clock and it is to output the S RDY signal, set the transmit enable bit, the receive enable bit, and the SRDY output enable bit to “1.” Serial I/O continues to output the final bit from the TXD pin after transmission is completed. SOUT2 pin for serial I/O2 goes to high impedance after transfer is completed. When in serial I/Os 1 and 3 (clock-synchronous mode) or in serial I/O2, an external clock is used as synchronous clock, write trans- mission data to the transmit buffer register or serial I/O2 register, during transfer clock is “H.” A/D Converter The comparator uses capacitive coupling amplifier whose charge will be lost if the clock frequency is too low. Therefore, make sure that f(X IN) is at least on 500 kHz during an A/D conversion. Do not execute the STP instruction during an A/D conversion. D/A Converter The accuracy of the D/A converter becomes rapidly poor under the V CC = 4.0 V or less condition; a supply voltage of VCC ≥ 4.0 V is recommended. When a D/A converter is not used, set all values of D/Ai conversion registers (i=1, 2) to “0016.” Instruction Execution Time The instruction execution time is obtained by multiplying the pe- riod of the internal clock φ by the number of cycles needed to execute an instruction. The number of cycles required to execute an instruction is shown in the list of machine instructions. The period of the internal clock φ is double of the X IN period in high-speed mode.

Rev.1.01 Jan 25, 2005 page 99 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) NOTES ON USAGE Handling of Power Source Pins In order to avoid a latch-up occurrence, connect a capacitor suit- able for high frequencies as bypass capacitor between power source pin (VCC pin) and GND pin (VSS pin), and between power source pin (VCC pin) and analog power source input pin (AVSS pin). Besides, connect the capacitor to as close as possible. For bypass capacitor which should not be located too far from the pins to be connected, a ceramic capacitor of 0.01 µF–0.1 µF is recom- mended. Power Source Voltage When the power source voltage value of a microcomputer is less than the value which is indicated as the recommended operating conditions, the microcomputer does not operate normally and may perform unstable operation. In a system where the power source voltage drops slowly when the power source voltage drops or the power supply is turned off, reset a microcomputer when the power source voltage is less than the recommended operating conditions and design a system not to cause errors to the system by this unstable operation. Flash Memory Version The CNVss pin determines the flash memory mode. To improve the noise reduction, connect a track between CNVss pin and Vss pin or Vcc pin with 1 to 10 kΩ resistance. The mask ROM version track of CNVss pin has no operational interference even if it is connected to Vss pin or Vcc pin via a resistor. Electric Characteristic Differences Between Mask ROM and Flash Memory Version MCUs There are differences in electric characteristics, operation margin, noise immunity, and noise radiation between Mask ROM and Flash Memory version MCUs due to the difference in the manufac- turing processes, built-in ROM, and layout pattern etc.When manufacturing an application system with the Flash Memory ver- sion and then switching to use of the Mask ROM version, please conduct evaluations equivalent to the system evaluations con- ducted for the flash memory version. DATA REQUIRED FOR MASK ORDERS The following are necessary when ordering a mask ROM produc- tion: 1.Mask ROM Confirmation Form 2.Mark Specification Form ✽ 3.Data to be written to ROM, in EPROM form (three identical cop- ies) ✽ For the mask ROM confirmation and the mark specifications, refer to the “Renesas Technology Corp.” Homepage (http://www.renesas.com/en/rom).

Rev.1.01 Jan 25, 2005 page 100 of 114 REJ03B0131-0101Z 3804 Group (Spec. H)

ELECTRICAL CHARACTERISTICS

Table 19 Absolute maximum ratings Power source voltages Input voltage P00–P07, P10–P17, P20–P27, P30, P31, P34–P37, P40–P47, P50–P57, P60–P67, VREF Input voltage P32, P33 Input voltage RESET, XIN Input voltage CNVSS Output voltage P00–P07, P10–P17, P20–P27, P30, P31, P34–P37, P40–P47, P50–P57, P60–P67, XOUT Output voltage P32, P33 Power dissipation Operating temperature Storage temperature VCC VI VI VI VI VO VO Pd Topr Tstg Symbol Parameter Conditions Ratings –0.3 to 6.5 –0.3 to VCC +0.3 –0.3 to 5.8 –0.3 to VCC +0.3 –0.3 to VCC +0.3 –0.3 to VCC +0.3 –0.3 to 5.8 1000 (Note) –20 to 85 –65 to 125 V V V V V V V mW Unit Note: This value is 300 mW except SP package. All voltages are based on Vss. Output transistors are cut off. Ta = 25°C

Rev.1.01 Jan 25, 2005 page 101 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) Recommended operating conditions Table 20 Recommended operating conditions (1) (VCC = 2.7 to 5.5 V, VSS = 0V, Ta = –20 to 85 °C, unless otherwise noted) 5.5 5.5 5.5 5.5 5.5 5.5 V CC 5.5 5.5 5.5 V CC VCC 0.2VCC 0.3Vcc 0.6 0.2VCC 0.16VCC 0.4 Power source voltage “H ” input voltage P00–P07, P10–P17, P20–P27, P30, P31, P34–P37, P40–P47, P50–P57, P60–P67 “H ” input voltage P32, P33 “H ” input voltage (when I2C-BUS input level is selected) SDA, SCL “H ” input voltage (when SMBUS input level is selected) SDA, SCL “H ” input voltage RESET, XIN, CNVSS “H ” input voltage XCIN “L” input voltage P00–P07, P10–P17, P20–P27, P30–P37,P40–P47, P50–P57, P60–P67 “L” input voltage (when I2C-BUS input level is selected) SDA, SCL “L” input voltage (when SMBUS input level is selected) SDA, SCL “L” input voltage RESET, CNV SS “L” input voltage XIN “L” input voltage XCIN Symbol Parameter Limits Min. V V V V V V V V V V V V V V V V V V V Unit 2.7 2.7 4.0 4.5 2.7 4.5 5.0 5.0 5.0 5.0 5.0 5.0 Typ. Max. f(XIN) ≤ 8.4 MHz f(XIN) ≤ 12.5 MHz f(XIN) ≤ 16.8 MHz f(XIN) ≤ 12.5 MHz f(XIN) ≤ 16.8 MHz Power source voltage (Note 1) VCC VSS VIH VIH VIL VIL VIL VIH When start oscillating (Note 2) High-speed mode f(φ) = f(XIN)/2 Middle-speed mode f(φ) = f(XIN)/8 0.8VCC 0.8VCC 0.7VCC 1.4 0.8VCC Notes 1: When using A/D converter, see A/D converter recommended operating conditions. 2: The start voltage and the start time for oscillation depend on the using oscillator, oscillation circuit constant value and operating temperature range, etc.. Particularly a high-frequency oscillator might require some notes in the low voltage operation. Conditions VIH VIL VIH VIH VIL VIL

Rev.1.01 Jan 25, 2005 page 102 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) Table 21 Recommended operating conditions (2) (VCC = 2.7 to 5.5 V, VSS = 0V, Ta = –20 to 85 °C, unless otherwise noted) Main clock input oscillation frequency (Note 1) f(XCIN) Symbol Parameter Limits Min. MHz MHz MHz MHz MHz kHz UnitTyp. Max. Notes 1: When the oscillation frequency has a duty cycle of 50%. 2: When using the microcomputer in low-speed mode, set the sub-clock input oscillation frequency on condition that f(XCIN) < f(XIN)/3. 32.768 f(XIN) Sub-clock input oscillation frequency (Notes 1, 2) Conditions High-speed mode f(φ) = f(XIN)/2 Middle-speed mode f(φ) = f(XIN)/8 2.7 ≤ VCC < 4.0 V 4.0 ≤ VCC < 4.5 V 4.5 ≤ VCC ≤ 5.5 V 2.7 ≤ VCC < 4.5 V 4.5 ≤ VCC ≤ 5.5 V 16.8 (15✕ VCC +39)✕ 1.1 16.8

Rev.1.01 Jan 25, 2005 page 103 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) Table 22 Recommended operating conditions (3) (VCC = 2.7 to 5.5 V, VSS = 0V, Ta = –20 to 85 °C, unless otherwise noted) –80 –80 –40 –40 –10 “H ” total peak output currentP00–P07, P10–P17, P20–P27, P30, P31, P34–P37 (Note 1) “H ” total peak output current P40–P47, P50–P57, P60–P67 (Note 1) “L” total peak output currentP00–P07, P10–P17, P30–P37 (Note 1) “L” total peak output current P20–P27 (Note 1) “L” total peak output current P40–P47,P50–P57, P60–P67 (Note 1) “H ” total average output currentP00–P07, P10–P17, P20–P27, P30, P31, P34–P37 (Note 1) “H ” total average output current P40–P47,P50–P57, P60–P67 (Note 1) “L” total average output currentP00–P07, P10–P17, P30–P37 (Note 1) “L” total average output current P20–P27 (Note 1) “L” total average output current P40–P47,P50–P57, P60–P67 (Note 1) “H ” peak output current P0 0–P07, P10–P17, P20–P27, P30, P31, P34–P37, P40–P47, P50–P57, P60–P67 (Note 2) “L” peak output current P0 0–P07, P10–P17, P30–P37, P40–P47, P50–P57, P60–P67 (Note 2) “L” peak output current P2 0–P27 (Note 2) “H ” average output current P0 0–P07, P10–P17, P20–P27, P30, P31, P34–P37, P40–P47, P50–P57, P60–P67 (Note 3) “L” average output current P0 0–P07, P10–P17, P30–P37, P40–P47, P50–P57, P60–P67 (Note 3) “L” average output current P2 0–P27 (Note 3) ΣIOH(peak) ΣIOH(peak) ΣIOL(peak) ΣIOL(peak) ΣIOL(peak) ΣIOH(avg) ΣIOH(avg) ΣIOL(avg) ΣIOL(avg) ΣIOL(avg) IOH(peak) IOL(peak) IOL(peak) IOH(avg) IOL(avg) IOL(avg) Symbol Parameter Limits Min. mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA UnitTyp. Max. Notes 1: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an aver- age value measured over 100 ms. The total peak current is the peak value of all the currents. 2: The peak output current is the peak current flowing in each port. 3: The average output current IOL (avg), IOH (avg) are average value measured over 100 ms.

Rev.1.01 Jan 25, 2005 page 104 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) Table 23 Electrical characteristics (1) (VCC = 2.7 to 5.5 V, VSS = 0V, Ta = –20 to 85 °C, unless otherwise noted) “H ” output voltage P00–P07, P10–P17, P20–P27, P30, P31, P34–P37, P40–P47, P50–P57, P60–P67 (Note 1) “L” output voltage P00–P07, P10–P17, P20–P27, P30–P37, P40–P47, P50–P57, P60–P67 “L” output voltage P20–P27 Hysteresis CNTR 0, CNTR1, CNTR2, INT0–INT4 Hysteresis RxD1, SCLK1 , SIN2, SCLK2 , RxD3, SCLK3 Hysteresis RESET “H ” input current P00–P07, P10–P17, P20–P27, P30–P37, P40–P47, P50–P57, P60–P67 “H ” input current RESET, CNV SS “H ” input current XIN “L” input current P00–P07, P10–P17, P20–P27, P30–P37, P40–P47, P50–P57, P60–P67 “L” input current RESET,CNV SS “L” input current XIN “L” input current (at Pull-up) P00–P07, P10–P17, P20–P27, P30, P31, P34–P37, P40–P47, P50–P57, P60–P67 RAM hold voltage Limits V V V V V V V V V µA µA µA µA µA µA µA µA V Parameter Min. Typ. Max.Symbol Unit Note 1: P35 is measured when the P35/TxD3 P-channel output disable bit of the UART3 control register (bit 4 of address 003316) is “0”. P45 is measured when the P45/TxD1 P-channel output disable bit of the UART1 control register (bit 4 of address 001B16) is “0”. IOH = –10 mA VCC = 4.0 to 5.5 V IOH = –1.0 mA VCC = 1.8 to 5.5 V IOL = 10 mA VCC = 4.0 to 5.5 V IOL = 1.6 mA VCC = 1.8 to 5.5 V IOL = 20 mA VCC = 4.0 to 5.5 V IOL = 1.6 mA VCC = 1.8 to 5.5 V VI = VCC (Pin floating. Pull-up transistors “off”) VI = VCC VI = VCC VI = VSS (Pin floating. Pull-up transistors “off”) VI = VSS VI = VSS VI = VSS VCC = 5.0 V VI = VSS VCC = 3.0 V When clock stopped VCC –2.0 VCC –1.0 –80 –30 1.8 Test conditions 0.4 0.5 0.5 4.0 –4.0 –210 –70 2.0 1.0 2.0 0.4 5.0 5.0 –5.0 –5.0 –420 –140 VCC VOH VOL VOL VT+–VT– VT+–VT– VT+–VT– IIH IIH IIH IIL IIL IIL IIL VRAM

Rev.1.01 Jan 25, 2005 page 105 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) Table 24 Electrical characteristics (2) (VCC = 2.7 to 5.5 V, Ta = –20 to 85 °C, f(XCIN)=32.768kHZ (Stoped in middle-speed mode), Output transistors “off”, AD converter not operated) Power source current Limits Parameter Max.Symbol Unit f(XIN) = 16.8 MHz f(XIN) = 12.5 MHz f(XIN) = 8.4 MHz f(XIN) = 4.2 MHz f(XIN) = 16.8 MHz (in WIT state) f(XIN) = 8.4 MHz f(XIN) = 4.2 MHz f(XIN) = 2.1 MHz f(XIN) = 16.8 MHz f(XIN) = 12.5 MHz f(XIN) = 8.4 MHz f(XIN) = 16.8 MHz (in WIT state) f(XIN) = 12.5 MHz f(XIN) = 8.4 MHz f(XIN) = 6.3 MHz f(XIN) = stopped In WIT state f(XIN) = stopped In WIT state Ta = 25 °C Ta = 85 °C f(XIN) = 16.8 MHz, VCC = 5V In Middle-, high-speed mode Test conditions ICC mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA µA µA µA µA µA µA µA High-speed mode Middle-speed mode Low-speed mode In STP state (All oscillation stopped) Increment when A/D conversion is executed Typ.Min. 5.5 4.5 3.5 2.2 2.2 2.7 1.8 1.1 3.0 2.4 2.0 2.1 1.7 1.5 1.3 410 4.5 400 3.7 0.55 0.75 1000 VCC = 5V VCC = 3V VCC = 5V VCC = 3V VCC = 5V VCC = 3V 8,3 6.8 5.3 3.3 3.3 4.1 2.7 1.7 4.5 3.6 3.0 3.2 2.6 2.3 2.0 630 6.8 600 5.6 3.0

Rev.1.01 Jan 25, 2005 page 106 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) A/D converter characteristics bit LSB 2tc(XIN) kΩ µA µA µA Resolution Absolute accuracy (excluding quantization error) Conversion time Ladder resistor Reference power at A/D converter operated source input current at A/D converter stopped A/D port inout current Max. 8-bit A/D mode (Note 1) 10-bit A/D mode (Note 2) 8-bit A/D mode (Note 1) 2.7 ≤ VREF ≤ 5.5 V 10-bit A/D mode (Note 2) 2.7 ≤ VREF ≤ 5.5 V 8-bit A/D mode (Note 1) 10-bit A/D mode (Note 2) VREF = 5.0 V VREF = 5.0 V Table 26 A/D converter characteristics (VCC = 2.7 to 5.5 V, VSS = AVSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) UnitLimits Parameter tCONV RLADDER IVREF II(AD) Test conditionsSymbol Symbol Parameter Limits Min. UnitTyp. Max.Conditions Table 25 A/D converter recommended operating conditions (VCC = 2.7 to 5.5 V, VSS = AVSS = 0 V,Ta = –20 to 85 °C, unless otherwise noted) Power source voltage (When A/D converter is used) Analog reference voltage Analog power source voltage Analog input voltage Main clock oscillation frequency (When A/D converter is used) V CC VREF AV SS VIA f(XIN) V V V V MH Z 2.7 2.7 2.0 0.5 0.5 0.5 5.0 5.0 2.7 ≤ V CC < 4.0 V 4.0 ≤ VCC < 4.5 V 4.5 ≤ VCC ≤ 5.5 V 5.5 5.5 VCC VCC 16.8 8-bit A/D mode (Note 1) 10-bit A/D mode (Note 2) Note 1: 8-bit A/D mode: When the conversion mode selection bit (bit 7 of address 003816) is “1”. 2: 10-bit A/D mode: When the conversion mode selection bit (bit 7 of address 003816) is “0”. Note 1: 8-bit A/D mode: When the conversion mode selection bit (bit 7 of address 003816) is “1”. 2: 10-bit A/D mode: When the conversion mode selection bit (bit 7 of address 003816) is “0”. Note 1: Using one D/A converter, with the value in the DA conversion register of the other D/A converter being “0016”. Table 27 D/A converter characteristics (VCC = 2.7 to 5.5 V, VREF = 2.7 V to VCC , VSS = AVSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) bit µs kΩ mA Resolution Absolute accuracy 4.0 ≤ VREF ≤ 5.5 V 2.7 ≤ VREF < 4.0 V Setting time Output resistor Reference power source input current (Note 1) Min. UnitLimitsParameter tsu RO IVREF Test conditionsSymbol D/A converter characteristics 100 200 150 Min. Typ. Typ. Max. 2 3.5 1.0 2.5 3.2 Table 28 Power source circuit timing characteristics (VCC = 2.7 to 5.5 V, VREF = 2.7 V to VCC , VSS = AVSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) msInternal power source stable time at power-on Min. UnitLimitsParameter td(P–R) Test conditionsSymbol Power source circuit timing characteristics Typ. Max. 22.7 ≤ Vcc < 5.5 V

Rev.1.01 Jan 25, 2005 page 107 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) Table 29 Timing requirements (1) (VCC = 2.7 to 5.5 V, VSS = 0V, Ta = –20 to 85 °C, unless otherwise noted) Timing requirements and switching characteristics tW (RESET) tC (XIN) tWH (XIN) tWL (XIN) tC (XCIN) tWH (XCIN) tWL (XCIN) tC (CNTR) tWH (CNTR) tWL (CNTR) tWH (INT) tWL (INT) Limits XIN cycle ns ns ns µs µs µs ns ns ns ns ns Parameter Max.Symbol Unit Typ. Reset input “L” pulse width Main clock XIN input cycle time Main clock XIN input “H ” pulse width Main clock XIN input “L” pulse width Sub-clock XCIN input cycle time Sub-clock XCIN input “H ” pulse width Sub-clock XCIN input “L” pulse width CNTR 0–CNTR 2 input cycle time CNTR 0–CNTR 2 input “H ” pulse width CNTR 0–CNTR 2 input “L” pulse width INT00, INT01, INT1, INT2, INT3, INT40, INT41 input “H ” pulse width INT00, INT01, INT1, INT2, INT3, INT40, INT41 input “L” pulse width Min. td(P-R) ms + 16 59.5 10000/(86VCC -219) 26✕ 103/(82VCC -3) 4000/(86VCC -219) 10000/(82VCC -3) 4000/(86VCC -219) 10000/(82VCC -3) 120 160 250 115 115 115 115 4.5≤V CC ≤5.5 V 4.0≤VCC <4.5 V 2.7≤VCC <4.0 V 4.5≤VCC ≤5.5 V 4.0≤VCC <4.5 V 2.7≤VCC <4.0 V 4.5≤VCC ≤5.5 V 4.0≤VCC <4.5 V 2.7≤VCC <4.0 V 4.5≤VCC ≤5.5 V 4.0≤VCC <4.5 V 2.7≤VCC <4.0 V 4.5≤VCC ≤5.5 V 4.0≤VCC <4.5 V 2.7≤VCC <4.0 V 4.5≤VCC ≤5.5 V 4.0≤VCC <4.5 V 2.7≤VCC <4.0 V 4.5≤VCC ≤5.5 V 4.0≤VCC <4.5 V 2.7≤VCC <4.0 V 4.5≤VCC ≤5.5 V 4.0≤VCC <4.5 V 2.7≤VCC <4.0 V

Rev.1.01 Jan 25, 2005 page 108 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) Note :When bit 6 of address 001A16 and bit 6 of address 003216 are “1” (clock synchronous). Divide this value by four when bit 6 of address 001A16 and bit 6 of address 003216 are “0” (UART). Table 30 Timing requirements (2) (VCC = 2.7 to 5.5 V, VSS = 0V, Ta = –20 to 85 °C, unless otherwise noted) Limits ns ns ns ns ns ns ns ns ns ns Parameter Max. Symbol UnitTyp.Min. 250 320 500 120 150 240 120 150 240 100 500 650 1000 200 260 400 200 260 400 100 130 200 100 130 150 4.5≤V CC ≤5.5 V 4.0≤VCC <4.5 V 2.7≤VCC <4.0 V 4.5≤VCC ≤5.5 V 4.0≤VCC <4.5 V 2.7≤VCC <4.0 V 4.5≤VCC ≤5.5 V 4.0≤VCC <4.5 V 2.7≤VCC <4.0 V 4.5≤VCC ≤5.5 V 4.0≤VCC <4.5 V 2.7≤VCC <4.0 V 4.5≤VCC ≤5.5 V 4.0≤VCC <4.5 V 2.7≤VCC <4.0 V 4.5≤VCC ≤5.5 V 4.0≤VCC <4.5 V 2.7≤VCC <4.0 V 4.5≤VCC ≤5.5 V 4.0≤VCC <4.5 V 2.7≤VCC <4.0 V 4.5≤VCC ≤5.5 V 4.0≤VCC <4.5 V 2.7≤VCC <4.0 V 4.5≤VCC ≤5.5 V 4.0≤VCC <4.5 V 2.7≤VCC <4.0 V 4.5≤VCC ≤5.5 V 4.0≤VCC <4.5 V 2.7≤VCC <4.0 V Serial I/O1, serial I/O3 clock input cycle time (Note) Serial I/O1, serial I/O3 clock input “H ” pulse width (Note) Serial I/O1, serial I/O3 clock input “L” pulse width (Note) Serial I/O1, serial I/O3 clock input setup time Serial I/O1, serial I/O3 clock input hold time Serial I/O2 clock input cycle time Serial I/O2 clock input “H ” pulse width Serial I/O2 clock input “L” pulse width Serial I/O2 clock input setup time Serial I/O2 clock input hold time tC (SCLK1 ), tC (SCLK3 ) tWH (SCLK1 ), tWH (SCLK3 ) tWL (SCLK1 ), tWL (SCLK3 ) tsu(RxD 1-SCLK1 ), tsu(RxD 3-SCLK3 ) th(SCLK1 -RxD 1), th(SCLK3 -RxD 3) tC (SCLK2 ) tWH (SCLK2 ) tWL (SCLK2 ) tsu(SIN2-SCLK2 ) th(SCLK2 -SIN2)

Rev.1.01 Jan 25, 2005 page 109 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) Note: When the P45/TxD1 P-channel output disable bit of the UART1 control register (bit 4 of address 001B16) is “0”. Table 31 Switching characteristics (VCC = 2.7 to 5.5 V, VSS = 0V, Ta = –20 to 85 °C, unless otherwise noted) Limits ns ns ns ns ns ns ns ns ns ns ns ns ns Parameter Max. 140 200 350 200 250 300 Symbol Unit Typ. Min. tC(S CLK1 )2-30, tC(SCLK3 )/2-30 tC(SCLK1 )2-35, tC(SCLK3 )/2-35 tC(SCLK1 )2-40, tC(SCLK3 )/2-40 tC(SCLK1 )2-30, tC(SCLK3 )/2-30 tC(SCLK1 )2-35, tC(SCLK3 )/2-35 tC(SCLK1 )2-40, tC(SCLK3 )/2-40 -30 -30 -30 tC(S CLK2 )/2-160 tC(SCLK2 )/2-200 tC(SCLK2 )/2-240 tC(SCLK2 )/2-160 tC(SCLK2 )/2-200 tC(SCLK2 )/2-240 4.5≤VCC ≤5.5 V 4.0≤VCC <4.5 V 2.7≤VCC <4.0 V 4.5≤VCC ≤5.5 V 4.0≤VCC <4.5 V 2.7≤VCC <4.0 V 4.5≤VCC ≤5.5 V 4.0≤VCC <4.5 V 2.7≤VCC <4.0 V 4.5≤VCC ≤5.5 V 4.0≤VCC <4.5 V 2.7≤VCC <4.0 V 4.5≤VCC ≤5.5 V 4.0≤VCC <4.5 V 2.7≤VCC <4.0 V 4.5≤VCC ≤5.5 V 4.0≤VCC <4.5 V 2.7≤VCC <4.0 V 4.5≤VCC ≤5.5 V 4.0≤VCC <4.5 V 2.7≤VCC <4.0 V 4.5≤VCC ≤5.5 V 4.0≤VCC <4.5 V 2.7≤VCC <4.0 V 4.5≤VCC ≤5.5 V 4.0≤VCC <4.5 V 2.7≤VCC <4.0 V 4.5≤VCC ≤5.5 V 4.0≤VCC <4.5 V 2.7≤VCC <4.0 V 4.5≤VCC ≤5.5 V 4.0≤VCC <4.5 V 2.7≤VCC <4.0 V 4.5≤VCC ≤5.5 V 4.0≤VCC <4.5 V 2.7≤VCC <4.0 V 4.5≤VCC ≤5.5 V 4.0≤VCC <4.5 V 2.7≤VCC <4.0 V Serial I/O1, serial I/O3 clock output “H ” pulse width Serial I/O1, serial I/O3 clock output “L” pulse width Serial I/O1, serial I/O3 output delay time (Note) Serial I/O1, serial I/O3 output valid time (Note) Serial I/O1, serial I/O3 rise time of clock output Serial I/O1, serial I/O3 fall time of clock output Serial I/O2 clock output “H ” pulse width Serial I/O2 clock output “L” pulse width Serial I/O2 output delay time Serial I/O2 output valid time Serial I/O2 fall time of clock output CMOS rise time of output (Note) CMOS fall time of output (Note) tWH (SCLK1 ) tWH (SCLK3 ) tWL (SCLK1 ) tWL (SCLK3 ) td(SCLK1 -TxD 1) td(SCLK3 -TxD 3) tV(SCLK1 -TxD 1) tV(SCLK3 -TxD 3) tr(SCLK1 ) tr(SCLK3 ) tf(SCLK1 ) tf(SCLK3 ) tWH (SCLK2 ) tWL (SCLK2 ) td(SCLK2 -SOUT2 ) tV(SCLK2 -SOUT2 ) tf(SCLK2 ) tr(CMOS) tf(CMOS) Test conditions Fig. 93

Rev.1.01 Jan 25, 2005 page 110 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) Fig.93 Circuit for measuring output switching characteristics (1) Measurement output pin CMOS out put 100pF 100pF 1kΩ Measurement output pin N-channel open-drain output Fig.94 Circuit for measuring output switching characteristics (2)

Rev.1.01 Jan 25, 2005 page 111 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) Fig. 95 Timing diagram (in single-chip mode) 0.2VCC tW L I N T 0 . 8 VC C tW H I N T 0 . 2 VC C 0.2VCC 0.8VCC 0 . 8 VC C 0.2VCC tWL(X IN) 0 . 8 VC C tWH(X IN) tC(XIN) XIN 0.2VCC 0 . 8 VC C tW(RESET) R E S E T 0.2VCC tW L C N T R 0.8VCC tW H C N T R tC C N T R tC(SCLK1 ), tC(SCLK2 ),tC(SCLK3 ), tW H SC L K tW H SC L K tW H SC L K th(SCLK1-R xD1), th(SCLK2-SIN2), th(SCLK3-R xD3 ) tsu(RxD1 -SCLK1 ), tsu(SIN2-SCLK2 ), tsu(R xD3 -SCLK3 ) TXD 1 TXD 3 SO U T R XD 1 R XD 3 SI N SCLK1 SCLK2 SCLK3 I N T1 ,I N T2 ,I N T3 I N N I N N CNTR 0, CNTR1, CNTR2 0.2VCC tW L XC I N ) 0.8VCC tW H XC I N tC XC I N ) XCIN tW L SC L K tW L SC L K tW L SC L K S i n g l e - c h i p m o d e t i m i n g d i a g r a m tf tr td( SC L K 1-TxD1 ) td( SC L K 2-SOUT 2) td( SC L K 3-TxD3 ) tv( SC L K 1-TxD1 ) tv( SC L K 2-SOUT 2) tv( SC L K 3-TxD3 )

Rev.1.01 Jan 25, 2005 page 112 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) Table 32 Multi-master I2C-BUS bus line characteristics Fig. 96 Timing diagram of multi-master I2C-BUS tB U F tH D S T A tH D D A T tL O W tR tF tHIGH tsu:DAT ts u S T A tHD:STA ts u S T O S C L P S S r P S D A S: S T A R T c o n d i t i o n S R E S T A R T c o n d i t i o n S T O P c o n d i t i o n Symbol Parameter Unit Bus free time Hold time for START condition Hold time for SCL clock = “0” Rising time of both SCL and SDA signals Data hold time Hold time for SCL clock = “1” Falling time of both SCL and SDA signals Data setup time Setup time for repeated START condition Setup time for STOP condition tBUF tHD;STA tLOW tR tHD;DAT tHIGH tF tSU;DAT tSU;STA tSU;STO Min. Max. Min. Max. µs µs µs ns µs µs ns ns µs µs Standard clock modeHigh-speed clock mode Note:C b = total capacitance of 1 bus line 4.7 4.0 4.7 4.0 250 4.7 4.0 1000 300 1.3 0.6 1.3 20+0.1Cb 0.6 20+0.1Cb 100 0.6 0.6 300 0.9 300

Rev.1.01 Jan 25, 2005 page 113 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) 64 33 321 E ce1 A2A1 bb1 b2e L A SEATING PLANE D SDIP64-P-750-1.78 Weight(g) –7 . 9 JEDEC CodeEIAJ Package Code Lead Material Alloy 42/Cu Alloy 64P4B Plastic 64pin 750mil SDIP Symbol Min Nom Max A b c E D L Dimension in Millimeters A1 0.38 –– – 3.8 – 0.4 0.5 0.59 0.9 1.0 1.3 0.65 0.75 1.05 0.2 0.25 0.32 56.2 56.4 56.6 16.85 17.0 17.15 – 1.778 – – 19.05 – 2.8 –– 0°– 15° –– 5. e PACKAGE OUTLINE QFP64-P-1414-0.80 1.11 Weight(g) JEDEC CodeEIAJ Package Code Lead Material Alloy 42 64P6N-A Plastic 64pin 14✕ 14mm body QFP Symbol Min Nom Max A b c D E H E L y Dimension in Millimeters H D A1 0.20.1 0.5 ––I2 1.3 ––M D 14.6 ––M E 14.6 10°0° 0.1 1.4 0.80.60.4 17.116.816.5 17.116.816.5 0.8 14.214.013.8 14.214.013.8 0.20.150.13 0.450.350.3 2.8 3.05 e e e E c H E 64 49 H D D M D M E A F b A1 A2 L y Recommended Mount Pad Detail F

Rev.1.01 Jan 25, 2005 page 114 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) LQFP64-P-1010-0.5 Weight(g) JEDEC CodeEIAJ Package Code Lead Material Cu Alloy 64P6Q-A Plastic 64pin 10✕ 10mm body LQFP 0.1 0.2 Symbol Min Nom Max A b c D E H E L y Dimension in Millimeters H D 0.225 ——I2 1.0 ——M D 10.4 ——M E 10.4 10¡0¡ 0.1 1.0 0.70.50.3 12.212.011.8 12.212.011.8 0.5 10.110.09.9 10.110.09.9 0.1750.1250.105 0.280.180.13 1.4 1.7 e e E H E 48 33 161 H D D M D M E A F y Recommended Mount Pad Lp 0.45 0.6 0.25 0.75 0.08 x b x M A1 A2 L Detail F Lp c e LQFP64-P-1414-0.8 Weight(g) JEDEC CodeEIAJ Package Code Lead Material Cu Alloy 64P6U-A Plastic 64pin 14✕ 14mm body LQFP 0.1 0.8 0.2 Symbol Min Nom Max A b c D E H E L y Dimension in Millimeters H D ——I2 ——M D 14.4 ——M E 14.4 0¡ 8¡ 0.1 0.2 1.0 0.70.50.3 16.215.8 14.113.9 16.215.8 14.0 14.113.9 14.0 16.0 16.0 0.1750.1250.105 0.450.370.32 1.4 1.7 e Lp 0.45 0.95 0.6 0.5 0.25 0.75 x Recommended Mount Pad Detail F E H E 1 16 48 33 H D D A y b x M e F M D M E e A1 A2 L Lp c

REVISION HISTORY

Rev. Date Description Page Summary (1/1) 3804 Group (Spec.H) Data Sheet First edition issued–1.00 Dec.10, 2004 1.01 Jan.25, 2005 2 Fig.1, 2 pin configurations are partly revised. P32→ P32/SDA, P33→ P33/SCL 11 “ (2) Bits 1, 2, 3 of address 001016: Middle-speed Mode Automatic Switch Func- tion” is partly revised. “G Middle-speed mode automatic switch by SCL/SDA Interrupt” is added. Note 2 of Fig.9 is added. 22 INTERRUPTS is partly revised. I Note is partly added. 31 I Precautoins of “ (3) Pulse output mode” is partly revised.

33 I Precautoins of “ (6) Programmable waveform generating mode” is partly re-

vised. I Precautoins of “ (7) Programmable one-shot generating mode” is partly re- vised. 93,94,95,96Fig.87, 88, 89, 90 are partly revised. P32→ P32/SDA, P33→ P33/SCL

Keep safety first in your circuit designs! 1.Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1.These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2.Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3.All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4.When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5.Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6.The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7.If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8.Please contact Renesas Technology Corp. for further details on these materials or the products contained therein. Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan http://www.renesas.com Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2730-6071 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Renesas Technology (Shanghai) Co., Ltd. Unit2607 Ruijing Building, No.205 Maoming Road (S), Shanghai 200020, China Renesas Technology Singapore Pte. Ltd.

1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632

Tel: <65> 6213-0200, Fax: <65> 6278-8001 RENESAS SALES OFFICES © 2004. Renesas Technology Corp., All rights reserved. Printed in Japan. Colophon .2.0