LT1374 LINER | Alldatasheet
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4.5A, 500kHz Step-Down Switching Regulator n Constant 500kHz Switching Frequency n High Power 16-Pin TSSOP Package Available n Uses All Surface Mount Components n Inductor Size Reduced to 1.8mH n Saturating Switch Design: 0.07W n Effective Supply Current: 2.5mA n Shutdown Current: 20mA n Cycle-by-Cycle Current Limiting n Easily Synchronizable The LT 1374 is a 500kHz monolithic buck mode switching regulator. A 4.5A switch is included on the die along with all the necessary oscillator, control and logic circuitry. High switching frequency allows a considerable reduction in the size of external components. The topology is current mode for fast transient response and good loop stability. Both fixed output voltage and adjustable parts are available. A special high speed bipolar process and new design tech- niques achieve high efficiency at high switching frequency. Efficiency is maintained over a wide output current range by using the output to bias the circuitry and by utilizing a supply boost capacitor to saturate the power switch. The LT1374 is available in standard 7-pin DD, TO-220, fused lead SO-8 and 16-pin exposed pad TSSOP packages. Full cycle-by-cycle short-circuit protection and thermal shut- down are provided. Standard surface mount external parts may be used, including the inductor and capacitors. There is the optional function of shutdown or synchronization. A shutdown signal reduces supply current to 20mA. Synchro- nization allows an external logic level signal to increase the internal oscillator from 580kHz to 1MHz. , LTC and LT are registered trademarks of Linear Technology Corporation. 5V Buck Converter LOAD CURRENT (A) EFFICIENCY (%) 100 2.0 2.5 3.0 3.5
1374 TA02
0.5 1.0 1.5 4.0 VOUT = 5V VIN = 10V L = 10mH Efficiency vs Load Current BOOST LT1374-5 VIN SHDN OUTPUT** 5V, 4.25A * RIPPLE CURRENT RATING ‡ IOUT/2 ** INCREASE L1 TO 10 mH FOR LOAD CURRENTS ABOVE 3.5A AND TO 20mH ABOVE 4A SEE APPLICATIONS INFORMATION INPUT 6V TO 25V
1374 TA01
0.27mF CC 1.5nF MBRS330T3 100mF, 10V SOLID TANTALUM C3* 10mF TO 50mF DEFAULT = ON CMDSH3 OR FMMD914 L1** 5mH V SW SENSE BIAS GND VC n Portable Computers n Battery-Powered Systems n Battery Chargers n Distributed Power FEATURES DESCRIPTIO U APPLICATIO SU TYPICAL APPLICATIO U
Operating Junction Temperature Range R PACKAGE 7-LEAD PLASTIC DD FRONT VIEW TAB IS GND FB OR SENSE* BOOST V IN GND V SW SYNC OR SHDN* V C TOP VIEW S8 PACKAGE 8-LEAD PLASTIC SO VIN BOOST FGND VSW VC BIAS SYNC OR SHDN* FB OR SENSE* qJA =8 0 °C/ W WITH FUSED (FGND) GROUND PIN CONNECTED TO GROUND PLANE OR LARGE LANDS LT1374CS8 LT1374CS8-5 LT1374CS8-SYNC LT1374CS8-5 SYNC LT1374HVCS8 LT1374IS8 LT1374IS8-5 LT1374IS8-SYNC LT1374IS8-5 SYNC LT1374HVIS8 TJMAX = 125°C, qJA = 30°C/ W WITH PACKAGE SOLDERED TO 0.5 SQUARE INCH COPPER AREA OVER BACKSIDE GROUND PLANE OR INTERNAL POWER PLANE. q JA CAN VARY FROM 20°C/W TO > 40°C/W DEPENDING ON MOUNTING TECHNIQUES ORDER PART NUMBER LT1374CR LT1374CR-5 LT1374CR-SYNC LT1374CR-5 SYNC LT1374HVCR LT1374IR LT1374IR-5 LT1374IR-SYNC LT1374IR-5 SYNC LT1374HVIR 1374 13745 1374SN 3745SN 1374HV 1374I 1374I5 374ISN 74I5SN 1374HVI (Note 1)ABSOLUTE AXI U RATI GSW WW U PACKAGE/ORDER I FOR ATIOUU W ORDER PART NUMBER FE16 PACKAGE 16-LEAD PLASTIC TSSOP TOP VIEW GND NC V IN VIN BOOST FB/SENSE NC GND GND VSW VSW SYNC SHDN V C BIAS GND T7 PACKAGE 7-LEAD PLASTIC TO-220 FB OR SENSE* BOOST V IN GND V SW SHDN V C FRONT VIEW TAB IS GND TJMAX = 125°C, qJA = 50°C/ W, qJC = 4°C/ W qJA = 40°C/ W EXPOSED PAD SOLDERED TO GROUND PLANE ORDER PART NUMBER LT1374CT7 LT1374CT7-5 LT1374IT7 LT1374IT7-5 LT1374CFE LT1374IFE *Default is the adjustable output voltage device with FB pin and shutdown function. Option -5 replaces FB with SENSE pin for fixed 5V output applications. -SYNC replaces SHDN with SYNC pin for applications requiring synchronization. Consult LTC Marketing for parts specified with wider operating temperature ranges. ORDER PART NUMBER
PARAMETER CONDITIONS MIN TYP MAX UNITS Feedback Voltage (Adjustable) 2.39 2.42 2.45 V All Conditions l 2.36 2.48 V Sense Voltage (Fixed 5V) 4.94 5.0 5.06 V All Conditions l 4.90 5.10 V SENSE Pin Resistance 71 0 1 4 k W Reference Voltage Line Regulation 5V £ VIN £ 25V (5V £ VIN £ 32V for LT1374HV) 0.01 0.03 %/V Feedback Input Bias Current l 0.5 2 mA Error Amplifier Voltage Gain (Notes 2, 8) 200 400 Error Amplifier Transconductance DI (VC) = –10mA (Note 8) 1500 2000 2700 mMho l 1000 3100 mMho VC Pin to Switch Current Transconductance 5.3 A/ V Error Amplifier Source Current V FB = 2.1V or VSENSE = 4.4V l 140 225 320 mA Error Amplifier Sink Current V FB = 2.7V or VSENSE = 5.6V l 140 225 320 mA VC Pin Switching Threshold Duty Cycle = 0 0.9 V VC Pin High Clamp 2.1 V Switch Current Limit V C Open, VFB = 2.1V or VSENSE = 4.4V, DC £ 50% l 4.5 6 8.5 A Slope Compensation (Note 9) DC = 80% 0.8 A Switch On Resistance (Note 7) I SW = 4.5A 0.07 0.1 W l 0.13 W Maximum Switch Duty Cycle V FB = 2.1V or VSENSE = 4.4V 90 93 % l 86 93 % Switch Frequency V C Set to Give 50% Duty Cycle 460 500 540 kHz l 440 560 kHz Switch Frequency Line Regulation 5V £ VIN £ 25V, (5V £ VIN £ 32V for LT1374HV) l 0 0.15 %/ V Frequency Shifting Threshold on FB Pin Df = 10kHz l 0.8 1.0 1.3 V Minimum Input Voltage (Note 3) l 5.0 5.5 V Minimum Boost Voltage (Note 4) I SW £ 4.5A l 2.3 3.0 V Boost Current (Note 5) I SW = 1A l 20 35 mA ISW = 4.5A l 90 140 mA VIN Supply Current (Note 6) V BIAS = 5V l 0.9 1.4 mA BIAS Supply Current (Note 6) V BIAS = 5V l 3.2 4.0 mA Shutdown Supply Current V SHDN = 0V, VIN £ 25V, VSW = 0V, VC Open 20 50 mA l 75 mA VSHDN = 0V, VIN £ 32V, VSW = 0V, VC Open 30 75 mA l 100 mA Lockout Threshold V C Open l 2.3 2.38 2.46 V Shutdown Thresholds V C Open Device Shutting Down l 0.13 0.37 0.60 V Device Starting Up l 0.25 0.45 0.7 V Synchronization Threshold l 1.5 2.2 V Synchronizing Range 580 1000 kHz SYNC Pin Input Resistance 40 k W Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: Gain is measured with a VC swing equal to 200mV above the switching threshold level to 200mV below the upper clamp level. Note 3: Minimum input voltage is not measured directly, but is guaranteed by other tests. It is defined as the voltage where internal bias lines are still regulated so that the reference voltage and oscillator frequency remain constant. Actual minimum input voltage to maintain a regulated output will depend on output voltage and load current. See Applications Information. Note 4: This is the minimum voltage across the boost capacitor needed to guarantee full saturation of the internal power switch. The l denotes specifications which apply over the full operating tempera- ture range, otherwise specifications are at TJ = 25°C. VIN = 15V, VC = 1.5V, Boost = VIN + 5V, switch open, unless otherwise noted.
ELECTRICAL CHARACTERISTICS
SWITCH CURRENT (A) SWITCH VOLTAGE (mV) 250 200 400 125°C 25°C 350 300
1374 G18
–40 °C Feedback Pin Voltage TEMPERATURE (°C) –50 2.430 2.425 2.420 2.415 2.410 100
1374 G03
–25 0 25 50 75 125 FEEDBACK VOLTAGE (V) Switch Peak Current Limit DUTY CYCLE (%) SWITCH PEAK CURRENT (A) 6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0
1374 G02
TEMPERATURE (°C) –50 500 400 300 200 25 75
1374 G04
–25 0 50 100 125 CURRENT (mA) CURRENT REQUIRED TO FORCE SHUTDOWN (FLOWS OUT OF PIN). AFTER SHUTDOWN, CURRENT DROPS TO A FEW mA AT 2.38V STANDBY THRESHOLD (CURRENT FLOWS OUT OF PIN) Standby and Shutdown Thresholds Shutdown Supply Current JUNCTION TEMPERATURE (°C) –50 2.40 2.36 2.32 0.8 0.4 25 75
1374 G05
–25 0 50 100 125 SHUTDOWN PIN VOLTAGE (V) STANDBY START-UP SHUTDOWN INPUT VOLTAGE (V) INPUT SUPPLY CURRENT (mA) 5 1 01 52 0
1374 G06
VSHDN = 0V Note 5: Boost current is the current flowing into the boost pin with the pin held 5V above input voltage. It flows only during switch on time. Note 6: VIN supply current is the current drawn when the BIAS pin is held at 5V and switching is disabled. If the BIAS pin is unavailable or open circuit, the sum of VIN and BIAS supply currents will be drawn by the VIN pin. Note 7: Switch on resistance is calculated by dividing VIN to VSW voltage by the forced current (4.5A). See Typical Performance Characteristics for the graph of switch voltage at other currents. Note 8: Transconductance and voltage gain refer to the internal amplifier exclusive of the voltage divider. To calculate gain and transconductance, refer to the SENSE pin on the fixed voltage parts. Divide values shown by the ratio VOUT/2.42. Note 9: Slope compensation is the current subtracted from the switch current limit at 80% duty cycle. See Maximum Output Load Current in the Applications Information section for further details. TYPICAL PERFOR A CE CHARACTERISTICS UW
FEEDBACK PIN VOLTAGE (V) SWITCHING FREQUENCY (kHz) OR CURRENT (mA)500 400 300 200 100 2.0
1374 G10
0.5 1.0 1.5 2.5 SWITCHING FREQUENCY FEEDBACK PIN CURRENT Frequency Foldback LOAD CURRENT (mA) 5.8 INPUT VOLTAGE (V) 6.0 6.2 6.4 10 100 1000
1374 G12
5.6 5.4 5.2 5.0 MINIMUM RUNNING VOLTAGE MINIMUM STARTING VOLTAGE Minimum Input Voltage with 5V Output TEMPERATURE (°C) –5 0 550 540 530 520 510 500 490 480 470 460 450 100
1374 G11
–25 0 25 50 75 125 FREQUENCY (kHz) Switching Frequency Maximum Load Current at VOUT = 10V INPUT VOLTAGE (V) CURRENT (A) 4.5 4.0 3.5 3.0 51 0 1 5 2 0
1374 G13
L = 20mH L = 10mH L = 5mH VOUT = 10V Maximum Load Current at VOUT = 3.3V INPUT VOLTAGE (V) CURRENT (A) 4.5 4.0 3.5 3.0 51 0 1 5 2 0
1374 G14
L = 20mH L = 10mH L = 5mH VOUT = 3.3V Maximum Load Current at VOUT = 5V INPUT VOLTAGE (V) CURRENT (A) 4.5 4.0 3.5 3.0 51 0 1 5 2 0
1374 G15
L = 20mH L = 10mH L = 5mH VOUT = 5V Shutdown Supply Current SHUTDOWN VOLTAGE (V) INPUT SUPPLY CURRENT (mA) 0.1 0.2 0.3 0.4
1374 G07
VIN = 25V VIN = 10V Error Amplifier Transconductance FREQUENCY (Hz) GAIN (mMho) PHASE (DEG) 3000 2500 2000 1500 1000 500 200 150 100 –50 100 10k 100k 10M
1374 G09
ERROR AMPLIFIER EQUIVALENT CIRCUIT ROUT 200k COUT 12pF VC RLOAD = 50W VFB 2 · 10–3)( Error Amplifier Transconductance JUNCTION TEMPERATURE (°C) –50 TRANSCONDUCTANCE (mMho) 2500 2000 1500 1000 500 0 50 75
1374 G08
–25 25 100 125 TYPICAL PERFOR A CE CHARACTERISTICS UW
FB/SENSE: The feedback pin is the input to the error amplifier which is referenced to an internal 2.42V source. An external resistive divider is used to set the output voltage. The fixed voltage (-5) parts have the divider included on-chip and the FB pin is used as a SENSE pin, connected directly to the 5V output. Three additional functions are performed by the FB pin. When the pin voltage drops below 1.7V, switch current limit is reduced. Below 1.5V the external sync function is disabled. Below 1V, switching frequency is also reduced. See Feedback Pin Function section in Applications Information for details. BOOST: The BOOST pin is used to provide a drive voltage, higher than the input voltage, to the internal bipolar NPN power switch. Without this added voltage, the typical switch voltage loss would be about 1.5V. The additional boost voltage allows the switch to saturate and voltage loss approximates that of a 0.07 W FET structure. Effi- ciency improves from 75% for conventional bipolar de- signs to > 89% for these new parts. V IN: This is the collector of the on-chip power NPN switch. This pin powers the internal circuitry and internal regulator when the BIAS pin is not present. At NPN switch on and off, high dI/dt edges occur on this pin. Keep the external bypass and catch diode close to this pin. All trace induc- tance on this path will create a voltage spike at switch off, adding to the V CE voltage across the internal NPN. Both VIN pins of the 16-lead TSSOP package must be shorted together on the PC board. GND: The GND pin connection needs consideration for two reasons. First, it acts as the reference for the regulated output, so load regulation will suffer if the “ground” end of the load is not at the same voltage as the GND pin of the IC. This condition will occur when load current or other currents flow through metal paths between the GND pin and the load ground point. Keep the ground path short between the GND pin and the load and use a ground plane when possible. The second consideration is EMI caused by GND pin current spikes. Internal capacitance between the V SW pin and the GND pin creates very narrow (<10ns) current spikes in the GND pin. If the GND pin is connected to system ground with a long metal trace, this trace may radiate excess EMI. Keep the path between the input bypass and the GND pin short. V SW: The switch pin is the emitter of the on-chip power NPN switch. This pin is driven up to the input pin voltage during switch on time. Inductor current drives the switch pin negative during switch off time. Negative voltage is clamped with the external catch diode. Maximum negative switch voltage allowed is – 0.8V. Both V SW pins of the 16-lead TSSOP package must be shorted together on the PC board. BOOST Pin Current SWITCH CURRENT (A) BOOST PIN CURRENT (mA) 12 3 45
1374 G16
DUTY CYCLE = 100% Inductor Core Loss INDUCTANCE (mH) CORE LOSS (W) CORE LOSS (% OF 5W LOAD) 1.0 0.1 0.01 0.001 10 15 20 1.2 0.8 0.4 0.2 0.12 0.08 0.04 0.02
1374 G01
Kool Mm® PERMALLOY m = 125 VOUT = 5V, VIN = 10V, IOUT = 1A CORE LOSS IS INDEPENDENT OF LOAD CURRENT UNTIL LOAD CURRENT FALLS LOW ENOUGH FOR CIRCUIT TO GO INTO DISCONTINUOUS MODE VC Pin Shutdown Threshold JUNCTION TEMPERATURE (°C) –50 1.4 1.2 1.0 0.8 0.6 0.4 100 –25 0 25 50 75 125 THRESHOLD VOLTAGE (V) SHUTDOWN TYPICAL PERFOR A CE CHARACTERISTICS UW UUUPI FU CTIO S
it much easier to frequency compensate the feedback loop and also gives much quicker transient response. Most of the circuitry of the LT1374 operates from an internal 2.9V bias line. The bias regulator normally draws power from the regulator input pin, but if the BIAS pin is connected to an external voltage higher than 3V, bias power will be drawn from the external source (typically the regulated output voltage). This will improve efficiency if the BIAS pin voltage is lower than regulator input voltage. High switch efficiency is attained by using the BOOST pin to provide a voltage to the switch driver which is higher than the input voltage, allowing the switch to saturate. This boosted voltage is generated with an external capacitor and diode. Two comparators are connected to the shut- down pin. One has a 2.38V threshold for undervoltage lockout and the second has a 0.4V threshold for complete shutdown. The LT1374 is a constant frequency, current mode buck converter. This means that there is an internal clock and two feedback loops that control the duty cycle of the power switch. In addition to the normal error amplifier, there is a current sense amplifier that monitors switch current on a cycle-by-cycle basis. A switch cycle starts with an oscilla- tor pulse which sets the R S flip-flop to turn the switch on. When switch current reaches a level set by the inverting input of the comparator, the flip-flop is reset and the switch turns off. Output voltage control is obtained by using the output of the error amplifier to set the switch current trip point. This technique means that the error amplifier commands current to be delivered to the output rather than voltage. A voltage fed system will have low phase shift up to the resonant frequency of the inductor and output capacitor, then an abrupt 180° shift will occur. The current fed system will have 90° phase shift at a much lower frequency, but will not have the additional 90° shift until well beyond the LC resonant frequency. This makes SYNC: (Excludes T7 package) The sync pin is used to synchronize the internal oscillator to an external signal. It is directly logic compatible and can be driven with any signal between 10% and 90% duty cycle. The synchroniz- ing range is equal to initial operating frequency, up to 1MHz. This pin replaces SHDN on -SYNC option parts. See Synchronizing section in Applications Information for details. SHDN: The shutdown pin is used to turn off the regulator and to reduce input drain current to a few microamperes. Actually, this pin has two separate thresholds, one at 2.38V to disable switching, and a second at 0.4V to force complete micropower shutdown. The 2.38V threshold functions as an accurate undervoltage lockout (UVLO). This can be used to prevent the regulator from operating until the input voltage has reached a predetermined level. V C: The VC pin is the output of the error amplifier and the input of the peak switch current comparator. It is normally UUUPI FU CTIO S used for frequency compensation, but can do double duty as a current clamp or control loop override. This pin sits at about 1V for very light loads and 2V at maximum load. It can be driven to ground to shut off the regulator, but if driven high, current must be limited to 4mA. BIAS: (SO-8 and FE16 Packages) The BIAS pin is used to improve efficiency when operating at higher input volt- ages and light load current. Connecting this pin to the regulated output voltage forces most of the internal cir- cuitry to draw its operating current from the output voltage rather than the input supply. This is a much more efficient way of doing business if the input voltage is much higher than the output. Minimum output voltage setting for this mode of operation is 3.3V . Efficiency improvement at VIN = 20V, VOUT = 5V, and IOUT = 25mA is over 10%. NC: No Connect. Leave floating or solder to any node. BLOCK DIAGRA W
Foldback graph in Typical Performance Characteristics). Figure 2. Frequency and Current Limit Foldback
1374 F02
load current with output voltage less than 50% of final value. the LT1374 to lose control of current limit. current foldback will decrease.
APPLICATIONS INFORMATIONWU UU MAXIMUM OUTPUT LOAD CURRENT Maximum load current for a buck converter is limited by the maximum switch current rating (I P) of the LT1374. This current rating is 4.5A up to 50% duty cycle (DC), decreasing to 3.7A at 80% duty cycle. This is shown graphically in Typical Performance Characteristics and as shown in the formula below: I P = 4.5A for DC £ 50% DC = Duty cycle = VOUT/VIN Example: with VOUT = 5V, VIN = 8V; DC = 5/8 = 0.625, and; Current rating decreases with duty cycle because the LT1374 has internal slope compensation to prevent current mode subharmonic switching. For more details, read Ap- plication Note 19. The LT1374 is a little unusual in this regard because it has nonlinear slope compensation which gives better compensation with less reduction in current limit. Maximum load current would be equal to maximum switch current for an infinitely large inductor , but with finite inductor size, maximum load current is reduced by one-half peak-to-peak inductor current. The following formula assumes continuous mode operation, implying that the term on the right is less than one-half of I IOUT(MAX) = Continuous Mode For the conditions above and L = 3.3mH, I A OUT MAX( ) - =- () -() æ Ł ö ł æ Ł ö ł() =- = 58 5 2 3 3 10 500 10 8 43 05 7 37 3 .· · .. . At VIN = 15V, duty cycle is 33%, so IP is just equal to a fixed 4.5A, and IOUT(MAX) is equal to: 51 5 5 2 3 3 10 500 10 15 45 1 35 .· · - () -() æ Ł ö ł æ Ł ö ł() =- = A Note that there is less load current available at the higher input voltage because inductor ripple current increases. This is not always the case. Certain combinations of inductor value and input voltage range may yield lower available load current at the lowest input voltage due to reduced peak switch current at high duty cycles. If load current is close to the maximum available, please check maximum available current at both input voltage extremes. To calculate actual peak switch current with a given set of conditions, use: II VV V LfV SW PEAK OUT OUT IN OUT IN ( ) =+ -() () ( ) ( )2 For lighter loads where discontinuous operation can be used, maximum load current is equal to: IOUT(MAX) = Discontinuous mode Example: with L = 1.2mH, VOUT = 5V, and VIN(MAX) = 15V, IAOUT MAX( ) () æ Ł ö ł æ Ł ö ł() () -() 4 5 500 10 1 2 10 15 2 5 15 5 18 2 2 36.· . · The main reason for using such a tiny inductor is that it is physically very small, but keep in mind that peak-to-peak inductor current will be very high. This will increase output ripple voltage. If the output capacitor has to be made larger to reduce ripple voltage, the overall circuit could actually wind up larger. CHOOSING THE INDUCTOR AND OUTPUT CAPACITOR For most applications the output inductor will fall in the range of 3mH to 20mH. Lower values are chosen to reduce physical size of the inductor. Higher values allow more output current because they reduce peak current seen by the LT1374 switch, which has a 4.5A limit. Higher values also reduce output ripple voltage, and reduce core loss. Graphs in the Typical Performance Characteristics section show maximum output load current versus inductor size and input voltage. A second graph shows core loss versus inductor size for various core materials. I P - () -() () ( ) ( ) VV V LfV OUT IN OUT IN2 If L V VV V PI N OUT IN OUT () ( ) ( ) ( ) () -()
When choosing an inductor you might have to consider maximum load current, core and copper losses, allowable component height, output voltage ripple, EMI, fault cur- rent in the inductor, saturation, and of course, cost. The following procedure is suggested as a way of handling these somewhat complicated and conflicting requirements. 1. Choose a value in microhenries from the graphs of maximum load current and core loss. Choosing a small inductor may result in discontinuous mode operation at lighter loads, but the LT1374 is designed to work well in either mode. Keep in mind that lower core loss means higher cost, at least for closed core geometries like toroids. The core loss graphs show both absolute loss and percent loss for a 5W output, so actual percent losses must be calculated for each situation. Assume that the average inductor current is equal to load current and decide whether or not the inductor must withstand continuous fault conditions. If maxi- mum load current is 0.5A, for instance, a 0.5A inductor may not survive a continuous 4.5A overload condition. Dead shorts will actually be more gentle on the induc- tor because the LT1374 has foldback current limiting. 2. Calculate peak inductor current at full load current to ensure that the inductor will not saturate. Peak current can be significantly higher than output current, espe- cially with smaller inductors and lighter loads, so don’t omit this step. Powdered iron cores are forgiving because they saturate softly, whereas ferrite cores saturate abruptly. Other core materials fall somewhere in between. The following formula assumes continu- ous mode of operation, but it errs only slightly on the high side for discontinuous mode, so it can be used for all conditions. II VV V fLV PEAK OUT OUT IN OUT IN -() () ( ) ( )2 VIN = Maximum input voltage f = Switching frequency, 500kHz 3. Decide if the design can tolerate an “open” core geom- etry like a rod or barrel, with high magnetic field radiation, or whether it needs a closed core like a toroid to prevent EMI problems. One would not want an open APPLICATIONS INFORMATIONWU UU core next to a magnetic storage media, for instance! This is a tough decision because the rods or barrels are temptingly cheap and small and there are no helpful guidelines to calculate when the magnetic field radia- tion will be a problem. 4. Start shopping for an inductor (see representative surface mount units in Table 2) which meets the requirements of core shape, peak current (to avoid Table 2 SERIES CORE VENDOR/ VALUE DC CORE RESIS- MATER- HEIGHT PART NO. ( mH) (Amps) TYPE TANCE( W ) IAL (mm) Coiltronics CTX2-1 2 4.1 Tor 0.011 KM m 4.2 CTX5-4 5 4.4 Tor 0.019 KM m 6.4 CTX8-4 8 3.5 Tor 0.020 KM m 6.4 CTX2-1P 2 3.4 Tor 0.014 52 4.2 CTX2-3P 2 4.6 Tor 0.012 52 4.8 CTX5-4P 5 3.3 Tor 0.027 52 6.4 Sumida CDRH125 10 4.0 SC 0.025 Fer 6 CDRH125 12 3.5 SC 0.027 Fer 6 CDRH125 15 3.3 SC 0.030 Fer 6 CDRH125 18 3.0 SC 0.034 Fer 6 Coilcraft DT3316-222 2.2 5 SC 0.035 Fer 5.1 DT3316-332 3.3 5 SC 0.040 Fer 5.1 DT3316-472 4.7 3 SC 0.045 Fer 5.1 Pulse PE-53650 4 4.8 Tor 0.017 Fer 9.1 PE-53651 5 5.4 Tor 0.018 Fer 9.1 PE-53652 9 5.5 Tor 0.022 Fer 10 PE-53653 16 5.1 Tor 0.032 Fer 10 Dale IHSM-4825 2.7 5.1 Open 0.034 Fer 5.6 IHSM-4825 4.7 4.0 Open 0.047 Fer 5.6 IHSM-5832 10 4.3 Open 0.053 Fer 7.1 IHSM-5832 15 3.5 Open 0.078 Fer 7.1 IHSM-7832 22 3.8 Open 0.054 Fer 7.1 Tor = Toroid SC = Semi-closed geometry Fer = Ferrite core material 52 = Type 52 powdered iron core material KMm = Kool Mm
are prone to failure if they undergo high surge currents. dead shorted, do not harm the capacitors. ally resonate with their ESL before ESR becomes effective. high ripple current ratings and tolerance of turn-on surges. of ceramic capacitors in the near future.
- After making an initial choice, consider the secondary
things like output voltage ripple, second sourcing, etc. opments in low profile, surface mounting, etc. tantalum surface mount capacitors. Table 3. Surface Mount Solid Tantalum Capacitor ESR
to be small compared to ESR or ESL. ous operation under these conditions must be tolerated. instead be connected to the unregulated input voltage. very low (< 3V) or if the input voltage is less than 5V. Figure 3. LT1374 Ripple Voltage Waveform
ceramic capacitor will work fine. peak load current of 4.25A, this gives a total drain of 85mA. perature and output overload. where these problems might occur.
1374 F04
Figure 4. Undervoltage Lockout
APPLICATIONS INFORMATIONWU UU Threshold voltage for lockout is about 2.38V, slightly less than the internal 2.42V reference voltage. A 3.5 mA bias current flows out of the pin at threshold. This internally generated current is used to force a default high state on the shutdown pin if the pin is left open. When low shut- down current is not an issue, the error due to this current can be minimized by making R LO 10k or less. If shutdown current is an issue, RLO can be raised to 100k, but the error due to initial bias current and changes with temperature should be considered. Rk R RV V VR A LO HI LO IN LO = () -() - () 23 8 23 8 35 to 100k 25k suggested .. m VIN = Minimum input voltage Keep the connections from the resistors to the shutdown pin short and make sure that interplane or surface capaci- tance to the switching nodes are minimized. If high resistor values are used, the shutdown pin should be bypassed with a 1000pF capacitor to prevent coupling problems from the switch node. If hysteresis is desired in the undervoltage lockout point, a resistor R FB can be added to the output node. Resistor values can be calcu- lated from: R RV V V V RA RR V V HI LO IN OUT FB HI OUT -+ () +[] - () = () ( ) 23 8 1 23 8 235 DD D m 25k suggested for RLO VIN = Input voltage at which switching stops as input voltage descends to trip level DV = Hysteresis in input voltage level Example: output voltage is 5V, switching is to stop if input voltage drops below 12V and should not restart unless input rises back to 13.5V. DV is therefore 1.5V and VIN = 12V. Let RLO = 25k. R k kA k k Rk k HI FB -+ () +[] - () = () = = () = 25 12 2 38 1 5 5 1 1 5 23 8 2 5 35 25 10 41 22 9 114 114 5 1 5 380 .. / . m SWITCH NODE CONSIDERATIONS For maximum efficiency, switch rise and fall times are made as short as possible. To prevent radiation and high frequency resonance problems, proper layout of the com- ponents connected to the switch node is essential. B field (magnetic) radiation is minimized by keeping catch diode, switch pin, and input bypass capacitor leads as short as possible. E field radiation is kept low by minimizing the length and area of all traces connected to the switch pin and BOOST pin. A ground plane should always be used under the switcher circuitry to prevent interplane cou- pling. A suggested layout for the critical components is shown in Figure 5. Note that the feedback resistors and compensation components are kept as far as possible from the switch node. Also note that the high current ground path of the catch diode and input capacitor are kept very short and separate from the analog ground line. The high speed switching current path is shown schemati- cally in Figure 6. Minimum lead length in this path is essential to ensure clean switching and low EMI. The path including the switch, catch diode, and input capacitor is the only one containing nanosecond rise and fall times. If you follow this path on the PC layout, you will see that it is irreducibly short. If you move the diode or input capacitor away from the LT1374, get your resumé in order. The other paths contain only some combination of DC and 500kHz triwave, so are much less critical.
Figure 5a. Suggested Layout (Topside Only Shown) SO-8 APPLICATIONS INFORMATIONWU UU CONNECT TO GROUND PLANE KEEP FB AND VC COMPONENTS AWAY FROM HIGH FREQUENCY, HIGH CURRENT COMPONENTS PLACE FEEDTHROUGHS AROUND GND PIN FOR GOOD THERMAL CONDUCTIVITY R3 D2 C4R2
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GROUND PLANEMINIMIZE LT1374, C3, D1 LOOP KELVIN SENSE VOUT TAKE OUTPUT DIRECTLY FROM END OF OUTPUT CAPACITOR
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BETTER THERMAL CONDUCTIVITY KEEP FB AND VC COMPONENTS AWAY FROM HIGH FREQUENCY, HIGH CURRENT COMPONENTS APPLICATIONS INFORMATIONWU UU Figure 5b. Suggested Layout (Topside Only Shown) TSSOP
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Figure 6. High Speed Switching Path
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The term inside the radical has a maximum value of 0.5 when input voltage is twice output, and stays near 0.5 for a relatively wide range of input voltages. It is common practice therefore to simply use the worst-case value and assume that RMS ripple current is one half of load current. At maximum output current of 4.5A for the LT1374, the input bypass capacitor should be rated at 2.25A ripple current. Note however, that there are many secondary considerations in choosing the final ripple current rating. These include ambient temperature, average versus peak load current, equipment operating schedule, and required product lifetime. For more details, see Application Notes 19 and 46, and Design Note 95. Input Capacitor Type Some caution must be used when selecting the type of capacitor used at the input to regulators. Aluminum electrolytics are lowest cost, but are physically large to achieve adequate ripple current rating, and size con- straints (especially height), may preclude their use. Ceramic capacitors are now available in larger values, and their high ripple current and voltage rating make them ideal for input bypassing. Cost is fairly high and footprint may also be somewhat large. Solid tantalum capacitors would be a good choice, except that they have a history of occasional spectacular failures when they are subjected to large current surges during power-up. The capacitors can short and then burn with a brilliant white light and lots of nasty smoke. This phenomenon occurs in only a small percentage of units, but it has led some OEM companies to forbid their use in high surge applications. The input bypass capacitor of regulators can see these high surges when a battery or high capacitance source is connected. Several manufacturers have developed a line of solid tantalum capacitors specially tested for surge capability (AVX TPS series for instance, see Table 3), but even these units may fail if the input voltage surge approaches the maximum voltage rating of the capacitor. AVX recom- mends derating capacitor voltage by 2:1 for high surge applications. The highest voltage rating is 50V, so 25V may be a practical upper limit when using solid tantalum capacitors for input bypassing. APPLICATIONS INFORMATIONWU UU Larger capacitors may be necessary when the input volt- age is very close to the minimum specified on the data sheet. Small voltage dips during switch on time are not normally a problem, but at very low input voltage they may cause erratic operation because the input voltage drops below the minimum specification. Problems can also occur if the input-to-output voltage differential is near minimum. The amplitude of these dips is normally a function of capacitor ESR and ESL because the capacitive reactance is small compared to these terms. ESR tends to be the dominate term and is inversely related to physical capacitor size within a given capacitor type. SYNCHRONIZING (Available as -SYNC Option) The LT1374-SYNC has the SHDN pin replaced with a SYNC pin, which is used to synchronize the internal oscillator to an external signal. The SYNC input must pass from a logic level low, through the maximum synchroni- zation threshold with a duty cycle between 10% and 90%. The input can be driven directly from a logic level output. The synchronizing range is equal to initial operating fre- quency up to 1MHz. This means that minimum practical sync frequency is equal to the worst-case high self- oscillating frequency (550kHz), not the typical operating frequency of 500kHz. Caution should be used when syn- chronizing above 700kHz because at higher sync frequen- cies the amplitude of the internal slope compensation used to prevent subharmonic switching is reduced. This type of subharmonic switching only occurs at input volt- ages less than twice output voltage. Higher inductor values will tend to eliminate this problem. See Frequency Compensation section for a discussion of an entirely different cause of subharmonic switching before assum- ing that the cause is insufficient slope compensation. Application Note 19 has more details on the theory of slope compensation. At power-up, when V C is being clamped by the FB pin (see Figure 2, Q2), the sync function is disabled. This allows the frequency foldback to operate in the shorted output con- dition. During normal operation, switching frequency is controlled by the internal oscillator until the FB pin reaches 1.5V, after which the SYNC pin becomes operational. If no synchronization is required, this pin should be connected to ground.
APPLICATIONS INFORMATIONWU UU THERMAL CALCULATIONS Power dissipation in the LT1374 chip comes from four sources: switch DC loss, switch AC loss, boost circuit current, and input quiescent current. The following formu- las show how to calculate each of these losses. These formulas assume continuous mode operation, so they should not be used for calculating efficiency at light load currents. Switch loss: P RI V V ns I V fSW SW OUT OUT IN Boost current loss: P VI VBOOST OUT OUT IN = () 50/ Quiescent current loss: PV V V VQ IN OUT OUT IN = () + () + æ Łç ö ł÷() 0 001 0 005 0 002 RSW = Switch resistance (» 0.07) 24ns = Equivalent switch current/voltage overlap time f = Switch frequency Example: with V IN = 10V, VOUT = 5V and IOUT = 3A: P W PW PW SW BOOST Q = ( ) ()() + æ Ł ö ł() ( )æ Ł ö ł =+= ()( ) = -00 7 3 5 24 10 3 10 500 10 0 32 0 36 0 68 53 5 0 01 5 10 0 001 5 0 005 5 0 002 00 4 ... Thermal resistance for LT1374 package is influenced by the presence of internal or backside planes. With a full plane under the 16-lead TSSOP package, thermal resis- tance will be about 40°C/W. To calculate die temperature, use the proper thermal resistance number for the desired package and add in worst-case ambient temperature: T J = TA + qJA (PTOT) With the TSSOP16 package (qJA = 40°C/W), at an ambient temperature of 50°C, For the DD package with a good copper plane under the device, thermal resistance will be about 30°C/W. For the conditions above: Die temperature is highest at low input voltage, so use lowest continuous input operating voltage for thermal calculations. FREQUENCY COMPENSATION Loop frequency compensation of switching regulators can be a rather complicated problem because the reactive components used to achieve high efficiency also intro- duce multiple poles into the feedback loop. The inductor and output capacitor on a conventional step-down con- verter actually form a resonant tank circuit that can exhibit peaking and a rapid 180 ° phase shift at the resonant frequency. By contrast, the LT1374 uses a “current mode” architecture to help alleviate phase shift created by the inductor. The basic connections are shown in Figure 9. Figure 10 shows a Bode plot of the phase and gain of the power section of the LT1374, measured from the V C pin to the output. Gain is set by the 5.3A/V transconductance of the LT1374 power section and the effective complex impedance from output to ground. Gain rolls off smoothly above the 600Hz pole frequency set by the 100mF output capacitor. Phase drop is limited to about 70 °. Phase recovers and gain levels off at the zero frequency (»16kHz) set by capacitor ESR (0.1W ).
impedance of the amplifier at frequencies above 500Hz. dominate all other effects with respect to loop response. Figure 10. Response from VC Pin to Output
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Figure 11. Error Amplifier Gain and Phase
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Figure 9. Model for Loop Response
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Figure 12. Overall Loop Characteristics
APPLICATIONS INFORMATIONWU UU What About a Resistor in the Compensation Network? It is common practice in switching regulator design to add a “zero” to the error amplifier compensation to increase loop phase margin. This zero is created in the external network in the form of a resistor (R C) in series with the compensation capacitor. Increasing the size of this resistor generally creates better and better loop stability, but there are two limitations on its value. First, the combination of output capacitor ESR and a large value for R C may cause loop gain to stop rolling off altogether, creating a gain margin problem. An approxi- mate formula for RC where gain margin falls to zero is: R Loop V G G ESR C OUT MP MA Gain = 1() = () () () ( ) 24 2. GMP = Transconductance of power stage = 5.3A/V GMA = Error amplifier transconductance = 2(10–3) ESR = Output capacitor ESR 2.42 = Reference voltage With VOUT = 5V and ESR = 0.03W , a value of 6.5k for RC would yield zero gain margin, so this represents an upper limit. There is a second limitation however which has nothing to do with theoretical small signal dynamics. This resistor sets high frequency gain of the error ampli- fier, including the gain at the switching frequency. If switching frequency gain is high enough, output ripple voltage will appear at the V C pin with enough amplitude to muck up proper operation of the regulator. In the marginal case, subharmonic switching occurs, as evi- denced by alternating pulse widths seen at the switch node. In more severe cases, the regulator squeals or hisses audibly even though the output voltage is still roughly correct. None of this will show on a theoretical Bode plot because Bode is an amplitude insensitive analysis. Tests have shown that if ripple voltage on the VC is held to less than 100mV P-P, the LT1374 will be well behaved. The formula below will give an estimate of VC ripple voltage when RC is added to the loop, assuming that R C is large compared to the reactance of C C at 500kHz. V R G V V ESR VL f C RIPPLE C MA IN OUT IN () ( ) ( ) 24. GMA = Error amplifier transconductance (2000mMho) If a computer simulation of the LT1374 showed that a series compensation resistor of 3k gave best overall loop response, with adequate gain margin, the resulting VC pin ripple voltage with V IN = 10V, V OUT = 5V, ESR = 0.1 W , L = 10mH, would be: V k VC RIPPLE( ) () æ Ł ö ł -() ( ) ( ) () æ Ł ö ł æ Ł ö ł 3 2 10 10 5 0 1 2 4 10 10 10 500 10 0 144
- . . This ripple voltage is high enough to possibly create subharmonic switching. In most situations a compromise value (< 2k in this case) for the resistor gives acceptable phase margin and no subharmonic problems. In other cases, the resistor may have to be larger to get acceptable phase response, and some means must be used to control ripple voltage at the V C pin. The suggested way to do this is to add a capacitor (CF) in parallel with the RC/CC network on the VC pin. Pole frequency for this capacitor is typically set at one-fifth of switching frequency so that it provides significant attenuation of switching ripple, but does not add unacceptable phase shift at loop unity-gain frequency. With R C = 3k, C fR k pFF C () ( ) () = æ Ł ö ł() 2 500 10 3 531 3p p · How Do I Test Loop Stability? The “standard” compensation for LT1374 is a 1.5nF capacitor for CC, with RC = 0. While this compensation will work for most applications, the “optimum” value for loop compensation components depends, to various extent, on parameters which are not well controlled. These include inductor value (–30% due to production tolerance, load
the loop behaves nonlinearly. this wouldn’t matter because amplitude is not critical. may require the addition of C F to control V C pin ripple. any temperature-dependent characteristics. Figure 13. Loop Stability Test Circuit
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Figure 14. Loop Stability Check
the output capacitor in production. tolerance but phase margin generally hangs in there. proper feedback voltage for the chip. maximum switch current, even with large inductor values. from the Electrical Characteristics table.
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- 2 10mF TO 50mF CMDSH-3 L1* 5mH BOOST LT1374-5 VIN VSW SENSE GND VC * INCREASE L1 TO 10 mH OR 20mH FOR HIGHER CURRENT APPLICATIONS. SEE APPLICATIONS INFORMATION ** MAXIMUM LOAD CURRENT DEPENDS ON MINIMUM INPUT VOLTAGE AND INDUCTOR SIZE. SEE APPLICATIONS INFORMATION
Figure 15. Positive-to-Negative Converter
promise value is often chosen that reduces output ripple. current is higher, use the continuous mode formula. Figure 16. Ripple Voltage on Positive-to-Negative Converter
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APPLICATIONS INFORMATIONWU UU This says that discontinuous mode can be used and the minimum inductor needed is found from: LHMIN = () ( ) æ Ł ö ł() 25 1 500 10 4 5 3 2 m In practice, the inductor should be increased by about 30% over the calculated minimum to handle losses and varia- tions in value. This suggests a minimum inductor of 1.3mH for this application, but looking at the ripple voltage chart shows that output ripple voltage could be reduced by a fac- tor of two by using a 15mH inductor. There is no rule of thumb here to make a final decision. If modest ripple is needed and the larger inductor does the trick, go for it. If ripple is non- critical use the smaller inductor. If ripple is extremely criti- cal, a second filter may have to be added in any case, and the lower value of inductance can be used. Keep in mind that the output capacitor is the other critical factor in deter- mining output ripple voltage. Ripple shown on the graph (Figure 16) is with two parallel capacitor’s ESR of 0.1W . This is reasonable for AVX type TPS “D” or “E” size surface mount solid tantalum capacitors, but the final capacitor chosen must be looked at carefully for ESR characteristics. Ripple Current in the Input and Output Capacitors Positive-to-negative converters have high ripple current in both the input and output capacitors. For long capacitor lifetime, the RMS value of this current must be less than the high frequency ripple current rating of the capacitor. The following formula will give an approximate value for RMS ripple current. This formula assumes continuous mode and large inductor value. Small inductors will give somewhat higher ripple current, especially in discontinu- ous mode. The exact formulas are very complex and appear in Application Note 44, pages 30 and 31. For our purposes here I have simply added a fudge factor (ff). The value for ff is about 1.2 for higher load currents and L ‡10mH. It increases to about 2.0 for smaller inductors at lower load currents. Capacitor ff I V VOUT OUT IN IRMS = () ( ) ff = Fudge factor (1.2 to 2.0) Diode Current Average diode current is equal to load current. Peak diode current will be considerably higher. Peak diode current: Continuous I VV V VV LfV V Discontinuous V Lf OUT IN OUT IN IN OUT IN OUT OUT Mode Mode = 2I OUT +() + () ( ) () ( ) +() () ( ) () ( ) Keep in mind that during start-up and output overloads, average diode current may be much higher than with normal loads. Care should be used if diodes rated less than 3A are used, especially if continuous overload conditions must be tolerated.
APPLICATIONS INFORMATIONWU UU 16-Lead Plastic TSSOP (4.4mm) (Reference LTC DWG # 05-08-1663, Exposed Pad Variation BB) FE16 TSSOP 1101 0.105 – 0.180 (.0041 – .0071) 0° – 8° 0.50 – 0.70 (.020 – .028) 4.30 – 4.48* (.169 – .176) 6.25 – 6.50 (.246 – .256) 3.0 (.118) 13 4 5 6 7 8 10 9 4.95 – 5.05* (.196 – .204) 3.8 (.149) 16 1514 13 12 11 1.15 (.0453) MAX 0.05 – 0.15 (.002 – .006) 0.65 (.0256) BSC 0.195 – 0.30 (.0077 – .0118) MILLIMETERS (INCHES) DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.150mm (.006") PER SIDE NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS 2. DIMENSIONS ARE IN RECOMMENDED SOLDER PAD 3. DRAWING NOT TO SCALE EXPOSED PAD HEAT SINK ON BOTTOM OF PACKAGE 0.45 –0.05
0.65 BSC
4.50 –0.10 6.60 –0.10 1.05 –0.10
(LTC DWG # 05-08-1462) R (DD7) 0396 0.026 – 0.036 (0.660 – 0.914) 0.143 +0.012 –0.020 ()3.632 +0.305 –0.508 0.040 – 0.060 (0.330 – 0.584) 0.095 – 0.115 (2.413 – 2.921) 0.004 +0.008 –0.004 ()0.102 +0.203 –0.102 0.050 – 0.012 (1.270 – 0.305) 0.059 (1.499) TYP 0.045 – 0.055 (1.143 – 1.397) 0.165 – 0.180 (4.191 – 4.572) 0.330 – 0.370 (8.382 – 9.398) 0.060 (1.524) TYP 0.390 – 0.415 (9.906 – 10.541) 15° TYP 0.300 (7.620) 0.075 (1.905) 0.183 (4.648) 0.060 (1.524) 0.060 (1.524) 0.256 (6.502) BOTTOM VIEW OF DD PAK HATCHED AREA IS SOLDER PLATED COPPER HEAT SINK
8-Lead Plastic Small Outline (Narrow 0.150) (LTC DWG # 05-08-1610) 1 2 3 4 0.150 – 0.157** (3.810 – 3.988) 8 7 6 5 0.189 – 0.197* (4.801 – 5.004) 0.228 – 0.244 (5.791 – 6.197) 0.016 – 0.050 0.406 – 1.270 0.010 – 0.020 0°– 8° TYP 0.008 – 0.010 (0.203 – 0.254) SO8 0996 0.053 – 0.069 (1.346 – 1.752) 0.014 – 0.019 (0.355 – 0.483) 0.004 – 0.010 (0.101 – 0.254) 0.050 (1.270) TYP DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE PACKAGE DESCRIPTIONU
7-Lead Plastic TO-220 (Standard) (LTC DWG # 05-08-1422) 0.040 – 0.060 (1.016 – 1.524) 0.026 – 0.036 (0.660 – 0.914) T7 (TO-220) (FORMED) 1197 0.135 – 0.165 (3.429 – 4.191) 0.700 – 0.728 (17.780 – 18.491) 0.045 – 0.055 (1.143 – 1.397) 0.165 – 0.180 (4.191 – 4.572) 0.095 – 0.115 (2.413 – 2.921) 0.013 – 0.023 (0.330 – 0.584) 0.620 (15.75) TYP 0.155 – 0.195 (3.937 – 4.953) 0.152 – 0.202 (6.604 – 8.128) 0.147 – 0.155 (3.734 – 3.937) DIA 0.390 – 0.415 (9.906 – 10.541) 0.330 – 0.370 (8.382 – 9.398) 0.460 – 0.500 (11.684 – 12.700) 0.570 – 0.620 (14.478 – 15.748) 0.230 – 0.270 (5.842 – 6.858) Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
Burst Mode is a registered trademark of Linear Technology Corporation.
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Figure 17. Dual Output SEPIC Converter energy is stored in L1A only, since no current flows in L1B.