STB36NM60N_V01 STMICROELECTRONICS | Alldatasheet

Document overview

  • Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
  • PDF pages: 15

Technical content

Datasheet sections

  • 1 Electrical ratings
  • 2 Electrical characteristics
  • 2.1 Electrical characteristics (curves)
  • 3 Test circuits
  • 4 Package information
  • 5 Packing information
  • 6 Revision history

Features

  • Designed for automotive applications and AEC-Q101 qualified
  • 100% avalanche tested
  • Low input capacitance and gate charge
  • Low gate input resistance

Applications

  • Switching applications

Description

This device is an N-channel Power MOSFET developed using the second generation of MDmesh™ technology. This revolutionary Power MOSFET associates a vertical structure to the company’s strip layout to yield one of the world’s lowest on-resistance and gate charge. It is therefore suitable for the most demanding high efficiency converters. D PAK2 TAB $0Y 7$% Order code VDS @ TJmax RDS(on) max. ID PTOT STB36NM60N 650 V 0.105 Ω 29 A 210 W Table 1. Device summary

1 Electrical ratings

Table 2. Absolute maximum ratings

  1. Pulse width limited by safe operating area.
  2. I SD ≤ 29 A, di/dt ≤ 400 A/µs, VDS peak ≤ V(BR)DSS, VDD = 80% V(BR)DSS

Table 3. Thermal data

  1. When mounted on FR-4 board of 1inch², 2oz Cu, t < 10 sec

2 Electrical characteristics

Table 4. On /off states Table 5. Dynamic

  1. C oss eq. is defined as a constant equivalent capacitance giving the same charging time as C oss when VDS

Table 6. Switching times Table 7. Source drain diode

  1. Pulse width limited by safe operating area
  2. Pulsed: pulse duration = 300µs, duty cycle 1.5%

2.1 Electrical characteristics (curves)

Figure 2. Safe operating area Figure 3. Thermal impedance Figure 4. Output characteristics Figure 5. Transfer characteristics Figure 6. Gate charge vs gate-source voltage Figure 7. Static drain-source on-resistance

3 Test circuits

Figure 14. Switching times test circuit for Figure 15. Gate charge test circuit Figure 16. Test circuit for inductive load Figure 17. Unclamped inductive load test circuit Figure 18. Unclamped inductive waveform Figure 19. Switching time waveform

4 Package information

specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 20. D²PAK (TO-263) type A package outline

Table 8. D²PAK (TO-263) type A mechanical data

Figure 21. D²PAK recommended footprint(a)

5 Packing information

Figure 22. Tape

Figure 23. Reel Table 9. D²PAK (TO-263) tape and reel mechanical data

6 Revision history

Table 10. Document revision history 16-Nov-2009 1 First release. 22-Jun-2011 2 Document status promoted from preliminary data to datasheet. 10-May-2012 3 Figure 6: Gate charge vs gate-source voltage has been modified. – Updated Section 4: Package information.