34921 FREESCALE | Alldatasheet
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Technical content
Features
Two Functionally Identical Pulse-Width Modulated (PWM) DC Motor Drivers One Switching, One Linear, and One Dual-Mode Regulator Dual Mode Switching/Linear 5.0 V Regulator Supervisory Functions (Power-ON Reset and Error Reset Circuitry) 8-Channel, 8-Bit Analog-to-Digital Converter (ADC) Charge Pump for High-Side MOSFET Drive Complete Support for Analog Quadrature Encoder Pb-Free package is designated by suffix AE Figure 1. 34921 Simplified Application Diagram
ORDERING INFORMATION
Range (TA) Package MC34921AE/R2 0°C to 70°C 64 LQFP-EP AE SUFFIX (Pb-Free) 98ARH98426A 64-LEAD LQFP-EP B+B+ 34921 GATEOUT 5.0 V 3.3 V VCORE Serial Ports A/D Inputs SA/CDCMA SB/LSOUT1 SA/CDCMB SB/LSOUT2 MCU 5.0 V / 3.3 V High-Side MOSFET B A A B Step Motor B+MISO MOSI SCLK CE CPWMA CPWMB DC Motor ADCMA ADCMB APWM DC Motor BDCMA BDCMB BPWM DGND GND AN0 AN3 A B C
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Figure 2. 34921 Simplified Internal Block Diagram
5 V SUPPLY
5 V SWITCH
5 V SELECT
3.3 V SWITCH
3.3 V Switching
Figure 3. Terminal Function Description Table 1. Terminal Function Description
2 VCORE SELECT Core Voltage Output
Core voltage regulator output voltage select. Step Motor Output A or DC Motor C Output A. Step Motor Output A or DC Motor C Output B. Step Motor Output B or Low-Side Output 1. Step Motor Output B or Low-Side Output 2. B+ Power Supply Input Motor and regulator input voltage. NC No Connect No internal connection to this terminal.
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3.3 V regulator switching output. Feedback terminal for 3.3 V switching regulator and internal logic supply.
12 VCORE SUPPLY Core Voltage
Core regulator input supply.
13 VCORE Core Voltage
Core regulator output voltage. 14, 15 ADCMA DC Motor A Output A DC motor driver A output A. 18, 19 ADCMB DC Motor A Output B DC motor driver A output B. 22 VBOOST Boost Voltage Boost voltage storage node. 23 CP2 Switching Capacitor 2 Charge pump capacitor connection 2. 26 CP1 Switching Capacitor 1 Charge pump capacitor connection 1.
27 GATEOUT High-Side MOSFET
Gate driver for external N-channel switch. 30, 31 BDCMB DC Motor B Output B DC motor driver B output B. 34, 35 BDCMA DC Motor B Output A DC motor driver B output A. 5.0 V regulator operating mode select. 5.0 V switching regulator switching output. 5.0 V regulator input voltage. 42 AN0/ANALOGOUT_A AN0/Analogout_A A/D input 0 or analog encoder output A. 43 AN1/ANALOGOUT_B AN1/Analogout_B A/D input 1 or analog encoder output B. 44 AN2/ANALOGIN_A AN2/Analogin_A A/D input 2 or analog encoder input A. 45 AN3/ANALOGIN_B AN3/Analogin_B A/D input 3 or analog encoder input B.
46 ENC_FILTB Analog Encoder
I/V amplifier channel B filter.
47 ENC_FILTA Analog Encoder
I/V amplifier channel A filter. 50 RST Reset Reset input and output. 51 MISO Master In Slave Out Serial data out to MCU. 52 MOSI Master Out Slave In Serial data in from MCU. 53 SCLK Serial Clock Serial data clock. Table 1. Terminal Function Description (continued)
54 CE Chip Enable Serial data strobe.
55 CPWMA/CDCPWM Motor Driver C PWM
Step motor driver Phase A PWM or DC motor driver PWM. 56 DGND Digital Ground Digital ground.
58 CPWMB Motor Driver C PWM
Step motor driver Phase B PWM.
59 APWM Motor Driver A PWM
PWM input for DC motor driver A.
60 BPWM Motor Driver B PWM
PWM input for DC motor driver B.
61 CDCMB/HSOUT2 Motor Driver C DC
Step motor driver C output or high-side output 2.
63 CDCMA/HSOUT1 Motor Driver C DC
Step motor driver C output or high-side output 1.
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Table 2. Maximum Ratings permanent damage to the device.
5.0 V Linear Regulator Maximum Output Voltage
5.0 V Switching Regulator Maximum Output Voltage
3.3 V Switching Regulator Maximum Output Voltage
- B+ = 34 V, Motor Stalled and Saturated
- ESD testing is performed in accord ance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω), the Machine Model (CZAP = 200
pF, RZAP = 0 Ω), and the Charge Device Model.
- 1s PCB test board JESD51-2 and SEMI G38-87.
- Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured at the package
center lead foot. 2s2p test board, exposed pad soldered to PCB.
- Terminal soldering temperature limit is for 10 seconds maxi mum duration. Not designed for immersion soldering. Exceeding these limits
may cause malfunction or permanent damage to the device.
- Maximum power dissipation at indicated ambient temperature in free air with no heatsink used.
Table 2. Maximum Ratings(continued) permanent damage to the device.
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Table 3. Static Electrical Characteristics Characteristics noted under conditions 16 V ≤ B+ ≤ 34 V, 0°C ≤ TA ≤ 70°C, and 0°C ≤ TJ ≤ 100°C unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
5.0 V Linear Regulator
- See Figure 10, Power-Up Sequencing, page 22.
5.0 V Switching Regulator
3.3 V Switching Regulator
- See Figure 10, Power-Up Sequencing, page 22.
Table 3. Static Electrical Characteristics (continued) Characteristics noted under conditions 16 V ≤ B+ ≤ 34 V, 0°C ≤ TA ≤ 70°C, and 0°C ≤ TJ ≤ 100°C unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
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- Motor driver A, B, C Top Side only. For C Bottom Side, see Motor Driver C in Step Mode: Current Limit Maximum Duty Cycle and Current
Characteristics noted under conditions 16 V ≤ B+ ≤ 34 V, 0°C ≤ TA ≤ 70°C, and 0°C ≤ TJ ≤ 100°C unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
- If any of these conditions for this not is true, then RST is activated until all operating conditions are met.
- The RST terminal uses an external pull-up, which may be to 5.0 V or 3.3 V.
- Alternately, the minimum B+ fault threshold voltage must not be lower than 12 V, and the B+ fault clear voltage must not be h igher than
15.25 V. The hysteresis may be greater than 2.0 V if this requirement is met. Characteristics noted under conditions 16 V ≤ B+ ≤ 34 V, 0°C ≤ TA ≤ 70°C, and 0°C ≤ TJ ≤ 100°C unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
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- Errors include effects of multiplexer and sample and hold circuitry, including droop.
- The Linearity Error is the worst case error caus ed by the differential and integral nonlinearity.
- An LSB (least significant bi t) is defined as follows:
- The ADC will read full scale at V IN = 5.0 V. If VIN on one input exceeds this value, the value of other inputs may become unreadable.
Characteristics noted under conditions 16 V ≤ B+ ≤ 34 V, 0°C ≤ TA ≤ 70°C, and 0°C ≤ TJ ≤ 100°C unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted. IMR is the Ideal Measurement Range. #BITS is the resolution of the ADC.
- Errors include effects of multiplexer and sample and hold circuitry, including droop.
- The Zero Error is defined as the number of LSB values away from the ideal value of 1/2 LSB that the ADC output count will transition
from 0 to 1 when the input is swept through the range of interest. The transition must occur within the specified range.
- An LSB is defined as follows:
- The Full Scale Error is defined as the num ber of LSB values away from the ideal value of -1/2 LSB from Full Scale that the ADC output
count actually transitions from -1 LSB count to Full Scale count when the input voltage is swept through the voltage range of interest. The transition must occur within the specified range. Characteristics noted under conditions 16 V ≤ B+ ≤ 34 V, 0°C ≤ TA ≤ 70°C, and 0°C ≤ TJ ≤ 100°C unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted. IMR is the Ideal Measurement Range. #BITS is the resolution of the ADC.
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Table 4. Dynamic Electrical Characteristics Characteristics noted under conditions 16 V ≤ B+ ≤ 34 V, 0°C ≤ TA ≤ 70°C, and 0°C ≤ TJ ≤ 100°C unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
- See Figure 4, Serial Interface Timing, page 16.
- This parameter is guaranteed by design but not production tested.
- See Figure 6, RST Timing, page 17.
Table 4. Dynamic Electrical Characteristics (continued) Characteristics noted under conditions 16 V ≤ B+ ≤ 34 V, 0°C ≤ TA ≤ 70°C, and 0°C ≤ TJ ≤ 100°C unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
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Figure 4. Serial Interface Timing Figure 5. Step Motor Crossover Delay Timing
Figure 6. RST Timing
Analog Integrated Circuit Device Data
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The serial interface of the MC34921 is a three input, one output interface similar to a Serial Peripheral Interface (SPI) port in general form, but different in specific clocking requirements due to the fact that an A/D converter cannot reliably run without a continuous clock. The 34921 serial interface communicates to a microcontroller unit (MCU) at up to 16 MHz. The serial signals are SCLK, CE, MOSI, and MISO. The SCLK signal pin requires a free-running clock (up to 16 MHz) which is provided by the MCU. This signal is required to ensure proper operation of both the ADC and the reset timer circuitry. The serial data transfers between the MCU and the 34921 via the MOSI and MISO terminals. The serial data from the MCU is handled in the MC34921 via two input registers -- the NORMAL input register contains bits controlling the motor drivers as well as the A/D converter, and the CONFIG register contains bits relating to the general configuration setup of the device. The MC34921 also has two output registers -- the NORMAL output register reports A/D conversion data as well as digital encoder data, and the IREQ output register reports under voltage, temperature, and other device status data. FUNCTIONAL TERMINAL DESCRIPTION GROUND (GND) Main ground. It is used for the B+ filters and motor filter grounds, as well as the ground return for external components which are used with the linear and switching regulators. COVER VOLTAGE OUTPUT SELECT (VCORE SELECT) This terminal is used to select the output voltage provided by the VCORE linear regulator. The VCORE Select potential is latched in during the MC34921's power-on sequence. The MC34921 will not respond to changes in VCORE Select after power up. UNIPOLAR STEP A/DC MOTOR C OUTPUT A (S A/ CDCMA) A low-side driver output is configurable for either stepper motor control (SA) or C DC motor (as CDCMA, which requires an external hardwire to pin 63) via the serial I/O. The driver is PWM controlled via the CPWMA/CDCPWM pin, and direction controlled via the Serial I/O. It includes an active voltage clamp, current limit, and thermal shutdown protection. UNIPOLAR STEP A/DC MOTOR C OUTPUT B (SA/ CDCMB) A low-side driver output is configurable for either stepper motor control (SA) or C DC motor (as CDCMB, it requires external hardwire to pin 61) via the serial I/O. The driver is PWM controlled via the CPWMA/CDCPWM pin, and direction controlled via the Serial I/O. It includes active voltage clamp, current limit, and thermal shutdown protection. UNIPOLAR STEP B/LOW-SIDE 1 (SB/LSOUT1) A low-side driver output is configurable for either stepper motor control (SB) or as a general purpose low-side driver (LSOUT1) via the serial I/O. The SB is PWM controlled via the CPWMB pin. The direction and LSOUT1 are controlled via the serial I/O. It includes active voltage clamp, current limit and thermal shutdown protection. UNIPOLAR STEP B/LOW-SIDE 2 (SB/LSOUT2) A low-side driver output is configurable for either stepper motor control (SB) or as a general purpose low-side driver (LSOUT2) via the serial I/O. The SB is PWM controlled via the CPWMB pin. The direction and LSOUT2 are controlled via the serial I/O. It includes active voltage clamp, current limit and thermal shutdown protection. POWER SUPPLY INPUT (B+) This is the main power supply input for the regulators and DC motor drivers.
3.3 V SWITCHING REGULATOR SWITCH OUTPUT
(3.3 V SWITCH) The high-side driver output is used for the 3.3v switching regulator. It uses the internal 200KHZ clock. 3.3 V REGULATOR FEEDBACK (3.3 V) This terminal is the error amp feedback for the 3.3v switching regulator. It is also the output point for the 3.3v switching supply. CORE VOLTAGE REGULATOR INPUT (VCORE SUPPLY) The input voltage terminal for the VCORE linear supply, which is usually provided by externally hardwiring the 3.3v switching regulator output. CORE VOLTAGE REGULATOR OUTPUT (VCORE) The output terminal of the VCORE linear regulator. Voltage options of 1.5v, 1.8v, or 2.5v are set by the potential of the VCORE Select pin at power up. It features current limit
Analog Integrated Circuit Device Data Freescale Semiconductor 19 34921 FUNCTIONAL DESCRIPTION FUNCTIONAL TERMINAL DESCRIPTION and thermal shutdown protection. It is typically used to supply a micro processor core or embedded DRAM. DC MOTOR A OUTPUT A (ADCMA) A high-side and low-side driver output terminal, which when combined with ADCMB forms the A H-bridge DC motor driver. The driver is PWM controlled via the APWM input, and direction controlled via the Serial I/O. It features current limit and thermal shutdown protection. DC MOTOR A OUTPUT B (ADCMB) A high-side and low-side driver output terminal, which when combined with ADCMA forms the A H-bridge DC motor driver. The driver is PWM controlled via the APWM input and direction controlled via the Serial I/O. It features current limit and thermal shutdown protection. BOOST VOLTAGE (VBOOST) This is the boost voltage storage node for the charge pump circuit. It provides the gate drive voltage for the high-side FETS in the DC motor drivers, switch mode controllers, and Gateout pin. SWTICHING CAPACITOR (CP1 AND CP2) These are the connections for the charge pump flying capacitor. HIGH-SIDE MOSFET GATE DRIVER (GATEOUT) The output terminal for an external N-channel high-side driver. Enabled via the Serial I/O, it provides gate drive control for an external N-channel MOSFET high-side switch. DC MOTOR B OUTPUT B (BDCMB) A high-side and low-side driver output terminal, which when combined with BDCMB, forms the B H-bridge DC motor driver. The drivers are PWM controlled via the BPWM input, and direction controlled via the Serial I/O. It features current limit and thermal shutdown protection. DC MOTOR B OUTPUT A (BDCMA) A high-side and low-side driver output terminal, which when combined with BDCMA, forms the B H-bridge DC motor driver. The drivers are PWM controlled via the BPWM input, and direction controlled via the Serial I/O. It features current limit and thermal shutdown protection.
5.0 V REGULATOR MODE SELECT (5 V SELECT)
This terminal is used to set the 5v regulator to operate in either linear or switching mode. Ground this terminal to operate in switching mode, or float to operate in linear mode.
5.0 V REGULATOR SWITCH OUTPUT (5 V SWITCH)
This terminal is the high-side driver output used for the 5v switching regulator. It uses the internal 200KHZ clock.
5.0 V REGULATOR INPUT SUPPLY (5 V SUPPLY)
The input voltage terminal for the 5v regulator. Limit it to 20v in linear mode. An additional series resistor is recommended to dissipate power off-chip.
5.0 V REGULATOR FEEDBACK (5 V)
This is the 5v feedback input terminal and output voltage point for the 5v regulator when in the switch configuration, and the output pin when tied to 5v SWITCH in linear configuration. It is also the power supply terminal for the MC34921AE on board logic. AN0/ANALOGOUT_A (AN0/ANALOGOUT_A) Mux input 0 for the A/D converter, which is also available in Freescale test mode as an output for the AN2 I/V converter. AN1/ANALOGOUT_B (AN1/ANALOGOUT_B) Mux input 1 for the A/D converter, which is also available in Freescale test mode as an output for the AN3 I/V converter. AN2/ANALOGIN_A (AN2/ANALOGIN_A) Mux input 2 for the A/D converter incorporating an I/V converter with offset and gain calibration via the Serial I/O. AN3/ANALOGIN_B (AN3/ANALOGIN_B) Mux input 3 for the A/D converter incorporating an I/V converter with offset and gain calibration via the Serial I/O. ANALOG ENCODER CHANNEL B FILTER (ENC_FILTB) Input to the AN3 I/V converter stage for feedback components used with the I/V converter op amp. ANALOG ENCODER CHANNEL A FILTER (ENC_FILTA) Input to the AN2 I/V converter stage for feedback components used with the I/V converter op amp. RESET (RST) Supervisory function I/O, incorporating a comparator input and an open drain output, and typically connected to the RST of a microprocessor. As an input, RST resets internal registers to default states, turns step motor outputs off, forces DC motor drive low-side drives on, and sets MISO to a high Z state. As an output, RST is set during B+ UVLO, all regulators UVLO, current limit, and thermal shutdown events. MASTER IN SLAVE OUT (MISO) This is the master-in-slave-out terminal; the serial output port of the Serial I/O, which typically connects to the MISO of a microprocessor. MISO reports two data frames: NORMAL
Analog Integrated Circuit Device Data
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FUNCTIONAL TERMINAL DESCRIPTION - A/D conversion and analog encoder signals, and INFO - Fault data and analog encoder signals. The output data is loaded into the output shift register on each rising edge of SCLK, while CE is held in a logic high state. This means the MISO pin shows the status of the most significant bit (bit 15) of the output frame until the first rising edge of SCLK after the CE pin is taken to a logic low state. The shift register will then shift data out on the MISO pin on each subsequent rising edge of SCLK while CE is held in the logic low state. During transfers, the most significant bit (MSB) is transferred first. After all 16 bits have been transferred, if any additional clocks are given while CE is in a logic low state, the data is undefined and should be ignored. MASTER OUT SLAVE IN (MOSI) This is the master-out-slave-in terminal; the serial input port of the Serial I/O, which typically connects to the MOSI of a microprocessor. It has two frames of operation - NORMAL and CONFIG, which are set by a bit in the NORMAL frame.The MOSI pin is used for serial instruction data input. MOSI information is clocked into the input shift register on the rising edge of SCLK. A logic high state present on MOSI will program a register bit on. The specific bit will turn on with the 16th rising edge of SCLK after placing the CE pin in a logic low state. Conversely, a logic low state present on the MOSI pin will program the register bit off. The specific bit will turn off with the 16th rising edge of SCLK after placing the CE pin in a logic low state. For each rising edge of the SCLK while CE is logic low, a data bit instruction (on or off) is loaded into the shift register per the data bit MOSI state. The last bit clocked in (bit 0) is the CONFIG bit. If this bit is in a logic high state at the 16th rising edge of SCLK after lowering the CE pin, the bits in the shift register will be loaded into the CONFIG register. If the bit is in a low logic state, the bits will be loaded into the NORMAL register. Care should be taken to keep the MOSI pin in a logic low state when it is not being used for transfers to avoid erroneous data. During transfers, the most significant bit (MSB) is clocked in first. SERIAL CLOCK (SCLK) As the serial clock terminal, the SCLK pin clocks the internal shift registers of the MC34921. The serial data input (MOSI) pin data is latched into the input shift register on the rising edge of the 16th clock after the falling edge of the chip select (CE ) pin. The serial data output (MISO) pin shifts data out of the shift register on the rising edge of the SCLK signal. False clocking of the shift register must be avoided to ensure validity of data. It is essential that one rising edge of SCLK occur while CE is in a logic high state to ensure the correct output data is latched into the output shift register. Clocking the SCLK pin for more than one clock period while CE is in a logic high state is not recommended and may have undesired effects. For this reason, it is recommended that the SCLK pin be clocked only once while CE is in a logic high state. The MC34921 is designed such that SCLK should be a continuous clock. This ensures that A/D sample rates are held as constant as possible. CHIP ENABLE (CE) The chip enable port of the Serial I/O, typically connects to the CE of a microprocessor. The logic state of the CE pin activates clocking in and shifting out of data in and out of the MC34921. While the CE pin is in the logic high state, the output data in the NORMAL registers and the INFO registers are latched (depending on the state of the IREQ bit in the previous communication frame) in on each rising edge of the clock such that the state of the MSB (bit 15) is readable on the serial data output (MISO) pin. When CE is in a low logic state both the input shift register and output shift register shift data at the rising edge of SCLK. MOTOR DRIVER C PWM INPUT A (CPWMA / CDCPWM) This is the PWM logic input for the SA/SA/CDCM motor drivers. The motor driver outputs follow this signal. MOTOR DRIVER C PWM INPUT B (CPWMB) This is the PWM logic input for the SB/SB motor drivers. The motor driver outputs follow this signal. DIGITAL GROUND (DGND) This terminal is used for the Serial I/O and A/D converter logic grounds, and should be kept isolated from the Analog ground on the application PCB. MOTOR DRIVER A PWM INPUT (APWM) The PWM logic input terminal for the ADCM motor drivers. The motor driver outputs follow this signal. MOTOR DRIVER B PWM INPUT (BPWM) The PWM logic input terminal for the BDCM motor drivers. The motor driver outputs follow this signal. MOTOR DRIVER C STEP MOTOR OUTPUT OR HIGH-SIDE OUTPUT 2 (CDCMB / HSOUT2) The high-side driver output is configurable for either C DC motor control (as CDCMB, it requires external hardwire to pin 4), or as a general purpose high-side driver (HSOUT2) via the serial I/O. The CDCMB is PWM controlled via the CPWMA/ CDCPWM pin. The direction and HSOUT2 are controlled via the serial I/O. It includes current limit and thermal shutdown protection. MOTOR DRIVER C STEP MOTOR OUTPUT OR HIGH-SIDE OUTPUT 1 (CDCMA / HSOUT1) The high-side driver output is configurable for either C DC motor control (as CDCMA, it requires external hardwire to pin 4), or as a general purpose high-side driver (HSOUT1) via the serial I/O. The CDCMA is PWM controlled via the CPWMA/ CDCPWM pin. The direction and HSOUT1 are controlled via the serial I/O. It includes current limit and thermal shutdown protection.
Figure 7. Internal Block Diagram Figure 8. 5.0 V Switching Regulator Mode Figure 9. 5.0 V Linear Regulator Mode switching noise on this terminal. switching regulator. Each has cycle-by-cycle current limiting.
5.0 V Regulator
3.3 V Regulator
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regulators is controlled such that -1.0v <= V5 - V3.3 <= 2.6v. Figure 10. Power-Up Sequencing the 3.3 V supply is in stable operation. cannot supply enough current for a particular application. for under-voltage monitoring. included when the system is in DC motor mode (LSOUTx). failure, the driver will default to a safe condition. motor drivers also have thermal shutdown protection. bit 13 determines the mode: 0 = step mode, 1 = DC mode.
5.0 V Reg ON
3.3 V Reg OFF
5.0 V Fault
3.3 V Start
3.3 V Reg ON
3.3 V ≥ Positive
3.3 V ≠ Positive
Table 5. VCORE Regulator Output Voltage Select
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externally applied RST signal. Figure 12. RST Terminal Interface regardless of whether the tdelay count has been completed. and tfilter), where tfilter is the 1.5 µs to 5.0 µs delay. upon an externally generated reset. Table 6. Regulator Shutdown Schedule of analog output small optical encoder modules.
- XDCMA and XDCMB: 0 means low-side ON, 1 means high-side ON, Z means both OFF.
responsibility to validate their application. Figure 13. Analog Encoder Interface Block Diagram current trim and force the proper bias point on the encoder. signal, the feedback resistor needs to be 50 kΩ. transimpedance amplifier is 2.5 V. current of up to ±8.0 µA in the encoder output. variations in the encoder, as well as aging and other effects. The gain can be changed over the serial interface at any time. the ANALOGOUT_x terminals for engineering evaluation. Otherwise, these terminals are general purpose A/D inputs. Table 7, page 26, for more information. offset calibration values for both channels.
34921 IC that uses the on-board voltage reference and
derives all the necessary timing signals from the SCLK input.
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frame (refer to Table 11, page 28). inputs AN0/ANALOGOUT_A or AN1/ANALOGOUT_B. the analog encoder interface, DENCA and DENCB. Table 7. A/D Input Conversion Channel Addressing completes during the frame prior to the data being returned.
- DENCA and DENCB values are captured at the output of the 3 or 6 Edge filter on SCLK rising edge, then immediately
shifted out in the MISO data when CE is high.
- Inputs are listed in order of conversion.
H components are such that a time constant is about 93.6 ns. Figure 14. A/D Converter Input Structure Note Start is bit 1 of the serial input normal frame. Table 8. A/D Done Bits
0 Rising Valid for second conversion
Table 9. A/D Channel of Current A/D Data
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Normal mode is the normal operating mode of the IC (as opposed to the Configuration mode or Information Request mode). Table 10. NORMAL Mode Input Frame Programming Model Table 11. NORMAL Input Frame Bit Allocation (29) page 31 and page 32, respectively, for operation. or 11. Refer to Table 19 Truth Table, page 31, for operation. or 11. Refer to Table 19 Truth Table, page 31, for operation. or 11. Refer to Table 19 Truth Table, page 31, for operation. 5 GATEOUT Assertion puts Vb on the GATEOUT terminal. Deassertion connects the GATEOUT terminal to ground. 42 A/Da[2:0] A/D conversion target channel. These bits determine which input(s) to the ADC are to be converted. and begin an analog-to-digital conversion. This bit is ignored if a conversion is already in progress. received. Bit 0 = 0 is a normal mode input frame.
- All defaults = 0 at power up.
- When in step motor mode, outputs are A, A, B, and B; when in DC motor mode, outputs B and B have no function.
interface (i.e., MOSI, MISO, SCLK, CE). Table 12. CONFIG Mode Input Frame Programming Model Table 13. CONFIG Input Frame Bit Allocation (32) Table 14. Calibration Register Addressing 1514 Mtest[1:0] Reserved for Freescale test. Set to [10]. 139 cal[4:0] Data for various calibration registers.
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development and verification. Do not use in normal operation. signals made available to the serial output frame. maintains A/D conversion accuracy. 2 sleep When asserted, causes the 34921 to enter a power-down state, and minimize power consumption. 1 IREQ Causes the next output frame sent to the host to contain internal information from the 34921. received. Bit 0 = 1 is a configuration mode input frame.
- All defaults = 0 at power up.
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Table 15. NORMAL Mode Output Frame Programming Model Table 16. NORMAL Mode Output Frame Bit Allocation Model NFO (IREQ) Mode is the mode in which the MC34921 IC reports status and error information via the serial interface. Table 17. NFO (IREQ) Mode Output Frame Programming Model I Table 18. INFO (IREQ) Mode Output Frame Bit Allocation 158 A/Dd[7:0] ADC data from last conversion. bit (Bit 1) in the Configuration mode input frame. 64 A/Dr[2:0] Report the input to the ADC that is represented in the A/Dd[7:0] (Bits 158). Analog encoder interface digital signals. These signals are used to drive a quadrature encoder on the MCU. 1510 Reserved These bits will report [011000]. 9 EXT This flag will report if the last generated reset was due to an external signal driving RST. operate, this flag will be asserted. bit (Bit 1) in the Configuration mode input frame. causes the voltage to droop. Analog encoder interface digital signals. These signals are used to drive a quadrature encoder on the MCU. occurs when the junction temperature reaches approximately 140ºC.
For inputs, ILIMIT = 0 means TSD, ILIMIT condition not encountered. ILIMIT = 1 means TSD, ILIMIT condition encountered. For outputs XDCMA and XDCMB, 0 means low-side ON, 1 means high-side ON, Z means both OFF. Table 19. DC Motors Truth Table Table 20. Low-Side Out (LSOUT) Drivers Truth Table (Motor Driver Configured for H-bridge DC Motor) Note The LSOUT terminals are controlled by the OUT1 and OUT2 signals (Bit 14 and Bit 15 in the NORMAL input frame).
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Table 21. High-Side Out (HSOUT) Drivers Truth Table (Motor Driver Configured for H-bridge DC Motor) Note: The HSOUT terminals are controlled by the OUT1 and OUT2 signals (Bit 14 and Bit 15 in the NORMAL input frame). Table 22. Step Motor Driver Truth Table (33)
- To reduce parasitic dissipation associat ed with the body diode, the counterphase is turned on for synchronous rectification.
- The current limit sense function may be disabled when the output s are disabled. Hence, the output will oscillate between the requested
state from the Truth Table and this state.
Figure 15. TYPICAL APPLICATION DIAGRAM
385 V SUPPLY
375 V SWITCH
365 V SELECT
Analog Integrated Circuit Device Data
34 Freescale Semiconductor
For the most current revision of the package, visit www.freescale.com and do a keyword search using the 98A number for the specific device related to the data sheet. NOTES: DIMENSIONS ARE IN INCHES. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. DATUMS A, B AND D TO BE DETERMINED AT SEATING PLANE C. DIMENSIONS D AND E TO BE DETERMINED AT SEATING PLANE C. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED THE MAXIMUM b DIMENSION BY MORE THAN 0.08 mm. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD OR PROTRUSION 0.07 mm. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 mm PER SIDE. D1 AND E1 ARE MAXIMUM PLASTIC BODY SIZED DIMENSIONS INCLUDING MOLD MISMATCH. EXACT SHAPE OF EACH CORNER IS OPTIONAL. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10 mm AND 0.25 mm FROM THE LEAD TIP.
0.2 H A-B D
B E/2 EE1 D/2 D D1/2 VIEW Y 4X 4X 16 TIPS
0.2 C A-B D
A D PIN 1 IDENTIFIER AB AB e/2 e60X X=A, B OR D CL VIEW Y X S0.05 0.25 GAGE PLANE (S) R (L1) LA1 VIEW AA Z Z24X SEATING PLANE A VIEW AA 0.08 C Z34X C H A-BM0.08 D C 64X b JJ SECTION AB-AB ROTATED 90˚ CLOCKWISE b c1c PLATING BASE METAL MILLIMETERS
12.00 BSC
10.00 BSC
0.50 BSC
1.00 REF
A b c D e E L S F G Z MIN --- 0.05 1.35 0.17 0.17 0.09 0.09 0.45 6.00 0.20 6.00 0.08 0.08 11˚ 11˚ MAX 1.60 0.15 1.45 0.27 0.23 0.20 0.16 0.75 7.00 --- --- 7.00 --- --- 13˚ 13˚ G F VIEW J-J EXPOSED PAD AE SUFFIX (Pb-Free) 64-TERMINAL LQFP EXPOSED PAD PLASTIC PACKAGE 98ARH98426A ISSUE 0
Analog Integrated Circuit Device Data Freescale Semiconductor 35 34921 PACKAGE DIMENSIONS NOTES
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