34920

34920 FREESCALE | Alldatasheet

Document overview

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• PDF pages: 29

Technical content

Features

• Individual Thermal Limit Protection
• User-Selectable Motors: 2 DC Moto rs (2.4 A / Motor), 2 Step Motors (W1-2 Phase Control), 1 DC Motor and 1 Step Motor
• 2 Buck Regulators (Switching @ 200 kHz)
• V V2 Output Voltage Is Programmable to 10 V to 15 V DC (Externally Set)
• Low-Voltage Detection Reset (V V1 and VVB+)
• Pb-Free Packaging Designated by Suffix Code EI

Figure 1. 34920 Simplified Application Diagram

ORDERING INFORMATION

Range (TA) Package MC34920FN/R2 -40°C to 125°C 44 PLCC MC34920EI/R2 + + DC MOTOR DC MOTOR 34920 MCU VVB+ VV2VV1 DR1A DR2A DR1B DR2BCP1 CP2 DR2PWM SDI DR1PWM SCLK V2_FB V1_FB VB+ V1_SWITCH V2_SWITCH RESET CS VB VVB+ GND

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Figure 2. 34920 Simplified Internal Block Diagram

Figure 3. 34920 Pin Connections Table 1. 34920 Pin Definitions 1 VB Output pin to VVb Pin to connect to VVb capacitor. 2 CP2 Capacitor to CP1 Pin for boost generator switch capacitor. 3 CP1 Capacitor to CP2 Pin for boost generator switch capacitor. 4 RESET Reset Output Active low Reset output. 5.0 V ±5% for its logic voltage. GND Substrate Ground Ground connections for digital IC circuitry. 8 V1_FB V1 Regulator Feedback Input Voltage feedback for the V1 regulator. 9 DR1_MODE Mode Select for Driver 1 Selects operational mode of Driver 1; Step = 1 / DC = 0.

10 V1_SWITCH Internal MOSFET Source for V1

Switching output for V1 regulator. VB+ VB+ (Bulk) Supply Voltage High-voltage supply for motors and regulators. 12 DR2A1 Driver 2, Bridge 1, Output A Motor driver output. 13 DR2SENSE1 Driver 2, Bridge 1, I Sense Current sense for current mode. 14 DR2B1 Driver 2, Bridge 1, Output B Motor driver output. 19 DR1A1 Driver 1, Bridge 1, Output A Motor driver output. 20 DR1SENSE1 Driver 1, Bridge 1, I Sense Current sense for current mode.

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21 DR1B1 Driver 1, Bridge 1, Output B Motor driver output. 22 DR1PWM Driver 1 PWM Input PWM input for Driver 1. Used only when DR1_MODE pin = 0. 24 DR2PWM Driver 2 PWM Input PWM input for Driver 2. Used only when DR2_MODE pin = 0. 25 DR1B2 Driver 1, Bridge 2, Output B Motor driver output. 26 DR1SENSE2 Driver 1, Bridge 2, I Sense Current sense for current mode. 27 DR1A2 Driver 1, Bridge 2, Output A Motor driver output. 32 DR2B2 Driver 2, Bridge 2, Output B Motor driver output. 33 DR2SENSE2 Driver 2, Bridge 2, I Sense Current sense for current mode. 34 DR2A2 Driver 2, Bridge 2, Output A Motor driver output.

36 V2_SWITCH Internal MOSFET Source for V2

Switching output for V2 regulator. 37 DR2_MODE Mode Select for Driver 2 Selects operational mode of Driver 2. Step = 1 / DC = 0. 38 V2_FB V2 Regulator Feedback Input Switch output for V2 regulator. 41 SDI Serial Port Data Input Serial input register serial data input. 42 SCLK Serial Data Port Clock Serial input register clock. 43 CS Serial Data Port Chip Select Serial input register chip select input. Active low. 44 AGND Analog Ground Ground connection for analog circuitry. Table 1. 34920 Pin Definitions (continued)

Analog Integrated Circuit Device Data Freescale Semiconductor 5 34920

ELECTRICAL CHARACTERISTICS

Table 2. Maximum Ratings permanent damage to the device.

1. RESET is an open drain (open collector) output with an internal pull-up resistor.
2. ESD testing is performed in accordance with the Human Body Model (HBM) (C ZAP = 100 pF, RZAP = 1500 Ω), the Machine Model (MM)

(CZAP = 200 pF, RZAP = 0 Ω), and the Charge Device Model (CDM), Robotic (CZAP = 4.0pF).

1. Maximum power dissipation at indicated ambient temperature in free air with no heatsink used.
2. Pin soldering temperature limit is for 10 seconds maximum dura tion. Not designed for immersion soldering. Exceeding these limits may

cause malfunction or permanent damage to the device.

1. R θJA is dependent on customer application and PCB layout.

Analog Integrated Circuit Device Data

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STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics

Analog Integrated Circuit Device Data Freescale Semiconductor 7 34920 STATIC ELECTRICAL CHARACTERISTICS Voltage Overshoot External VCC Load Current from 0.01 to 0.500 A, tRISE > 100 ns VOVRSHT – 5.0% – Load Ripple

0.5 A maximum

– 100 – mV VBOOST GENERATOR Charge Pump Output Voltage ILOAD = 1.0 mA VVB -VVB+ 10 – 14 V BIPOLAR CURRENT REGULATED STEP MOTOR DRIVE SYSTEM Peak Step Motor Current, Phase A or B Motor Not Stalled ISTEPMOTOR PEAK – – 0.6 A Maximum Allowable Voltage Drop Across Any H-Bridge Switch ILOAD = 0.6 A (from Output to GND) or ILOAD = 0.6 A (from VVB+ to Output) VDROP – – 1.6 V Comparator High Threshold Voltage CURR_I0_PHASEX=0, CURR_I1_PHASEX=0 VTH 450 550 650 mV Comparator Medium Threshold Voltage CURR_I0_PHASEX=1, CURR_I1_PHASEX=0 VTM 300 – 440 mV Comparator Low Threshold Voltage CURR_I0_PHASEX=0, CURR_I1_PHASEX=1 VTL 105 – 255 mV VOOFF Output Leakage Current for Step Motor Driver Outputs VOOFF = 5.0 V IOOFF -1.0 0.1 1.0 mA Step Motor Driver Thermal Shutdown Junction Temperature TJ (SHUTDOWN) 155 – 175 oC Step Motor Driver Thermal Enable Junction Temperature TJ (ENABLE) 135 – 155 oC Single MOSFET Typical Value @ TJ = 25°C RDS(ON) – 1.43 – Ω DC MOTOR DRIVE SYSTEM Maximum Allowable Voltage Drop Across Any H-Bridge Switch ILOAD = 0.75 A (from Output to GND) or ILOAD = 0.75 A (from VVB+ to Output) (Using 2 H-Bridges in Parallel) VDROP – – 1.3 V Peak DC Motor Driver Current Motor Not Stalled (Using 2 H-Bridges in Parallel) IDCMOTOR PEAK CURRENT – – 1.2 A DC Motor Overcurrent Threshold (7) Motor Stalled (Paralleled H-Bridges Used for DC Motor Drive) IDCMOTOROCT 1.6 2.0 2.5 A DC Motor Driver Sustaining Current Value Current Allowed to Sustain for a Minimum of 100 ms (OCT delay), Current Ripple 100 mA (Peak-to-Peak or Less) IDC_SUSTAIN 1.6 2.0 2.4 A Notes 7. Because the current clamp is applied to the top H-bridge transi stors only, overcurrent protection applies to motor currents. But note that no short circuit protection exists against shorts from the DC motor outputs (DR1A1, DR1A2, DR1B1, or DR1B2 to substrate ground or to VB+. Table 3. Static Electrical Characteristics (continued)

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STATIC ELECTRICAL CHARACTERISTICS Differential DC Motor Driver Output Voltage VVB++ Rising Monotonically from 0 V to 42 V (1.0 µs < tR < 10 ms) OR VVB+ Falling Monotonically from 42 V to 0 V (1.0 µs < tF < 10 ms) VDCMD – – 4.0 V DC Motor Driver Thermal Shutdown Output Voltage IOH = 0.1 V VOH_DCM VVB+ - 0.5 V – – V DC Motor Driver Thermal Shutdown Junction Temperature TJ (SHUTDOWN) 155 – 175 oC DC Motor Driver Thermal Enable Junction Temperature TJ (ENABLE) 135 – 155 oC Equivalent Resistance Using 2 H-Bridges in Parallel, Nom Value @ TJ = 25°C RDS(ON) – 0.73 – Ω RESET RESET High-State Output Voltage IOH = -0.1 mA VOH VCC - 0.5 V – – V RESET Low-State Output Voltage VV1_FB < VV1T+ VOL – – 0.2 V Input Low Voltage State VCC + 3.3 V ±10% VCC + 5.0 V ±5% VIL 0.8 1.5 V Input High-Voltage State VCC + 3.3 V ±10% VCC + 5.0 V ±5% VIH 2.1 3.3 V RESET VV1_FB Low Threshold Voltage at V1_FB VV1T- 1.9 2.08 2.2 V RESET VV1_FB High Threshold Voltage at V1_FB VV1T+ 2.05 2.23 2.35 V RESET VVB+ Low Threshold VB+ VVB+T- 13.5 15.4 16.5 V RESET VVB+ High Threshold VB+ VVB+T+ 13.5 16.6 20 V

Analog Integrated Circuit Device Data Freescale Semiconductor 9 34920 DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 4. Dynamic Electrical Characteristics

Analog Integrated Circuit Device Data

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DYNAMIC ELECTRICAL CHARACTERISTICS RESET RESET Delay VV1_FB ≥ VV1T+ tDELAY 15 33 50 ms VCC Out-of-Tolerance Persistence Time RESET De-Asserted, VV1_FB < VV1T- tPERSIST 10 20 30 µs RESET Rise Time 10% to 90% (8) tR – 630 750 ns RESET Fall Time 90% to 10% (8) tF – 11 50 ns Notes 8. Test circuit is 50 pF capacitor from RESET to GND.

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The 34920 is a multifunctional analog IC that can be used in printer and scanner applications. It integrates two switching voltage regulator circuits, four H-bridge drivers, and a reset circuit in a single IC. All 34920 control lines are compatible with CMOS type 3.3 V and 5.0 V logic. SWITCHING VOLTAGE REGULATOR CIRCUITS Two switching voltage regulators provide the following voltages from an unregulated input of 21 V to 42 V DC. Both are buck-type switching regulators using a MOSFET (internal to the 34920), current sense resistor (internal to the 34920), Schottky diode (external to the 34920), external inductor, and filter capacitor.

• V1 Voltage Regulator – This regulator is programmable, has a duty cycle of 37%, and provides either 3.3 V (+5%/-4%) or 5.0 V (+5% / -4%) at a current of 10 mA (minimum) to 500 mA (maximum).
• V2 Voltage Regulator – This regulator has a programmable output voltage (by means of an external resistor divider network) in the range of 10 V to 15 V ±2% with a VB+ supply voltage range of 21 V to 42 V. The V2 voltage regulator is controlled by an Enable bit in the serial register that allows software to turn this regulator on and off. However, the Enable bit does not effect the V1 voltage regulator. The Enable bit will disable the V2 voltage regulator and disable all motor driver circuits. MOTOR DRIVERS The two motor drivers can be selectable as either a bi- directional DC motor driver, with PWM control and peak currents of 2.4 A, or a bipolar step motor driver, with average current levels of 183 mA and 550 mA per phase, and quarter step mode capability. In step mode, both drivers are capable of being operated in the quarter step mode. RESET GENERATION The 34920 provides an output, RESET, that drives an external reset signal to the system microprocessor and / or the system digital logic IC. This signal is an active low logic level signal that is derived by monitoring the level of the VB+ and V1_FB pins. When RESET is asserted, either internally or from an external source, all 34920 motor driver outputs will be in their inactive states, and the serial input port will be loaded with the reset value. FUNCTIONAL INTERNAL BLOCK DESCRIPTION INPUT POWER SUPPLY (VVB+) The input voltage for the switching regulators and motor drivers. VVB+ has a voltage range of 21 V to 42 V. CMOS LOGIC LEVEL CMOS logic level specifications are described on page 6 of the Static Electrical Characteristics table.

34920 INPUT

Table 5, page 13, describes the 34920 input specifications. SERIAL INPUT PORT The 34920 provides a serial input port for bit depth of 13 bits of input. This port provides an interface between the 34920 and the digital controller IC. This port is write-only. The interface consists of three signal lines: chip select (CS, active low), serial clock (SCLK), and serial data input (SDI). The digital controller initiates a serial transfer by pulling low the chip select line (CS). It then generates 13 clock pulses on the SCLK pin while presenting the serial data on the serial data input (SDI). The 34920 presents the data on SDI one setup time (t DSU) before the rising edge of SCLK. The data is held constant for the data hold time (t DHD) beyond the SCLK rising edge. The data is shifted into the 34920 on the rising edge of SCLK. The least significant bit (LSB) is the first to be shifted out of the 34920 on the rising edge of SCLK, followed by the remaining bits to the last of the 13 bits, which is the most significant bit (MSB). The CS line is then returned to a high state. The low-to-high transition of CS will load the data into the internal 34920 input register, where all the inputs are presented to their appropriate functions in a parallel fashion. Note The minimum off-time (CS signal equal to logic [1]) for the CS signal needs to be at least 1.0 t DSU delay + 1.0 t DHD delay. This will provide the time for the 34920 to clear the serial input data register (transfer the serial data in parallel to internal latches that use the data) and thereby avoid a data overrun condition and loss of data. See the serial input port timing data in the Dynamic Electrical Characteristics table, page 9.

Table 5. 34920 Input Specifications V1_FB Voltage feedback for the V1 regulator. VCC VCC power input for internal use. The 34920 accepts either 3.3 V ±10% or 5.0 V ±5% for its logic voltage. V2_FB Voltage feedback for the V2 regulator. CS Serial input register chip select input. Active low. SCLK Serial input register clock. SDI Serial input register serial data input. DRxPWM PWM input for the DC motor driver for either Driver 1 or Driver 2. DRx_MODE Selects mode of each motor driver. Step = 1/ DC = 0. DR1_CURR_I1_PHASEA Second of two inputs that control the current level in the step motor Phase A winding (Driver 1 / Step Mode). DR1_CURR-I0_PHASEA First of two inputs that control the current level in the step motor Phase A winding (Driver 1 / Step Mode). conventional current flow from DR1A1 to DR1B1 (Driver 1 / Step Mode). DR1_CURR_I1_PHASEB Second of two inputs that control the current level in the step motor Phase B winding (Driver 1 / Step Mode). DR1_CURR_I0_PHASEB First of two inputs that control the current level in the step motor Phase B winding (Driver 1/ Step Mode). conventional current flow from DR1A2 to DR1B2 (Driver 1 / Step Mode). DR2_CURR_I1_PHASEA Second of two inputs that control the current level in the step motor Phase A winding (Driver 2 / Step Mode). DR2_CURR_I0_PHASEA One of two inputs that control the current level in the step motor Phase A winding (Driver 2 / Step Mode). conventional current flow from DR2A1 to DR2B1 (Driver 2 / Step Mode). DR2_CURR_I1_PHASEB Second of two inputs that control the current level in the step motor Phase B winding (Driver 2 / Step Mode). DR2_CURR_I0_PHASEB One of two inputs that control the current level in the step motor Phase B winding (Driver 2 / Step Mode). conventional current flow from DR2A2 to DR2B2 (Driver 2 / Step Mode).

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serial input port. These signals are listed in bit order from LSB (first bit to be shifted in) to MSB (last bit to be shifted in). Table 6. Serial Input Port Definition for Step / Step Mode 34920 in the minimum power consumption state. SDR2_DIR_PH_B 4 0 Controls the direction of the current flow through Phase B of the SDR2 step motor. SDR2_DIR_PH_A 7 0 Controls the direction of the current flow through Phase A of the SDR2 step motor. SDR1_DIR_PH_B 10 0 Controls the direction of the current flow through Phase B of the SDR1 step motor. SDR1_DIR_PH_A 13 0 Controls the direction of the current flow through Phase A of the SDR1 step motor.

Table 7. Serial Input Port Definition for DC Motor / DC Motor Mode (9) 34920 in the minimum power consumption state. Not Used 2 X Not used in this mode. Not Used 3 X Not used in this mode. Not Used 4 X Not used in this mode. Not Used 5 X Not used in this mode. Not Used 6 X Not used in this mode. Not Used 8 X Not used in this mode. Not Used 9 X Not used in this mode. Not Used 10 X Not used in this mode. Not Used 11 X Not used in this mode. Not Used 12 X Not used in this mode.

1. DR1_MODE and DR2_MODE pins = logic [0] for DC motor drive for both drivers.

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Table 8. Serial Input Port Definition for DR1 = Step / DR2 = DC Motor Mode 34920 in the minimum power consumption state. Not Used 2 X Not used in this mode. Not Used 3 X Not used in this mode. Not Used 4 X Not used in this mode. Not Used 5 X Not used in this mode. Not Used 6 X Not used in this mode. SDR1_DIR_PH_B 10 1 Controls the direction of the current flow through Phase B of the SDR1 step motor. SDR1_DIR_PH_A 13 1 Controls the direction of the current flow through Phase A of the SDR1 step motor.

the internal regulator reference voltages of 2.5 V ±2%. Table 9. Serial Input Port Definition for DR1 = DC Motor / DR2 = Step Mode 34920 in the minimum power consumption state. SDR2_DIR_PH_B 4 0 Controls the direction of the current flow through Phase B of the SDR2 step motor. SDR2_DIR_PH_A 7 0 Controls the direction of the current flow through Phase A of the SDR2 step motor. Not Used 8 X Not used in this mode. Not Used 9 X Not used in this mode. Not Used 10 X Not used in this mode. Not Used 11 X Not used in this mode. Not Used 12 X Not used in this mode.

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Figure 6. Voltage Regulator Functions regulator output voltages to be equal to 0 V. Output voltages VV1 and VV2 are short circuit protected. Table 10. Voltage Regulator Output Requirements

1. This voltage is programmable within a range of 10 V to 15 V via external resistors. The voltage tolerance around any set point is ±2%
2. Maximum peak duration is 400 ms.

Analog Integrated Circuit Device Data Freescale Semiconductor 19 34920 FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION values for V1 and V2 voltage regulators on page 6 of the Static Electrical Characteristics table. POWER-SAVING MODE OF OPERATION The V2 voltage regulator can be disabled via the serial interface by setting the V2_Enable bit (bit 1 – LSB) to a value of 0. This provides a reduction in the bias current provided by the V1 supply. V1 VOLTAGE REGULATOR Implementation of the V1 switching voltage regulator is accomplished through the use of an internal switch MOSFET, internal MOSFET current sense resistor, external Schottky diode, external inductor, and filter capacitor. The frequency of operation of this regulator is controlled by the internal clock, which is 200 kHz ±25 kHz. The duty cycle (on-time) for this internal regulator clock is a fixed 37.5%. This regulator switches out of phase from the V2 regulator to minimize ripple current on VB+. The line regulation range is 21 V < VVB+ < 42 V. The load side regulation is specified on page 6 of the Static Electrical Characteristics table. This converter is designed so that the current limit threshold is lowered during the power-on period to allow for a “softer” start-up, thereby reducing electrical stress in the external components. This limiting is required for their safe operation. The voltage is set externally with a resistor (1% tolerance) divider network. The V1_FB input voltage should be chosen, using external voltage divider resistors, so as to provide a regulator feedback voltage, for the required output regulated voltage, to equal the internal regulator reference voltage of 2.50 V ±2%. The V1 regulator is ideal for providing either 3.3 V or 5.0 V with a precision of +5% / -4%. Output current sensing is implemented by sensing the voltage across an internal sense resistor connected between VB+ and the drain of the internal MOSFET. Current is measured on a cycle-by-cycle basis. The purpose of this current sense is to prevent damage to the 34920 and its associated external components. V2 VOLTAGE REGULATOR The V2 switching voltage regulator is implemented as a buck regulator with an internal switch MOSFET, internal MOSFET current sense resistor, external Schottky diode, external inductor, and filter capacitor. The frequency of operation of this regulator is controlled by the internal clock, which is 200 kHz ±25 kHz. This regulator switches out of phase from the V1 regulator to minimize ripple current on VB+. This converter is designed so that the current limit threshold is lowered during the power-on period to allow for a “softer” start-up, thereby reducing electrical stress in the external components. This limiting is required for their safe operation. The output voltage is variable with ±2% precision, with a VVB+ supply voltage range of 21 V to 42 V. The exact voltage will be set externally with a resistor (1% tolerance) divider network. The V2_FB input voltage should be chosen, using external voltage divider resistors, so as to provide a regulator feedback voltage, for the required output regulated voltage, to equal the internal regulator reference voltages of 2.50 V ±2%. Output current sensing is implemented by sensing the voltage across an internal sense resistor connected between VB+ and the drain of the internal MOSFET. Current is measured on a cycle-by-cycle basis. The purpose of this current sense is to prevent any damage to the 34920 and its associated external components. Note There is a V2_Enable bit in the Serial Communication Input register (bit 1). When this bit is set to logic [1], the V2 voltage regulator is enabled. When this bit = logic [0], the V2 voltage regulator is disabled. Refer to Tables 5 through 9, pp. 13–17, for a description of this bit. The V2_Enable bit will also disable the motor drivers. VB GENERATOR The boost voltage generator circuit is a charge pump circuit using two external capacitors to provide the necessary voltage to drive internal 34920 loads. This circuit is driven at a frequency of 200 kHz ±25 kHz. The VB generator is utilized exclusively by the 34920. There is no provision for external loading. Also, there is no disable feature for the VB generator. MOTOR DRIVE SYSTEMS The 34920 provides two motor drivers. Both drivers are mode selectable to be either a multi-current level bi- directional driver for bipolar step motors or a bi-directional DC motor driver with PWM control. The DR1_MODE (Mode1) and DR2_MODE (Mode2) pins select whether the appropriate motor driver will drive a step motor (pin = 1) or DC motor (pin = 0). Figures 7 and 8 depict the two motor configurations.

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Figure 7. Simplified Step Application Diagram Showing 1 of 2 Step Drive Circuits

Figure 8. Simplified DC Application Diagram Showing 1 of 2 Motor Drive Circuits The drive circuitry is powered by the VVB+ supply voltage. 550 mA. Current mode operation supports quarter stepping. zero as quickly as possible. TJ (ENABLE), at which time the driver is re-enabled. low until VVB+ has dropped below 4.0 V.

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FUNCTIONAL INTERNAL BLOCK DESCRIPTION DC MOTOR DRIVE SYSTEM This drive circuitry provides bi-directional drive to a DC motor via two inputs, DCM_PWM (an external pin, CMOS- compatible input) and DRx_DIR_DCM (a bit in the serial input port; refer to Tables 7 through 9, pp. 15–17). This drive is powered from VB+. The DC motor control circuitry uses voltage mode control. To drive a DC motor the 34920 outputs DR2A1 and DR2A2 must be connected together externally, then connected to the DC motor “+” lead. Likewise, the 34920 outputs DR2B1 and DR2B2 must be connected together externally, then connected to the DC motor “-“ lead (see Figure 8). This drive provides internal overtemperature sensing for protection. During an overtemperature event, when the device TJ is at or above TJ (SHUTDOWN), the internal thermal protection circuit disables the drive outputs by driving both outputs to the high state until the device temperatures have dropped below the lower thermal threshold temperature TJ (ENABLE), at which time the drive is re-enabled. The crossover delay must be controlled to provide sufficient time for cross-condition suppression. At no time can both the upper and lower output devices on the same side of the H-bridge be allowed to conduct simultaneously. Also, following a turn-on event a blanking period is included to prevent false turn-offs owing to the initial turn-on current spike, which results from motor circuit capacitance. Note During power-on the DC Motor Driver circuit inhibits its outputs when VVB+ is at 4.0 V or greater until RESET is released. Likewise, during power-down of the machine the DC Motor Driver circuit inhibits its outputs from the point when RESET goes low until VVB+ has dropped below 4.0 V. RESET FUNCTIONALITY The 34920 provides an output, RESET, that drives an external reset signal to the system microprocessor and/or the system digital logic IC. This signal is an active low logic level signal that is derived by monitoring the level of the VCC pin. This output is the equivalent of an open drain- (or open collector-) type output, with an internal 2.5 kΩ pull-up to VCC. This output pin can be driven by other external sources and therefore the state of RESET must be monitored by the 34920. Note When RESET is asserted either internally or from an external source, all 34920 motor drive outputs will be in their inactive states, and the serial input port will be loaded with the “Reset Value” (refer to Tables 6 through 9). The V2 voltage regulator will be enabled. During power-up this output asserts a logic low level, and it monitors the V1 regulator output voltage and detects the point that it reaches VV1T+ . The output will then remain low for a delay of 15 ms to 50 ms before releasing to a high state. A second case is if VV1_FB is at or above VV1T+ for a period longer than the delay period of tDELAY and VVB+ is still less than VVB+T- . In this situation RESET will remain low until VVB+ is greater than VVB+T- , at which point RESET will be released immediately and there will be no delay period. If VVB+ passes through VVB+T+ during the tDELAY period, RESET will remain low until the end of the tDELAY period, which started at the time VV1_FB passed through the VV1T+ level. During power-down this output immediately asserts a logic low at the point when VV1_FB drops down to the trip point of VV1T- . Also, if VVB+ drops below VVB+T- and VV1_FB is still at or above VV1T- , RESET will be pulled low. RESET BEHAVIOR The following conditions describe the behavior of the RESET circuit. A Note on Terminology Assertion of RESET is defined as the RESET pin outputting a logic low voltage, and de- assertion is when the pin is pulled up to the VCC voltage. On the power-up condition, RESET behaves as follows:

• If 1.0 V < V V1_FB < VV1T+ or VVB+ < VVB+T+ , RESET will be asserted. Important If VV1_FB < 1.0 V, RESET is undefined.
• I f RESET is asserted owing to VV1_FB < VV1T- , then when VV1_FB rises monotonically from below VV1T- to above VV1T+ , RESET will de-assert after a duration of tDELAY.
• I f RESET is asserted owing to VVB+ < VVB+T+ and VV1_FB ≥ VV1T+ , then when VVB+ rises to the VVB+T+ level RESET will de-assert with no delay. The only case where a delay would be seen is if the time period from where VV1_FB rises to the VV1T+ level to the point where VVB+ rises to the VVB+T+ level is less than the tDELAY period. Then the delay in de-asserting RESET would be the remaining tDELAY time, thereby maintaining the full tDELAY period, between the time when VV1_FB reaches VV1T+ and the de-assertion of RESET, that is required for a reliable system reset. On the power-down condition, RESET behaves as follows:
• I f RESET is not asserted, and the VV1_FB voltage monotonically decreases to a value below the negative- going threshold of VV1T- and remains below VV1T- for longer than tPERSIST (10 µs to 30 µs), RESET will be asserted. RESET will remain asserted while 1.0 V < VV1_FB < VV1T+ . If VV1_FB falls below 1.0 V, the RESET signal is undefined.
• RESET will also be asserted when VVB+ decreases below the VVB+T+ level. This will occur even if the VV1_FB level is still above VV1T- .

• If the V V1_FB supply falls below VV1T- and remains there for less than tPERSIST (10 µs to 30 µs), RESET will not be asserted. However, if the condition lasts longer than tPERSIST, RESET will be asserted for a duration of tDELAY. The 10 µs-to-30 µs persistence time specified in tPERSIST is for ESD rejection. The reset trigger will be a retriggerable one-shot, where the delay pulse will be 10 µs to 30 µs for the delay timeout. ENVIRONMENTAL SPECIFICATIONS AMBIENT TEMPERATURE AND RELATIVE HUMIDITY Table 11 lists the temperature and relative humidity for operating and storage conditions for the 34920. ESD IMMUNITY Refer to the Maximum Ratings table, page 5. OVERTEMPERATURE PROTECTION The 34920 implements overtemperature detection and shutdown functions. The overtemperature circuitry monitors the device’s internal temperature and activates thermal shutdown circuitry when the temperature exceeds TJ (SHUTDOWN) (155°C minimum, 175°C maximum). The thermal shutdown condition is maintained until the die temperature falls below TJ (ENABLE) (135°C minimum, 155°C maximum). Each voltage regulator and motor driver circuit has its own individual shutdown circuit.

Table 11. Ambient Temperature and Humidity

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Table 12. Step Motor Truth Table Table 13. DC Motor Drive System Truth Table

34920 can be properly reset during a power-down situation. be aware that the VCC pin is not monitored for undervoltage. without the 34920 issuing a reset. Figure 9. Voltage Regulator Functions

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For the most current package revision, visit www.freescale.com and perform a keyword search using the “98A” listed below. FN SUFFIX EI-PIN PLASTIC PACKAGE 98ASB42598B ISSUE E

Analog Integrated Circuit Device Data Freescale Semiconductor 27 34920 PACKAGING PACKAGE DIMENSIONS FN SUFFIX EI-PIN PLASTIC PACKAGE 98ASB42598B ISSUE E

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REVISION HISTORY

REVISION DATE DESCRIPTION OF CHANGES 2.0 8/2006 • Implemented Revision History page

• Converted to Freescale format and updated to the prevailing form and style
• Added EI Pb-FREE suffix

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