34825 FREESCALE | Alldatasheet
Document overview
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Technical content
Features
- Identifies various types of power supplies to set low or high battery-charging-current levels
- Internal power switch to offer OVP against up to 28 V failed power supply input
- Supports stereo/mono headset with or without microphone and remote controller with pure passive components
- Supports USB or UART R/D test cables
- High speed (480 Mbps) USB 2.0 compliant
- Supports 32 ID resistance values with a high accuracy 5- bit ADC
- Accessory attachment and det achment detection with an interrupt signal to the host IC
- I 2C interface
- 1 0 μA quiescent current in Standby mode
- Pb-free packaging designated by suffix code EP I2C VDDIO I2C_SCL BASEBAND 34825 I2C_SDA INT RXD TXD TEST2 SPK_L ID DP DM TEST1 SPK_R MIC ISET OUT VBUS VDD GND CHARGERGPIO UART USB XCVR AUDIO TEST PORT VBUS ID GND USB CONNECTOR Li+
Figure 1. 34825 Simplified Application Diagram
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Figure 2. 34825 Simplified Internal Block Diagram
Figure 3. 34825 Pin Connections Table 1. 34825 Pin Definitions A functional description of each pin can be found in the Functional Pin Description section on page 13.
1 SPK_R Input Speaker right channel Right channel input for speaker signals
2 SPK_L Input Speaker left channel Left channel input for speaker signals
3 MIC Output Microphone output Microphone output to the baseband of the cell phone system
4 D+ IO D+ of the USB
5 D- IO D- of the USB
6 RXD Output UART receiver Receive line of the UART
7 TXD Input UART transmitter Transmit line of the UART
8 TEST2 Output TEST cable type
pulled up to the VDDIO voltage. pin also functions as a hardware reset to the IC.
10 TEST1 Output TEST cable indicator Open-drain output to indicate the connection of a test cable
11 VDD Input Power supply IC power supply input
12 INT Output Interrupt output Open-drain interrupt output
13 I2C_SDA IO I2C data Data line of the I2C interface
14 I2C_SCL Input I2C clock Clock line of the I2C interface
15 OUT Output Power output The output of the power MOSFET pass switch
16 ISET Output Charge current setting Open-drain output to set the charger current
17 VBUS Input VBUS power supply VBUS line of the Mini or micro-USB connector
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18 DM IO D- of the USB
19 DP IO D+ of the USB
20 ID Input ID of the USB
21 GND Ground Ground Ground
Table 1. 34825 Pin Definitions (continued) A functional description of each pin can be found in the Functional Pin Description section on page 13.
Analog Integrated Circuit Device Data Freescale Semiconductor 5 34825
ELECTRICAL CHARACTERISTICS
Table 2. Maximum Ratings Exceeding these ratings may cause a malfunction or permanent damage to the device.
- ESD testing is performed in accordance with the Human Body Model (HBM) (C ZAP = 100 pF, RZAP = 1500 Ω), and the Machine Model
- Device mounted on the Freescale EVB test board per JEDEC DESD51-2.
- Pin soldering temperature limit is for 10 seconds maximum dura tion. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
- Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow
enter the core ID to view all orderable parts (i.e. MC33xxxD enter 33xxx)], and review parametrics.
Analog Integrated Circuit Device Data
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STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics conditions, unless otherwise noted.
Analog Integrated Circuit Device Data Freescale Semiconductor 7 34825 STATIC ELECTRICAL CHARACTERISTICS SPK_L and SPK_R Switches On resistance (20 Hz to 470 kHz) Matching between channels On resistance flatness (from -1.2 to 1.2 V) RSPK_ON RSPK_ONMCT RSPK_ONFLT 1.6 0.05 0.01 3.0 0.15 0.05 Ω D+ and D- Switches On resistance (0.1 Hz to 240 MHz) Matching between channels On resistance flatness (from 0.0 to 3.3 V) RUSB_ON RUSB_ONMCT RUSB_ONFLT 0.1 0.02 5.0 0.5 0.1 Ω RXD and TXD Switches On resistance On resistance flatness (from 0.0 to 3.3V) RUART_ON RUART_ONFLT 5.0 Ω MIC Switch On resistance (at below 2.5 V MIC bias voltage) On resistance flatness (from 1.8 to 2.3 V) RMIC_ON RMIC_ONFLT 100 5.0 Ω Pull-down Resistors between SPK_L or SPK_R Pins to GND RPD_AUDIO - 100 - kΩ Signal Voltage Range SPK_L, SPK_R, D+, D-, RXD, TXD, MIC -1.5 -0.3 1.5 3.6 V PSRR - From VDD (100 mVrms) to DP/DM Pins(4) 20 Hz to 20 kHz with 32/16 Ω load. VA_PSRR - - -60 dB Total Harmonic Distortion(4) 20 Hz to 20 kHz with 32/16 Ω load. THD - - 0.05 Crosstalk between Two Channels less than 1.0MHz VA_CT - -60 - dB Off-Channel Isolation Less than 1.0 MHz VA_ISO - -80 - dB POWER SUPPLY TYPE IDENTIFICATION Data Source Voltage Loaded by 0~200 μA VDAT_SRC 0.5 0.6 0.7 V Data Source Current IDAT_SRC 0 - 200 μA Data Detect Voltage Low threshold High threshold VDAT_REF 0.3 0.8 0.35 0.9 0.4 1.0 V Data Sink Current DM pin is biased between 0.15 to 3.6 V IDAT_SINK 65 100 135 μA DP, DM Pin Capacitance CDP/DM - 8 - pF DP, DM Pin Impedance All switches are off RDP/DM - 50 - MΩ Table 3. Static Electrical Characteristics (continued) conditions, unless otherwise noted.
Analog Integrated Circuit Device Data
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STATIC ELECTRICAL CHARACTERISTICS ID DETECTION ID_Float Threshold Detection threshold VFLOAT - 2.3 - V Pull-up Current Source When ADC result is 1xxxx When ADC result is 0xxxx IID 1.9 30.4 2.0 2.1 33.6 μA ID Shorted to Ground Detection Detection current Detection voltage threshold IVCBL VVCBL_L 1.0 1.2 1.4 mA mV LOGIC INPUT AND OUTPUT VDDIO Logic Input Level Input LOW level Input HIGH level VDDIO_IL VDDIO_IH 1.5 0.5 V V Push-pull Logic Output (TEST2) Output HIGH level (loaded by 1.0 mA current) Output LOW level (loaded by 4.0 mA current) VOH VOL 0.7VDDIO 0.4 V Open-Drain Logic Output (TEST1, INT) Output LOW level (loaded by 4.0 mA current) VODOL - - 0.4 V I2C INTERFACE(4) Low Voltage on I2C_SDA, I2C_SCL Inputs VI2C_IL -0.2 - 0.3VDDIO V High Voltage on I2C_SDA, I2C_SCL Inputs VI2C_IH 0.7VDDIO - VDDIO V Low Voltage on I2C_SDA Output VI2C_OL - - 0.4 V Current Load when I2C_SDA Outputs Low Voltage II2C_OL 0 - 4.0 mA Leakage Current on I2C_SDA, I2C_SCL Outputs II2C_LEAK -1.0 - 1.0 μA Input Capacitance of the I2C_SDA, I2C_SCL Pins CI2CIN - - 8.0 pF Notes 1. The OUT pin discharge MOSFET is shown in Figure 15. This MOSFET will be turned on when the power MOSFET is off. conditions, unless otherwise noted.
Analog Integrated Circuit Device Data Freescale Semiconductor 9 34825 DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 4. Dynamic Electrical Characteristics conditions, unless otherwise noted.
Analog Integrated Circuit Device Data
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DYNAMIC ELECTRICAL CHARACTERISTICS I2C Reset Timing I2C reset pulse width I2C_SDA/I2C_SCL concurrent low time without causing a reset tRSTI2C tNRSTI2C 13.5 8.8 ms I2C INTERFACE(4) SCL Clock Frequency fSCL - - 400 kHz Bus Free Time between a STOP and START Condition tBUF 1.3 - - μs Hold Time Repeated START Condition tHD:STA 0.6 - - μs Low Period of SCL Clock tLOW 1.3 - - μs High Period of SCL Clock tHIGH 0.6 - - μs Setup Time for a Repeated START condition tSU:STA 0.6 - - μs Data Hold Time tHD:DAT 0 - - μs Data Setup Time tSU:DAT 100 - - ns Rising Time of Both SDA and SCL Signals tR 20+0.1CB - - ns Falling Time of Both SDA and SCL Signals tF 20+0.1CB - - ns Setup Time for STOP Condition tSU:STO 0.6 - - μs Input Deglitch Time (for Both Rising and Falling Edges) tDGT 55 - 300 ns Notes 2. The protection delay is defined as the interval between VBUS voltage rising above the OVP rising threshold, and the OUT pin voltage dropping below the OVP rising threshold voltage for a VBUS ramp rate of >1.0 V/μs. 3. The OVP deglitch timer is only for the falling edge threshold. 4. These parameters are not tested. They are guaranteed by design. conditions, unless otherwise noted.
- 4 0 - 2 00 2 04 06 08 0760 780 800 820 840 860 880 900 VBUS Supply Current (μA) Temperature (°C) Analog Integrated Circuit Device Data
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ELECTRICAL PERFORMANCE CURVES Figure 10. VBUS Supply Current vs Temperature In Figure 11. OUT Voltage vs VBUS Voltage
Analog Integrated Circuit Device Data Freescale Semiconductor 13 34825 FUNCTIONAL DESCRIPTION INTRODUCTION FUNCTIONAL DESCRIPTION INTRODUCTION The 34825 is designed to support cell phones that adopt the micro or mini-USB connector as the sole wired interface between the cell phone and external accessories. Using the micro-USB connector for charging and USB data communication is required by the OMTP standard for the UCS. The 34825 further extends the micro-USB connector to support other accessories to eliminate all other mechanical connectors in a cell phone. The supported accessories include various audio headsets, UART connection, R/D test cables for firmware downloading, and other user defined accessories, in addition to the chargers defined in the Battery Charging Specification, Revision 1.0, from the USB Implementer’s Forum and the CEA-936-A USB Carkit Specification, from the Consumer Electronics Association (CEA). The supported chargers are listed in Table 7. The 34825 offers two mechanisms to assist the identification of the accessory. The ID detection mechanism allows the cell phone to measure the ID resistor value between the ID pin and the ground with a 5-bit ADC. The VBUS detection mechanism allows the cell phone to find out the connection status between the D+ and D- pins. Together, the exact accessory can be determined. A detection flow is initiated by a change in the VBUS pin voltage or by a change in the ID pin floating status. Detaching the accessory from the micro or mini-USB connector causes the VBUS voltage or/ and the ID resistance to change. The identification flow will be initiated to confirm if an accessory is still connected. The host can also initiate the identification flow by resetting an ACTIVE bit in the register from 1 to 0. Upon the completion of the identification flow, an interrupt signal is sent to the host IC, so the host IC can take further actions. The 34825 contains switches that the host IC can control via an I 2C interface. Based on the accessory, the host IC can configure the switch connections in the 34825, so that the signal paths for the USB communication, or the UART communication, or audio accessories can be established between the micro or mini-USB connector pins and the system ICs. If the accessory is a power supply, the supplied voltage is switched to the Li-ion battery charging function in the cell phone via an internal power MOSFET. The host IC controls the 34825 via the I2C serial bus. The register map in the 34825 contains status information of the device and the control bits that the host IC can access to control the 34825. FUNCTIONAL PIN DESCRIPTION SPEAKER RIGHT CHANNEL (SPK_R) Right channel of the baseband speaker output. SPEAKER LEFT CHANNEL (SPK_L) Left channel of the baseband speaker output. MICROPHONE OUTPUT (MIC) Microphone output to the baseband. D+ OF THE USB TRANSCEIVER (D+) D+ line of the USB transceiver. D- OF THE USB TRANSCEIVER (D-) D- line of the USB transceiver. UART RECEIVER (RXD) Receiver line of the UART. UART TRANSMITTER (TXD) Transmitter line of the UART. TEST2 INDICATOR (TEST2) Push-pull output to indicate the type of the connected test cable. IO POWER SUPPLY (VDDIO) Power supply input for the logic IO interface. Generally the IO power supply voltage should be the same as the IO voltage used in the cell phone system. VDDIO is also one of the hardware reset input sources. A falling edge at this pin will reset the 34825. See Reset for more information. TEST1 INDICATOR (TEST1) Open-drain output to indicate the attachment of a test cable. POWER SUPPLY (VDD) Power supply input. Bypass to ground with a 1.0 μF capacitor. INTERRUPT OUTPUT (INT) Active low open-drain output. The INT pin sends an interrupt signal to the host IC when an interrupt event happens. The INT output returns to high voltage once all interrupt bits are read. DATA LINE OF THE I2C INTERFACE (I2C_SDA) Data line of the I2C interface.
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FUNCTIONAL PIN DESCRIPTION I2C CLOCK (I2C_SCL) Clock line of the I2C interface. The I2C_SCL input together with the I2C_SDA input forms one of the hardware reset input sources. POWER OUTPUT (OUT) Output of the power MOSFET in the 34825. This pin is connected to a charger input. Bypass to ground with a 1.0 μF capacitor. CHARGE CURRENT SETTING (ISET) Open-drain output to set the charge current according to the power supply current capability. VBUS POWER SUPPLY (VBUS) USB VBUS input. Bypass this pin to ground with a less than 10 nF capacitor. When the accessory is an audio kit, this pin is the microphone input to the 34825. D- OF THE USB CONNECTOR (DM) D- line of the mini or micro-USB connector. D+ OF THE USB CONNECTOR (DP) D+ line of the mini or micro-USB connector. ID OF THE USB CONNECTOR (ID) ID pin of the mini or micro-USB connector. GROUND (GND) Ground.
Figure 12. 34825 Functional Internal Block Diagram registers in the 34825. The 34825 is a slave device. is connected to the ID pin or not.
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Figure 13. Mode Transition Diagram high-impedance in this mode. moves to the Active mode for further accessory identification. the ACTIVE bit to 0 through an I2C programming operation.
Analog Integrated Circuit Device Data
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FUNCTIONAL DEVICE OPERATION ACCESSORY IDENTIFICATION ACCESSORY IDENTIFICATION Accessories are categorized into two groups. Powered accessories are accessories that supply power to the VBUS pin while non-powered accessories do not. When the accessory is a powered one, the VBUS-detection mechanism will check the connection between the D+ and the D- pins as part of the power supply type identification (PSTI). A powered accessory may or may not have an ID resistor. A non- powered accessory must have an ID resistor for the identification purpose. Accessories that have an ID resistor are grouped into three types, as listed in Table 21. 1. Test Accessories. Such accessories include two USB test cables that are powered accessories, and two UART test cables that are non-powered accessories. A test accessory has an ID resistor and four ID resistor values are reserved for them (see Table 21 for the ID resistor assignment). Two logic output pins, TEST1 and TEST2, are offered to indicate the attachment of such accessories (see Table 8). The USB or the UART switches in the IC will be turned on automatically when a test accessory is attached. 2. Accessories with a remote controller. Two accessories are offered to support remote control (RC) keys. The ID resistor values are 619 kΩ and 1.0 MΩ respectively, as given in Table 21. Such accessories are non-powered accessories. The 34825 monitors the ID pin continuously for key pressing when such an accessory is connected. 13 ID resistors are assigned to the remote control keys, as listed in Table 21. 3. Other accessories. The rema ining ID resistor values are reserved for users to assign to their own accessories. The identification flow chart is shown in Figure 14. In the Standby mode, the 34825 monitors both the ID pin and the VBUS pin simultaneously. If an accessory is detected, the identification state machine will find out in parallel the ID resistor value and the type of the power supply (if a powered accessory is attached). When the 34825 is in the Active mode with the ACTIVE bit = 1, the host IC can force the ACTIVE bit to 0 via the I 2C bus to initiate the identification state machine. The details on the identification flow for the VBUS- detection mechanism and the ID detection mechanism are described as following.
Figure 14. Detailed Accessory Identification Flow Diagram resistance recognition and the corresponding ADC results vs. Table 6. A rising edge of the ID_FLOAT bit represents the detachment of the accessory. Table 21. The rest of the ADC results are resistor value of the accessory.
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than 30 Ω of resistance, the ID_GND pin is set to “1”. Table 6. ADC Output vs. Resistor Values (Unit: kΩ)
- If the ID resistance is below 1.90 kΩ (nominal value), the ADC result is set to 00000.
- If the ID line is floating, the ADC result is set to 11111
Specification, from the Consumer Electronics Association. offered to assist the identification of the power supply type. detection result, the power supply type can be determined. Table 7. Power Supply Type vs. Detection Result
accessory is one of the four test cables listed in Table 21. of the 34825 are given in the following sections. microphone switch connects the MIC pin to the VBUS pin. Figure 15. Analog and Digital Switches
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be charged when the battery is fully discharged. The VBUS line is capable of withstanding a 28 V voltage. detached or the IC is reset. Figure 16. The five pins in the mini or micro-USB connector
- Error key press: if the ke y pressing time is less than
TKP, The 34825 ignores this key press.
- Short key press: if the key pressing time is between
TKP and TLKP, the KP bit is set to inform the host IC. when the interrupt register is read.
- Long key press: if the key pressing time is longer than
AutoPSAVE bit in the Control register.
Table 8. TEST1, TEST2, and Switch Status vs. Test Cables
- These values are default values and can be changed by t he TEST1 and TEST2 bits in the S/W Control 2 register.
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D+ signal to high to start the USB attaching sequence. outputs low impedance to allow a higher charge current. Specification for more information. detaching detection flow starts.
Figure 18. The Detachment Detection Flow reset from the VDDIO is detected to generate a reset signal. hardware reset. All registers will be reset.
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Figure 19. Sources of Reset in 34825 Figure 20. Hardware Reset Using the I2C Bus Figure 21. Hardware Reset Using the VDDIO Input is set in the Interrupt register.
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Figure 25. Master Reads Slave Immediately after First Byte (Read Mode) Table 9. Register Map Table 10. Interrupt Register
0 R/C ATTACH 0 1: accessory attached
1 R/C DETACH 0 1: accessory detached
2 R/C KP 0 1: remote controller short key is pressed
3 R/C LKP 0 1: remote controller long key is pressed
4 R/C LKR 0 1: remote controller long key is released
5 R/C OVP_EN 0 1: VBUS voltage higher than the OVP threshold
6 R/C OTP_EN 0 1: The temperature of 34825 is above the OTP threshold
7 R/C OVP_OTP_DIS 0 1: OVP or OTP event is removed
Table 11. Interrupt Mask Register
0 R/W ATTACH_m 0 1: interrupt disabled
1 R/W DETACH_m 0 1: interrupt disabled
2 R/W KP_m 0 1: interrupt disabled
3 R/W LKP_m 0 1: interrupt disabled
4 R/W LKR_m 0 1: interrupt disabled
5 R/W OVP_EN_m 0 1: interrupt disabled
6 R/W OTP_EN_m 0 1: interrupt disabled
7 R/W OVP_OTP_DIS_m 0 1: interrupt disabled
Table 12. ADC Result Register Table 13. Timing Set Register Table 14. Timing Table
Table 15. S/W Control Register 1 00: open all switches connected to the VBUS line. 11: open all switches connected to the VBUS line. Table 16. S/W Control Register 2
2 R/W TEST1 1 TEST1 output
3 R/W TEST2 0 TEST2 output
4 R/W ISETB 0 ISET output
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Table 17. Status Register
0 R ADC_Status x ADC conversion status
1 R VBUS_DET x VBUS voltage is higher than the POR
2 R ID_FLOAT x ID line is floating
3 R ID_GND 0 ID pin is shorted to ground
4 R DP/DM_SHORT 0 DP/DM shorted
5 R USB_CHG 0 A USB charger is connected
6 R FET_STATUS x The on/off status of the power MOSFET
7 R Reserved 0
Table 18. Control Register
0 R/W Reserved 0
1 R/W Reserved x
the RST bit is set and the RESET bit is cleared automatically.
3 R/W Reserved 0
4 R/W Reserved 0
5 R/W AutoPSAVE 1 Automatic Power Save mode detection control
1: enable automatic Power Save mode detection.
6 R/W Reserved 1
7 R/W Reserved 0
Table 19. Time Delay Register Table 20. Device Mode Register
1 R/W ACTIVE 0 Indicate either the device is in Active mode
2 R/W PSAVE 0 To indicate either the device is in Power Save mode
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Analog Integrated Circuit Device Data Freescale Semiconductor 33 34825 TYPICAL APPLICATIONS
APPLICATION INFORMATION
ID RESISTANCE VALUE ASSIGNMENT The ID resistors used with the 34825 are standard 1% resistors. Table 21 lists the complete 32 ID resistor assignment. The ones with the Assigned Functions filled are the ones that are already used with special functions. The ones reserved can be assigned to other functions. Table 21. ID Resistance Assignment (Unit: kΩ) The remote control architecture is illustrated in Figure 26. network are given in Table 22. Table 22. Remote Control Resistor Values (Unit: kΩ) Figure 26. Remote Control Architecture
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signals need DC-blocking capacitors to remove the DC level. Figure 27. Interface Circuit in a Cell Phone System
Analog Integrated Circuit Device Data Freescale Semiconductor 35 34825 TYPICAL APPLICATIONS PACKAGE DIMENSIONS PACKAGE DIMENSIONS For the most current package revision, visit www.freescale.com and perform a keyword search using the “98A” listed below. EP SUFFIX 20 LD. QFN 98ASA00037D REVISION O
20 LD. QFN 98ASA00037D REVISION O Analog Integrated Circuit Device Data
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20 LD. QFN 98ASA00037D REVISION O Analog Integrated Circuit Device Data Freescale Semiconductor 37 34825 PACKAGE DIMENSIONS
Analog Integrated Circuit Device Data
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REVISION HISTORY
REVISION DATE DESCRIPTION OF CHANGES 1.0 8/2009 • Initial Release
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