34708

MC34708 FREESCALE | Alldatasheet

Document overview

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• PDF pages: 159

Technical content

Features

• Six multi-mode buck regulators for direct supply of the processor core, memory, and peripherals
• Boost regulator for USB OTG support
• Eight regulators with internal and external pass devices for thermal budget optimization
• USB/UART/Audio switching for mini-micro USB connector
• 10-bit ADC for monitoring battery and other inputs
• Real time clock and crystal oscill ator circuitry with coin cell backup/ charger
• SPI/I 2C bus for control and register interface

Figure 1. MC34708 Simplified Application Diagram

Applications

Portable Navigation Devices VK SUFFIX (PB-FREE)

206 MAPBGA

8.0 X 8.0 (0.5 MM PITCH) VM SUFFIX (PB-FREE) 13.0 X 13.0 (0.8 MM PITCH) /g1/g2/g /g4/g5/g6/g2/g7 /g1/g8/g9/g10/g11/g12/g10 /g1/g2/g3/g4/g5/g2 /g1 /g14/g15/g16/g17/g18 /g10/g13/g14/g15/g16/g17 /g6/g18/g18/g19/g20/g7/g5/g11/g21/g4/g19/g19/g11/g5 /g5/g14/g7 /g6/g7/g2/g19 /g22/g23/g20/g24/g25/g26/g14/g27 /g25/g25/g /g19/g19/g1 /g6/g7/g6/g8/g9 /g6/g8/g9/g10/g11 /g12/g1 /g1/g2/g3/g4/g5/g2 /g22/g23/g20/g24/g25/g26/g14/g27 /g6/g20/g21/g22/g2 /g9/g24 /g25/g 0/g /g 6/g /g 8/g1 /g25/g25/g /g7/g1 /g1 /g6/g7/g6/g8/g9 /g6/g8/g9/g10/g11 /g12/g1 /g25/g18/g12/g10/g12/g26 /g /g26/g17/g27/g21/g22/g12/g9/g28/g12/g10/g21 /g25/g18/g12/g10/g12/g26 /g8/g12/g9/g27/g22/g8/g26/g29/g12/g21 /g 0/g26/g 1/g12/g10 /g 0/g26/g 1/g12/g10 /g10/g13/g14/g15 /g6/g18/g18/g19/g20/g7/g5/g11/g21/g4/g19/g19/g11/g5 /g1/g26/g20/g29/g15/g1/g12/g2 /g2 /g 2/g9/g18/g18/g12/g10/g24 /g /g20/g15/g /g26/g29/g15/g 2/g9/g18/g18/g12/g10/g24 /g1 /g26/g17/g 4/g8 /g25/g 4/g10/g12/g12/g29 /g 5/g25/g 2 /g /g 6/g16 /g19/g20/g 4/g15/g /g29/g22/g17/g18 /g 5/g25/g 2 /g6/g9/g18/g9 /g2/g17/g27/g20/g26/g15 /g /g20/g29/g12/g15/g20/g29/g 6/g26/g17/g18/g 5/g2/g7/g1 /g 7/g 8 /g 9 /g40 /g41 /g 8 /g42 /g 7 /g4 /g44 /g 7/g45 /g46 /g 7/g 7 /g47/g12/g29/g12/g10/g9/g2 /g15/g 0/g17/g10/g22/g26/g21/g12 /g /g4/g6/g15/g6/g10/g20/g48/g12/g10 /g 5/g25/g 2/g15/g25/g 1/g20/g18/g 4/g8 /g14/g1/g28/g29/g30/g31/g32 /g7/g11/g33/g4/g5/g20/g14/g34/g3/g35 /g12/g1 /g1/g9/g49/g12/g10/g9

Analog Integrated Circuit Device Data Freescale Semiconductor 2 MC34708 Table of Contents

Analog Integrated Circuit Device Data

3 Freescale Semiconductor

1 Orderable Parts

number search for the following device numbers. Table 1. Orderable Part Variations

1. To Order parts in Tape & Reel, add the R2 suffix to the part number.

Analog Integrated Circuit Device Data

5 Freescale Semiconductor

2 Part Identification

This section provides an explanation of the part numbers and their alpha numeric breakdown.

2.1 Description

Part numbers for the chips have fields that identify the specific part configuration. You can use the values of these fields to determine the specific part you have received.

2.2 Format and Examples

Part numbers for a given device have the following format, followed by a device example: Table 2 - Part Numbering - Analog: MC tt xxx r v PP RR - MC34708VKR2

2.3 Fields

These tables list the possible values for each field in the part number (not all combinations are valid). Table 2: Part Numbering - Analog FIELD DESCRIPTION VALUES MC Product Category • MC- Qualified Standard

• PC- Prototype Device tt Temperature Range
• 33 = -40 °C to > 105 °C
• 34 = -40 °C to  105 °C
• 35 = -55 °C to  125 °C xxx Product Number • Assigned by Marketing r Revision • (default blank) v Variation • (default blank) RR Tape and Reel Indicator • R2 = 13 inch reel hub size

3 Internal Block Diagram

3.1 Simplified Internal Diagram

Figure 2. Simplified Internal Block Diagram

10 Bit GP

32 KHz

7 Freescale Semiconductor

4 Pin Connections

4.1 Pinout Diagram

Figure 3. Top View Ballmap

4.2 Pin Definitions

Table 3. MC34708 Pin Definitions

1. Input supply to the IC core circuitry
2. Application supply voltage sense
3. Battery positive terminal
4. Battery current sensing point 2
5. Battery supply voltage sense

Coulomb counter Not supported. Coulomb counter Not supported. Coulomb Counter Not supported. Coulomb Counter Not supported.

9 Freescale Semiconductor

Table 3. MC34708 Pin Definitions (continued)

11 Freescale Semiconductor

D10 ICTEST I Connect to ground for normal mode operation.

G3 VINUSB I Input option for UVUSB; tie to SWBST at top level.

13 Freescale Semiconductor

5 General Product Characteristics

5.1 Maximum Ratings

Table 4. Maximum Ratings

• BATT, BP, BPSNS
• L I C E L L 4.8 4.8 V Input Sense Pins
• CHRGFB
• BATTISNSP, BATTISNSN 7.5 5.5 V LED Drivers Pins
• CHRGLEDR, CHRGLEDG 7.5 V IC Core Reference
• VCOREDIG
• VCORE, VCOREREF, VDDLP
• VALWAYS 1.5 3.6 7.5 V Switching Regulators Pins
• SWxIN, SWxLX, SWBSTFB
• SWxFB, SWxPWGD, SWxCFG
• S W B S T L X 5.5 3.6 7.5 V LDO Regulator Pins
• VREFDDR, VHALF
• VPLL, VGEN1, VINGEN1, VSRTC
• VINREFDDR,VDAC, VUSB2, VGEN2,
• VINPLL, VDACDRV, LDOVDD, VUSB2DRV, VGEN2DRV 1.5 2.5 3.6 5.5 V GPIO Pins
• GPIOVDD, GPIOLVx, PWMx 2.5 V Control Logic Pins
• I C T E S T
• XTAL1, XTAL2
• CLK32KVCC, CLK32K, CLK32KMCU, WDI, STANDBY,INT, PWRON1, PWRON2, GLBRST, PUMSx, SPIVCC, CS, CLK, MOSI, MISO, SDWNB 1.8 2.5 3.6 V Mini/Micro USB Interface Pins
• VBUS input sense pin
• VUSB
• UID, DP, DM, DPLUS, DMINUS, RXD, TXD, MIC, SPKR, SPKL, VINUSB 3.6 5.5 V ADC Interface Pins
• ADINx, TSX1/ADIN12, TSX2/ADIN13, TSY1/ADIN14, TSY2/ADIN15, TSREF 4.8 V

5.2 Thermal Characteristics

• Human Body Model All pins
• Charge Device Model All pins
• Air Gap Discharge Model for UID, VBUS, DP, and DM pins
• Human Body Model (HBM) for UID, VBUS, DP, and DM pins 2000 500 15000 8000 V (2) (2) (3) Notes 2. ESD testing is performed in accordance with the Human Body Model (HBM) (C ZAP = 100 pF, RZAP = 1500 ), and the Charge Device Model (CDM), Robotic (CZAP = 4.0 pF). 3. Need external ESD protection diode array to meet IEC1000-4-2 15000 V Air Gap discharge requirement. (CZAP= 150 pF, RZAP=330 ohm).

Table 5. Thermal Ratings

• Single layer board (1s) - 93 °C/W (6), (7) RθJMA Junction to Ambient Natural Convection
• Four layer board (2s2p) - 53 °C/W (6), (8) RθJMA Junction to Ambient (@200 ft/min.)
• Single layer board (1s) - 80 °C/W (6), (8) RθJMA Junction to Ambient (@200 ft/min.)
• Four layer board (2s2p) - 49 °C/W (6), (8) RθJB Junction to Board - 34 °C/W (9) RθJC Junction to Case - 25 °C/W (10) θJT Junction to Package Top
• Natural Convection - 3.0 °C/W (11)

13 X 13 MM, THERMAL RESISTANCE AND PACKAGE DISSIPATION RATINGS

• Single layer board (1s) - 57 °C/W (6), (7) RθJMA Junction to Ambient Natural Convection
• Four layer board (2s2p) (8)

Table 4. Maximum Ratings (continued)

15 Freescale Semiconductor

• Single layer board (1s) - 48 °C/W (6), (8) RθJMA Junction to Ambient (@200 ft/min.)
• Four layer board (2s2p) - 32 °C/W (6), (8) RθJB Junction to Board - 22 °C/W (9) RθJC Junction to Case - 15 °C/W (10) θJT Junction to Package Top
• Natural Convection - 3.0 °C/W (11) Notes 4. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause a malfunction or permanent damage to the device. 5. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts (i.e. MC33xxxD enter 33xxx), and review parametrics. 6. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 7. Per JEDEC JESD51-2 with the single layer board horizontal. Board meets JESD51-9 specification. 8. Per JEDEC JESD51-6 with the board horizontal. 9. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 10. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). 11. Thermal characterization parameter indicating the temperat ure difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.

Table 5. Thermal Ratings (continued)

5.2.1 Power Dissipation

the ADC for specific temperature readouts, see Channel 3 Die Temperature. thresholds specified in Table 6. The temperature range can be determined by reading the THERMxxxS bits. Thermal protection is integrated to power off the MC34708 PMIC and disables the charger circuitry in case of over dissipation. and an interrupt will be generated to notify the software that the hardware is reaching its thermal limit. Table 6. Thermal Protection Thresholds

1. Equivalent to approx. 30 mW min, 60 mW max

Table 7. Die Temp Debounce Settings

17 Freescale Semiconductor

5.3 Electrical Characteristics

5.3.1 Recommended Operating Conditions

5.3.2 General PMIC Specifications

Table 8. Recommended Operating Conditions Table 9. Pin Logic Thresholds

1. SPIVCC is typically connected to the output of buck regulator SW5 and set to 1.800 V
2. Input has internal pull-up to VCOREDIG equivalent to 200 kOhm
3. Input state is latched in first phase of cold start, refer to Serial Interfaces for a description of the PUMS configuration
4. Input state is not latched
5. A weak pull-down represents a nominal internal pull-down of 100 nA unless otherwise noted
6. RESETB, RESETBMCU, SDWNB, SW1PWGD, SW2PWGD have open drain outputs, external pull-ups are required
7. SPIVCC needs to remain enabled for proper detec tion of WDI High to avoid involuntary shutdown
8. The maximum should never exceed the ma ximum rating of the pin as given in Pin Connections
9. The weak pull-down on CS is disabled if a VIH is detected at startup to avoid extra consumption in I2C mode
10. The output drive strength is programmable

19 Freescale Semiconductor

5.3.3 Current Consumption

table follows for standard use cases. Table 10. Current Consumption Summary (25) at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted.

• RTC Logic
• VCORE Module
• V S R T C
• 3 2 k Oscillator
• Clk32KMCU buffer active(10 pF load) 4.0 8.0 A OFF (good battery) All blocks disabled, main battery attached * Core and RTC module
• D i g i t a l C o r e
• RTC Logic
• V S R T C
• 3 2 k Oscillator
• CLK32KMCU buffer active (10 pF load)
• Charger Detect 20 55 A ON Standby Low Power Mode (Standby pin asserted and ON_STBY_LP=1)
• D i g i t a l C o r e
• RTC Logic
• VCORE Module
• V S R T C
• CLK32KMCU/CLK32K active (10 pF load)
• 3 2 k Oscillator
• I REF
• SW1, SW2, SW3, SW4A, SW4B, SW5 in PFM (24),(28)
• VDDREF, VPLL, VGEN1, VGEN2, VUSB2, VDAC in low power mode (23),(26)
• M i n i - U S B 340 424 A ON Standby Digital Core
• RTC Logic
• VCORE module
• V S R T C
• CLK32KMCU/CLK32K active (10 pF load)
• 3 2 k Oscillator
• D i g i t a l
• I REF
• SW1, SW2, SW3 SW4A, SW4B, SW5 in PFM (24),(28)
• VDDREF, VPLL, VGEN1, VGEN2, VUSB2, VDAC on  in low power mode (24),(26)
• M i n i - U S B
• PLL (for mini USB) 480 561 A

• D i g i t a l C o r e
• RTC Logic
• VCORE Module
• VSRTC CLK32KMCU/CLK32K active (10 pf)
• 3 2 k Oscillator
• I REF
• SW1, SW2, SW3 SW4A, SW4B, SW5 in Apskip SWBST (24),(27),(28)
• VDDREF, VPLL, VGEN1, VGEN2, VUSB2, VDAC on  in low power mode (23),(26)
• D i g i t a l
• P L L
• M i n i - U S B 1600 3000 A Notes 23. Equivalent to approx. 30 mW min, 60 mW max 24. Current in RTC Mode is from LICELL=2.5 V; in all other modes from BP = 3.6 V. 25. External loads are not included (1) 26. VUSB2, VGEN2 external pass PNPs 27. SWBST in auto mode 28. SW4A output 2.5 V

at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted.

Analog Integrated Circuit Device Data

21 Freescale Semiconductor

6 General Description

6.1 Features

• Six Buck Switching Regulators
• Two Single/Dual Phase Buck Regulators
• Four Single Phase Buck Regulators
• PFM/Auto Pulse Skip/PWM Operation Mode
• Dynamic Voltage Scaling
• 5 V Boost Regulator
• USB On-the-go Support
• Eight LDO Regulators
• Two with Selectable Internal or External Pass Devices
• Five with Embedded Pass Devices
• One with an External PNP Device Analog to Digital Converter
• Seven General Purpose Channels
• Internal Dedicated Channels
• Resistive Touchscreen Interface Auxiliary Circuits
• Mini/Micro USB Switch
• Bidirectional Audio/Data/UART
• Accessory Identification Circuit
• General Purpose I/Os
• PWM Outputs
• Two general purpose LED Drivers. Clocking and Oscillators
• Real Time clock
• Time and day Counters
• Time of day Alarm
• 32.768 kHz Crystal Oscillator
• Coin Cell Battery Backup and Charger Serial Interface
• SPI
• I 2C

6.2 Block Diagram

Figure 4. Functional Block Diagram

6.3 Functional Description

The MC34708 Power Management Integrated Circuit (PMIC) represents a complete system power solution in a single package. eight LDO regulators for direct supply of the processor core, memory and peripherals.

5 V BOOST

23 Freescale Semiconductor

7 Functional Block Description

7.1 Startup Requirements

switching regulators that are not enabled are discharged at the beginning of the Cold start with weak pull downs on the output. over to the mode that it is programmed to in the SPI. programmable options, to avoid sneak paths, under/over-voltage issues, startup surges, etc, without any change in hardware. Table 11 shows the initial setup for the voltage level of the switching and linear regulators, and whether they get enabled. Table 11. Power Up Defaults

1. The SWx node are activated in APS m ode when enabled by the startup sequencer.

does VUSB, regardless of 5.0 V present on UVBUS. By default VUSB is supplied by SWBST. Table 12. Power Up Sequence i.MX53

0 SW2 (VCC)

3 SW3 (VDDA)

4 SW1A/B (VDDGP)

5 SW4A/B, VREFDDR (DDR/SYS)

7 SW5 (I/O), VGEN1

8 VUSB (31), VUSB2

9 VDAC

1. The VUSB regulator is only enabled if 5.0 V is present on the VBUS pin. By

default VUSB will be supplied by the VBUS pin.

25 Freescale Semiconductor

7.2 Bias and References Block Description and Application

is kept powered as long as there is a valid supply and/or coin cell. Table 14 shows the main characteristics of the core circuitry. Table 13. Power Up Sequence i.MX50

0 SW2

1 SW3

2 SW1A/B

3 VDAC

4 SW4A/B, VREFDDR

5 SW5

6 VGEN2, VUSB2

7 VPLL

8 VGEN1

9 VUSB (32)

1. The VUSB regulator is only enabled if 5.0 V is present on the VBUS pin. By

default VUSB will be supplied by the VBUS pin. Table 14. Core Voltages Electrical Specifications at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted.

• ON mode and OFF with good battery mode, and charging
• RTC mode 1.5 0.0 V (33) CCOREDIG VCOREDIG bypass capacitor - 1.0 - F VDDLP (DIGITAL CORE SUPPLY - LOWER POWER) VDDLP Output voltage
• ON mode with good battery
• OFF mode with good battery
• RTC mode 1.5 1.2 1.2 V (34) CDDLP VDDLP bypass capacitor - 100 - pF (35) VCORE (ANALOG CORE SUPPLY) VCORE Output voltage
• ON mode and charging
• OFF and RTC mode 2.775 0.0 V (33) CCORE VCORE bypass capacitor - 1.0 - F

7.3 Clocking and Oscillators

7.3.1 Clock Generation

(for example, if the crystal is not present), an internal 32 kHz oscillator will be used instead. CLK32KMCU can be provided as a reference to the SRTC module where tamper protection is implemented.

7.3.1.1 Clocking Scheme

occasionally referred to as “32 kHz” for brevity’s sake. transition due to for instance a sag in the regulator output voltage or absence of a signal on the clock output pins. and an interrupt will be generated if the corresponding CLKM mask bit is cleared.

7.3.1.2 Oscillator Specifications

equivalent (such as Micro Crystal CC5V-T1A or Epson FC135) and is capable of handling its parametric variations. characteristics noted above. The oscillator accuracy depends largely on the temperature characteristics of the used crystal. 1.0 Hz timer and RTC registers; see SRTC Support for more detail.

1. 3.0 V < BP < 4.5 V, no external loading on VCOREDIG, VDDLP, VCORE, or REFCORE. Extended operation down to UVDET, but no
2. Maximum capacitance on V DDLP should not exceed 1000 pF, including the board capacitance.

at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted.

27 Freescale Semiconductor

7.3.2 SRTC Support

Table 15. Oscillator and Clock Main Electrical Specifications at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted.

• Oscillator and RTC Block from BP
• Oscillator and RTC Block from LICELL 1.8 1.8 4.5 3.6 V IINRTC Operating Current Crystal Oscillator and RTC Module
• All blocks disabled, no main battery attached, coin cell is attached to LICELL - 2.0 5.0 tSTART-RTC RTC oscillator startup time
• Upon application of power - - 1.0 sec VRTCLO Output Low
• CLK32K Output sink 100 A
• CLK32KMCU Output source 50 A 0.0 - 0.2 V VRTCHI Output High
• CLK32K Output source 100 A
• CLK32KMCU Output sink 50 A CLK32K VCC -0.2 VSRTC-0.2 - CLK32K VCC VSRTC V tCLK32KET CLK32K Rise and Fall Time, CL = 50 pF
• CLK32KDRV [1:0] = 00
• CLK32KDRV [1:0] = 01 (default)
• CLK32KDRV [1:0] = 10
• CLK32KDRV [1:0] = 11 6.0 2.5 3.0 2.0 ns tCKL32K MCUET CLK32KMCU Rise and Fall Time
• C L = 12 pF - 22 - ns CLK32KDC/ CLK32K MCUDC CLK32K and CLK32KMCU Output Duty Cycle
• Crystal on XTAL1, XTAL2 pins 45 - 55 RMS Output Jitter
• 1 Sigma for Gaussian distribution - - 30 ns RMS

Figure 5. SRTC Block Diagram

7.3.2.1 VSRTC

SRTC module integrated on certain FSL processors. The VSRTC regulator is enabled as soon as the RTCPORB is detected. The VSRTC cannot be disabled. 0111, 1000, or 1001), VSRTC will be set to 1.2 V for all modes (on, on standby, on standby low power mode, off, and coincell). Table 16. VSRTC Electrical Specifications at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted.

• Valid Coin Cell range
• V a l i d B P 1.8 1.8 3.6 4.5 V ISRTC Operating Current Load Range ILMIN to ILMAX 0.0 - 50 A COSRTC Bypass Capacitor Value - 0.1 - F VSRTC - ACTIVE MODE - DC VSRTC Output Voltage VOUT
• V INMIN < VIN < VINMAX
• I LMIN < IL < ILMAX
• Off and coincell mode 1.15 1.20 1.28 V 34708 VCOREDIG PWRONx SPIVCC=1.8 V GP Domain=1.1 V LP Dominant=1.2 V VSRTC=1.2 V CKIL: VSRTC 0.1 F Coin Cell Battery Main Battery CLK32KMCU VSRTC & Detect On Detect Best of Supply On/Off Button VCOREDIG 32 kHz Open Drain output for RTC wake-up Processor I/O Core Supply SOG Supply SRTC HP-RC LP-RTC 32 kHz for DSM timing

29 Freescale Semiconductor

7.3.2.2 Real Time Clock

crystal oscillator for the time base and is powered by the coin cell backup supply when BP has dropped below operational range. equal to the value in TODA and the DAY counter is equal to the value in DAYA, the TODAI interrupt will be generated. function is implemented with the RTCRSTI bit. A clock calibration system is provided to adjust the 32,768 cycle counter that generates the 1.0 Hz timer for RTC timing registers. calibration word can be sent via the SPI to compensate the RTC for inaccuracy in its reference oscillator.

• V INMIN < VIN < VINMAX
• I LMIN < IL < ILMAX
• On mode (On, Standby, Standby LPM) 1.15 1.2 1.25 V VSRTC Output Voltage VOUT
• V I N M I N < VIN < VINMAX
• I LMIN < IL < ILMAX
• On mode (On, Standby, Standby LPM) 1.25 1.3 1.35 V ISRTCQ Active Mode Quiescent Current VINMIN < VIN < VINMAX, IL = 0
• VSRTC = 1.2 V
• VSRTC = 1.3 V 1.7 2.7

at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted.

The available correction range should be sufficient to ensure drift accuracy in compliance with standards for DRM time keeping. Note that the 32.768 kHz oscillator is not affected by RTCCAL settings; calibration is only applied to the RTC time base counter. Therefore, the frequency at the clock output CLK32K is not affected. The RTC system calibration is enabled by programming the RTCCALMODE[1:0] for desired behavior by operational mode. RTC power draw is switched to the coin cell (configured with RTCCALMODE=01). not skewed the clock beyond desired tolerances.

7.3.3 Coin Cell Battery Backup

should be placed from LICELL to ground under all circumstances. powers on, or after enabling the coin cell charger when the IC was already on. current is fixed at ICOINHI. be stopped for the BP below UVDET. The bit COINCHEN itself is only cleared when an RTCPORB occurs. Table 17. RTC Calibration Settings Table 18. RTC Calibration Enabling

00 RTC Calibration disabled (default)

01 RTC Calibration enabled in all modes except coin cell only

10 Reserved for future use. Do not use.

11 RTC Calibration enabled in all modes

31 Freescale Semiconductor

7.4 Interrupt Management

7.4.1 Control

by driving the INT pin high; this is true whether the communication interface is configured for SPI or I2C. to go low. If a new interrupt occurs while the processor clears an existing interrupt bit, the interrupt line will remain high. interrupt bit was already high, the interrupt line will go high after unmasking. The sense registers contain status and input sense bits, so the system processor can poll the current state of interrupt sources. They are read only, and not latched or clearable. later in this section. Due to the asynchronous nature of the debounce timer, the effective debounce time can vary slightly. Table 19. Coin Cell Voltage Specifications Table 20. Coin Cell Electrical Specifications at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted.

7.4.2 Interrupt Bit Summary

refer to the related chapters. Table 21. Interrupt, Mask and Sense Bits

33 Freescale Semiconductor

1. Debounce timing for the falling edge can be extended with PWRONxDBNC[1:0]; refer to Turn On Events for details.

7.5 Power Generation

The MC34708 PMIC provides reference and supply voltages for the application processor as well as peripheral device. the boost to ensure sufficient headroom for the LDO through the normal discharge range of the main battery. they can be configured as interrupts.

7.5.1 Power Tree

Refer to the representative tables and text specifying each supply for information on performance metrics and operating ranges. Table 22 summarizes the available power supplies. Table 22. Power Tree Summary

35 Freescale Semiconductor

7.5.2 Modes of Operation

hardwiring the Power Up Mode Select (PUMS) pins. it is kept topped off until needed. The MC34708 PMIC provides the timekeeping, based on an integrated low power oscillator running with a standard watch crystal. Figure 6. Power Control State Machine Flow Diagram

Analog Integrated Circuit Device Data Freescale Semiconductor 36 MC34708 Functional Block Description The following are text descriptions of the power states of the system for additional details of the state machine to complement the drawing in Figure 6. Note that the SPI control is only possible in the Watchdog, On and User Off Wait states and that the interrupt line INT is kept low in all states except for watchdog and on.

7.5.2.1 Coin Cell

The RTC module is powered from either the battery or the coincell, due to insufficient voltage at VALWAYS, and the IC is not in a Power Cut. No Turn On event is accepted in the Coin Cell state. Transition out (to the Off state) requires VALWAYS restoration with a threshold above UVDET. RESETB and RESETBMCU are held low in this mode. The RTC module remains active (32 kHz oscillator + RTC timers), along with VALWAYS level detection to qualify exit to the Off state. VCOREDIG is off and the VDDLP regulator is on, the rest of the system is put into its lowest power configuration. If the coin cell is depleted (VSTRC drops to 0.9 - 0.8 V while in the Coin Cell state), a complete system reset will occur. At next power application / Turn On event, the system will startup reinitialized with all SPI bits including those that reset on RTCPORB restored to their default states.

7.5.2.2 Off (with good battery)

If the supply VALWAYS is above the UVDET threshold, only the IC core circuitry at VCOREDIG and the RTC module are powered, all other supplies are inactive. To exit the Off mode, a valid turn on event is required. No specific timer is running in this mode. RESETB, RESETBMCU are held low in this mode. If the supply VALWAYS is below the UVDET threshold, no turn on events are accepted. If a valid coin cell is present, the core gets powered from LICELL. The only active circuitry is the RTC module and the detection VCORE module powering VCOREDIG at 1.5 V. If there is a USB supply or Charger inserted, the IC circuitry at VCORE, VCOREDIG, and the RTC Module will be powered up. To exit the OFF mode, a valid turn ON event is required.

7.5.2.3 Cold Start

Cold Start is entered upon a Turn On event from Off, Warm Boot, successful PCUT, or a Silent System Restart. The first 8.0 ms is used for initialization which includes bias generation, PUMSx configuration latching, and qualification of the input supply level BP. The switching and linear regulators are then powered up sequentially to limit the inrush current; see the Power Up section for sequencing and default level details. The reset signals RESETB and RESETBMCU are kept low. The Reset timer starts running when entering Cold Start. The Cold Start state is exited for the Watchdog state and both RESETB and RESETBMCU become high (open drain output with external pull-ups) when the reset timer is expired. The input control pins WDI, and STANDBY are ignored.

7.5.2.4 Watchdog

The system is fully powered and under SPI control. RESETB and RESETBMCU are high. The Watchdog timer starts running when entering the Watchdog state. When expired, the system transitions to the On state, where WDI will be checked and monitored. The input control pins WDI and STANDBY are ignored while in the Watchdog state.

7.5.2.5 On Mode

The system is fully powered and under SPI control. RESETB and RESETBMCU are high. The WDI pin must be high to stay in this mode. The WDI IO supply voltage is referenced to SPIVCC (normally connected to SW5 = 1.8 V); SPIVCC must therefore remain enabled to allow for proper WDI detection. If WDI goes low, the system will transition to the Off state or Cold Start (depending on the configuration; refer to the section on Silent System Restart with WDI Event for details).

7.5.2.6 User Off Wait

The system is fully powered and under SPI control. The WDI pin no longer has control over the part. The Wait mode is entered by a processor request for user off by setting the USEROFFSPI bit high. This is normally initiated by the end user via the power key; upon receiving the corresponding interrupt, the system will determine if the product has been configured for User Off or Memory Hold states (both of which first require passing through User Off Wait) or just transition to Off.

Analog Integrated Circuit Device Data

37 Freescale Semiconductor

Functional Block Description The Wait timer starts running when entering User Off Wait mode. This leaves the processor time to suspend or terminate its tasks. When expired, the Wait mode is exited for User Off mode or Memory Hold mode depending on warm starts being enabled or not via the WARMEN bit. The USEROFFSPI bit is being reset at this point by RESETB going low.

7.5.2.7 Memory Hold and User Off (Low Power Off states)

As noted in the User Off Wait description, the system is directed into low power Off states based on a SPI command in response to an intentional turn off by the end user. The only exit then will be a turn on event. To an end user, the Memory Hold and User Off states look like the product has been shut down completely. However, a faster startup is facilitated by maintaining external memory in self-refresh mode (Memory Hold and User Off mode) as well as powering portions of the processor core for state retention (User Off only). The Switching regulator mode control bits allow selective powering of the buck regulators for optimizing the supply behavior in the low power Off modes. Linear regulators and most functional blocks are disabled (the RTC module, SPI bits resetting with RTCPORB, and Turn On event detection are maintained). By way of example, the following descriptions assume the typical use case where SW1 supplies the processor core(s), SW2 is applied to the processor’s VCC domain, SW3 supplies the processors internal memory/peripherals, and SW4 supplies the external memory, and SW5 supplies the I/O rail. The buck regulators are intended for direct connection to the aforementioned loads.

7.5.2.8 Memory Hold

RESETB and RESETBMCU are low, and both CLK32K and CLK32KMCU are disabled (CLK32KMCU active if DRM is set). To ensure that SW1, SW2, SW3, and SW5 shut off in Memory Hold, appropriate mode settings should be used such as SW1MHMODE, = SW2MHMODE, = SW3MHMODE, = SW5MHMODE set to = 0 (refer to the mode control description later in this section). Since SW4 should be powered in PFM mode, SW4MHMODE could be set to 1. Upon a Turn On event, the Cold Start state is entered, the default power up values are loaded, and the MEMHLDI interrupt bit is set. A Cold Start out of the Memory Hold state will result in shorter boot times compared to starting out of the Off state, since software does not have to be loaded and expanded from flash. The startup out of Memory Hold is also referred to as Warm Boot. No specific timer is running in this mode. Buck regulators that are configured to stay on in MEMHOLD mode by their SWxMHMODE settings will not be turned off when coming out of MEMHOLD and entering a Warm Boot. The switching regulators will be reconfigured for their default settings as selected by the PUMSx pins in the normal time slot that would affect them.

7.5.2.9 User Off

RESETB is low and RESETBMCU is kept high. The 32 kHz peripheral clock driver CLK32K is disabled; CLK32KMCU (connected to the processor’s CKIL input) is maintained in this mode if the CLK32KMCUEN and USEROFFCLK bits are both set, or if DRM is set. The memory domain is held up by setting SW4UOMODE = 1. Similarly, the SW1 and/or SW2 and or SW3 supply domains can be configured for SWxUOMODE=1 to keep them powered through the User Off event. If one of the switching regulators can be shut down in User Off, its mode bits would typically be set to 0. Since power is maintained for the core (which is put into its lowest power state), and since MCU RESETBMCU does not trip, the processor’s state may be quickly recovered when exiting USEROFF upon a turn on event. The CLK32KMCU clock can be used for very low frequency / low power idling of the core(s), minimizing battery drain, while allowing a rapid recovery from where the system left off before the USEROFF command. Upon a Turn On event, Warm Start state is entered, and the default power up values are loaded. A Warm Start out of User Off will result in an almost instantaneous startup of the system, since the internal states of the processor were preserved along with external memory. No specific timer is running in this mode.

7.5.2.10 Warm Start

Entered upon a Turn On event from User Off. The first 8.0 ms is used for initialization, which includes bias generation, PUMSx latching, and qualification of the input supply level BP. The switching and linear regulators are then powered up sequentially to limit the inrush current; see Startup Requirements for sequencing and default level details. If SW1, SW2, SW3, SW4, and/or SW5, were configured to stay on in User Off mode by their SWxUOMODE settings, they will not be turned off when coming out

Analog Integrated Circuit Device Data Freescale Semiconductor 38 MC34708 Functional Block Description of User Off and entering a Warm Start. The buck regulators will be reconfigured for their default settings as selected by the PUMSx pins in the respective time slot defined in the sequencer selection. RESETB is kept low and RESETBMCU is kept high. CLK32KMCU is kept active if CLK32KMCU was set. The reset timer starts running when entering Warm Start. When expired, the Warm Start state is exited for the Watchdog state, a WARMI interrupt is generated, and RESETB will go high.

7.5.2.11 Internal MemHold Power Cut

As described in the Power Cut Description, a momentary power interruption will put the system into the Internal MemHold Power Cut state if PCUTs are enabled. The backup coin cell will now supply the MC34708 core, along with the 32 k crystal oscillator, the RTC system, and coin cell backed up registers. All regulators will be shut down to preserve the coin cell and RTC as long as possible. Both RESETB and RESETBMCU are tripped, bringing the entire system down, along with the supplies and external clock drivers, so the only recovery out of a Power Cut state is to reestablish power and initiate a Cold Start. If the PCT timer expires before power is re-established, the system transitions to the Off state and awaits a sufficient supply recovery.

7.5.3 Power Control Logic

7.5.3.1 Power Cut Description

When the supply at VALWAYS drops below the UVDET threshold, due to battery bounce or battery removal, the Internal MemHold Power Cut mode is entered and a Power Cut (PCUT) timer starts running. The backup coin cell will now supply the RTC as well as the on chip memory registers and some other power control related bits. All other supplies will be disabled. The maximum duration of a power cut is determined by the PCUT timer PCT [7:0] preset via the SPI. When a PCUT occurs, the PCUT timer will be started. The contents of PCT [7:0] does not reflect the actual count down value, but will keep the programmed value, and therefore does not have to be reprogrammed after each power cut. If power is not re-established above the LOWBATT threshold before the PCUT timer expires, the state machine transitions to the Off mode at expiration of the counter, and clears the PCUTEXB bit by setting it to 0. This transition is referred to as an “unsuccessful” PCUT. In addition the PMIC will bring the SDWNB pin low for one 32 kHz clock cycle before powering down. Upon re-application of power before expiration (a “successful PCUT”, defined as VALWAYS first rising above the UVDET threshold and then battery above the LOWBATT threshold before the PCUT timer expires), a Cold Start is engaged after the UVTIMER has expired. In order to distinguish a non-PCUT initiated Cold Start from a Cold Start after a PCUT, the PCI interrupt should be checked by software. The PCI interrupt is cleared by software or when cycling through the Off state. Because the PCUT system quickly disables the entire power tree, the battery voltage may recover to a level with the appearance of a valid supply once the battery is unloaded. However, upon a restart of the IC and power sequencer, the surge of current through the battery and trace impedances can once again cause the BP node to droop below UVDET. This chain of cyclic power down / power up sequences is referred to as “ambulance mode”, and the power control system includes strategies to minimize the chance of a product falling into and getting stuck in ambulance mode. First, the successful recovery out of a PCUT requires the VABTT node to rise above LOBATT threshold, providing hysteretic margin from the LOBATTT (H to L) threshold. Secondly, the number of times the PCUT mode is entered is counted with the counter PCCOUNT [3:0], and the allowed count is limited to PCMAXCNT [3:0] set through SPI. When the contents of both become equal, then the next PCUT will not be supported and the system will go to Off mode, after the PCUT time expires. After a successful power up after a PCUT (i.e., valid power is reestablished, the system comes out of reset, and the processor reassumes control), software should clear the PCCOUNT [3:0] counter. Counting of PCUT events is enabled via the PCCOUNTEN bit. This mode is only supported if the power cut mode feature is enabled by setting the PCEN bit. When not enabled, then in case of a power failure, the state machine will transition to the Off state. SPI control is not possible during a PCUT event and the interrupt line is kept low. SPI configuration for PCUT support should also include setting the PCUTEXPB = 1 (See Silent Restart from PCUT Event).

39 Freescale Semiconductor

7.5.3.2 Silent Restart from PCUT Event

during the PCUT event (i.e., a successful power cut). In this case, a silent restart may be appropriate.

7.5.3.3 Silent System Restart with WDI Event

will go to Cold Start without passing through Off mode (i.e., does not generate an OFFB signal). programmable PCMAXCNT counter. an inconspicuous restart without fanfare may be more appropriate than launching into the welcoming routine. A PCUT event does not trip the WDIRESETI bit. as programmed by WDIRESET as described above.

7.5.3.4 Turn On Events

to the processor what event caused the system to power on, an interrupt bit is associated with each of the Turn On events. was already on at the time of the turn on event, the interrupt is still generated.

• Power Button Press: PWRON1 or PWRON2 pulled low with corresponding interrupts and sense bits PWRON1I, or PWRON2I and PWRON1S, or PWRON2S. A power on/off button is connected from PWRONx to ground. The PWRONx can be hardware debounced through a programmable debouncer PWRONxDBNC [1:0] to avoid a response upon a very short (i.e., unintentional) key press. BP should be above UVDET to allow a power up. The PWRONxI interrupt is generated for both the falling and the rising edge of the PWRONx pin. By default, a 30 ms interrupt debounce is applied to both falling and rising edges. The falling edge debounce timing can be extended with PWRONxDBNC[1:0] as defined in the following table. The PWRONxI interrupt is cleared by software or when cycling through the Off mode.

Table 23. PWRONx Hardware Debounce Bit Settings(37)

1. The sense bit PWRONxS is not debounced and follows the state of the PWRONx pin.

• Battery Attach: This occurs when BP crosses the LOWBATT threshold which is equivalent to attaching a charged battery to the product.
• USB Attach: VBUS pulled high with corresponding interrupt and sense bits USBDET and USBDETS. This is equivalent to plugging in a USB cable connected to a host powering the VBUS line. The battery voltage should be above LOWBATT. For details on the USB detection, see Mini/Micro USB Switch.
• RTC Alarm: TOD and DAY become equal to the alarm setting programmed. This allows powering up a product at a preset time. BP should be above LOWBATT. For details and related interrupts, see Real Time Clock.
• System Restart: System restart which may occur after a system reset as described earlier in this section. This is an optional function, see Turn Off Events. BP should be above LOWBATT.
• Global System Reset: The global reset feature powers down the part, disables the charger, resets the SPI registers to their default value including all the RTCPORB registers (except the DRM bit, and the RTC registers), and then powers back on. To enable a global reset, the GLBRST pin needs to be pulled low for greater than GLBRSTTMR [1:0] seconds and then pulled back high (defaults to 12 s). BP should be above LOWBATT.

7.5.3.5 Turn Off Events

• Power Button Press (via WDI): User shutdown of a product is typically done by pressing the power button connected to the PWRONx pin. This will generate an interrupt (PWRONxI), but will not directly power off the part. The product is powered off by the processor’s response to this interrupt, which will be to pull WDI low. Pressing the power button is therefore, under normal circumstances, not considered as a turn off event for the state machine. However, since the button press power down is the most common turn off method for end products, it is described in this section as the product implementation for a WDI initiated Turn Off event. Note that the software can configure a user initiated power down, via a power button press for transition to a Low Power Off mode (Memory Hold or User Off) for a quicker restart than the default transition into the Off state.
• Power Button System Reset: A secondary application of the PWRONx pins is the option to generate a system reset. This is recognized as a Turn Off event. By default, the system reset function is disabled but can be enabled by setting the PWRONxRSTEN bits. When enabled, a four second long press on the power button will cause the device to go to the Off mode, and as a result, the entire application will power down. An interrupt SYSRSTI is generated upon the next power up. Alternatively, the system can be configured to restart automatically by setting the RESTARTEN bit.
• Thermal Protection: If the die gets overheated, the thermal protection will power off the part to avoid damage. A Turn On event will not be accepted while the thermal protection is still being tripped. The part will remain in Off mode until cooling sufficiently to accept a Turn On event. There are no specific interrupts related to this, other than the warning interrupts.
• BP lower than VBAT_TRKL: When the voltage at BP drops below VBAT_TRKL[1:0] - 100mV, the state machine will transition to the Off mode. The SDWNB pin is used to notify the processor that the PMIC is going to immediately shutdown. The PMIC will bring the SDWNB pin low for one 32 kHz clock cycle before powering down. This signal will then be brought back high into the power off state.

Table 24. Global Reset Time Settings Table 25. Turn OFF Voltage Threshold

41 Freescale Semiconductor

7.5.3.6 Timers

event, the duration listed below is therefore the effective minimum time period.

7.5.3.6.1 Timing Diagrams

A Turn On event timing diagrams shown in Figure 7. Figure 7. Power Up Timing Diagram Table 26. Timer Main Characteristics

7.5.3.7 Power Monitoring

The voltage at BATT and BP are monitored by detectors as summarized in Table 27. low threshold to indicate to the processor that the battery is weak and a shutdown is imminent. The LOWBATT detection threshold is debounced by the VBATTDB[2:0] SPI bits shown in Table 28.

7.5.3.8 Power Saving

7.5.3.8.1 System Standby

timing in and out of such deep sleep modes. pin. The configuration of the regulators in standby is pre-programmed through the SPI. STANDBY pin is asserted. The PLL is disabled in this mode so the mini USB will only be able to detect if a charger is inserted. Table 27. LOWBATT Detection Thresholds

1. Default setting for LOWBATT[1:0] is 11.
2. The above specified thresholds are ±50 mV accurate for the indicated transition
3. A hysteresis is applied to the detectors on the order of 100 mV

Table 28. VBATTDB Debounce Times

43 Freescale Semiconductor

been detected. If a device has been detected then the software can bring up the appropriate application etc. adjustments accordingly as soon as it is running.

7.5.3.8.2 Standby Delay

11), STBYDLY will delay the STANDBY initiated response for the entire IC until the STBYDLY counter expires. full 32 k cycle of additional delay). Table 29. Standby Pin and Polarity Control

1. STANDBY = 0: System is not in Standby STANDBY = 1: System is in Standby

Table 30. Delay of STANDBY- Initiated Response

00 No Delay

01 One 32 k period (default)

10 Two 32 k periods

11 Three 32 k periods

7.5.4 Buck Switching Regulators

DVS control for processor power optimization, or to support technologies with a mix of device types with different voltage ratings. interfaces, which can run at the same voltage level. SW5 is used to supply the I/O domain for the system. is optimized to maximum battery life based on load conditions. Buck modes of operation are programmable for explicitly defined or load-dependent control. mode A built in current limiter ensures that during normal operation the maximum current through the coil is not exceeded. Point of Load feedback is intended for minimizing errors due to board level IR drops.

7.5.4.1 General Control

put into PFM mode to optimize efficiency. will be reset to their default values defined by PUMSx settings by the startup sequencer. Table 32 summarizes the Buck regulators programmability for Normal and Standby modes. Table 31. Buck Operating Modes is always running in PFM mode. Useful at light loads for optimized efficiency. in full PWM mode operation regardless of load conditions. Table 32. Switching regulator Mode Control for Normal and Standby Operation

0000 Off Off

0001 PWM Off

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Off mode will not be off when the startup sequencer is started).

0010 PWMPS Off

0011 PFM Off

0100 APS Off

0101 PWM PWM

0110 PWM APS

0111 Off Off

1000 APS APS

1001 PWM PWMPS

1010 PWMPS PWMPS

1011 PWMPS APS

1100 APS PFM

1101 PWM PFM

1110 PWMPS PFM

1111 PFM PFM

Table 33. Switching regulator Control In Memory Hold

0 Off

1 PFM

1. For Memory Hold mode, an activated SWx should use the

Standby set point as programmed by SWxSTBY[4:0]. Table 34. Switching regulator Control In User Off

1. For User Off mode, an activated SWx should use the Standby

set point as programmed by SWxSTBY[4:0].

lower set point, the SW1xPWGD pin will go low and will go high again when the higher/lower set point is reached.

7.5.4.2 Switching Frequency

be programmed to 2.0 MHz or 4.0 MHz by setting the PLLX SPI bit as shown in Table 35. operation for PWM mode. The PLL can be configured for continuous operation with PLLEN = 1.

7.5.4.3 SW1

Table 35. Buck Regulator Frequency Table 36. SW1 Configuration

47 Freescale Semiconductor

Figure 8. SW1 Single Phase Output Mode Block Diagram Figure 9. SW1 Dual Phase Output Mode Block Diagram

output voltage for both the SW1A and SW1B. Table 37. SW1A/B Output Voltage Programmability

49 Freescale Semiconductor

Table 38. SW1A/B Electrical Specification at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted.

• PWM operation, 0 < IL < IMAX
• PFM operation, 0 < IL < ILMAX 3.0 2.8 4.5 4.5 V VSW1ACC Output Voltage Accuracy
• PWM mode including ripple, load regulation, and transients
• PFM Mode, including ripple, load regulation, and transients Nom-25 Nom-25 Nom Nom Nom+25 Nom+25 mV (44) ISW1 Continuous Output Load Current, VINMIN < BP < 4.5 V
• PWM mode single/dual phase (parallel)
• SW1 in PFM mode 2000 mA ISW1PEAK Current Limiter Peak Current Detection
• V IN = 3.6 V, Current through Inductor - 4.0 - A ISW1 TRANSIENT Transient Load Change A VSW1OS- START Start-up Overshoot, IL = 0 - 25 mV tON-SW1 Turn-on Time
• Enable to 90% of end value IL = 0 - - 500 µs fSW1 Switching Frequency
• PLLX = 0
• PLLX = 1 2.0 4.0 MHz ISW1Q Quiescent Current Consumption
• PWMPS or APS MODE, IL=0 mA
• PFM MODE, IL=0 mA 240 µA SW1 Efficiency,
• P F M , 0 . 9 V, 1.0 mA
• PWM Pulse skipping, 1.1 V, 200 mA
• PWM Pulse skipping, 1.1 V, 800 mA
• P W M , 1 . 1 V, 1600 mA % (45) Notes: 44. Transient loading for load steps of ILMAX/2. 45. Efficiency numbers at V IN = 3.6 V, excludes the quiescent current

7.5.4.4 SW2

SW2 is fully integrated synchronous Buck PWM voltage-mode control DC/DC regulator. Figure 10. SW2 Block Diagram SW2 can be programmed in step sizes of 12.5 mV as shown in Table 39. Table 39. SW2 Output Voltage Programmability

51 Freescale Semiconductor

Table 40. SW2 Electrical Specifications at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted.

• PWM operation, 0 < IL < IMAX
• PFM operation, 0 < IL < ILMAX 3.0 2.8 4.5 4.5 V VSW2ACC Output Voltage Accuracy
• PWM mode including ripple, load regulation, and transients
• PFM Mode, including ripple, load regulation, and transients Nom-25 Nom-25 Nom Nom Nom+25 Nom+25 mV (46) ISW2 Continuous Output Load Current, VINMIN < BP < 4.65 V
• PWM mode
• PFM mode 1000 mA ISW2PEAK Current Limiter Peak Current Detection
• V IN = 3.6 V Current through Inductor - 2.0 - A ISW2 TRANSIENT Transient Load Change
• 100 mA/µs - - 0.500 A VSW2OS- START Start-up Overshoot, IL = 0 - - 25 mV tON-SW2 Turn-on Time
• Enable to 90% of end value IL = 0 - - 500 µs

• PLLX = 0
• PLLX = 1 2.0 4.0 MHz ISW2Q Quiescent Current Consumption
• PWMPS or APS MODE, IL = 0 mA; device not switching
• PFM MODE, IL = 0 mA; device not switching 160 µA SW2 Efficiency
• P F M , 0 . 9 V, 1.0 mA
• PWM Pulse skipping, 1.2 V, 120 mA
• PWM Pulse skipping, 1.2 V, 500 mA
• P W M , 1 . 2 V, 1000 mA % (47) Notes: 46. Transient loading for load steps of ILMAX/2. 47. Efficiency numbers at V IN = 3.6 V, excludes the quiescent current.

at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted.

53 Freescale Semiconductor

7.5.4.5 SW3

SW3 is fully integrated synchronous Buck PWM voltage mode control DC/DC regulator. Figure 11. SW3 Block Diagram SW3 can be programmed in step sizes of 25 mV as shown in Table 41. Table 41. SW3 Output Voltage Programmability

Table 42. SW3 Electrical Specification at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted.

• PWM operation, 0 < IL < IMAX
• PFM operation, 0 < IL < ILMAX 3.0 2.8 4.5 4.5 V VSW3ACC Output Voltage Accuracy
• PWM mode including ripple, load regulation, and transients
• PFM Mode, including ripple, load regulation, and transients Nom-3% Nom-3% Nom Nom Nom+3% Nom+3% mV (48) ISW3 Continuous Output Load Current, VINMIN < BP < 4.65 V
• PWM mode
• PFM mode 500 mA ISW3PEAK Current Limiter Peak Current Detection
• V IN = 3.6 V Current through Inductor - 1.0 - A ISW3 TRANSIENT Transient Load Change
• 100 mA/µs - - 250 mA VSW3OS- START Start-up Overshoot, IL = 100 mA/µs - - 25 mV tON-SW3 Turn-on Time
• Enable to 90% of end value IL = 0 - - 500 µs fSW3 Switching Frequency
• PLLX = 0
• PLLX = 1 2.0 4.0 MHz ISW3Q Quiescent Current Consumption
• PWMPS or APSMODE, IL = 0 mA; device not switching
• PFM MODE, IL = 0 mA; device not switching 160 µA SW3 Efficiency,
• P F M , 1 . 2 V, 1.0 mA
• PWM Pulse skipping, 1.2 V, 120 mA
• PWM Pulse skipping, 1.2 V, 250 mA
• PWM, 1.2V, 500 mA % (49) Notes: 48. Transient loading for load steps of ILMAX/2 49. Efficiency numbers at VIN = 3.6 V, Excludes the quiescent current,

55 Freescale Semiconductor

7.5.4.6 SW4

SW4CFG pin. The SW4CFG pin is sampled at startup. Figure 12. SW4A/B Separate Output Mode Block Diagram Table 43. SW4A/B Configuration

Figure 13. SW4 Single Phase Output Mode Block Diagram

57 Freescale Semiconductor

Figure 14. SW4 Dual Phase Output Mode Block Diagram into PWM mode to change the voltage. Table 44. SW4A/B Output Voltage Select

00 SW4x[4:0] See Table 45

11 Invalid Invalid

Table 45. SW4A/B Output Voltage Programmability Table 46. SW4A/B Electrical Specifications at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted.

• PWM operation, 0 < IL < IMAX
• PFM operation, 0 < IL < ILMAX 3.0 2.8 4.5 4.5 V (51) VSW4ACC Output Voltage Accuracy
• PWM mode including ripple, load regulation, and transients
• PFM Mode, including ripple, load regulation, and transients Nom-3% Nom-3% Nom Nom Nom+3% Nom+3% mV (50) ISW4 Continuous Output Load Current, VINMIN < BP < 4.5 V
• PWM mode (separate)
• PWM mode single/dual phase
• PFM mode 500 1000 mA ISW4PEAK Current Limiter Peak Current Detection
• V IN = 3.6 V Current through Inductor (separate)
• Current through Inductor 1.0 2.0 A iSW4 TRANSIENT Transient Load Change, 100 mA/µs
• Single/Dual Phase
• Separate 500 250 mA VSW4OS- START Start-up Overshoot, IL = 100 mA/µs - - 25 mV

59 Freescale Semiconductor

• Enable to 90% of end value IL = 0 - - 500 µs fSW4 Switching Frequency
• PLLX = 0
• PLLX = 1 2.0 4.0 MHz ISW4Q Quiescent Current Consumption
• PWMPS or APS MODE, IL = 0 mA; High output voltage range (VSW4x = 3.15 V or 2.5 V) device not switching
• PWMPS or APS MODE, IL = 0 mA; Low output voltage range (VSW4x = 1.3 V). device not switching
• PFM MODE, IL = 0 mA; device not switching 500 260 µA SW4 Efficiency
• P F M , 3 . 1 5 V, 10 mA (A)
• PWM Pulse skipping, 3.15 V, 50 mA (A)
• PWM Pulse skipping, 3.15 V, 250 mA (A)
• PWM, 3.15 V, 500 mA (A)
• P F M , 1 . 2 V, 10 mA (B)
• PWM Pulse skipping, 1.2 V, 50 mA (B)
• PWM Pulse skipping, 1.2 V, 250 mA (B)
• P W M 1 . 2 V, 500 mA (B) % (52) Notes: 50. Transient loading for load steps of IL MAX / 2. 51. When SW4A/B is set to 3.0 V and above the regulator may drop out of regulation when BP nears the output voltage. 52. Efficiency numbers at V IN = 3.6 V, excludes the quiescent current.

at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted.

7.5.4.7 SW5

SW5 is fully integrated synchronous Buck PWM voltage mode control DC/DC regulator. Figure 15. SW5 Block Diagram power up the regulator should be forced into PWM mode to change the voltage. Table 47. SW5 Output Voltage Programmability

61 Freescale Semiconductor

Table 48. SW5 Electrical Specifications at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted.

• PWM operation, 0 < IL < IMAX
• PFM operation, 0 < IL < ILMAX 3.0 2.8 4.5 4.5 V VSW5ACC Output Voltage Accuracy
• PWM mode including ripple, load regulation, and transients
• PFM Mode, including ripple, load regulation, and transients Nom-3% Nom-3% Nom Nom Nom+3% Nom+3% mV (53) ISW5 Continuous Output Load Current, VINMIN < BP < 4.5 V
• PWM mode
• PFM mode 1000 mA ISW5PEAK Current Limiter Peak Current Detection
• V IN = 3.6 V Current through Inductor - 1.0 - A ISW5 TRANSIENT Transient Load Change
• 100 mA/µs - - 500 mA VSW5 OS-START Start-up Overshoot, IL = 0 - - 25 mV tON-SW5 Turn-on Time
• Enable to 90% of end value IL = 0 - - 500 µs fSW5 Switching Frequency
• PLLX = 0
• PLLX = 1 2.0 4.0 MHz ISW5Q Quiescent Current Consumption
• PWMPS or APS MODE, IL = 0 mA; device not switching
• PFM MODE, IL = 0 mA; device not switching 160 µA SW5 Efficiency
• P F M , 1 . 8 V, 1.0 mA
• PWM Pulse skipping, 1.8 V, 50 mA
• PWM Pulse skipping, 1.8 V, 500 mA
• P W M , 1 . 8 V, 1000 mA % (54) Notes 53. Transient Loading for load Steps of ILMAX/2 54. Efficiency numbers at VIN = 3.6 V, Excludes the quiescent current.

7.5.4.8 Dynamic Voltage Scaling

which could cause logic disruptions on their loads.

• Normal operation: output value selected by SPI bits SWx[5:0]. Voltage transitions initiated by SPI writes to SWx[5:0] are governed by the DVS stepping rate shown in the following tables.
• Standby (Deep Sleep): can be higher or lower than normal operatio n, but is typically selected to be the lowest state retention voltage of a given process. Set by SPI bits SWxSTBY[5:0] and controlled by a Standby event. Voltage transitions initiated by Standby are governed by the SWxDVSSPEED[1:0] SPI bits shown in Table 49. The following table summarizes the set point control and DVS time stepping applied to SW1A/B and SW2. The Regulator have a strong sourcing and sinking capability in the PWM mode. Therefore, the rising/falling slope is determined by the regulator in PWM mode, however, if the regulators are programmed in PFM, PWMPS, or APS mode during a DVS transition, the falling slope can be influenced by the load. Additionally, as the current capability in PFM mode is reduced, controlled DVS transitions in PFM mode could be affected. Critically timed DVS transitions are best assured with PWM mode operation. Voltage transitions programmed through SPI(SWx[4:0]) on SW3 and SW5 will step in increments of 25 mV per 4.0 s, SW4A/B will step in increments of 25 mV per 8.0 s when SW4xHI[1:0]=00, and SW4A/B will step in increments of 25 mV per 16 s when SW4xHI[1:0]=00. Additionally, SW3, SW4/B, and SW5 include standby mode set point programmability. The following diagram shows the general behavior for the switching regulators when initiated with SPI programming or standby control. SW1 and SW2 also contain Power Good (outputs from the MC34708 to the application processor). The power good signal is an active high signal. When SWxPWRGDB is high, it means that the regulators output has reached its programmed voltage. The SWxPWRGDB voltage outputs will be low during the DVS period and if the current limit is reached on the switching regulator. The SWxPWRGD will be low from a low to high or a high to low transition of the regulator output voltage. During the DVS period, the over-current condition on the switching regulator should be masked. If the current limit is reached outside of a DVS period, the SWxPWRGD pin will stay low until the current limit condition is removed.

Table 49. DVS Control Logic Table for SW1A/B and SW2

0 SWx[4:0]

1 SWxSTBY[4:0]

Table 50. DVS Speed Selection

63 Freescale Semiconductor

Figure 16. Voltage Stepping with DVS

7.5.5 Boost Switching Regulator

SWBST is a boost switching regulator with a programmable output, which defaults to 5.0 V on power up, operating at 2.0 MHz. diode, inductor, and capacitor are required. Figure 17. Boost Regulator Architecture SWBST output voltage programmable via the SWBST[1:0] SPI bits as shown in Table 51. Table 51. SWBST Voltage Programming

mode based on the load current. By default SWBST is powered up in Auto mode. Table 52. SWBST Mode Control

00 Off

01 PFM

10 Auto (default)

11 PWM

Table 53. SWBST Electrical Specifications at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted.

• 3 . 0 V < VIN < 4.5 V, 0 < IL < ILMAX Nom-4% VNOM Nom+3% V (55) VSWBSTACC Output Ripple
• 3 . 0 V < VIN < 4.5 V 0 < IL < ILMAX, excluding reverse recovery of Schottky diode - - 120 mV Vp-p SWBSTACC Average Load Regulation
• V IN = 3.6 V, 0 < IL < ILMAX - 0.5 - mV/mA VSWBST LINEAREG Average Line Regulation
• 3 . 0 V < VIN < 4.5 V IL = ILMAX - 50 - mV ISWBST Continuous Load Current
• 3 . 0 V < VIN < 4.5 V, VOUT = 5.0 V - 380 - mA ISWBSTPEAK Peak Current Limit
• At SWBSTIN, VIN = 3.6 V - 1800 - mA VSWBSTOS- START Start-up Overshoot, IL = 0 mA - - 500 mV tON-SWBST Turn-on Time
• Enable to 90% of VOUT IL = 0 - - 2.0 ms fSWBST Switching Frequency - 2.0 - MHz VSWBST TRANSIENT Transient Load Response, IL from 1.0 to 100 mA in 1.0 µs
• Maximum transient Amplitude - - 300 mV VSWBST TRANSIENT Transient Load Response, IL from 100 to 1.0 mA in 1.0 µs
• Maximum transient Amplitude - - 300 mV VSWBST TRANSIENT Transient Load Response, IL from 1.0 to 100 mA in 1.0 µs
• Time to settle 80% of transient - - 500 µs VSWBST TRANSIENT Transient Load Response, IL from 100 to 1.0 mA in 1.0 µs
• Time to settle 80% of transient - - 20 ms SWBST Efficiency, IL = ILMAX 65 80 - % ISWBSTBIAS Bias Current Consumption
• PFM or Auto mode - 35 - µA

65 Freescale Semiconductor

7.5.6 Linear Regulators (LDOs)

kept powered as long as there is a valid supply and/or coin cell.

7.5.6.1 General Features

The following applies to all linear regulators, unless otherwise specified.

• Specifications are for an am bient temperature of –40 to 85 °C.
• Advised bypass capacitor is the Murata GR M155R60G225ME95, which comes in a 0402 case.
• In general, parametric performance s pecifications assume the use of low ESR X5R/X7R ceramic capacitors with 20% accuracy and 15% temperature spread, for a worst case stack up of 35% from the nominal value. Use of other types with wider temperature variation may require a larger room-temperature nominal capacitance value to meet performance specs over temperature. In addition, capacitor derating as a function of DC bias voltage requires special attention. Finally, minimum bypass capacitor guidelines are provided for stability and transient performance. Larger values may be applied; performance metrics may be altered and generally improved, but should be confirmed in system applications.
• Regulators which require a minimum output capacitor ESR (thos e with external PNPs) can avoid an external resistor if ESR is assured with capacitor specifications or board level trace resistance.
• The output voltage tolerance specified for each of the linear regulators include process variation, temperature range, static line regulation, and static load regulation.
• The PSRR of the regulators is measured with the perturbating signal at the input of the regulator. The power management IC is supplied separately from the input of the regulator and does not contain the perturbated signal. During measurements, care must be taken not to reach the drop out of the regulator under test.
• In the Low Power mode, the output perfo rmance is degraded. Only those parameters listed in the Low Power mode section are guaranteed. In this mode, the output current is limited to much lower currents than in the active mode.
• Regulator performance is degraded in the extended input volt age range. This means that the supply still behaves as a regulator, and will try to hold up the output voltage by turning the pass device fully on. As a result, the bias current will increase and all performance parameters will be heavily degraded, such as PSRR and load regulation.
• Note that the minimum operating range specifications in some cases may be conflicting, due to numerous set point and biasing options, as well as the potential to run BP into one of the software or hardware shutdown thresholds. The specifications are general guidelines that should be interpreted with some care in such cases.
• When a regulator gets disabled, the output will be pulled towa rds ground by an internal pull-down. The pull-down is also activated when RESETb goes low.
• 3 2 kHz spur levels are specified for fully loaded conditions. ILEAK-SWBST NMOS Off Leakage
• S W B S T I N = 4.5 V, SWBSTMODE [1:0] = 0 - 1.0 6.0 µA Notes: 55. V IN is the low side of the inductor that is connected to BP.

at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted.

• Short-circuit Protection (SCP) is included on certain LDOs (see the SCP section later in this section). Exceeding the SCP threshold will disable the regulator and generate a system interrupt. The output voltage will not sag below the specified voltage with the rated current being drawn. For the lower current LDOs without SCP, they are less accessible to the user environment and essentially self-limiting.
• The power tree of a given application must be scrubbed for crit ical use cases to ensure consistency and robustness in the power strategy.

7.5.6.2 LDO Regulator Control

regulators in a Low Power mode. corresponding mode bits for the operational behavior desired. regulator. Therefore, depending on the configuration selected, the automatic Low Power mode determines availability. For regulators with internal pass devices, the previous table can be simplified by elimination of the VxMODE column. Table 54. LDO Regulator Control (external pass device LDOs)

0 X X X Off

1 X 1 0 On

1. STANDBY refers to a Standby event as described earlier

Table 55. LDO Regulator Control (internal pass device LDOs)

0 X X Off

1. STANDBY refers to a Standby event as described earlier

67 Freescale Semiconductor

7.5.6.3 Transient Response Waveforms

overshoot and DC shift. This is also valid for the mode transition response. Figure 18. Transient Waveforms set, so at startup, none of the regulators in an overload condition are disabled.

7.5.6.5 VPLL

inputs can be connected to either BP or a 2.2 V nominal external switched mode power supply rail, to improve power dissipation. Table 56. VPLL Voltage Control Table 57. VPLL Electrical Specification BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted.

• VPLL all settings, BP biased
• VPLL, [1:0] = 10, 11, External Switch UVDET 1.75 2.15 1.8 2.2 4.5 4.5 4.5 V IPLL Operating current Load range - - 50 mA VPLL ACTIVE MODE – DC VPLL Output Voltage VOUT
• V INMIN < VIN < VINMAX,
• I LMIN < IL < ILMAX VNOM – 0.05 VNOM VNOM + 0.05 V VPLL-LOPP Load Regulation
• 1 . 0 mA < IL < ILMAX For any VINMIN < VIN < VINMAX - 0.35 - mV/mA VPLL-LIPP Line Regulation
• V INMIN < VIN < VINMAX For any ILMIN < IL < ILMAX - 5.0 - mV IPLL-Q Quiescent Current
• V INMIN < VIN < VINMAX IL = 0 - 8.0 - µA VPLL ACTIVE MODE – AC VPLLPSRR PSRR, IL = 75% of ILMAX, 20 Hz to 20 kHz
• V IN = UVDET
• V IN = VNOM + 1.0 V, > UVDET dB VPLLNOISE Output Noise Density, VIN = VINMIN IL = 75% of ILMAX
• 100 Hz – 1.0 kHz
• > 1 . 0 kHz – 1.0 MHz 2.5 dB/dec V/Hz

69 Freescale Semiconductor

7.5.6.6 VREFDDR

utilizes a voltage follower to drive the load.

• Enable to 90% of end value VIN = VINMIN, VINMAX IL = 0 - - 120 µs tOFF-VPLL Turn-off Time
• Disable to 10% of initial value VIN = VINMIN, VINMAX, IL = 0 0.05 - 10 ms VPLLOS- START Start-up Overshoot
• V IN = VINMIN, VINMAX IL = 0 - 1.0 2.0 VPLL-LO TRANSIENT Transient Load Response
• V IN = VINMIN, VINMAX - 50 70 mV VPLL-LI TRANSIENT Transient Line Response
• I L = 75% of ILMAX - 5.0 8.0 mV

Table 58. VREFDDR Electrical Specification at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted.

• V INMIN < VIN < VINMAX ILMIN < IL < ILMAX 0.6 VIN/2 0.9 V VREFDDRTOL Output Voltage tolerance
• V INMIN < VIN < VINMAX IL = 1.0 mA -6.5 - 6.5 % (58) VREFDDR LOPP Load Regulation
• 1 . 0 mA < IL < ILMAX For any VINMIN < VIN < VINMAX - 5.0 - mV/mA IREFDDRQ Quiescent Current
• V INMIN < VIN < VINMAX IL = 0 - 8.0 - µA VREFDDR ACTIVE MODE – AC tON-VREFDDR Turn-on Time
• Enable to 90% of end value VIN = VINMIN, VINMAX IL = 0 - - 100 µs tOFF- VREFDDR Turn-off Time
• Disable to 10% of initial value VIN = VINMIN, VINMAX, IL = 0 0.05 - 10 ms VREFDDROS Start-up Overshoot
• V IN = VINMIN, VINMAX IL = 0 - 1.0 2.0

BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted.

7.5.6.7 VUSB2

NSS12100UW3TCG. For stability reasons, a small minimum ESR may be required. A short-circuit condition will shut down the VUSB2 regulator and generate an interrupt for SCPI. when working with the internal pass FET is 65 mA, and could be up to 350 mA when working with an external PNP.

• V IN = VINMIN, VINMAX - 5.0 - mV Notes 58. guaranteed at 25 °C only

Table 59. VUSB2 Voltage Control Table 60. VUSB2 Electrical Specification at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted.

• Internal pass FET
• External PNP Not exceeding PNP max power 0.0 0.0 350 mA VUSB2IN Extended Input Voltage Range
• Performance may be out of specification UVDET - 4.5 V VUSB2 ACTIVE MODE - DC VUSB2 Output Voltage VOUT
• V INMIN < VIN < VINMAX ILMIN < IL < ILMAX VNOM - 3% VNOM VNOM + 3% V

at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted.

71 Freescale Semiconductor

• 1 . 0 mA < IL < ILMAX For any VINMIN < VIN < VINMAX - 0.25 - mV/mA VUSB2LIPP Line Regulation
• V INMIN < VIN < VINMAX For any ILMIN < IL < ILMAX - 8.0 - mV VUSB2SCTH Short-circuit Protection Threshold Internal pass FET mode
• V INMIN < VIN < VINMAX Short-circuit VOUT to GND ILMAX +20% - - mA IUSB2Q Active Mode Quiescent Current, VINMIN < VIN < VINMAX
• I L = 0, Internal PMOS configuration
• V INMIN < VIN < VINMAX IL = 0, External PNP configuration µA VUSB2 LOW POWER MODE - DC VUSB2 Output Voltage VOUT
• V INMIN < VIN < VINMAX ILMINLP < IL < ILMAXLP VNOM - 3% VNOM VNOM + 3% V IUSB2 Current Load Range ILMINLP to ILMAXLP 0.0 - 3.0 mA IUSB2Q Low Power Mode Quiescent Current
• V INMIN < VIN < VINMAX IL = 0 - 8.0 10.5 µA VUSB2 ACTIVE MODE - AC VUSB2PSRR PSRR, IL = 75% of ILMAX 20 Hz to 20 kHz
• V IN = VINMIN + 100 mV
• V IN = VNOM + 1.0 V dB VUSB 2NOISE Output Noise Density, VIN = VINMIN IL = 75% of ILMAX
• 100 Hz – 1.0 kHz
• > 1 . 0 kHz – 1.0 MHz 1.0 dB/dec V/Hz tON-VUSB2 Turn-on Time
• Enable to 90% of end value VIN = VINMIN, VINMAX IL = 0 - - 1.0 ms tOFF-VUSB2 Turn-off Time
• Disable to 10% of initial value VIN = VINMIN, VINMAX IL = 0 0.05 - 10 ms VUSB2OS- START Start-up Overshoot
• V IN = VINMIN, VINMAX IL = 0 - 1.0 2.0 VUSB2LO TRANSIENT Transient Load Response, VIN = VINMIN, VINMAXx
• VUSB2=01, 10, 11
• VUSB2=00 1.0 2.0 mV VUSB2LI TRANSIENT Transient Line Response
• I L = 75% of ILMAX - 5.0 8.0 mV tMOD-VUSB2 Mode Transition Time
• From low power to active and from active to low power VIN = VINMIN, VINMAX IL = ILMAXLP - - 100 µs VUSBMODE RES Mode Transition Response
• From low power to active and from active to low power VIN = VINMIN, VINMAX IL = ILMAXLP - 1.0 2.0

at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted.

7.5.6.8 VDAC

efficiency during deep sleep modes. reasons, an ESR of 110 m 20%is required. A short-circuit condition will shut down the VDAC regulator and generate an interrupt for SCPI. current along with an external PNP, is 250 mA. Table 61. VDAC Voltage Control Table 62. VDAC Electrical Specification at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted.

• Not exceeding PNP max power 0.0 - 250 mA VDACIN Extended Input Voltage Range
• Performance may be out of specification UVDET - 4.5 V VDAC ACTIVE MODE – DC VDAC Output Voltage VOUT
• V INMIN < VIN < VINMAX ILMIN < IL < ILMAX VNOM – 3% VNOM VNOM + 3% V VDACLOPP Load Regulation
• 1 . 0 mA < IL < ILMAX For any VINMIN < VIN < VINMAX - 0.20 - mV/mA VDACLIPP Line Regulation
• V INMIN < VIN < VINMAX For any ILMIN < IL < ILMAX - 5.0 - mV VDACSCTH Short-circuit Protection Threshold
• V INMIN < VIN < VINMAX Short-circuit VOUT to GND ILMAX +20% - - mA IDACQ Active Mode Quiescent Current
• V INMIN < VIN < VINMAX IL = 0 - 30 - µA

73 Freescale Semiconductor

7.5.6.9 VGEN1, VGEN2

reduced power dissipation in the pass devices. VGEN2 is powered directly from the battery.

• V INMIN < VIN < VINMAX ILMINLP < IL < ILMAXLP VNOM – 3% VNOM VNOM + 3% V IDAC Current Load Range ILMINLP to ILMAXLP 0.0 - 3.0 mA IDACQ Low Power Mode Quiescent Current
• V INMIN < VIN < VINMAX IL = 0 - 8.0 - µA VDAC ACTIVE MODE – AC VDACPSRR PSRR - IL = 75% of ILMAX 20 Hz to 20 kHz
• V IN = VINMIN + 100 mV
• V IN = VNOM + 1.0 V dB VDACNOISE Output Noise Density, VIN = VINMIN IL = 75% of ILMAX
• 100 Hz – 1.0 kHz
• > 1 . 0 kHz – 10 kHz
• > 1 0 kHz – 1.0 MHz -115 -126 -132 V/Hz VDACSPURS Spurs
• 32.768 kHz and harmonics - - -120 dB tON-VDAC Turn-on Time
• Enable to 90% of end value VIN = VINMIN, VINMAX IL = 0 - - 1.0 ms tOFF-VDAC Turn-off Time
• Disable to 10% of initial value VIN = VINMIN, VINMAX, IL = 0 0.05 - 10 ms VDACOS- START Start-up Overshoot
• V IN = VINMIN, VINMAX IL = 0 - 1.0 2.0 VDACLO TRANSIENT Transient Load Response
• V IN = VINMIN, VINMAX - 1.0 2.0 VDACLI TRANSIENT Transient Line Response
• I L = 75% of ILMAX - 5.0 8.0 mV tMODE-VDAC Mode Transition Time
• From low power to active VIN = VINMIN, VINMAX IL = ILMAXLP - - 100 µs VDACMODE RES Mode Transition Response
• From low power to active and from active to low power VIN = VINMIN, VINMAX IL = ILMAXLP - 1.0 2.0

at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted.

the ON Semiconductor NSS12100UW3TCG. For stability, a small minimum ESR may be required. A short-circuit condition will shut down the VGEN1 and VGEN2 regulators, and generate an interrupt for SCPI. Table 63. VGEN1 Control Register Bit Assignments Table 64. VGEN2 Control Register Bit Assignments Table 65. VGEN1 Electrical Specification at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted.

• All settings 1.75 1.8 1.85 V IGEN1 • Operating Current Load Range ILMIN to ILMAX 0.0 - 250 mA

75 Freescale Semiconductor

• V INMIN < VIN < VINMAX ILMIN < IL < ILMAX VNOM – 3% VNOM VNOM + 3% V VGEN1LOPP Load Regulation
• 1 . 0 mA < IL < ILMAX For any VINMIN < VIN < VINMAX - 0.25 - mV/mA VGEN1LIPP Line Regulation
• V INMIN < VIN < VINMAX For any ILMIN < IL < ILMAX - 5.0 - mV VGEN1SCTH Short-circuit Protection threshold
• V INMIN < VIN < VINMAX Short-circuit VOUT to GND ILMAX +20% - - mA IGEN1Q Active Mode Quiescent Current
• V INMIN < VIN < VINMAX IL = 0 - 12 - µA VGEN1 LOW POWER MODE - DC VGEN1 Output Voltage VOUT
• V INMIN < VIN < VINMAX ILMINLP < IL < ILMAXLP VNOM - 3% VNOM VNOM + 3% V IGEN1 Current Load Range ILMINLP to ILMAXLP 0.0 - 3.0 mA IGEN1Q Low Power Mode Quiescent Current
• V INMIN < VIN < VINMAX IL = 0 - 12 - µA VGEN1 ACTIVE MODE - AC VGEN1PSRR PSRR
• I L = 75% of ILMAX 20 Hz to 20 kHz VGEN1[2:0] = 000-101
• IL = 75% of ILMAX 20 Hz to 20 kHz VGEN1[2:0] = 110-111 dB VGEN 1NOISE Output Noise Density, VIN = VINMIN IL = 75% of ILMAX
• 100 Hz – 1.0 kHz
• > 1 . 0 kHz – 10 kHz
• > 1 0 kHz – 1.0 MHz -115 -126 -132 V/Hz VGEN 1SPURS Spurs
• 32.768 kHz and harmonics - - -100 dB tON-VGEN1 Turn-on Time
• Enable to 90% of end value VIN = VINMIN, VINMAX, IL = 0 - - 1.0 ms tOFF-VGEN1 Turn-off Time
• Disable to 10% of initial value VIN = VINMIN, VINMAX, IL = 0 0.01 - 10 ms VGEN1OS- START Start-up Overshoot
• V IN = VINMIN, VINMAX, IL = 0 - 1.0 2.0 VGEN1LO TRANSIENT Transient Load Response
• V IN = VINMIN, VINMAX - 1.0 2.0 VGEN1LI TRANSIENT Transient Line Response
• I L = 75% of ILMAX - 5.0 8.0 mV

at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted.

• From low power to active and from active to low power VIN = VINMIN, VINMAX IL = ILMAXLP - - 100 µs VGEN 1MODERES Mode Transition Response
• From low power to active and from active to low power VIN = VINMIN, VINMAX IL = ILMAXLP - 1.0 2.0

Table 66. VGEN2 Electrical Specification at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted.

• All settings, BP biased VNOM +0.25 - 4.5 V IGEN2 Operating Current Load Range ILMI to ILMAX
• Internal Pass FET 0.0 - 50 mA IGEN2 Operating Current Load Range ILMIN to ILMAX
• External PNP, Not exceeding PNP max power 0.0 - 250 mA VGEN2IN Extended Input Voltage Range
• BP Biased, Performance may out of specification for output levels VGEN2 [2:0] = 010 to 111 UVDET - 4.5 mV/mA COVGEN2 Minimum Bypass Capacitor Value
• Used as a condition for all other parameters 1.1 2.2 - µF ESRVGEN2 Bypass Capacitor ESR
• 1 0 kHz – 1.0 MHz 20 - 100 VGEN2 ACTIVE MODE - DC VGEN2 Output Voltage VOUT
• V INMIN < VIN < VINMAX ILMIN < IL < ILMAX VNOM - 3% VNOM VNOM + 3% V VGEN2LOPP Load Regulation
• 1 . 0 mA < IL < ILMAX, For any VINMIN < VIN < VINMAX - 0.20 - mV/mA VGEN2LIPP Line Regulation
• V INMIN < VIN < VINMAX For any ILMIN < IL < ILMAX - 8.0 - mV VGEN2SCTH Short-circuit Protection Threshold Internal pass FET mode
• V INMIN < VIN < VINMAX Short-circuit VOUT to GND ILmax +20% - - mA IGEN2Q Active Mode Quiescent Current
• V INMIN < VIN < VINMAX IL = 0 - 30 - µA

at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted.

77 Freescale Semiconductor

• V INMIN < VIN < VINMAX ILMINLP < IL < ILMAXLP VNOM - 3% VNOM VNOM + 3% V IGEN2 Current Load Range ILMINLP to ILMAXLP 0.0 - 3.0 mA IGEN2Q Low Power Mode Quiescent Current
• V INMIN < VIN < VINMAX IL = 0 - 8.0 - µA VGEN2 ACTIVE MODE - AC VGEN2PSRR PSRR - IL = 75% of ILmax, 20 Hz to 20 kHz
• V IN = VINMIN + 100 mV
• V IN = VNOM + 1.0 V dB VGEN 2NOISE Output Noise Density - VIN = VINMIN IL = 75% of ILMAX
• 100 Hz – 1.0 kHz
• > 1 . 0 kHz – 10 kHz
• > 1 0 kHz – 1.0 MHz -115 -126 -132 V/Hz tON-VGEN22 Turn-on Time
• Enable to 90% of end value VIN = VINMIN, VINMAX, IL = 0 - - 1.0 ms tOFF-VGEN2 Turn-off Time
• Disable to 10% of initial value VIN = VINMIN, VINMAX, IL = 0 0.05 - 10 ms VGEN2OS- START Start-up Overshoot
• V IN = VINMIN, VINMAX IL = 0 - 1.0 2.0 VGEN2LO TRANSIENT Transient Load Response
• V IN = VINMIN, VINMAX - 1.0 2.0 VGEN2LI TRANSIENT Transient Line Response
• I L = 75% of ILMAX - 5.0 8.0 mV tMODE-VGEN2 Mode Transition Time
• From low power to active VIN = VINMIN, VINMAX, IL = ILMAXLP - - 100 µs VGEN 2MODERES Mode Transition Response
• From low power to active and from active to low power V IN = VINMIN, VINMAX, IL = ILMAXLP - 1.0 2.0

at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted.

7.6 Battery Management

7.7 Analog to Digital Converter

The ADC core is a 10-bit converter. The ADC core and logic run at an internally generated frequency of approximately 1.33 MHz.

7.7.1 Input Selector

The ADC has 16 input channels. Table 67 gives an overview of the characteristics of each of these channels. Table 67. ADC Inputs

4 Reserved Reserved Reserved Reserved

6 Reserved Reserved Reserved Reserved

7 Reserved Reserved Reserved Reserved

1. Equivalent to -4.0 A to +4.0 A of current with a 20 mOhm sense resistor.
2. Input must not exceed the BP voltage.
3. Input must not exceed BO or VCORE.

79 Freescale Semiconductor

7.7.2 Control

ADCDONEI is generated. The interrupt can be masked with the ADCDONEM bit. The ADC is automatically calibrated every time the PMIC is powered on. conversions from 0 to 600 S. ADDLY3[3:0] controls the delay after the final conversion, and is only valid when ADCONT is high. ADDLY1, 2, and 3 are set to 0 by default. Table 68. ADC Input Specification Table 69. ADDLYx[3:0]

in 4 SPI registers (ADC 4 - ADC 7).

7.7.3 Dedicated Readings

7.7.3.1 Channel 0 Battery Voltage

7.7.3.2 Channel 1 Battery Current (Optional)

ADC by monitoring the voltage drop over the sense resistor between BATTISNSN and BATTISNSP. readings correspond to the current flowing into the battery, and negative readings to the current flowing out of the battery. excessively high values can impact the operating life of the device due to extra voltage drop across the sense resistor. Table 70. Battery Voltage Reading Coding Table 71. Battery Current Reading Coding

81 Freescale Semiconductor

Figure 19. Input Configuration with Battery Current Sense

7.7.3.3 Channel 2 Application Supply

7.7.3.4 Channel 3 Die Temperature

The relation between the read out code and temperature is given in Table 73.

7.7.3.5 Channel 4 Reserved

7.7.3.6 Channel 5 VBUS Voltage

the ADC by multiplying by 0.4.

7.7.3.7 Channel 6 and 7 Reserved

Table 72. Application Supply Voltage Reading Coding Table 73. Die Temperature Voltage Reading

7.7.3.8 Channel 8 Coin Cell Voltage

exceeds the input voltage range of the ADC, the LICELL voltage is scaled as V(LICELL)*2/3. See .

7.7.3.9 Channel 9-11 ADIN9-ADIN11

There are 3 general purpose analog input channels that can be measured through the ADIN9-ADIN11 pins.

7.7.3.10 Channel 12-15 ADIN12-ADIN15

respectively mapped on ADC channels 12, 13, 14, and 15.

7.7.4 Touch Screen Interface

reference. Several readout possibilities are offered. respectively mapped on ADC channels 12, 13, 14, and 15. is masked. Pen detection is only active when TSEN is low. screen conversions, the ADC does not rely on TSREF and the reference is disabled. represents the voltage drop over the contact resistance created by the known current source, multiplied by 2. screen is touched with a finger or a stylus. to read channels indicated in TSSEL0, TSSEL1, and TSSEL2. When TSSTOP[2:0] = 111, all eight addresses will be read. Table 74. Coin Cell Voltage Reading Coding

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system to be pre-biased for the change in touch screen plate polarity. It will read out as ‘0’. the ADC sequence will be overwritten by the Touchscreen data. the last address is converted. TSDLY1, 2, and 3 are set to 0 by default.

• Enable the touch screen with TSEN
• Select the touch screen sequence by pr ogramming the TSSEL0-TSSEL7 SPI bits.
• Program the TSSTOP[2:0]
• Program the delay between the conversi on via the TSDLY1 and TSDLY2 settings.
• Trigger the ADC via the TSSTART SPI bit
• Wait for an interrupt indicating the conversion is done TSDONEI
• And then read out the data in the ADRESULTx registers

Table 75. Touch Screen Action Select

00 Dummy to discharge TSREF cap

01 X plate

10 Y –plate

11 Contact

Table 76. TSDLYx[3:0]

7.7.5 ADC Specifications

Table 77. ADC Electrical Specifications at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted.

• Single ended voltage readings
• Differential readings 0.0 -1.2 2.4 1.2 V tCONVERT Conversion Time per channel - - 10 s Integral Non-linearity - - 3.0 LSB Differential Non-linearity - - 1.0 LSB Zero Scale Error (Offset) - - 5.0 LSB Full Scale Error (Gain) - - 10 LSB Drift over temperature - - 1.0 LSB tON-OFF-ADC Turn on/off time - - 31 s BATTERY CURRENT READING(62) Amplifier Gain 19 20 21 Amplifier Offset -2.0 - 2.0 mV Sense Resistor - 20 - m DIE TEMPERATURE VOLTAGE READING Die Temperature Read Out Code at 25 °C - 680 - Decimal Slope temperature change per LSB - 0.426 - °C/LSB Slope error - - 5.0 % Notes 62. Amplifier Bias Current account ed for in overall ADC current drain

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7.8 Auxiliary Circuits

7.8.1 General Purpose I/Os

configuration these outputs can only be pulled up to 2.5 V maximum. Each individual GPIO has a dedicated 16-bit control register. Table 78 provides detailed bit descriptions. Table 78. GPIOLVx Control

7.8.2 PWM Outputs

PWMxCLKDIV registers shown in Table 79.The base clock will be the 2.0 MHz divided by 32. Table 79. PWMx Duty Cycle Programming Table 80. PWMx Clock Divider Programming

000000 Base Clock

000001 Base Clock / 2

001111 Base Clock / 16

111111 Base Clock / 64

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7.8.3 General Purpose LED Drivers

the red LED will automatically turn on. bit = 1, and programming the duty cycle > 0/32. LEDs of different colors, color mixing can be achieved. each of the drivers using the corresponding CHRGLEDxRAMP bits, only when the repetition rate is 256 Hz. Table 81. LED Driver Control Table 82. General Purpose LED Drivers Current Programming Table 83. General Purpose LED Drivers Duty Cycle Programming

32/32 will take 500 ms, while going to from 8/32 to 16/32 takes 125 ms. when CHRGLEDxRAMP = 0, the change is immediate rather than spread out over a PWM sweep. intensity is set through the PWM duty cycle. in the application, the switching edges of the output drivers are softened. Table 84. General Purpose LED Drivers Period Control Table 85. LED Driver Electrical Specifications and TA = 25 °C under nominal conditions, unless otherwise noted.

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7.8.4 Mini/Micro USB Switch

is also able to identify some non-supported accessories, such as video cables, phone-powered devices, etc. Figure 20. USB Interface

7.8.4.1 Supplies

VUSB2 (detailed Linear Regulators (LDOs)), and VUSB. The IC also provides the 5.0 V supply for USB OTG operation. the main battery. The VUSBSEL SPI bit is used to make the selection between a host or OTG mode operation.

3.3 V USB Analog supply

means that the M0 and MOTG switches are open, while the M1 switch is closed. VINUSB to VBUS will be open. powered by the host by software. Table 86. VUSB Input Source Control (66)

1 OTG mode: SWBST internally switched to supply the VUSB regulator (switch M1 closed, M0 open), and

SWBST will drive VBUS from the VINUSB pin as long as SPI bit OTGEN is set = 1.

1. VUSBSEL = 1 and OTGEN = 1 only close the switch between the VINUSB and VBUS pins, but do not enable the SWBST boost

Table 87. VUSB/OTG Switch Configuration Table 88. VUSB Electrical Characteristics at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted.

• Supplied by VBUS
• Supplied by SWBST 4.4 5.0 5.25 5.75 V IUSB Operating Current Load Range ILMIN to ILMAX 0.0 - 100 mA COVUSB Bypass Capacitor Value Range 0.65 2.2 - F ESRVUSB Bypass Capacitor ESR
• 1 0 kHz - 1.0 MHz 0.0 - 0.1

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7.8.4.2 Accessory Identification

connected. The 32 kHz crystal must be placed across the XTAL 1 and XTAL2 pins for the accessory identification to work. register is set to indicate the device type, and the ATTACH bit in the USB Interrupt Status register is set to inform the baseband. If the attached accessory can't be identified, the Unknown_Atta bit in the USB Interrupt Status register is set. There are three types of accessories that the MC34708 will automatically detect.

1. Recognized and supported. The following accessories are identified and configured automatically: USB port, UART, Audio

Type 1 cable, TTY accessory, USB jig cables, and UART jig cables.

1. Recognized but not supported. The following accessories can be identified but are not supported by the MC34708 PMIC:

detected during a device attach. The over-voltage interrupt is debounce by SUP_OVP_DB[1:0] bits on Table 91.

• V INMIN < VIN < VINMAX ILMIN < IL < ILMA VNOM - 4% 3.3 VNOM + 4% V VUSBLOPP Load Regulation
• 0 < IL < ILMAX from DM / DP, For any VINMIN < VIN < VINMAX - 1.0 - mV/mA VUSBLIPP Line Regulation
• V INMIN < VIN < VINMAX, For any ILMIN < IL < ILMAX - - 20 mV VUSBSCTH Short-circuit Protection threshold
• V INMIN < VIN < VINMAX, Short-circuit VOUT to ground IMAX+20% - - mA tOFF-VUSB Turn-off Time
• Disable to 0.8 V, per USB OTG specification parameter VA_SESS_VLD VIN = VINMIN, VINMAX IL = 0 - - 1.3 sec VUSB ACTIVE MODE - AC VUSBPSRR PSRR - IL = 75% of ILMAX 20 Hz to 20 kHz
• V IN = VINMIN + 100 mV 35 40 - dB VUSBNOISE Output Noise - VIN = VINMIN IL = 75% of ILMAX
• 100 Hz – 50 kHz
• > 5 0 kHz – 1.0 MHz 1.0 0.2 V/Hz

at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted.

1. Not recognized accessories. All accessories that are not recognized are identified as unknown accessories.

Table 89. VBUS Debounce Times Table 90. VBUS High/low Detection Threshold Table 91. Over-voltage Debounce Time SUP_OVP_DB[1:0]

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Figure 21. Identification Flow State Diagram

7.8.4.3 Id Identification

bit will be set to 1. A falling edge of this bit starts the identification flow, and a rising edge starts the detachment detection flow. The ID_DET_END signal is used to indicate the end of the identification. After the ID_FLOATS bit is set to 0, the identification flow is started, and an ADC_EN signal is set to enable an ADC conversion. control when the attached accessory is an Audio Type 1 cable. register. The ADC_EN signal is cleared automatically after the conversion finishes. If the ID resistance is below 2.0 k, the ADC Result is set to 00000. If the ID line is floating, the ADC Result is set to 11111.

7.8.4.4 Stuck Key Identification

baseband of the stuck key status. generated, and the identification flow is re-started to determine the ID resistance of the attached cable.

Figure 22. Stuck Key Process Flow Diagram

7.8.4.5 Power Supply Type Identification

The PSTI (Power Supply Type Identification) circuit is used in Active mode to identify the type of the connected power supply. with the ID detection result, is used to determine what powered accessory is connected. The PSTI circuit is shown in Figure 23. Its operation is described as follows. When the MC34708 detects that the VBUS_DET bit is set, the PSTI identification flow starts.

1. Wait for a Detection Delay t D (programmable in the USB Time Delay register).
2. During t D, check to see whether ID_FLOAT = 0. If yes, then wait for the ID_DET_END to be set and check whether the

attached accessory is an A/V cable.

1. If the result is an A/V cable, set the A/V_CHG and ATTACH interrupt bits, as well as the A/V bit in USB Device Type/Status

register, to inform the baseband and finish the identification flow. If not, go to step 4.

1. Enable the PSTI (PSTI_EN set to '1') at t1. When PSTI_EN rises, the SW1 switch is turned on to drive the VDAT_SRC

current from the DM line. At t2, the PSTI starts to compare the DM line voltage with references VDAT_REF and VCR_REF. determine the type of accessory, based on the DM voltage.

1. The state machine checks if the ID pin is floating. If the ID pin is not floating at t3, the PSTI circuit turns off SW1 and SW2,
2. The state machine decides on the attached accessory, based on the ID identification, and the VBUS identification results.

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Figure 23. Power Supply Type Identification Circuit Block Diagram Figure 24. Operating Waveforms for the PSTI Circuit

can be found in the SPI/I2C Register Map section. The details of some important control bits are described as follows. Table 92. Timing Delays for PSTI Circuit at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted.

• T D = 0000
• T D = 0001
• T D = 0010
• T D = 0011
• T D = 0100
• ...
• T D = 1111 ... 100 200 300 400 500 ... 1600 ... ms tSW t2 - t1 20 - - ms tSW t3 - t2 20 - - ms tSW t4 - t1 100 - - ms tSW t6 - t3 100 - - ms

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7.8.4.6 Control Functions

7.8.4.6.1 Timing of the S witching Action (WAIT BIT)

Figure 25. Operating Waveforms of the Wait Bit

7.8.4.6.2 Automatic Switchi ng OR Manual Switching (Switch_open & Manual S/W Bits)

S/W bit and the Switch_Open bits in the USB Manual SW/Result and USB Control/Device mode registers respectively. If the Switch_Open bit is '0', the audio, UART, and USB switches are off. Result register and the switches to be turned on is found in SPI/I2C Register Map section. Switch_Open = 1, sets the switches according to the Manual S/W bit.

information when RAW DATA = 1 can be found in Audio Type 1 Operation Mode. Type 1 and other accessories will not be affected by the RAW DATA bit. LKR and the button bits will not set when RAW DATA = 0. Type 1 and other accessories will not be affected by the RAW DATA bit.

7.8.4.7 Analog and Digital Switches

identification result, the configuration of the switches vs. the device type is shown in Table 93. on whenever the FET_ON bit is '0'. Figure 26. Analog and Digital Switches

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7.8.4.8 Audio Type 1 Operation Mode

turned on, and the MOTG, and M0 switches are turned off, to isolate the VBUS pin. Figure 28. If a key is pressed for a time less than 20 ms, the MC34708 ignores it. If the key is still pressed after 20 ms, the time: Error key press, short key press, and long key press.

1. Error key press: if the key press time is less than TKP, the Error bit in the USB Button register and the short key press bit

Button register is read or the next key press happens. The KP bit is cleared when the Interrupt 1 register is read.

1. Short key press: if the key press time is between TKP an d TLKP, the KP bit and the corresponding button bit in USB

register is read. The KP bit is cleared when the USB Interrupt Sense register is read.

1. Long key press: if the key press time is longer than TLKP, the long key press bit LKP in the USB Interrupt Sense register,

Interrupt 2 register is set to interrupt the baseband again. Figure 27. Audio Accessory with Remote Control and Microphone Table 93. Switch Configuration When Controlled by the Device Type Register

1. Switches M0, M1, and MOTG are controlled by software by the OTGEN and VUSBSEL bits.

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Functional Block Description

7.8.4.9 JiG Cable USB and UART

The JIG cable is used for test and development and has an ID resistance to differentiate it from a regular USB cable. The Jig cable has 2 ID resistance values to resemble a USB JIG type1/2, and 2 ID resistance values to resemble a UART JIG type1/2 cable.

7.8.4.9.1 USB JIG Cable 1 or 2

Under normal operation, setting the control bits when the identified accessory is a USB JIG 1 or 2 cable, both the DPLUS to DP, the DMINUS to DM switches are switched on. When SW_HOLD = 0, the switching action of DPLUS to DP, and the DMINUS to DM switches are controlled by the WAIT bit. If WAIT = 1, the signal switches will be turned ON after a WAIT. If WAIT = 0, the signal switches won't be turned on until the WAIT bit is set to '1' by the SPI/I2C. When SW_HOLD = 1, regardless of what the WAIT is set to, '0' or '1', the signal switches are turned on, once the USB JIG cable is identified. The ID detector and the VBUS detector both monitor the detachment of the USB JIG cable. The ID detection circuit continues to be ON for detachment detection in the Active mode. When the ID_FLOAT is set, the Detach bit in the Interrupt Status 0 register is set to inform the host. When the USBDETS is set to '0', which means either the VBUS power is removed or the cable is detached, the Detach bit is also set to inform the host. The mini USB interface moves to the Standby mode. If the Detach bit is set, due to the removing only the VBUS or the ID resistance, and the cable is not detached completely, the identification flow will be triggered again. The ID_FLOAT bit or USBDETS bit still indicate that an accessory is connected when the mini USB interface moves to the Standby mode. All the signal switches are turned off

7.8.4.9.2 UART JIG Cable 1 or 2

Under normal operation, setting the control bits when the identified accessory is a UART JIG cable 1 or 2, both the RxD to DP and the TxD to DM switches are switched on. When SW_HOLD = 0, the switching action of RxD to DP, and the TxD to DM switches, are controlled by the WAIT bit. If WAIT = 1, the signal switches will be turned on after a WAIT time. If WAIT = 0, the signal switches won't be turned on until the WAIT bit is set to '1' by the SPI/I2C. When SW_HOLD = 1, regardless of what the WAIT is set to, '0' or '1', the signal switches are turned on, once the UART JIG cable is identified. The ID detection comparator continues to be ON for detachment detection in the Active mode. When the ID_FLOAT is set, the Detach bit in the Interrupt Status 0 register is set to inform the host that the accessory is detached. The mini USB interface then enters the Standby mode.

7.8.4.10 TTY Operation Mode

A TTY converter is a type of audio accessory. It has its own ID resistance. When a TTY converter is attached, this sets the TTY bit in the USB Device Type register and the Attach interrupt bit in the Interrupt Status 0 register. During normal operation, when setting the control bits, the automatic switch configuration of the TTY converter, is similar to that of an Audio Type 1 accessory. The SPK_R to DP switch, and MIC to VBUS switch are turned on, but the SPK_L to DM switch can only be turned on when TTY_SKPL bit in USB Control register is manually set to 1. In addition, the MOTG, and M0 switches are turned off to isolate the VBUS pin.The TTY accessory doesn’t support the remote control key. The Power Save mode operation and the detachment detection are the same as those of the Audio Type 1 device.

7.8.4.11 UART Operation Mode

During normal operation, when setting the control bits, when the identified accessory is a UART cable, both the RxD and the TxD switches are switched on (see Figure 30). The ID detection comparator continues to be ON for detachment detection in the Active mode. When the ID_FLOAT is set, the Detach bit in the USB interrupt Sense register, is set to inform the host that the accessory is detached. The MC34708 USB detection then enters Standby mode.

Figure 30. UART Operation

7.8.4.12 USB Host (PC or HUB) Operation Mode

input current limit and sets the bit USB in the USB Device type register. the baseband. The MC34708 USB detection then enters the Standby mode. Figure 31. USB Operation

7.8.4.13 USB charger or Dedi cated Charger Operation Mode

MINUS switches are turned on for the USB Charger, but not for the Dedicated Charger. detachment. Unplugging the mini-USB connector and unplugging the AC side, both lead to the same detachment conclusion. The Detach bit is set to inform the host. The MC34708 USB detection then enters the Standby mode.

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or A/V in the USB device type register. Detach bit is set to inform the host. Then the MC34708 USB detection enters the Standby mode.

7.8.4.15 Charger Input Current Limit Setting

When the Manual SW_B bit is set to 1, the MC34708 automatically detects what device is attached.

7.8.4.16 Unknown Accessory Operation Mode

7.8.4.17 Software Reset

consequence of the software reset is the same as the hardware reset. All register bits reset by the Mini-USB will be reset.

7.8.4.18 ID Resistance Value Assignment

Functions filled are ones that are already used with special functions. The ones reserved can be assigned to other functions. Table 94. ID Detection Thresholds master or no device) is attached.

1. UID maximum voltage is 5.25 V

Table 95. ID Resistance Assignment

Figure 32. Remote Control Architecture

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7.8.4.19 USB Interface Electrical Specifications

Table 96. ID Remote Control Values Table 97. USB Interface Electrical Characteristics at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted.

• In Standby mode
• When accessory is attached & INT_MASK = ‘1’
• In Active mode (VDD < VBUS)
• In Active mode (VDD < VBUS) 125 550 850 160 650 1000 IVBUS VBUS Supply Quiescent Current
• In VBUS OTG
• In Active mode - Audio or TTY 1.5 0.5 mA Accessory Detect Switch RSPK_ON RSPK_ONMCT RSPK_ONFLT SPK_L and SPK_R Switches
• On resistance (20 Hz to 470 kHz)
• Matching between channels
• On resistance flatness (from -1.2 to 1.2 V) 3.0 0.3 W RUSB_ON RUSB_ONMCT RUSB_ONFLT D+ and D- Switches
• On resistance (0.0 Hz to 240 MHz)
• Matching between channels
• On resistance flatness (from 0.0 to 3.3 V) 5.0 0.1 0.02 8.0 1.0 0.4 W

• On resistance
• On resistance flatness (from 0.0 to 3.3 V) 6.0 W RMIC_ON MIC Switches
• On resistance (at 1.5 V MIC bias voltage) - 75 150 W RPD_AUDIO Pull-Down Resistors between SPK_L or SPK_R Pins to GND - 100 - k Signal Voltage Range
• M I C
• SPK_L, SPK_R
• D+, D-, RxD, TxD -1.5 -0.3 1.5 1.5 3.6 V VA_PSRR PSRR - From BP (100 mVrms) to DP/DM Pins
• 2 0 Hz to 20 kHz with 32/16  load. - - -60 dB THD Total Harmonic Distortions
• 2 0 Hz to 20 kHz with 32/16  load. - - 0.05 VA_CT Crosstalk between Two Channels
• 2 0 Hz to 20 kHz with 32/16  load. - - -50 dB VA_ISO Off Channel Isolation
• Less than 1.0 MHz - - -100 dB Power Supply Type Identification VDAT_SRC Data Source Voltage
• Loaded by 0~200 μA 0.5 0.6 0.7 V IDAT_SRC Data Source Current 0.0 - 200 μA VDAT_REF Data Detect Voltage 0.3 0.35 0.4 V VCR_REF Car Kit Detect Voltage 0.8 0.9 1.0 V IDAT_SINK Data Sink Current
• DM pin is biased between 0.15 to 3.0 V 65 100 135 μA CDP/DM DP, DM Pin Capacitance - 8.0 - pF RDP/DM DP, DM Pin Impedance
• All switches are off (Switch_Open = 0) - 50 - ID Detection VFLOAT ID FLOAT Threshold
• Detection threshold - 2.3 - V tID_FLOAT ID FLOAT Detection Deglitch Time - 20 - ms IID Pull-up Current Source
• When ADC Result is 1xxxx
• When ADC Result is 0xxxx 1.9 30.4 2.0 2.1 33.6 μA IVCBL VVCBL_L VVCBL_H Video Cable Detection
• Detection current
• Detection voltage low threshold
• Detection voltage high threshold 1.0 1.2 118 1.4 mA mV mV

at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted.

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7.9 Serial Interfaces

7.9.1 SPI Interface

integrated pull down), then the bus configuration will be latched for SPI mode. conventions for bit positions corresponding to common functionality with previous generation FSL products.

7.9.1.1 SPI Interface Description

For a SPI read, the first bit sent to the IC must be a zero indicating a SPI read cycle. Next, the six bit address is sent MSB first. can clock them in on the rising edge of the SPI clock. internal contents of the field addressed do not change when the 32nd CLK is sent. Table 98. SPI / I2C Bus Configuration

1. CS held low at Cold Start, configures the interface for SPI mode; once activated, CS functions as the SPI Chip Select.
2. CS tied to VCOREDIG at Cold St art, configures the interface for I2C mode; the pin is not used in I2C mode, other than for configuration.
3. In I 2C mode, the MOSI pin is hardwired to ground, or VCOREDIG is used to select between two possible addresses.

at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted.

written to the SPI register whose address was sent at the start of the SPI cycle on the falling edge of the 32nd SPI clock. the data is transferred into the actual registers on the falling edge of the 32nd CLK. high again. The MISO line will be tri-stated while CS is low. at the beginning of the SPI sequence. Figure 33. SPI Transfer Protocol Single Read/Write Access Figure 34. SPI Transfer Protocol Multiple Read/Write Access

24 Bits Data

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7.9.1.2 SPI Timing Requirements

Figure 35. SPI Interface Timing Diagram Table 99. SPI Interface Timing Specifications(72)

1. This table reflects a maxi mum SPI clock frequency of 26 MHz.

Analog Integrated Circuit Device Data Freescale Semiconductor 110 MC34708 Functional Block Description

7.9.2 I 2C Interface

7.9.2.1 I 2C Configuration

When configured for I2C mode, the interface may be used to access the complete register map previously described for SPI access. Since SPI configuration is more typical, references within this document will generally refer to the common register set as a “SPI map” and bits as “SPI bits”; however, it should be understood that access reverts to I2C mode when configured as such. The SPI pins CLK and MISO are reused for the SCL and SDA lines respectively. Selection of I2C mode for the interface is configured by hard-wiring the CS pin to VCOREDIG on the application board. The state of CS is latched in during the initialization phase of a Cold Start sequence, so the I2CS bit is defined for bus configuration before the interface is activated. The pull-down on CS will be deactivated if the high state is detected (indicating I2C mode). In I2C mode, the MISO pin is connected to the bus as an open drain driver, and the logic level is set by an external pull-up. The part can function only as an I2C slave device, not as a host.

7.9.2.2 I 2C Device ID

I2C interface protocol requires a device ID for addressing the target IC on a multi-device bus. To allow flexibility in addressing for bus conflict avoidance, pin programmable selection is provided to allow configuration for the address LSB(s). This product supports 7-bit addressing only; support is not provided for 10-bit or general Call addressing. Because the MOSI pin is not utilized for I2C communication, it is reassigned for pin programmable address selection by hardwiring to VCOREDIG or GND at the board level when configured for I2C mode. MOSI will act as Bit 0 of the address. The I2C address assigned to FSL PM ICs (shared amongst our portfolio) is given as follows: 00010-A1-A0, the A1 and A0 bits are allowed to be configured for either 1 or 0. The A1 address bit is internally hardwired as a “0”, leaving the LSB A0 for board level configuration. The designated address then is defined as: 000100-A0.

7.9.2.3 I 2C Operation

The I2C mode of the interface is implemented generally following the Fast Mode definition which supports up to 400 kbits/s operation. (Exceptions to the standard are noted to be 7-bit only addressing, and no support for general Call addressing) Timing diagrams, electrical specifications, and further details on this bus standard, is available on the internet, by typing  “I2C specification” in the web search string field. Standard I2C protocol utilizes bytes of 8 bits, with an acknowledge bit (ACK) required between each byte. However, the number of bytes per transfer is unrestricted. The register map is organized in 24 bit registers which corresponds to the 24 bit words supported by the SPI protocol of this product. To ensure that I2C operation mimics SPI transactions in behavior of a complete 24 bit word being written in one transaction, software is expected to perform write transactions to the device in 3-byte sequences, beginning with the MSB. Internally, data latching will be gated by the acknowledge at the completion of writing the third consecutive byte. Failure to complete a 3-byte write sequence will abort the I2C transaction and the register will retain its previous value. This could be due to a premature STOP command from the master, for example. I2C read operations are also performed in byte increments separated by an ACK. Read operations also begin with the MSB and 3-bytes will be sent out unless a STOP command or NACK is received prior to completion. The following examples show how to write and read data to the IC. The host initiates and terminates all communication. The host sends a master command packet after driving the start condition. The device will respond to the host if the master command packet contains the corresponding slave address. In the following examples, the device is shown always responding with an ACK to transmissions from the host. If at any time a NAK is received, the host should terminate the current transaction and retry the transaction.

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Figure 36. I2C 3-byte Write Example Figure 37. I2C 3-byte Read Example

7.9.3 SPI/I 2C Specification

7.10 Configuration Registers

7.10.1 Register Set structure

implied as generically applicable to the register set accessible by either interface. Table 100. SPI/I2C Electrical Characteristics at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted.

• Output sink 100 A 0.0 - 0.2 V VMISOHI/ VINTHI Output High MISO, INT
• Output source 100 A SPIVCC-0.2 - SPIVCC V VCC-SPI SPIVCC Operating Range 1.75 - 3.6 V tMISOET MISO Rise and Fall Time, CL = 50 pF, SPIVCC = 1.8 V
• S P I D R V [1:0] = 00
• S P I D R V [1:0] = 01 (default)
• S P I D R V [1:0] = 10
• S P I D R V [1:0] = 11 6.0 2.5 3.0 2.0 ns

Table 101. Register Set

0 Interrupt Status 0 16 Memory A 32 Regulator Mode 0 48 ADC5

1 Interrupt Mask 0 17 Memory B 33 GPIOLV0 Control 49 ADC6

2 Interrupt Sense 0 18 Memory C 34 GPIOLV1 Control 50 ADC7

3 Interrupt Status 1 19 Memory C 35 GPIOLV2 Control 51 Input Monitoring

4 Interrupt Mask 1 20 RTC Time 36 GPIOLV3 Control 52 Supply Debounce

5 Interrupt Sense 1 21 RTC Alarm 37 USB Timing 53 VBUS monitoring

6 Power Up Mode Sense 22 RTC Day 38 USB Button 54 LED Control

7 Identification 23 RTC Day Alarm 39 USB Control 55 PWM Control

8 Regulator Fault Sense 24 Regulator 1 A/B Voltage 40 USB Device Type 56 Unused

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7.10.2 Specific Registers

7.10.2.1 IC and Version Identification

7.10.2.2 Embedded Memory

can be maintained in these registers to validate confidence in the RTC contents when power is restored after a power cut event. Alternatively, the banks can be used for any system need for bit retention with coin cell backup.

9 Reserved 25 Regulator 2 & 3 Voltage 41 Unused 57 Unused

10 Reserved 26 Regulator 4 A/B Voltage 42 Unused 58 Unused

11 Reserved 27 Regulator 5 Voltage 43 ADC 0 59 Unused

12 Unused 28 Regulator 1 & 2 Mode 44 ADC 1 60 Unused

13 Power Control 0 29 Regulator 3, 4 and 5 Mode 45 ADC 2 61 Unused

14 Power Control 1 30 Regulator Setting 0 46 ADC 3 62 Unused

15 Power Control 2 31 SWBST Control 47 ADC4 63 Unused

Table 102. IC Revision Bit Assignment

• Pass 2.4 = 010 METAL_LAYER_REV[2:0] XXX Represents the metal layer revision
• Pass 2.4 = 100 FIN[2:0] 000 FIN version
• Pass 2.4 = 000 FAB[2:0] 000 FAB Version
• Pass 2.4 = 000

7.10.3 SPI/I 2C Register Map

The complete SPI bitmap is given in Table 103. Table 103. SPI/I2C Register Map Legend Table 104. SPI/I2C Register Map

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7 Identification

12 Unused NU h00_00_00

16 Memory A

17 Memory B

18 Memory C

19 Memory D

20 RTC Time

21 RTC Alarm

22 RTC Day

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37 USB Timing

38 USB Button

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39 USB control

43 ADC 0

44 ADC 1

45 ADC 2

46 ADC 3

47 ADC 4

48 ADC 5

49 ADC 6

50 ADC 7

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54 LED Control

55 PWM Control

7.10.4 SPI Register’s Bit Description

Table 105. Register 0, Interrupt Status 0 Table 106. Interrupt Mask 0

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Table 107. Register 2, Interrupt Sense 0 Table 108. Register 3, Interrupt Status 1

Table 109. Register 4, Interrupt Mask 1

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Table 110. Register 5, Interrupt Sense 1 Table 111. Register 6, Power Up Mode Sense

1. L = Loaded PUMSx level at startup.

Table 112. Register 7, Identification

Table 113. Register 8, Regulator Fault Sense Table 114. Register 9 , Reserved Table 115. Register 10, Reserved Table 116. Register 11, Reserved Table 117. Register 12, Unused

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Table 118. Register 13, Power Control 0

1. Reset by RTCPORB but not during a GLBRST (global reset)

Table 119. Register 14, Power Control 1 Table 120. Register 15, Power Control 2

Table 121. Register 16, Memory A Table 122. Register 17, Memory B Table 123. Register 18, Memory C Table 124. Register 19, Memory D Table 125. Register 20, RTC Time

1. Reset by RTCPORB but not during a GLBRST (global reset)

Table 126. Register 21, RTC Alarm

1. Reset by RTCPORB but not during a GLBRST (global reset)

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Table 127. Register 22, RTC Day

1. Reset by RTCPORB but not during a GLBRST (global reset)

Table 128. Register 23, RTC Day Alarm

1. Reset by RTCPORB but not during a GLBRST (global reset)

Table 129. Register 24, Regulator 1A/B Voltage Table 130. Register 25, Regulator 2 & 3 Voltage Table 131. Register 26, Regulator 4A/B

Table 132. Register 27, Regulator 5 Voltage Table 133. Register 28, Regulators 1 & 2 Operating Mode

1. SWxMODE[3:0] bits will be reset to their default values by the startup sequencer, based on PUMS settings. An enabled

switch will default to APS mode for both Normal and Standby operation. Table 134. Register 29, Regulators 3, 4, and 5 Operating Mode

1. SWxMODE[3:0] bits will be reset to their default values by the startup sequencer, based on PUMS settings. An enabled

regulator will default to APS mode for both Normal and Standby operation.

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Table 135. Register 30, Regulator Setting 0 Table 136. Register 31, SWBST Control Table 137. Register 32, Regulator Mode 0

Table 138. Register 33, GPIOLV0 Control

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Table 139. Register 34, GPIOLV1 Control

Table 140. Register 35, GPIOLV2 Control

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Table 141. Register 36, GPIOLV3 Control

Table 142. Register 37, USB timing conversion of the resistance at ID pin when RAW DATA = 0.

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Table 143. Register 38, USB Button Table 144. Register 39, USB Control immediately when this bit is changed to 1. bits in Timing Set 2 register before turning on the switches. ADC Result changes on ID pin to the host. status changes and report the key press events to the host.

1: Switch selection according to the Manual S/W bit. 10: VBUS connects to MIC. M0, MOTG.

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Table 145. Register 40, USB Device Type Table 146. Register 41 and 42, Unused Table 147. Register 43, ADC 0 000 and read up to and including this channel value. THERM 8 R/W DIGRESETB 0x0 0 = Disable manual LED control.

TSEN 12 R/W DIGRESETB 0x0 Enable the Touch screen from low power mode. must be off for Pen Detection. Table 148. Register 44, ADC 1 ADDLY1[3:0] 3-0 R/W DIGRESETB 0x0 This will allow delay before the ADC readings. ADDLY2[3:0] 7:4 R/W DIGRESETB 0x0 This will allow delay between each of ADC readings in a set. TSDLY1[3:0] 15-12 R/W DIGRESETB 0x0 This will allow delay before the ADC Touch screen readings. ADC readings to prevent code replacement in the system. to prevent code replacement in the system. Table 149. Register 45, ADC 2

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Table 150. Register 46, ADC 3 TSSEL0[1:0] 9-8 R/W DIGRESETB 0x0 Touchscreen Selection to place in ADRESULT0. TSSEL1[1:0] 11-10 R/W DIGRESETB 0x0 Touchscreen Selection to place in ADRESULT1. TSSEL2[1:0] 13-12 R/W DIGRESETB 0x0 Touchscreen Selection to place in ADRESULT2. TSSEL3[1:0] 15-14 R/W DIGRESETB 0x0 Touchscreen Selection to place in ADRESULT3. TSSEL4[1:0] 17-16 R/W DIGRESETB 0x0 Touchscreen Selection to place in ADRESULT4. TSSEL5[1:0] 19-18 R/W DIGRESETB 0x0 Touchscreen Selection to place in ADRESULT5. TSSEL6[1:0] 21-20 R/W DIGRESETB 0x0 Touchscreen Selection to place in ADRESULT6. TSSEL7[1:0] 23-22 R/W DIGRESETB 0x0 Touchscreen Selection to place in ADRESULT7. Table 151. Register 47, ADC 4 Table 152. Register 48, ADC5

Table 153. Register 49, ADC6 Table 154. Register 50, ADC7 Table 155. Register 51, Input Monitoring Table 156. Register 52, Input Debounce

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Table 157. Register 53, VBUS Monitoring Table 158. Register 54, LED Control Table 159. Register 55, PWM Control Table 160. Register 56 to 63, Unused

8 Typical Applications

details on component references and additional components such as filters, refer to the individual sections.

8.1 Application Diagram

Figure 38. Typical Application Schematic i.e., PA thermistor, Light Sensor, Etc.

32.768 KHz

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8.2 Bill of Material

equivalent components may be used. Table 161. MC34708 Bill of Material (81)

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• NSS12100UW3
• 2SB1733 On Semi Rohm VDAC PNP 54 1 C36 2.2 F VVDAC VUSB2 55 1 Q1 PNP transistor
• NSS12100UW3
• 2SB1733 On Semi Rohm VUSB2 PNP 56 1 C29 2.2 F VUSB2 VUSB 57 1 C47 2.2 F VUSB VGEN1 58 1 C38 4.7 F VGEN1 VGEN2 59 1 Q5 PNP Transistor
• NSS12100UW3
• 2SB1733 On Semi Rohm VGEN2 PNP 60 1 C41 2.2 F VGEN2 WORKAROUNDS 61 1 U2

1.5 V LDO

• NCP4682
• NCP4685 On Semi 1.5 V LDO for workaround. See erratum #23 on ER34708 62 1 D15 Schottky diode Low voltage Schottky diode 63 1 C58 100 nF LDO input capacitor

1 C59 100 nF LDO output capacitor

1. Freescale does not assume liability, endorse, or warrant comp onents from external manufacturers that are referenced in circuit

Analog Integrated Circuit Device Data Freescale Semiconductor 148 MC34708 Typical Applications

8.3 MC34708 Layout Guidelines

8.3.1 General board recommendations

1. It is recommended to use an 8 layer board stack-up arranged as follows:

• High current signal
• G N D
• S i g n a l
• Power
• Power
• S i g n a l
• G N D
• High current signal 2. Allocate TOP and BOTTOM PCB Layers for POWER ROUTIN G (high current signals), copper-pour the unused area. 3. Use internal layers sandwiched between two GND planes for the SIGNAL routing.

8.3.2 Component Placement

Sense resistors should be placed as Close to the IC as possible. Route the high current path flowing from VBATT to BATTISNSN as thick and as short as possible to reduce power losses.

8.3.3 General Routing Requirements

1. Some recommended things to keep in mind for manufacturability:

• Via in pads require a 4.5 mil Minimum annular ring. Pad must be 9.0 mils larger than the hole
• Max copper thickness for lines less than 5.0 mils wide is 0.6 oz copper
• Minimum allowed spacing between line and hole pad is 3.5 mils
• Minimum allowed spacing between line and line is 3.0 mils 2. Care must be taken with SWxFB pins traces. These signals are susceptible to noise and must be routed far away from power, clock, or high power signals, like the ones on the SWxIN, SWx, SWxLX, SWBSTIN, SWBST, and SWBSTLX pins. 3. Shield feedback traces of the switching regulators and keep them as short as possible (trace them on the bottom so the ground and power planes shield these traces). 4. Sense pins must be directly connected to the 0.02 Ohm sense resistor R1 (BATTISNSN and BATTISNSP). 5. Avoid coupling trace between important signal/low noise supplies (like VREFCORE, VCORE, VCOREDIG) from any switching node (i.e. SW1ALXx, SW2LXx, SW3LXx, SW4ALX, SW4BLX, SW5LXx and SWBSTLXx). 6. Make sure that all components related to an specific block are referenced to the corresponding ground, e.g. all components related to the SW1 converter must referenced to GNDSW1A1 and GNDSW1A2.

8.3.4 Parallel Routing Requirements

1. SPI/I 2C signal routing:

• CLK is the fastest signal of the system, so it must be given special care. Here are some tips for routing the communication signals:
• To avoid contamination of these delicate signals by nearby high power or high frequency signals, it is a good practice to shield them with ground planes placed on adjacent layers. Make sure the ground plane is uniform throughout the whole signal trace length.

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Figure 39. Recommended Shielding for Critical Signals.

• These signals can be placed on an outer layer of the board to reduce their capacitance in respect to the ground plane.
• The crystal connected to the XTAL1 and XTAL2 pi ns must not have a ground plane directly below.
• The following are clock signals: CLK, CLK32K, CLK32KMCU, XTAL1, and XTAL2. These signals must not run parallel to each other, or in the same routing layer. If it is necessary to run clock signals parallel to each other, or parallel to any other signal, then follow a MAX PARALLEL rule as follows:
• Up to 1 inch parallel length – 25 mil minimum separation
• Up to 2 inch parallel length – 50 mil minimum separation
• Up to 3 inch parallel length – 100 mil minimum separation
• Up to 4 inch parallel length – 250 mil minimum separation
• Care must be taken with these signals not to contami nate analog signals, as they are high frequency signals. Another good practice is to trace them perpendicularly on different layers, so there is a minimum area of proximity between signals. 2. The traces BATTISNSN and BATTISNSP that go to the R1 resistor must run in parallel.

8.3.5 Differential Routing

1. DP and DM traces should be routed as 90 ohm differential signals.
2. DPLUS and DMINUS traces should be routed as 90 ohm differential signals.

8.3.6 Switching Regulator Layout Recommendations

1. Per design, the MC34708 is designed to operate with only 1 input bulk capacitor. However, it is recommended to add a

range of 100 nF and should be placed right next to or under the IC, closest to the IC pins.

1. Make high-current ripple traces low inductance (short, high W/L ratio).
2. Make high-current traces wide or copper islands.
3. Make high-current traces SYMETRICAL for dual–phase regulators (SW1, SW4).

Analog Integrated Circuit Device Data

151 Freescale Semiconductor

8.4 Thermal Considerations

8.4.1 Rating Data

The thermal rating data of the packages has been simulated with the results listed in Table 5. Junction to Ambient Thermal Resistance Nomenclature: the JEDEC specification reserves the symbol RθJA or θJA (Theta-JA) strictly for junction-to-ambient thermal resistance on a 1s test board in natural convection environment. RθJMA or θJMA (Theta- JMA) will be used for both junction-to-ambient on a 2s2p test board in natural convection and for junction-to-ambient with forced convection on both 1s and 2s2p test boards. It is anticipated that the generic name, Theta-JA, will continue to be commonly used. The JEDEC standards can be consulted at http://www.jedec.org/

8.4.2 Estimation of Junction Temperature

An estimation of the chip junction temperature TJ can be obtained from the equation TJ = TA + (RθJA x PD) with TA = Ambient temperature for the package in °C RJA = Junction to ambient thermal resistance in °C/W PD = Power dissipation in the package in W The junction to ambient thermal resistance is an industry standard value that provides a quick and easy estimation of thermal performance. Unfortunately, there are two values in common usage: the value determined on a single layer board RθJA and the value obtained on a four layer board RθJMA. Actual application PCBs show a performance close to the simulated four layer board value although this may be somewhat degraded in case of significant power dissipated by other components placed close to the device. At a known board temperature, the junction temperature TJ is estimated using the following equation TJ = TB + (RθJB x PD) with TB = Board temperature at the package perimeter in °C RθJB = Junction to board thermal resistance in °C/W PD = Power dissipation in the package in W When the heat loss from the package case to the air can be ignored, acceptable predictions of junction temperature can be made. See Thermal Characteristics for more details on thermal management.

9 Package Mechanical Dimensions

13x13 mm, 0.8 mm pitch package. www.freescale.com and perform a keyword search for the drawing’s document number. Table 162. Package Drawing Information

Analog Integrated Circuit Device Data

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Package Mechanical Dimensions 9.1 206-pin MAPBGA (8 x 8), 0.5 mm VK SUFFIX (PB-FREE) 206-PIN 98ASA00312D ISSUE 0

Analog Integrated Circuit Device Data Freescale Semiconductor 154 MC34708 Package Mechanical Dimensions VK SUFFIX (PB-FREE) 206-PIN 98ASA00312D ISSUE 0

Analog Integrated Circuit Device Data

155 Freescale Semiconductor

Package Mechanical Dimensions 9.2 206-pin MAPBGA (13 x 13), 0.8 mm VM SUFFIX (PB-FREE) 206-PIN 98ASA00299D ISSUE A

Analog Integrated Circuit Device Data Freescale Semiconductor 156 MC34708 Package Mechanical Dimensions VM SUFFIX (PB-FREE) 206-PIN 98ASA00299D ISSUE A

157 Freescale Semiconductor

10 Reference Section

Table 163. MC34708 Reference Documents

Analog Integrated Circuit Device Data Freescale Semiconductor 158 MC34708

Revision History

REVISION DATE DESCRIPTION OF CHANGES 6.0 7/2011 • Initial release 7.0 10/2011 • Corrected the two pins SW2PWGD and SDWNB, and associated drawings.

• Changed LED Driver Electrical Specifications, VPLL Matching from 3.0 to 4.0%
• Changed VPLL Electrical Specification, tON-VPLL from 100 to 120 s
• Changed SWBST Electrical Specifications, ILEAK_SWBST from 5.0 to 6.0 A
• Added Max limit to Charger Input Current Limit (Using the USB input).
• Added note (58) to VREFDDR
• Changed R USB ON value to 5.0 typ, 8.0 max
• Set MIC bias to 1.5 V, and changed ON resistance values to 75 typ and 150 max.
• Added Efficiency values for all Buck Converter
• Added diodes to the LX pin on SW1, SW2, SW3, SW4A, SW4B, and SW5.
• Updated schematics to reflect the LX pin diodes on SW1, SW2, SW3, SW4A, SW4B, and SW5, and removed the 10 F VBUSVIN input capacitor. 8.0 7/2012 • Removed charger and coulomb counter functionality throughout the document. Section 7.6 removed.
• Updated Figure 1, Figure 2, Figure 3, Figure 4 , Figure 38, Figure 20, Figure 26, Figure 28, Figure 30, Figure 31, Figure 40.
• Update Table 3
• Pin function changed to “O” on pins VCORE, VCOREDIG, VALWAYS, VCOREREF, VDDLP , and TSREF.
• Pin function to “I” on pins ADIN11, TSX1/ADIN12, TSX2/ADIN13, TSY1/ADIN14 and TSY2/ADIN15
• Description for unsupported charger and coulomb counter pins modified.
• Clarified ICTEST description
• Update Table 4 with maximum pin rating for all blocks.
• Added Table 7 “Die Temp Debounce Settings”
• Updated thermal monitor operation in section 5.2.1
• Removed PRETMR, ITRICKLE, VSRT and ADC specifications in Table 9.
• Changed typ current spec for ON Standby (LPM) from 260 uA to 340uA, changed ON Standby Digital Core from 370uA to 480uA and removed all charger conditions in Table 10.
• Updated section 6.1 feature list
• Renamed all instances of APSKIP to APS.
• Updated Table 15: VSRTC quiescent current to 1.7uA @1.2V setting and 2.7uA @ 1.3V setting.
• GLBRSTTMR[1:0], value “00” changed to Invalid option in Table 24.
• Removed interrupt, mask and sense bit related to charger and coulomb counter in Table 21.
• Changed debounce time for THERMxxx interrupts.
• Updated SW4A/B operation and removed 3.3V setting from SW4A/B in section 7.5.4.6
• Removed AUX attach in section 7.5.3.4
• Replaced “Under Voltage Detection” event in section 7.5.3.5 with “BP lower than VBAT_TRKL” event.
• Changed UVDET threshold to 3.1V (rising)/ 2.65V (falling) in Table 27
• Added PWMPS mode description on Table 31
• Changed quiescent currents for all switching regulators ISWxQ in PWMPS and APS modes.
• LDO Short Circuit Protection feature no longer supported.
• Changed ADC channels 4 and 7 to “Reserved”
• Added Figure 19
• Removed VBATTREMTH specification from Table 77
• Added section 7.8.3
• Removed charger support from section 7.8.4
• Removed IVBUS quiescent current specification for dedicated charger condition in Table 97
• Updated components to BOM in section 8.2
• Updated SPI register map
• Replaced Figures 42-45 with Table 104 SPI/I2C Register Map
• Updated Table 101 and Table 104 to match removed functionality
• Updated Table 105 through Table 158 to match removed functionality

Document Number: MC34708 Rev. 8.0 Information in this document is provided solely to enable system and software implementers to use Freescale products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. Freescale reserves the right to make changes without further notice to any products herein. Freescale makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including “typicals,” must be validated for each customer application by customer’s technical experts. Freescale does not convey any license under its patent rights nor the rights of others. Freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: store.esellerate.net/store/Policy.aspx?Selector=RT&s=STR0326182960&pc. How to Reach Us: Home Page: freescale.com Web Support: freescale.com/support Freescale, the Freescale logo, AltiVec, C-5, CodeTest, CodeWarrior, ColdFire, C- Ware, Energy Efficient Solutions logo, Kinetis, mobileGT, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony, and VortiQa are trademarks of ColdFire+, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, Ready Play, SafeAssure, SMARTMOS, TurboLink, Vybrid, and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.