34701_07 FREESCALE | Alldatasheet
Document overview
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- PDF pages: 38
Technical content
Features
- Operating Voltage from 2.8 V to 6.0 V
- High-Accuracy Output Voltages
- Fast Transient Response
- Switcher Output Current Up to 1.5 A
- Undervoltage Lockout and Overcurrent Protection
- Enable Inputs and Programmable Watchdog Timer
- Voltage Margining via I 2C™ Bus
- Reset with Programmable Power-ON Delay
- Pb-Free Packaging Designated by Suffix Code EK I2C is a trademark of Philips Corporation.
Figure 1. 34701 Simplified Application Diagram
ORDERING INFORMATION
Range (TA) Package MC34701EK/R2 -40 to 85°C 32 SOICW EK (PB-FREE) SUFFIX 98AARH99137A 32-PIN SOICW Other Circuits RT VBD VDDH (I/Os) VDDL (Core) MPC8xxx 34701 2.8 V to 6.0 V Input VIN2 CLKSEL FREQ PORESET GND SDA SCL Adjustable:
0.8 V to VIN -
Adjustable:
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Figure 2. 34701 Simplified Internal Block Diagram
Figure 3. Pin Connections Table 1. Pin Function Description A functional description of each pin can be found in the FUNCTIONAL PIN DESCRIPTION section beginning on page 16. tied to VDDI) is set to 300 kHz. 2 INV Inverting Input Buck Controller Error Amplifier inverting input. 4, 5 VIN2 Input Voltage 2 Buck regulator power input. Drain of the high-side power MOSFET. 6, 7 SW Switch Buck regulator switching node. This pin is connected to the inductor. GND Ground Analog ground of the IC, thermal heatsinking. 10, 11 PGND Power Ground Buck regulator power ground. 12 VBD Boost Drain Drain of the internal boost regulator power MOSFET. the VBST pin is 7.75V nominal. 14 BOOT Bootstrap Bootstrap capacitor input. 15 SDA Serial Data I2C bus pin. Serial data. 16 SCL Serial Clock I2C bus pin. Serial clock. 17 LCMP Linear Compensation Linear regulator compensation pin. 18 LFB Linear Feedback Linear regulator feedback pin. 19 LDO Linear Regulator Input pin of the linear regulator power sequence control circuit.
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the proper value of the current sensing resistor RS. 21 LDRV Linear Drive LDO gate drive of the external pass N-channel MOSFET. inputs determines operation mode and type of power sequencing of the IC. inputs determines operation mode and type of power sequencing of the IC.
29 RT Reset Timer This pin allows programming of the Power-ON Reset delay by means of an external
30 RST Reset Output
voltage (e.g., the output of the LDO) by an external resistor. pin. The CLKSEL pin is also used for the I2C address selection. 32 CLKSYN Clock Synchronization Oscillator output/synchronization input pin. Table 1. Pin Function Description (continued) A functional description of each pin can be found in the FUNCTIONAL PIN DESCRIPTION section beginning on page 16.
Analog Integrated Circuit Device Data Freescale Semiconductor 5 34701
ELECTRICAL CHARACTERISTICS
Table 2. Maximum Ratings
- ESD1 testing is performed in accordance with the Human Body Model (C ZAP = 100 pF, RZAP = 1500 Ω), ESD2 testing is performed in
accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 Ω), and the Charge Device Model.
Analog Integrated Circuit Device Data
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Storage Temperature T STG -65 to 150 °C Peak Package Reflow Temperature During Reflow (2), (3) TPPRT Note 3 °C Maximum Junction Temperature T JMAX 125 °C Thermal Resistance Junction to Ambient (Single Layer) (4), (5) Junction to Ambient (Four Layers) (4), (5) RθJA °C/W Thermal Resistance, Junction to Base (6) RθJB 18 °C/W Operational Package Temperature (Ambient Temperature) T A -40 to 85 °C Notes 2. Pin soldering temperature limit is for 10 seconds maximum du ration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. 3. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), MC33xxxD enter 33xxx), and review parametrics.. 4. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board and board thermal resistance. 5. Per JEDEC JESD51-6 with the board horizontal 6. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. Table 2. Maximum Ratings (continued)
Analog Integrated Circuit Device Data Freescale Semiconductor 7 34701 STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics the typical application circuit (see Figure 33) unless otherwise noted.
- Design information only. This parameter is not production tested.
- IVOUT refers to load current on output switcher.
Analog Integrated Circuit Device Data
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STATIC ELECTRICAL CHARACTERISTICS BUCK CONVERTER (CONTINUED) High-Side Power MOSFET Q1 RDS(ON) (9), (10) ID = 500 mA, TA = 25°C, VBST = 8.0 V RDS(ON)Q1 –6 0– mΩ Low-Side Power MOSFET Q2 RDS(ON) (9), (10) ID = 500 mA, TA = 25°C, VBST = 8.0 V RDS(ON)Q2 –6 5– mΩ Buck Converter Peak Current Limit (High Level) I LIMH -4.0 -2.7 -1.5 A VOUT Pulldown MOSFET Q3 Current Limit TA = 25°C, VBST = 8.0 V ILIMPQ3 0.75 – 2.0 A VOUT Pull-down MOSFET Q3 RDS(ON) (10) ID = 1.0 A, VBST = 8.0 V RDS(ON)PQ3 –– 1 . 9 Ω Thermal Shutdown (VOUT Pull-down MOSFET Q3) (9) TSD 150 170 190 °C Thermal Shutdown Hysteresis (9) THYS –1 0– ° C Notes 9. Design information only. This parameter is not production tested. 10. ID is the MOSFET drain current. Table 3. Static Electrical Characteristics (continued) the typical application circuit (see Figure 33) unless otherwise noted.
Analog Integrated Circuit Device Data Freescale Semiconductor 9 34701 STATIC ELECTRICAL CHARACTERISTICS ERROR AMPLIFIER (BUCK CONVERTER) Input Impedance (11) RIN – 500 – k Ω Output Impedance (11) ROUT – 150 – Ω DC Open Loop Gain (11) AVOL –8 0– d B Gain Bandwidth Product (11) GBW –3 5– M H z Slew Rate (11) vSR – 200 – V/ µs Output Voltage – High Level VIN1 > 3.3 V, IOEA = -1.0 mA (11), (12) V EA_OH –2 . 0– V Output Voltage – Low Level V EA_OL –0 . 4– V Oscillator Ramp (11) VSCRamp –0 . 5– V OSCILLATOR CLKSYN Pin (open) Low Level Output Voltage IOL = +1.0 mA (13) VOSC_OL –– 0 . 4 V CLKSYN Pin (open) High Level Output Voltage IOH = -1.0 mA (14) VOSC_OH VDDI - 0.4 V – – V CLKSYN Pin (grounded) Input Voltage Threshold V OSC_IH 1 . 2–2 . 0 V CLKSYN Pin Pullup Resistance R PU 60 – 240 k Ω Frequency Adjusting Reference Voltage V FREQ –1 . 2 6– V BOOST REGULATOR Regulator Output Voltage IBST = 20 mA, VIN1 = VIN2 = 2.8 V to 6.0 V VBST 7.3 7.7 8.3 V Power MOSFET Q5 RDS(ON)(11) IBD = 500 mA, TA = 25°C RDS(ON)Q5 – 650 1000 mΩ Regulator Recommended Output Capacitor C BST –1 0– µF Regulator Recommended Output Capacitor Maximum ESR ESRC BST – 100 – m Ω Notes 11. Design information only. This parameter is not production tested. 12. IOEA Refers to Error Amplifier Output Current. 13. IOL Refers to I/O Low Level 14. IOH Refers to I/O High Level the typical application circuit (see Figure 33) unless otherwise noted.
Analog Integrated Circuit Device Data
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STATIC ELECTRICAL CHARACTERISTICS LINEAR REGULATOR (LDO) LDO Feedback Voltage (16) VIN1 = VIN2 = 2.8 V to 6.0 V, ILDO = 10 mA to 1000 mA. Includes Load Regulation Error V LFB 0.784 0.800 0.816 V LDO Voltage Margining Step Size V MLDO –1 . 0– % LDO Voltage Margining Highest Positive Value V MP 5 . 9–7 . 9 % LDO Voltage Margining Lowest Negative Value V MN - 7 . 9–- 5 . 9 % LDO Line Regulation (16) VIN1 = VIN2 = 2.8 V to 6.0 V, ILDO = 1000 mA REGLNVLDO -1.0 – 1.0 LDO Load Regulation (16) ILDO = 10 mA to 1000 mA REGLDVLDO -1.0 – 1.0 LDO Ripple Rejection, Dropout Voltage (16) VDO = 1.0 V, VRIPPLE = +1.0 V p-p Sinusoidal, f = 300 kHz, ILDO = 500 mA (15) VLDO_RR –4 0– dB LDO Maximum Dropout Voltage (VIN - VLDO), using IRL2703 (16) VLDO = 2.5 V, ILDO = 1000 mA VDO –5 0 7 5 mV LDO Current Sense Comparator Threshold Voltage (VCS - VLDO) V CSTH 35 50 65 mV LDO Pin Input Current, VLDO = 5.25 V I LDO 1.0 1.9 4.0 mA LDO Feedback Input Current (LFB Pin), VLFB = 0.8 V I LFB -1.0 – 1.0 µA LDO Drive Output Current (LDRV Pin), VLDRV = 0 V I LDRV -5.0 -3.3 -2.0 mA CS Pin Input Leakage Current VCS = 5.25 V I CSLK 50 – 200 µA LDO Pulldown MOSFET Q4 Current Limit TA = 25°C, VBST = 8.0 V (LDO Pin) I LIMQ4 0.75 – 2.0 A LDO Pulldown MOSFET Q4 RDS(ON) ID = 1.0 A, VBST = 8.0 V RDS(ON)Q4 –– 1 . 9 Ω LDO Recommended Output Capacitance C LDO –1 0– µF LDO Recommended Output Capacitor ESR R LDO –5 . 0– m Ω Thermal Shutdown (LDO Pull-down MOSFET Q4) (15) TSD 150 170 190 °C Thermal Shutdown Hysteresis (15) TSDHYS –1 0– ° C Notes 15. Design information only. This parameter is not production tested. 16. IDO refers to Load Current on External LDOFET - IRL2703 is the Intersil MOSFET. the typical application circuit (see Figure 33) unless otherwise noted.
Analog Integrated Circuit Device Data Freescale Semiconductor 11 34701 STATIC ELECTRICAL CHARACTERISTICS CONTROL AND SUPERVISORY CIRCUITS Enable (EN1, EN2) Input Voltage Threshold V EN-TH 1.0 1.5 2.0 V Enable (EN1, EN2) Pulldown Resistance R EN-PD 30 55 90 k Ω RST Low-Level Output Voltage, IOL = 5.0 mA V OL –– 0 . 4 V RST Leakage Current, OFF State, Pulled Up to 5.25 V I LKG-RST –– 1 0 µA RST Undervoltage Threshold on VOUT (∆VOUT/VOUT) (17) VOUTI Th -14 – -0.5 % RST Overvoltage Threshold on VOUT (∆VOUT/VOUT) (17) VOUTI Th 0.5 – 14 % RST Undervoltage Threshold on VLDO (∆VLDO/VLDO) (17) VLDOI Th -12 – -4.0 % RST Overvoltage Threshold on VLDO (∆VLDO/VLDO) (17) VLDOI Th 4.0 – 12 % RST Timer Voltage Threshold V TH-RT 1.0 1.2 1.5 V RST Timer Source Current (RT pin at 0 V) I S-RT - 1 7–- 3 4 m A RST Timer Leakage Current I LKG-RT -1.0 – 1.0 µA RST Timer Saturation Voltage, Reset Timer Current = 300 µAV SAT-RT – 35 100 mV Maximum Recommended Value of the Reset Timer Capacitor C t –– 4 7 µF CLKSEL Threshold Voltage V THCLKS 1.2 1.6 2.0 V CLKSEL Pullup Resistance R PU-CLKS 60 120 240 k Ω ADDR Threshold Voltage (17) VTHADDR 1.2 1.6 2.0 V ADDR Pullup Resistance R PU-ADDR 60 120 240 k Ω Thermal Shutdown (IC sensor) (17) TLIM 150 170 190 °C Thermal Shutdown Hysteresis (17) TLIMHYS –1 0– ° C SDA, SCL PINS I2C BUS (STANDARD) Input Threshold Voltage (Pin SCL), Rising Edge (17) VLTH 1 . 3–1 . 7 V Input Threshold Voltage (Pin SDA) V LTH 1 . 3–1 . 7 V SDA, SCL Input Current, Input Voltage = 5.25 V (VIN1) I IN –1 . 0 1 0 µA SDA Low-Level Output Voltage, 3.0 mA Sink Current V OL –– 0 . 4 V SDA, SCL Capacitance (17) CInput – 7.0 10 pF Notes 17. Design information only. This parameter is not production tested. the typical application circuit (see Figure 33) unless otherwise noted.
Analog Integrated Circuit Device Data
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DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 4. DYNAMIC ELECTRICAL CHARACTERISTICS the typical application circuit (see Figures 33) unless otherwise noted.
- Design information only. This parameter is not production tested.
- see Figure 4 for more details
Analog Integrated Circuit Device Data Freescale Semiconductor 13 34701 DYNAMIC ELECTRICAL CHARACTERISTICS BOOST REGULATOR Boost Regulator MOSFET Maximum ON Time (21) tON –2 4– µs Boost Regulator Control Loop Propagation Delay (21) tBST_PD –5 0– n s Boost Switching Node VBD Rise Time (21) IBST = 20 mA tB_RISE –5 . 0 ns Boost Switching Node VBD Fall Time (21) IBST = 20 mA tB_FALL –3 . 0– ns LINEAR REGULATOR (LDO) Fault Condition Time-Out t FAULT 7.0 10 15 ms Retry Timer Cycle t Ret 70 100 150 ms RESET MONITOR (RST) Monitoring LFB Pin Delay t D_RST_LFB 1 2–2 8 µs Monitoring INV Pin Delay t D_RST_INV 1 2–2 8 µs SCA, SCL PIN, I2C BUS (STANDARD) SCL Clock Frequency (21) fSCL – – 100 kHz Bus Free Time Between a STOP and a START Condition (21) tBUF 4.7 – – µs Hold Time (Repeated) START Condition (After this period, the first clock pulse is generated.) (21) tHD-STA 4.0 – – µs Low Period of the SCL Clock (21) tLOW 4.7 – – µs High Period of the SCL Clock (21) tHIGH 4.0 – – µs SDA Fall Time from VIH_MAX to VIL_MIN, Bus Capacitance 10 pF to 400 pF, 3.0 mA Sink Current (21), (23) tF – – 250 ns Setup Time for a Repeated START Condition (21) tSU-STA 4.7 – – µs Data Hold Time for I2C Bus Devices (21), (22) tHD-DAT 0.0 – – µs Data Setup Time (21) tSU-DAT 250 – – ns Setup Time for STOP Condition (21) tSU-STO 4.0 – – µs Capacitive Load for Each Bus Line (21) CB – – 400 pF Notes 21. Design information only. This parameter is not production tested. 22. The device provides an internal hold time of at least 300 ns for the SDA signal (refer to the VIH_MIN of the SCL signal) to bridge the undefined region of the falling edge of SCL. 23. VIH is High Level Voltage on I 2C bus lines and VIL is Low Level Voltage on I2C bus lines Table 4. DYNAMIC ELECTRICAL CHARACTERISTICS (continued) the typical application circuit (see Figures 33) unless otherwise noted.
Analog Integrated Circuit Device Data
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Figure 4. Definition of Time on the I2C Bus Figure 5. fOSC vs. Temperature Figure 6. fOSC vs. Rf Figure 7. Switcher Efficiency vs. Load Current Figure 8. Switcher ILim vs. Temperature
Analog Integrated Circuit Device Data
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The 34701 power supply integrated circuit provides the means to efficiently supply the Freescale Power QUICC and other families of Freescale microprocessors. It incorporates a high-performance synchronous buck regulator, supplying the microprocessor’s core, and a low dropout (LDO) linear regulator providing the microprocessor I/O and bus voltages. This device incorporates many advanced features; e.g., precisely maintained up/down power sequencing, ensuring the proper operation and protection of the CPU and power system. At the same time, it provides high flexibility of configuration, allowing the maximum optimization of the power supply system. FUNCTIONAL PIN DESCRIPTION OSCILLATOR FREQUENCY PIN (FREQ) This switcher frequency selection pin can be adjusted by connecting external resistor RF to the FREQ pin. The default switching frequency (FREQ pin left open or tied to VDDI) is set to 300 kHz. INVERTING INPUT PIN (INV) Buck Controller Error Amplifier inverting input. OUTPUT VOLTAGE PIN (VOUT) Output voltage of the buck converter. Input pin of the switching regulator power sequence control circuit. INPUT VOLTAGE 2 PINS (VIN2) Buck regulator power input. Drain of the high-side power MOSFET. SWITCH PINS (SW) Buck regulator switching node. This pin is connected to the inductor. GROUND PINS (GND) Analog ground of the IC, thermal heatsinking. POWER GROUND PINS (PGND) Buck regulator power ground. BOOST DRAIN PIN (VBD) Drain of the internal boost regulator power MOSFET. BOOST VOLTAGE PIN (VBST) Internal boost regulator output voltage. The internal boost regulator provides a 20 mA output current to supply the drive circuits for the integrated power MOSFETs and the external N-channel power MOSFET of the linear regulator. The voltage at the VBST pin is 7.75V nominal. BOOTSTRAP PIN (BOOT) Bootstrap capacitor input. SERIAL DATA PIN (SDA) I2C bus pin. Serial data. SERIAL CLOCK PIN (SCL) I2C bus pin. Serial clock. LINEAR COMPENSATION PIN (LCMP) Linear regulator compensation pin. LINEAR FEEDBACK PIN (LFB) Linear regulator feedback pin. LINEAR REGULATOR PIN (LDO) Input pin of the linear regulator power sequence control circuit. CURRENT SENSE PIN (CS) Current sense pin of the LDO. Overcurrent protection of the linear regulator external power MOSFET. The voltage drop over the LDO current sense resistor RS is sensed between the CS and LDO pins. The LDO current limit can be adjusted by selecting the proper value of the current sensing resistor RS. LINEAR DRIVE PIN (LDRV) LDO gate drive of the external pass N-channel MOSFET. INPUT VOLTAGE 1 PIN (VIN1) The input supply pin for the integrated circuit. The internal circuits of the IC are supplied through this pin.
X7R capacitor is recommended. Power Sequencing mode selection. outputs are active and stable and the RST output is released. accuracy if R t is less than 10 kΩ. the output of the LDO) by an external resistor. is out of regulation (high or low), the RST pin is pulled low. There is a 20 µs delay filter preventing erroneous resets. for the I2C address selection. Oscillator output/synchronization input pin. Table 5. Operating Mode Selection
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operation and protection of the CPU and power system. Figure 11. 34701 Functional Internal Block Diagram voltage of 7.75 V nominal value.
1.0 A), the low-side switch is turned off and the current
charges the output capacitor through the internal rectifier. scaled down to approximately one fifth of their original values. voltage falls below the regulation limit again. waveforms (picture not to scale).
Figure 12. Boost Regulator Startup (Not To Scale) excellent line and load regulation. Figure 13. Switching Regulator Current Limit switcher (respectively LDO). Figure 14. Switching Converter Overcurrent Protection
0.5 I pk
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Figure 15. LDO Converter Overcurrent Protection coordinated with the linear regulator. frequency resistor selection. synchronization input when the CLKSEL pin is grounded. internal slope compensation ramp to the external clock. to be 50% duty cycle. Minimum pulse width is 1.0 µs. current sense comparator threshold voltage. coordinated with the switching regulator. watchdog timer is reset and the new time-out period begins. Figure 16. Watchdog Operation
Analog Integrated Circuit Device Data Freescale Semiconductor 21 34701 FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION When the Window Watchdog function is selected, the timer cannot be cleared during the Closed Window time, which is 50% of the total watchdog period. When the watchdog is cleared, the timer is reset and starts a new time- out period. If the watchdog is not cleared during the Open Window time, the RST will become active (LOW) for a time determined by the RC components of the RT timer plus 10 ms.
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the low-side (synchronous MOSFET M2), and control circuit. affecting the LDO operation. do not activate the soft start. I2C Bus Operation, beginning on page 26 of this datasheet.
- There are two possible power sequencing modes,
Standard and Inverted, as explained in more detail below. The third mode of operation is Power Sequencing Disabled. Figure 17. Standard Power Up / Down Sequence
1.0 V/ms
3.3 V Input Supply (I/O Voltage)
1.5 V Core Voltage
3.3 V Input
Figure 18. Standard Power Up / Down Sequence page 17, shows the Power Sequencing mode selection. Figure 19. Inverted Power Up / Down Sequence in +5.0 V
- I/O supply voltage not to exceed core voltage by more
- Core supply voltage not to exceed I/O voltage by more
achieved through the intrinsic operation of the regulators.
3.3 V I/O Voltage (VLDO)
1.5 V Core Voltage (VOUT)
5.0 V Input
3.3 V I/O Voltage (VOUT)
1.5 V Core Voltage(VLDO)
Analog Integrated Circuit Device Data
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FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES Standard Power Sequencing Control Comparators monitor voltage differences between the LDO (LDO pin) and the switcher (VOUT pin) outputs as follows: LDO > VOUT + 1.9 V, turn off LDO. The LDO can be forced off. This occurs whenever the LDO output voltage exceeds the switcher output voltage by more than 1.9 V. 2. LDO > VOUT + 2.0 V, shunt LDO to ground. If turning off the LDO is insufficient and the LDO output voltage exceeds the switcher output voltage by more than 2.0 V, a 1.5 Ω shunt MOSFET is turned on that discharges the LDO load capacitor to ground. The shunt MOSFET is used for switcher output shorts to ground and for power down in case of VIN1 ≠ VIN2 with the switcher output falling faster than the LDO. 3. LDO < VOUT + 1.9 V cancel (2). 4. LDO < VOUT + 1.8 V, cancel (1) above, re-enable LDO. Normal operation resumes when the LDO output voltage is less than 1.8 V above the switcher output voltage. LDO < VOUT - 0.1 V, turn off switcher. The switcher can be forced off. This occurs whenever the LDO is less than VOUT - 0.1 V. LDO < VOUT - 0.3 V, turn on Sync (LS) MOSFET and 1.5 Ω VOUT sink MOSFET. The Buck High-Side MOSFET is forced off and the Sync MOSFET is forced on. This occurs when the switcher output voltage exceeds the LDO output by more than 300 mV. 7. LDO > VOUT - 0.3 V, cancel (6). 8. LDO > VOUT - 0.1 V, cancel (5). Normal operation resumes when LDO < VOUT - 0.1 V . Inverted Power Sequencing Control Comparators monitor voltage differences between the switcher (VOUT pin) and LDO (LDO pin) outputs as follows: 1. VOUT > LDO + 1.8 V, turn off VOUT . The switcher VOUT can be forced off. This occurs whenever the VOUT output voltage exceeds the LDO output voltage by more than 1.8 V. VOUT > LDO + 2.0 V, shunt VOUT to ground. If turning off the switcher VOUT is insufficient and the VOUT output voltage exceeds the LDO output voltage by more than 2.0 V, a 1.5 Ω shunt MOSFET and the switcher synchronous MOSFET are turned on to discharge the VOUT load capacitor to ground. The shunt MOSFET and synchronous MOSFET are used for LDO output shorts to ground and for power-down in case of VIN1 ≠ VIN2 with LDO output falling faster than the VOUT . 3. VOUT < LDO + 1.8 V, cancel (1) and (2) above, re- enable VOUT . Normal operation resumes when the VOUT output voltage is less than 1.8 V above the LDO output voltage. 4. VOUT < LDO + 2.0 V, cancel (2) 5. VOUT < LDO - 0.2 V, turn off LDO. The LDO can be forced off. This occurs whenever the VOUT is less than VLDO - 0.2 V. VOUT < LDO - 0.3 V, turn on the 1.5 Ω LDO sink MOSFET. This occurs when the LDO output voltage exceeds the VOUT output by more than 300 mV. 7. VOUT < LDO - 0.2 V, cancel (6). 8. VOUT < LDO - 0.1 V, cancel (5). Normal operation resumes when VOUT > LDO - 0.1 V. STANDARD OPERATING MODE Single 3.3 V Supply, VIN = VIN1 = VIN2 = 3.3 V The 3.3 V supplies the microprocessor I/O voltage, the switcher supplies core voltage (e.g., 1.5 V nominal), and the LDO operates independently (see Figure 17, page 22). Power sequencing depends only on the normal switcher intrinsic operation to control the Buck High-Side MOSFET. Power-Up When VIN is rising, initially VOUT is below the regulation point and the Buck High-Side MOSFET is on. In order not to exceed the 2.1 V differential requirement between the I/O (VIN) and the core (VOUT), the switcher must start up at 2.1 V or less and be able to maintain the 2.1 V or less differential. The maximum slew rate for V IN is 1.0 V/ms. Power-Down When VIN is falling, VOUT falls below the regulation point; therefore, the Buck High-Side MOSFET is on. In the case where VOUT is falling faster than VIN, the Buck High-Side MOSFET attempts to maintain VOUT. In the case where VIN is falling faster than VOUT, the Buck High-Side MOSFET is also on, and the VOUT load capacitor is discharged through the Buck High-Side MOSFET to VIN. Thus, provided VIN does not fall too fast, the core voltage (VOUT) does not exceed the I/O voltage (VIN) by more than a maximum of 0.4 V. Shorted Load 1. VOUT shorted to ground. This causes the I/O voltage to exceed the core voltage by more than 2.1 V. No load protection. 2. VIN shorted to ground. Until the switcher load capacitance is discharged, the core voltage exceeds the I/O voltage by more than 0.4 V. By the intrinsic operation of the switcher, the load capacitor is discharged rapidly through the Buck High-Side MOSFET to VIN. VOUT shorted to supply. No load protection. 34701 is protected by current limit and Thermal Shutdown.
Analog Integrated Circuit Device Data Freescale Semiconductor 25 34701 FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES Single 5.0 V Supply, VIN1 = VIN2, or Dual Supply VIN1 ≠ VIN2 The LDO supplies the microprocessor I/O voltage. The switcher supplies the core (e.g., 1.5 V nominal) (see Figure 18, page 23). Power-Up This condition depends upon the regulator current limit, load current and capacitance, and the relative rise times of the VIN1 and VIN2 supplies. There are two cases: 1. LDO rises faster than VOUT . The LDO uses control methods (1) and (2) described in the section Methods of Control on page 23. 2. VOUT rises faster than LDO. The switcher uses control methods (5) and (6) described in the section Methods of Control on page 23. Power-Down This condition depends upon the regulator load current and capacitance and the relative fall times of the VIN1 and VIN2 supplies. There are two cases: 1. VOUT falls faster than LDO. The LDO uses control methods (1) and (2) described in the section Methods of Control on page 23. In the case VIN1 = VIN2, the intrinsic operation turns on both the Buck High-Side MOSFET and the LDO external Pass MOSFET, and discharges the LDO load capacitor into the VIN supply. LDO falls faster than VOUT . The switcher uses control methods (5) and (6) described in the section Methods of Control on page 23. Shorted Load 1. VOUT shorted to ground. The LDO uses method (1) and (2) described in the section Methods of Control on page 23. 2. LDO shorted to ground. The switcher uses control methods (5) and (6) described in the section Methods of Control on page 23. 3. VIN1 shorted to ground. Device is not working. 4. VIN2 shorted to ground with VIN1 and VIN2 different. This is equivalent to the switcher output shorted to ground. 5. VOUT shorted to supply. No load protection. 34701 is protected by current limit and Thermal Shutdown. 6. LDO shorted to supply. No load protection. 34701 is protected by current limit and Thermal Shutdown. INVERTED OPERATING MODE Single 3.3 V Supply, VIN = VIN1 = VIN2 = 3.3 V The 3.3 V supplies the microprocessor I/O voltage, the LDO supplies core voltage (e.g., 1.5 V nominal), and the switcher VOUT operates independently. Power sequencing depends only on the normal LDO intrinsic operation to control the Pass MOSFET. Power-Up When VIN is rising, initially LDO is below the regulation point and the Pass MOSFET is on. In order not to exceed the
2.1 V differential requirement between the I/O (VIN) and the
core (LDO), the LDO must start up at 2.1 V or less and be able to maintain the 2.1 V or less differential. The maximum slew rate for V IN is 1.0 V/ms. Power-Down When VIN is falling, LDO falls below the regulation point; therefore, the Pass MOSFET is on. In the case where LDO is falling faster than VIN, the Pass MOSFET attempts to maintain LDO. In the case where VIN is falling faster than LDO, the Pass MOSFET is also on, and the LDO load capacitor is discharged through the Pass MOSFET to VIN. Thus, provided VIN does not fall too fast, the core voltage (LDO) does not exceed the I/O voltage (VIN) by more than maximum of 0.4 V. Shorted Load 1. LDO shorted to ground. This will cause the I/O voltage to exceed the core voltage by more than 2.1 V. No load protection. VIN shorted to ground. Until the LDO load capacitance is discharged, the core voltage exceeds the I/O voltage by more than 0.4 V. By the intrinsic operation of the LDO, the load capacitor is discharged rapidly through the Pass MOSFET to VIN. LDO shorted to supply. No load protection. Single 5.0 V Supply, VIN1 = VIN2, or Dual Supply VIN1 ≠ VIN2 The switcher VOUT supplies the microprocessor I/O voltage. The LDO supplies the core (e.g., 1.5 V nominal) (see Figure 19, page 23). Power-Up This condition depends upon the regulator current limit, load current and capacitance, and the relative rise times of the VIN1 and VIN2 supplies. There are two cases: VOUT rises faster than LDO. The switcher VOUT uses control methods (1) and (2) described in the section Methods of Control on page 23. LDO rises faster than VOUT . The LDO uses control methods (5) and (6) described in the section Methods of Control on page 23. Power-Down This condition depends upon the regulator load current and capacitance and the relative fall times of the VIN1 and VIN2 supplies. There are two cases:
26 Freescale Semiconductor
- LDO falls faster than VOUT . The VOUT uses control
load capacitor into the VIN supply.
- LDO shorted to ground. The VOUT uses methods (1)
- VOUT shorted to ground. The LDO uses control
- VIN1 shorted to ground. Device is not working.
- VIN2 shorted to ground. This is equivalent to the
switcher VOUT output shorted to ground.
- LDO shorted to supply. No load protection. 34701 is
protected by current limit and Thermal Shutdown.
- VOUT shorted to supply. No load protection. 34701 is
protected by current limit and Thermal Shutdown. by sending the Acknowledge bit (Ack) to the master device. Figure 20. Communication Start Using 7-Bit Address configuration of the oscillator synchronization CLKSYN pin. synchronization input for the external clock signal. definition of the selectable portion of the device address. ADDR pin to ground through a 10 kΩ resistor. Figure 21. Address Bit Definition for 7-Bit Address Figure 22. Data Transfer for Write Operations Table 6. Definition of Selectable Portion of Device
11101 A1 A0
The address field is selected from the list in Table 7. Figure 23. Command Byte field definitions for the entire set of operation options. operation one, followed by a null value field (all zeros). command, one for each supply. Table 7. Address Field Definitions
001 Voltage Margining W
011 Watchdog W
Table 8. Command Byte Definitions
01100000 W D O F F
01101001 W D 320 ms
01101010 W D 8 0 m s
01101011 W D 2 0 m s
01101101 W D 320 ms
01101110 W D 8 0 m s
01101111 W D 2 0 m s
- The Watchdog timer is turned ON automatically after
Table 9. First Command Definitions
28 Freescale Semiconductor
Figure 24. Voltage Margining Programming watchdog timer programming command example. Figure 25. Watchdog Timer Programming defined in Table 8, page 27. Figure 26. Data Transfer Example - Watch Dog Timer Figure 27. Data Transfer Example - LDO Voltage
Figure 28. Data Transfer Example - LDO and Switcher
30 Freescale Semiconductor
Figure 29. Buck Regulator Control Circuit voltage, thus providing the feed-forward function. control loop gain and phase versus frequency. is the inductance value of the output filter inductor L. generator (Vm1 = 0.5 V typ.).
Analog Integrated Circuit Device Data
32 Freescale Semiconductor
Linear Regulator Current Limit As described in the Linear Regulator Functional Description section, the current limit of the linear regulator can be adjusted by means of an external current sense resistor R S. The voltage drop caused by the regulator output current flowing through the current sense resistor RS is sensed between the LDO and the CS pins. When the sensed voltage exceeds 50 mV (typical), the current limit timer starts to time out while the control circuit limits the output current. If the overcurrent condition lasts for more than 10 ms, the linear regulator is shut off and turned on again after 100 ms. This type of operation provides equivalent protection to the analog “current foldback” operation. It is important to keep in mind that the amount of capacitive load which can be supplied by the by the linear regulator is limited by the setting of the LDO current limit. During the power-up period, the linear regulator operates in the current limit, supplying the current into the load of the LDO, which includes all the capacitors connected to the regulator output. If the total amount load is so large that the regulator could not reach its regulation voltage in 10 ms during the power-up, it turns off and tries to power up again after 100 ms. This situation may lead to the power-up oscillations. Linear Regulator External MOSFET The linear regulator uses an external N-channel power MOSFET to provide a pass element for the power path. The selection of the proper type of the external power MOSFET is critical for optimum performance and safe operation of the linear regulator. The power MOSFET’s threshold voltage, R DS(on), gate charge, capacitances and transconductance are important parameters for the stable operation of the linear regulator while the package of the power MOSFET determines the maximum power dissipation, and hence the maximum output current for the required input-to-output voltage drop. The power dissipation of the external MOSFET can be calculated from the simple formula: Where P D(Q) is the power MOSFET power dissipation VIN is the LDO input voltage, VLDO is the LDO output voltage, ILDO is the LDO output load current. Table 10 shows the recommended power MOSFET types for the 34701 linear regulator, their typical power dissipation, and thermal resistance junction-to-case. NOTE: Freescale does not assume liability, endorse, or warrant components from external manufacturers referenced in figures or tables. Although Freescale offers component recommendations, it is the customer’s responsibility to validate their application. *When mounted to an FR4 using 0.5 sq.in. drain pad size The maximum power dissipation is limited by the maximum operating junction temperature TJmax. The allowed power dissipation in the given application can be calculated from the following expression: Where PD(Q)max is the power MOSFET maximum allowed dissipation, TJmax is the power MOSFET maximum operating junction temperature, TA is the ambient temperature, RthJC is the power MOSFET thermal resistance junction-to-case, RthCB is the thermal resistance case-to-board, RthBA is the thermal resistance board-to-ambient of the PC board. PCB Layout Considerations As with any power application, the proper PCB layout plays a critical role in the overall power regulator performance. While good careful printed circuit board layout significantly improves regulation parameters and electromagnetic compatibility (EMC) performance of the switching regulator, poor layout practices can lead not only to significant degradation of regulation and EMC parameters but even to total dysfunction of the whole regulator IC. Extreme care should be taken when laying out the ground of the regulator circuit. In order to avoid any inductive or capacitive coupling of the switching regulator noise into the sensitive analog control circuits, the noisy power ground and the clean quiet signal ground should be well separated on the printed circuit board, and connected only at one connection point. The power routing should be made by heavy traces or areas of copper. The power path and its return should be placed, if possible, atop each other on the different layers or opposite sides of the PC board. The switching regulator input and output capacitors should be physically placed very close to the power pins (VIN2, SW, PGND) of the 34701 switching regulator; and their ground pins, together with the 34701 power ground pins (PGND), should be connected by a single island of the power ground copper to create the “single-point” grounding. Figure 32 illustrates the 34701 switching regulator grounding concept. The bootstrap capacitor Cb should be tightly connected to the integrated circuit as well.Table 10. Recommended Power MOSFETs Part No. Package Typ. P D RthJ-C IRL2703S D2PAK 2.0 W 3.3 °C/W MTD20N03HDL DPAK 1.75 W* 1.67 °C/W PDQ() ILDO VIN VLDO–()×= PDQ() max TJmax TA–
Figure 32. 34701 Buck Regulator Layout power path of the linear regulator.
34 Freescale Semiconductor
Figure 33. Simplified Block Diagram and Basic Application
Figure 34. 34701 Typical Application Circuit
- R11 can be adjusted according to the required LDO current limit.
- L1 = 4.7uH, DO3316P-472HC from Coilcraft
or CDRH104R-4R7 from Sumida. or 1812PS-103M from Coilcraft.
- C3, C10 = 100uF/6.3V, 10THB100ML POSCAP capacitor from Sanyo.
- C2 = 10uF/10V, ceramic capacitor .
Analog Integrated Circuit Device Data
36 Freescale Semiconductor
Important: For the most current package revision, visit www.freescale.com and perform a “keyword” search for the “98A” number. CASE 1324–02 ISSUE A NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETERS. 2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 3. DATUMS B AND C TO BE DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. 4. THIS DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSION OR GATE BURRS. MOLD FLASH, PROTRUSION OR GATE BURRS SHALL NOT EXCEED 0.15 MM PER SIDE. THIS DIMENSION IS DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. 5. THIS DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH AND PROTRUSIONS SHALL NOT EXCEED 0.25 MM PER SIDE. THIS DIMENSION IS DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. 6. THIS DIMENSION DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.4 MM PER SIDE. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD SHALL NOT LESS THAN 0.07 MM. 7. EXACT SHAPE OF EACH CORNER IS OPTIONAL. 8. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10 MM AND 0.3 MM FROM THE LEAD TIP. 9. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM. THIS DIMENSION IS DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTER–LEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. CL10.9 7.4 16 17 0.10 A 2.35 SEATING PLANE 0.9 SECTION B–B 0.65 R0.08 MIN B A PIN 1 ID (0.29) 0.38 0.25 (0.203) ÇÇÇÇ Ç ÇÇ Ç ÇÇÇÇ ÉÉÉ ÉÉÉ PLATING BASE METAL SECTION A–A ROTATED 90 CLOCKWISE/C0095 0.19 0.22
0.13 M CA M B
A C7.6 11.1 10.3 5.15 A 32X 30X 2.65 0.3 A 2X 16 TIPS B C BB 0.29 0.13 0.50° 0°0.25 GAUGE PLANE MIN 98AARH99137A
Analog Integrated Circuit Device Data Freescale Semiconductor 37 34701
REVISION HISTORY
REVISION DATE DESCRIPTION OF CHANGES 5.0 2/2006 • Changed Document Order No. 6.0 2/2007 • Updated to the current Freescale form and style.
- Changed the status from Advance Information to Final.
- Added Peak Package Reflow Temperature During Reflow (2), (3)
- Added Notes (2) and (3)
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