33993

33993 FREESCALE | Alldatasheet

Document overview

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Technical content

Features

• Designed to Operate 5.5 V ≤ VPWR ≤ 26 V
• Switch Input Voltage Range -14 V to VPWR, 40 V Max
• Interfaces Directly to Microprocessor Using 3.3 V / 5.0 V SPI Protocol
• Selectable Wake-Up on Change of State
• Selectable Wetting Current (16 mA or 2.0 mA)
• 8 Programmable Inputs (Switches to Battery or Ground)
• 14 Switch-to-Ground Inputs
• V PWR Standby Current 100 µA Typical, VDD Standby Current 20 µA Typical
• Active Interrupt ( INT) on Change-of-Switch State
• Pb-Free Packaging Designated by Suffix Code EW

Figure 1. MC33993 Simplified Application Diagram

ORDERING INFORMATION

Range (TA) Package MC33993DWB/R2 -40°C to 125°C 32 SOICW MCZ33993EW/R2 VDD VDD VPWR Power Supply LVI Enable Watchdog ResetVDD SI SO SCLK INT CS AMUX MOSI MISO AN0 VBAT SP0 SP1 SP7 SG1 SG0 SG12 SG13 WAKE 33993 SCLK CS INT MCU GND VBAT VBAT

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Figure 2. 33993 Simplified Internal Block Diagram

Figure 3. 33993 Pin Connections Table 1. 33993 Pin Definitions A functional description of each pin can be found in the Functional Pin Description section beginning on page 9. 1 GND Ground Ground for logic, analog, and switch to battery inputs. 2 SI SPI Slave In SPI control data input pin from MCU to the 33993. 3 SCLK Serial Clock SPI control clock input pin. Programmable switch-to-battery or switch-to-ground input pins. Switch-to-ground input pins. 16 VPWR Battery Input Battery supply input pin. Pin requires external reverse battery protection. 17 WAKE Wake-Up Open drain wake-up output. Designed to control a power supply enable pin. 29 INT Interrupt Open-drain output to the MCU. Used to indicate an input switch change of state. 30 AMUX Analog Multiplex Output Analog multiplex output. 31 VDD Voltage Drain Supply 3.3 / 5.0 V supply. Sets SPI communication level for the SO driver. 32 SO SPI Slave Out Provides digital data from 33993 to the MCU.

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ELECTRICAL CHARACTERISTICS

Table 2. Maximum Ratings permanent damage to the device.

1. Exceeding these limits may cause malf unction or permanent damage to the device.
2. ESD testing is performed in accordance with the Human Body Model (HBM) (C ZAP = 100 pF, RZAP = 1500 Ω), the Machine Model (MM)

(CZAP = 200 pF, RZAP = 0 Ω), and the Charge Device Model (CDM), Robotic (CZAP = 4.0pF).

1. Maximum power dissipation at T J =150°C junction temperature with no heat sink used.
2. Pin soldering temperature limit is for 10 seconds maximum dura tion. Not designed for immersion soldering. Exceeding these limits may

cause malfunction or permanent damage to the device.

1. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow

MC33xxxD enter 33xxx), and review parametrics.

Analog Integrated Circuit Device Data Freescale Semiconductor 5 33993 STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics

1. Device operational. Table paramet ers may be out of specification.
2. Thermal shutdown of 16 mA pull-up and pull-down current sources only. 2.0 mA current source / sink and all other functions remain
3. This parameter is guaranteed by design but is not production tested.

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STATIC ELECTRICAL CHARACTERISTICS DIGITAL INTERFACE Input Logic Voltage Thresholds (9) VINLOGIC 0.8 – 2.2 V SCLK, SI, Tri-State SO Input Current

0 V to VDD

ISCLK, ISI, ISO (TRI) -10 – 10 µA CS Input Current CS = VDD ICS -10 – 10 µA CS Pull-Up Current CS = 0 V ICS 30 – 100 µA SO High-State Output Voltage I SO (HIGH) = -200 µA VSO (HIGH) VDD - 0.8 – VDD V SO Low-State Output Voltage I SO (HIGH) = 1.6 mA VSO (LOW) – – 0.4 V Input Capacitance on SCLK, SI, Tri-State SO (10) CIN – – 20 pF INT Internal Pull-Up Current – 15 40 100 µA INT Voltage INT = Open Circuit V INT (HIGH) VDD - 0.5 – VDD V INT Voltage I INT = 1.0 mA V INT (LOW) – 0.2 0.4 V WAKE Internal Pull-Up Current I WAKE (PU) 20 40 100 µA WAKE Voltage WAKE = Open Circuit V WAKE (HIGH) 4.0 4.3 5.3 V WAKE Voltage I WAKE = 1.0 mA V WAKE(LOW) – 0.2 0.4 V WAKE Voltage Maximum Voltage Applied to WAKE Through External Pull-Up V WAKE(MAX) – – 40 V Notes 9. Upper and lower logic threshold voltage levels apply to SI, CS, and SCLK. 10. This parameter is guaranteed by design but is not production tested. Table 3. Static Electrical Characteristics (continued)

Analog Integrated Circuit Device Data Freescale Semiconductor 7 33993 DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 4. Dynamic Electrical Characteristics

1. This parameter is guaranteed by design but not production tested.
2. Rise and Fall time of the incoming SI, CS, and SCLK signals are suggested for design considerations to prevent the occurrence of double
3. Time required for valid output status data to be available on SO pin.
4. Time required for output states data to be terminated at SO pin.
5. Time required to obtain valid data out from SO following the rise of SCLK with 200 pF load.

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Figure 4. 33993 SPI Timing Characteristics Figure 5. Sleep Mode to Normal Mode Operation Figure 6. Normal Mode Interrupt Operation

0.7 VDD

0.2 VDD

Analog Integrated Circuit Device Data Freescale Semiconductor 9 33993 FUNCTIONAL DESCRIPTION INTRODUCTION FUNCTIONAL DESCRIPTION INTRODUCTION The 33993 device is an integrated circuit designed to provide systems with ultra-low quiescent sleep / wake-up modes and a robust interface between switch contacts and a microprocessor. The 33993 replaces many of the discrete components required when interfacing to microprocessor- based systems while providing switch ground offset protection, contact wetting current, and system wake-up. The 33993 features 8-programmable switch-to-ground or switch-to-battery inputs and 14 switch-to-ground inputs. All switch inputs may be read as analog inputs through the analog multiplexer (AMUX). Other features include a programmable wake-up timer, programmable interrupt timer, programmable wake-up /interrupt bits, and programmable wetting current settings. This device is designed primarily for automotive applications but may be used in a variety of other applications such as computer, telecommunications, and industrial controls. FUNCTIONAL PIN DESCRIPTION CHIP SELECT (CS) The system MCU selects the 33993 to receive communication using the chip select (CS) pin. With the CS in a logic low state, command words may be sent to the 33993 via the serial input (SI) pin, and switch status information can be received by the MCU via the serial output (SO) pin. The falling edge of CS enables the SO output, latches the state of the INT pin, and the state of the external switch inputs. Rising edge of the CS initiates the following operation: 1. Disables the SO driver (high impedance) 2. INT pin is reset to logic [1], except when additional switch changes occur during CS low. (See Figure 6.) Activates the received command word, allowing the 33993 to act upon new data from switch inputs. To avoid any spurious data, it is essential the high-to-low and low-to-high transitions of the CS signal occur only when SCLK is in a logic low state. Internal to the 33993 device is an active pull-up to VDD on the CS. In Sleep mode the negative edge of the CS (VDD applied) will wake up the 33993 device. Data received from the device during CS wake-up may not be accurate. SERIAL CLOCK (SCLK) The system clock (SCLK) pin clocks the internal shift register of the 33993. The SI data is latched into the input shift register on the falling edge of SCLK signal. The SO pin shifts the switch status bits out on the rising edge of SCLK. The SO data is available for the MCU to read on the falling edge of SCLK. False clocking of the shift register must be avoided to ensure validity of data. It is essential the SCLK pin be in a logic low state whenever CS makes any transition. For this reason, it is recommended, though not necessary, that the SCLK pin is commanded to a low logic state as long as the device is not accessed and CS is in a logic high state. When the CS is in a logic high state, any signal on the SCLK and SI pins will be ignored and the SO pin is tri-state. SPI SLAVE IN (SI) The SI pin is used for serial instruction data input. SI information is latched into the input register on the falling edge of SCLK. A logic high state present on SI will program a one in the command word on the rising edge of the CS signal. To program a complete word, 24 bits of information must be entered into the device. SPI SLAVE OUT (SO) The SO pin is the output from the shift register. The SO pin remains tri-stated until the CS pin transitions to a logic low state. All open switches are reported as zero, all closed switches are reported as one. The negative transition of CS enables the SO driver. The first positive transition of SCLK will make the status data bit 24 available on the SO pin. Each successive positive clock will make the next status data bit available for the MCU to read on the falling edge of SCLK. The SI / SO shifting of the data follows a first-in-first-out protocol, with both input and output words transferring the most significant bit (MSB) first. INTERRUPT (INT) The INT pin is an interrupt output from the 33993 device. The INT pin is an open-drain output with an internal pull-up to VDD. In Normal mode, a switch state change will trigger the INT pin (when enabled). The INT pin and INT bit in the SPI register are latched on the falling edge of CS. This permits the MCU to determine the origin of the interrupt. When two 33993 devices are used, only the device initiating the interrupt will have the INT bit set. The INT pin is cleared on the rising edge of CS. The INT pin will not clear with rising edge of CS if a switch contact change has occurred while CS was low. In a multiple 33993 device system with WAKE high and VDD on (Sleep mode), the falling edge of INT will place all 33993s in Normal mode.

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FUNCTIONAL PIN DESCRIPTION WAKE-UP (WAKE) The WAKE pin is an open-drain output and a wake-up input. The pin is designed to control a power supply Enable pin. In the Normal mode, the WAKE pin is low. In the Sleep mode, the WAKE pin is high. The WAKE pin has a pull-up to the internal +5.0 V supply. In Sleep mode with the WAKE pin high, falling edge of WAKE will place the 33993 in Normal mode. In Sleep mode with VDD applied, the INT pin must be high for negative edge of WAKE to wake up the device. If VDD is not applied to the device in Sleep mode, INT does not affect the WAKE operation. BATTERY INPUT (VPWR) The VPWR pin is battery input and Power-ON Reset to the 33993 IC. The VPWR pin requires external reverse battery and transient protection. Maximum input voltage on VPWR is 50 V. All wetting, sustain, and internal logic current is provided from the VPWR pin. VOLTAGE DRAIN SUPPLY (VDD) The VDD input pin is used to determine logic levels on the microprocessor interface (SPI) pins. Current from VDD is used to drive SO output and the pull-up current for CS and INT pins. VDD must be applied for wake-up from negative edge of CS or INT. GROUND (GND) The GND pin provides ground for the IC as well as ground for inputs programmed as switch-to-battery inputs. PROGRAMMABLE SWITCHES 0–7 (SP0 – SP7) The 33993 device has 8 switch inputs capable of being programmed to read switch-to-ground or switch-to-battery contacts. The input is compared with a 4.0 V reference. When programmed to be switch-to-battery, voltages greater than 4.0 V are considered closed. Voltages less than 4.0 V are considered open. The opposite holds true when inputs are programmed as switch-to-ground. Programming features are defined in Table 5 through Table 10 in the Logic Commands and Registers section of this datasheet. Voltages greater than the VPWR supply voltage will source current through the SP inputs to the VPWR pin. Transient battery voltages greater than 40 V must be clamped by an external device. SWITCH-TO-GROUND INPUTS 0–13 (SG0 – SG13) The SGn pins are switch-to-ground inputs only. The input is compared with a 4.0 V reference. Voltages greater than 4.0 V are considered open. Voltages less than 4.0 V are considered closed. Programming features are defined in Table 5 through Table 10 in the Logic Commands and Registers section of this datasheet. Voltages greater than the VPWR supply voltage will source current through the SG inputs to the VPWR pin. Transient battery voltages greater than 40 V must be clamped by an external device.

6.0 MHz may be used for programming and reading switch

illustrates the configuration between an MCU and one 33993. information between the 33993 and the MCU. Figure 7. SPI Interface with Microprocessor transfer data in / out of the ICs. Figure 8. SPI Parallel Interface with Microprocessor Figure 9. SPI Serial Interface with Microprocessor

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FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES OPERATIONAL MODES POWER SUPPLY The 33993 is designed to operate from 5.5 V to 40 V on the VPWR pin. Characteristics are provided from 8.0 V to 16 V for the device. Switch contact currents and the internal logic supply are generated from the VPWR pin. The VDD supply pin is used to set the SPI communication voltage levels, current source for the SO driver, and pull-up current on INT and CS. The VDD supply may be removed from the device to reduce quiescent current. If VDD is removed while the device is in Normal mode, the device will remain in Normal mode. If VDD is removed in Sleep mode, the device will remain in Sleep mode until wake-up input is received (WAKE high to low, switch input or interrupt timer expires). Removing VDD from the device disables SPI communication and will not allow the device to wake up from INT and CS pins. POWER-ON RESET (POR) Applying VPWR to the device will cause a Power-ON Reset and place the device in Normal mode. Default settings from Power-ON Reset via VPWR or Reset Command are as follows:

• Programmable Switch – Set to Switch to Battery
• All Inputs Set as Wake-Up
• Wetting Current On (16 mA)
• Wetting Current Timer On (20 ms)
• All Inputs Tri-State
• Analog Select 00000 (No Input Channel Selected) MODES OF OPERATION The 33993 has two operating modes, Normal mode and Sleep mode. A discussion on Normal mode begins below. A discussion on Sleep mode begins on page 17. NORMAL MODE Normal mode may be entered by the following events:
• Application of V PWR to the IC
• Change-of-Switch State (when enabled)
• Falling Edge of WAKE
• Falling Edge of INT (with VDD = 5.0 V and WAKE at Logic [1])
• Falling Edge of CS (with VDD = 5.0 V)
• Interrupt Timer Expires Only in Normal mode with VDD applied can the registers of the 33993 be programmed through the SPI. The registers that may be programmed in Normal mode are listed below. Further explanation of each register is provided in subsequent paragraphs.
• Programmable Switch Register (Settings Command )
• Wake-Up / Interrupt Register (Wake-Up / Interrupt Command )
• Wetting Current Register (Metallic Command )
• Wetting Current Timer Register (Wetting Current Timer Enable Command )
• Tri-State Register (Tri-State Command )
• Analog Select Register (Analog Command )
• Calibration of Timers (Calibration Command )
• Reset (Reset Command ) Figure 6 is a graphical description of the device operation in Normal mode. Switch states are latched into the input register on the falling edge of CS. The INT to the MCU is cleared on the rising edge of CS. However, INT will not clear on rising edge of CS if a switch has closed during SPI communication (CS low). This prevents switch states from being missed by the MCU.

software at any time in Normal mode. to set the switch contact current level (refer to Table 7). logic [1] will set the switch contact wetting current to 16 mA. Register via software at any time in Normal mode. form on the switch contact surface. Figure 10. Contact Wetting and Sustain Current Table 5. Settings Command Table 6. Wake-Up / Interrupt Command

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disabled, power dissipation for the IC must be considered. Register via software at any time in Normal mode. will place the input as an analog input with high impedance. Table 7. Metallic Command Table 8. Wetting Current Timer Enable Command Table 9. Tri-State Command

the device on a periodic basis. Table 10. Analog Command Table 11. Analog Channel

00000 No Input Selected 01100 SG11

00001 SG0 01101 SG12

00010 SG1 01110 SG13

00011 SG2 01111 SP0

00100 SG3 10000 SP1

00101 SG4 10001 SP2

00110 SG5 10010 SP3

00111 SG6 10011 SP4

01000 SG7 10100 SP5

01001 SG8 10101 SP6

01010 SG9 10110 SP7

01011 SG10

Table 12. Calibration Command Table 13. Reset Command

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logic [0], closed switches are indicated with logic [1]. Table 14. SPI Command Summary

0 SG9 SG8 SG7 SG6 SG5 SG4 SG3 SG2 SG1 SG0

• Programmable Switch – Set to Switch-to-Ground
• All Inputs Set as Wake-Up
• Wetting Current On (16 mA)
• Wetting Current Timer On (20 ms)
• All inputs Tri-State-Disabl ed (comparator is active)
• Analog select 00000 (no input channel selected) With the device programmed as above, an interrupt will be generated with each switch contact change of state (open-to- close or close-to-open) and 16 mA of contact wetting current will be source for 20 ms. The INT pin will remain low until switch status is acknowledged by the microprocessor. It is critical to understand INT will not be cleared on the rising edge of CS if a switch closure occurs while CS is low. The maximum duration a switch state change can exist without acknowledgement depends on the software response time to the interrupt. Figure 4, page 8, shows the interaction between changing input states and the INT and CS pins. If desired the user may disable interrupts (wake up/ interrupt command) from the 33993 device and read the switch states on a periodic basis. Switch activation and deactivation faster than the MCU read rate will not be acknowledged. The 33993 device will exit the Normal mode and enter the Sleep mode only with a valid sleep command. SLEEP MODE Sleep mode is used to reduce system quiescent currents. Sleep mode may be entered only by sending the sleep command. All register settings programmed in Normal mode will be maintained in Sleep mode. The 33993 will exit Sleep mode and enter Normal mode when any of the following events occur:
• Input Switch Change of State (when enabled)
• Interrupt Timer Expire
• Falling Edge of WAKE
• Falling Edge of INT (with VDD = 5.0 V and WAKE at Logic [1])
• Falling Edge of CS (with VDD = 5.0 V)
• Power-ON Reset (POR) The VDD supply may be removed from the device during Sleep mode. However removing VDD from the device in Sleep mode will disable a wake-up from falling edge of INT and CS. Note In cases where CS is used to wake the device, the first SO data message is not valid. The sleep command contains settings for two programmable timers for Sleep mode, the interrupt timer and the scan timer, as shown in Table 17. The interrupt timer is used as a periodic wake-up timer. When the timer expires, an interrupt is generated and the device enters Normal mode. Table 18 shows the programmable settings of the Interrupt timer.

Table 15. Serial Output (SO) Bit Data Table 16. Serial Output (SO) Response Register

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command and may be set to 000 (no period) to 111 (64 ms). compared with the switch state prior to sleep command. page 13) is generated and the device enters Normal mode. until the scan timer expires again. 33993 device exits Sleep mode and enters Normal mode. Figure 11. Sleep Current Waveform Table 17. Sleep Command Table 18. Interrupt Timer Table 19. Scan Timer

000 No Scan

Analog Integrated Circuit Device Data Freescale Semiconductor 19 33993 FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS

• Generate an interrupt
• Force all 16 mA pull-up and pull-down current sources to revert to 2.0 mA current sources.
• Maintain the 2.0 mA current source and all other functionality
• Set the thermal flag bit in the SPI output register The thermal flag bit in the SPI word will be cleared on rising edge of CS provided the die temperature has cooled below the thermal limit. When die temperature has cooled below thermal limit, the device will resume previously programmed settings.

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that allow the device to be used in a variety of applications.

• Sensor Power Supply
• Switch Monitor for Metallic or Elastomeric Switches
• Analog Sensor Inputs (Ratiometric)
• Power MOSFET / LED Driver and Monitor
• Multiple 33993 Devices in a Module System The following paragraphs describe the applications in detail. SENSOR POWER SUPPLY Each input may be used to supply current to sensors external to a module. Many sensors such as Hall effect, pressure sensors, and temperature sensors require a supply voltage to power the sensor and provide an open collector or analog output. Figure 12 shows how the 33993 may be used to supply power and interface to these types of sensors. In an application where the input makes continuous transitions, consider using the wake-up / interrupt command to disable the interrupt for the particular input.

Figure 12. Sensor Power Supply switch may be achieved by paralleling SGn or SPn inputs. a high contact resistance. Resistance of 1.0 kΩ is common. SO data stream will be logic [0]. ratiometric reading of variable resistive input.

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Figure 14. MOSFET or LED Driver Output

• wetting current timer enable command – Disable SPn wetting current timer (refer to Table 8, page 14)
• metallic command – Set SPn to 16 mA or 2.0 mA gate drive current (refer to Table 7, page 14)
• settings command – Set SPn as switch-to-battery (refer to Table 5, page 13)
• tri-state command – Disable tri-state for SPn (refer to Table 9, page 14) After the tri-state command has been sent (tri-state disable), the MOSFET gate will be pulled to ground. From this point forward the MOSFET may be turned on and off by sending the settings command :
• settings command – SPn as switch-to-ground (MOSFET ON)
• settings command – SPn as switch-to-battery (MOSFET OFF) Monitoring of the MOSFET drain in the OFF state provides open load detection. This is done by using an SGn input comparator. With the SGn input in tri-state, the load will pull up the SGn input to battery. With open load the SGn pin is pulled down to ground through an external resistor. The open load is indicated by a logic [1] in the SO data bit. The analog command may be used to monitor the drain voltage in the MOSFET ON state. By sourcing 2.0 mA of current to the 1.5 kΩ resistor, the analog voltage on the SGn pin will be approximately: As the voltage on the drain of the MOSFET increases, so does the voltage on the SGn pin. With the SGn pin selected as analog, the MCU may perform the A / D conversion. Using this method for controlling unclamped inductive loads is not recommended. Inductive flyback voltages greater than VPWR may damage the IC. The SP0 – SP7 pins of this device may also be used to send signals from one module to another. Operation is similar to the gate control of a MOSFET. For LED applications a resistor in series with the LED is recommended but not required. The switch-to-ground inputs are recommended for LED application. To drive the LED use the following commands:
• wetting current timer enable command – Disable SGn wetting current timer
• metallic command – Set SGn to 16 mA From this point forward the LED may be turned on and off using the tri-state command :
• tri-state command – Disable tri-state for SGn (LED ON)
• tri-state command – Enable tri-state for SGn (LED OFF) These parameters are easily programmed via SPI commands in Normal mode. MULTIPLE 33993 DEVICES IN A MODULE SYSTEM Connecting power to the 33993 and the MCU for Sleep mode operation may be done in several ways. Table 20 shows several system configurations for power between the MCU and the 33993 and their specific requirements for functionality. Multiple 33993 devices may be used in a module system. SPI control may be done in parallel or serial. However when parallel mode is used, each device is addressed independently (refer to MCU Interface Description, page 11). Therefore when sending the sleep command, one device will enter sleep before the other. For multiple devices in a system, it is recommended that the devices are controlled in serial (S0 SP0 SG0 SG13 16 2.0

4.0 V Ref +

Table 20. Sleep Mode Power Supply 5.0 V 0 V SPI wake-up is not possible. flow through MCU to VDD that has been switched off. Negative edge of CS will put 33993 in Normal mode. 0 V 0 V SPI wake-up is not possible.

Analog Integrated Circuit Device Data Freescale Semiconductor 23 33993 TYPICAL APPLICATIONS INTRODUCTION from first device is connected to SI of second device). With two devices, 48 clock pulses are required to shift data in. When the WAKE feature is used to enable the power supply, both WAKE pins should be connected to the enable pin on the power supply. The INT pins may be connected to one interrupt pin on the MCU or may have their own dedicated interrupt to the MCU. The transition from Normal to Sleep mode is done by sending the sleep command. With the devices connected in serial and the sleep command sent, both will enter Sleep mode on the rising edge of CS. When Sleep mode is entered, the WAKE pin will be logic [1]. If either device wakes up, the WAKE pin will transition low, waking the other device. A condition exists where the MCU is sending the sleep command (CS logic [0]) and a switch input changes state. With this event the device that detects this input will not transition to Sleep mode, while the second device will enter Sleep mode. In this case two switch status commands must be sent to receive accurate switch status data. The first switch status command will wake the device in Sleep mode. Switch status data may not be valid from the first switch status command because of the time required for the input voltage to rise above the 4.0 V input comparator threshold. This time is dependant on the impedance of SGn or SPn node. The second switch status command will provide accurate switch status information. It is recommended that software wait 10 ms to 20 ms between the two switch status commands, allowing time for switch input voltages to stabilize. With all switch states acknowledged by the MCU, the sleep sequence may be initiated. All parameters for Sleep mode should be updated prior to sending the sleep command. The 33993 IC has an internal 5.0 V supply from VPWR pin. A POR circuit monitors the internal 5.0 V supply. In the event of transients on the VPWR pin, an internal reset may occur. Upon reset the 33993 will enter Normal mode with the internal registers as defined in Table 14, page 16. Therefore it is recommended that the MCU periodically update all registers internal to the IC. USING THE WAKE FEATURE The 33993 provides a WAKE output and wake-up input designed to control an enable pin on system power supply. While in the Normal mode, the WAKE output is low, enabling the power supply. In the Sleep mode, the WAKE pin is high, disabling the power supply. The WAKE pin has a passive pull-up to the internal 5.0 V supply but may be pulled up through a resistor to VPWR supply (see Figure 16, page 24) When the WAKE output is not used the pin should be pulled up to the VDD supply through a resistor as shown in Figure 15, page 24. During the Sleep mode, a switch closure will set the WAKE pin low, causing the 33993 to enter the Normal mode. The power supply will then be activated, supplying power to the VDD pin and the microprocessor and the 33993. The microprocessor can determine the source of the wake-up by reading the interrupt flag. COST AND FLEXIBILITY Systems requiring a significant number of switch interfaces have many discrete components. Discrete components on standard PWB consume board space and must be checked for solder joint integrity. An integrated approach reduces solder joints, consumes less board space, and offers wider operating voltage, analog interface capability, and greater interfacing flexibility.

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Figure 15. Power Supply Active in Sleep Mode Figure 16. Power Supply Shutdown in Sleep Mode

Analog Integrated Circuit Device Data Freescale Semiconductor 25 33993 PACKAGING PACKAGE DIMENSIONS PACKAGING PACKAGE DIMENSIONS For the most current package revision, visit www.freescale.com and perform a keyword search using the “98A” listed below. DWB SUFFIX EW SUFFIX (PB-FREE) 32-PIN SOICW 98ARH99137A REVISION B

Analog Integrated Circuit Device Data

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EW SUFFIX (PB-FREE) 32-PIN SOICW 98ARH99137A REVISION B

Analog Integrated Circuit Device Data Freescale Semiconductor 27 33993

REVISION HISTORY

REVISION DATE DESCRIPTION OF CHANGES 4.0 6/2007 • Implemented Revision History page

• Converted to Freescale form and style.
• Added MCZ33993EW/R2 to the ordering information.

Rev. 4.0 RoHS-compliant and/or Pb-free versions of Freescale products have the functionality and electrical characteristics of their non-RoHS-compliant and/or non-Pb-free counterparts. For further information, see http://www.freescale.com or contact your Freescale sales representative. For information on Freescale’s Environmental Products program, go to http:// www.freescale.com/epp. Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”, must be validated for each customer application by customer’s technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc., 2003-2007. All rights reserved. How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. Technical Information Center, EL516

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