33989

33989 FREESCALE | Alldatasheet

Document overview

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• PDF pages: 66

Technical content

Features

• V DD1: Low Drop Voltage Regulator, Current Limitation, Overtemperature Detection, Monitoring, and Reset Function
• V DD1: Total Current Capability 200 mA
• V2: Tracking Function of V DD1 Regulator. Control Circuitry for External Bipolar Ballast Transistor for High Flexibility in Choice of Peripheral Voltage and Current Supply
• Low Stand-By Current Consumpt ion in Stop and Sleep Modes
• High-Speed 1 MBaud CAN Physical Interface
• Four External High Voltage Wake -up Inputs Associated with HS1 VBAT Switch
• 150 mA Output Current Capability for HS1 V BAT Switch Allowing Drive of External Switches Pull-Up Resistors or Relays
• V SUP Failure Detection
• 40 V Maximum Transient Voltage
• Pb Free designated by suffix code EG

Figure 1. MC33989 Simplified Application Diagram

ORDERING INFORMATION

Range (TA) Package MC33989DW/R2 - 40°C to 125°C 28 SOICW MCZ33989EG/R2 Twisted Pair CAN Bus Wake-Up Inputs Local Module Supply Safe Circuits 33989 MOSI SCLK MISO SPI CS 5.0 V MCU VPWR CANH CANL HS1 WD VDD1 INT RST MOSI SCLK MISO TX RX GND VSUP V2CTRL CS

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Figure 2. 33989 Simplified Internal Block Diagram

1.0 MB/s CAN

Figure 3. 33989 Pin Connections Table 1. 33989 Pin Definitions A functional description of each pin can be found in the Functional Pin Description section beginning on page 18. 1 RX Output Receive Data CAN bus receive data output pin. 2 TX Input Transmit Data CAN bus transmit data input pin.

3 VDD1 Power

5.0 V regulator output pin. Supply pin for the MCU.

4 RST Output Reset This is the device reset output pin whose main function is to reset the

MCU. This pin has an internal pullup current source to VDD. 5 INT Output Interrupt This output is asserted LOW when an enabled interrupt condition occurs. The output is a push-pull structure. frame to provide a 33989-to-PCB thermal path. 10 V2 Input Voltage Source Two Sense input for the V2 regulator using an external series pass transistor. V2 is also the internal supply for the CAN transceiver.

11 V2CTRL Power

12 VSUP Power Voltage Supply Supply input pin for the 33989. 14–17 L0:L3 Input Level 0: 3 Inputs from external switches or from logic circuitry. 22 CANH Output CAN High CAN high output pin. 23 CANL Output CAN Low CAN low output pin. 24 SCLK Input System Clock Clock input pin for the Serial Peripheral Interface (SPI). 26 MOSI Input Master Out/Slave In SPI data received by the 33989. 27 CS Input Chip Select The CS input pin is used with the SPI bus to select the 33989.

28 WD Output Watch Dog The WD output pin is asserted LOW if the software watchdog is not

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ELECTRICAL CHARACTERISTICS

Table 2. Maximum Ratings permanent damage to the device.

1. ESD1 testing is performed in accordance with the Human Body Model (C ZAP = 100 pF, 1.5 k), the Machine Model (MM) (CZAP = 200 pF,

RZAP = 0 Ω), and the Charge Device Model (CDM), Robotic (CZAP = 4.0pF).

1. According to ISO 7637 specification. See Table 6, page 24.
2. Load Dump test according to ISO 7637 part 1.
3. Transient test according to ISO 7637 part 1, pulses 1, 2, 3a, and 3b according to schematic in Table 17, page 35.

Analog Integrated Circuit Device Data Freescale Semiconductor 5 33989 Operating Junction Temperature TJ -40 to 150 °C Storage Temperature TS -55 to 165 °C Ambient Temperature TA -40 to 125 °C Thermal Resistance Junction to GND Pins (5) RΘJ/P 20 °C/W Peak Package Reflow Temperature During Reflow (6), (7) TPPRT Note 7. °C Notes 5. Ground pins 6, 7, 8, 9, 20, 21, 22, and 23 6. Pin soldering temperature limit is for 10 seconds maximum dura tion. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. 7. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standerd J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), MC33xxxD enter 33xxx), and review parametrics. Table 2. Maximum Ratings (continued) permanent damage to the device.

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STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.

1. V DD1 > 4.0 V, Reset high, Logic pin high level reduced, device is functional.
2. Device is fully functional. Al l functions are operating. All modes available and operating. Watchdog, HS1 turn ON turn OFF, CAN cell

operating, L0:L3 inputs operating, SPI read/write operation. Overtemperature may occur.

1. Current measured at V SUP pin.
2. With CAN cell in Sleep-Disable state. If CAN cell is Sleep- Enabled for wake-up, an additional 60 µA must be added to specified value.
3. Oscillator running means Forced Wake-up or Cyclic Sense of Software Watchdog is Stop mode are not activated.

Analog Integrated Circuit Device Data Freescale Semiconductor 7 33989 STATIC ELECTRICAL CHARACTERISTICS BATFAIL Flag Hysteresis (13) VBF(HYS) — 1.0 — V Battery Fall Early Warning Threshold In Normal and Standby Mode BFEW 5.3 5.8 6.3 V Battery Fall Early Warning Hysteresis In Normal and Standby Mode (13) BFEWH 0.1 0.2 0.3 V POWER OUTPUT (VDD1) (14) VDD1 Output Voltage IDD1 from 2.0 to 200 mA TAMB -40 to 125°C, 5.5 V < VSUP < 27 V VDD1OUT 4.9 5.0 5.1 V VDD1 Output Voltage IDD1 from 2.0 to 200 mA, 4.5 V < VSUP < 5.5 V VDD1OUT2 4.0 — — V Dropout Voltage IDD1 = 200 mA VDD1DRP — 0.2 0.5 V Dropout Voltage, Limited Output Current IDD1 = 50 mA, 4.5 V < VSUP VDD1DRP2 — 0.1 0.25 V IDD1 Output Current Internally Limited IDD1 200 285 350 mA Junction Thermal Shutdown Normal or Standby Modes TSD 160 — 200 Junction Over Temperature Pre-Warning VDDTEMP Bit Set TPW 125 — 160 Temperature Threshold Difference TSD - TPW 20 — 40 °C Reset Threshold 1 Selectable by SPI. Default Value After Reset. RSTTH1 4.5 4.6 4.7 V Reset Threshold 2 Selectable by SPI RSTTH2 4.1 4.2 4.3 V VDD1 Range for Reset Active VDDR 1.0 — — V Reset Delay Time Measured at 50% of Reset Signal tD 4.0 µs Line Regulation (C at VDD1 = 47 µF Tantal)

9.0 V VSUP < 18, IDD = 10 mA

LR1 — 5.0 25 mV Line Regulation (C at VDD1 = 47 µF Tantal) 5.5 < VSUP < 27 V, IDD = 10 mA LR2 — 10 25 mV Load Regulation (C at VDD1 = 47 µF Tantal) 1.0 mA < IIDD < 200 mA LD — 25 75 mV Thermal Stability VSUP = 13.5 V, 1 = -100 mA Not Tested (15) THERMS — 30 50 mV Notes 13. With CAN cell in Sleep-Disable state. If CAN cell is Sleep- Enabled for wake-up, an additional 60 µA must be added to specified value. 14. I DD1 is the total regulator output current. VDD specification with external capacitor. Stability requirement: C > 47 µF ESR < 1.3 Ω (tantalum capacitor). In reset, normal request, normal and standby modes. Measure with C = 47 µF Tantalum. 15. Guaranteed by design; however, it is not production tested. Table 3. Static Electrical Characteristics (continued) values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.

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STATIC ELECTRICAL CHARACTERISTICS POWER OUTPUT (VDD1) IN STOP MODE (16) VDD1 Output Voltage IDD1 < = 2.0 mA VDDSTOP 4.75 5.00 5.25 V VDD1 Output Voltage IDD1 < = 10 mA VDDSTOP2 4.75 5.00 5.25 V IDD1 Stop Output Current to Wake-up SBC IDD1SWU 10 17 25 mA IDD1 Over Current to Wake-up Deglitcher Time (17) IDD1DGLT 40 55 75 µs Reset Threshold RSTSTOP1 4.5 4.6 4.7 V Reset Threshold RSTSTOP2 4.1 4.2 4.3 V Line Regulation (C at VDD1 = 47 µF Tantal) 5.5 V < VSUP < 27 V, IDD = 2.0 mA LRS — 5.0 25 mV Load Regulation (C at VDD1 = 47 µF Tantal) 1 mA < IDD < 10 mA LDS — 15 75 mV Max Decoupling Capacitor at VDD1 Pin, in Stop Mode(18) VDDst-cap — — 200 µF TRACKING VOLTAGE REGULATOR (V2) (19) V2 Output Voltage (C at V2 = 10 µF Tantal) I2 from 2.0 to 200 mA, 5.5 V < VSUP < 27 V 0.99 1.0 1.01 VDD1 I2 Output Current (for information only) Depending Upon External Ballast Transistor 200 — — mA V2 Control Drive Current Capability Worst Case at TJ = 125°C 12CTRL 0.0 — 10 mA V2LOW Flag Threshold V2LTH 3.75 4.0 4.25 V LOGIC OUTPUT PIN (MISO) (20) Low Level Output Voltage IOUT = 1.5 mA VOL 0.0 — 1.0 V High Level Output Voltage IOUT = 250 µA VOH VDD1-0.9 — VDD1 V Tri-Stated MISO Leakage Current

0 V < VMISO < VDD

-2.0 — 2.0 µA Notes 16. If stop mode is used, the capacitor connected at VDD pin should not exceed the maximum specified by the “VDDst-cap” parameter. If capacitor value is exceeded, upon entering stop mode, VDD output current may exceed the IDDSWU and prevent the device to stay in stop mode. 17. Guaranteed by design; however, it is not production tested. 18. Guaranteed by design. 19. V2 specification with external capacitor - Stability requirement: C > 42 µF and ESR < 1.3 Ω (Tantalum capacitor), external resistor between base and emitter required - Measurement conditions: Ballast transistor MJD32C, C = 10 µF Tantalum, 2.2 k resistor between base and emitter of ballast transistor 20. Push/Pull structure with tri-state condition CS high. values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.

Analog Integrated Circuit Device Data Freescale Semiconductor 9 33989 STATIC ELECTRICAL CHARACTERISTICS LOGIC INPUT PINS (MOSI, SCLK, CS) High Level Input Voltage VIH 0.7 VDD1 — VDD1 + 0.3 V Low Level Input Voltage VIL -0.3 — 0.3 VDD1 V High Level Input Current on CS LIH -100 — -20 µA Low Level Input Current on CS LIL -100 — -20 µA MOSI and SCLK Input Current LN -10 — 10 µA RESET PIN (RST) (21) High Level Output Current 0 < VOUT < 0.7 VDD IOH -300 -250 -150 µA Low Level Output Voltage (I0 = 1.5 mA)

5.5 V < VSUP < 27 V

0.0 — 0.9 V Low Level Output Voltage (I0 = 0 µA 1.0 V < VSUP < 5.5 V VOL 0.0 — 0.9 V Reset Pull Down Current V > 0.9 V IPDW 2.3 — 5.0 mA Reset Duration After VDD1 High RSTDUR 3.0 3.4 4.0 ms WATCHDOG OUTPUT PIN (WD) (22) Low Level Output Voltage (I0 = 1.5 mA)

1.0 V < VSUP < 27 V

0.0 — 0.9 V High Level Output Voltage (I0 = 250 µA) VOH VDD1-0.9 — VDD1 V INTERRUPT PIN (INT) (22) Low Level Output Voltage (I0 = 1.5 mA) VOL 0.0 — 0.9 V High Level Output Voltage (I0 = 250 µA) VOH VDD1-0.9 — VDD1 V HIGH SIDE OUTPUT PIN (HS1) RDSON at TJ = 25°C, and IOUT - 150 mA VSUP > 9.0 V RON25 — 2.0 2.5 Ω RDSON at TA = 125°C, and IOUT - 150 mA VSUP > 9.0 V RON125 — — 4.5 Ω RDSON at TA = 125°C, and IOUT - 120 mA 5.5 < VSUP < 9.0 V RON125-2 — 3.5 5.5 Ω Output Current Limitation LLIM 160 — 500 mA HS1 Overtemperature Shutdown OVT 155 — 190 °C HS1 Leakage Current LLEAK — — 10 µA Output Clamp Voltage at IOUT = -10 mA No Inductive Load Drive Capability VCL -1.5 — -0.3 V Notes 21. Push/Pull structure with tri-state condition CS high. 22. Output pin only. Supply from VDD1. Structure switch to ground with pull-up current source. values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.

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STATIC ELECTRICAL CHARACTERISTICS LOGIC INPUTS (L0:L3) Negative Switching Threshold 5.5 V < VSUP < 6.0 V

6.0 V < VSUP < 18 V

18 V < VSUP < 27 V

2.0 2.5 2.7 2.5 3.0 3.2 3.0 3.6 3.7 V Positive Switching Threshold 5.5 V < VSUP < 6.0 V 2.7 3.0 3.5 3.3 4.0 4.2 3.8 4.6 4.7 V Hysteresis 0.6 — 1.3 V Input Current -0.2 V < VIN < 40 V LIN -10 — 10 µA CAN SUPPLY (V2) Supply Current Cell Recessive State IRES — 1.5 3.0 mA Supply Current Cell Dominant State without Bus Load IDOM — 2.0 6.0 mA Supply Current Cell, CAN in Sleep State Wake-up Enable V2 Regulator OFF ISLEEP — 55 70 µA Supply Current Cell, CAN in Sleep State Wake-up Disable V2 Regulator OFF (23) IDIS — — 1.0 µA Notes 23. Push/Pull structure. values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.

Analog Integrated Circuit Device Data Freescale Semiconductor 11 33989 STATIC ELECTRICAL CHARACTERISTICS CANH AND CANL Bus Pins Common Mode Voltage VCM -27 — 40 V Differential Input Voltage (Common Mode Between -3.0 and 7.0 V) Recessive State at RXD Dominant State at RXD VCANH-VCANL 900 500 mV Differential Input Hysteresis (RXD) VHYS 100 — — mV Input Resistance RIN 5.0 — 100 KΩ Differential Input Resistance RIND 10 — 100 KΩ Unpowered Node Input Current ICANUP — — 1.5 mA CANH Output Voltage TXD Dominant State TXD Recessive State VCANHD VCANHR 2.75 4.5 3.0 V CANL Output Voltage TXD Dominant State TXD Recessive State VCANLD VCANLR 0.5 2.0 2.25 V Differential Output Voltage TXD Dominant State TXD Recessive State VDIFFD VDIFFR 1.5 3.0 100 V mV CANH AND CANL Output Current Capability (Dominant State) CANH CANL ICANH ICANL — -35 mA Overtemperature Shutdown TSHUT 160 180°C — °C CANL Over Current Detection Error Reported in CANR ICANL/OC 60 — 200 mA CANH Over Current Detection Error Reported in CANR ICANH/OC -200 — -60 mA TX AND RX TX Input High Voltage VIH 0.7 VDD — VDD + 0.4 V TX Input Low Voltage VILP -0.4 — 0.3 VDD V TX High Level Input Current, VTX = VDD LIH -10 — 10 µA TX Low Level Input Current, VTX = 0 V LIL -100 -50 -20 µA RX Output Voltage High, IRX = 250 µA VOH VDD-1 — — V RX Output Voltage Low, IRX = 1.0 mA VOL — — 0.5 V values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.

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DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 4. Dynamic Electrical Characteristics values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.

1. Guaranteed by design; however it is not production tested.

Analog Integrated Circuit Device Data Freescale Semiconductor 13 33989 DYNAMIC ELECTRICAL CHARACTERISTICS Normal Request Mode Timeout Normal Request Modes NRTOUT 308 350 392 ms Watchdog Period 1 - Stop Stop Mode WD1STOP 6.82 9.75 12.7 ms Watchdog Period 2 - Stop Stop Mode WD2STOP 31.5 45 58.5 ms Watchdog Period 3 - Stop Stop Mode WD3STOP 70 100 130 ms Watchdog Period 4 - Stop Stop Mode WD4STOP 245 350 455 ms Stop Mode Watchdog Period Accuracy Stop Mode f2ACC -30 — 30 Cyclic Sense/FWU Timing 1 Sleep and Stop Modes CSFWU1 3.22 4.6 5.98 ms Cyclic Sense/FWU Timing 2 Sleep and Stop Modes CSFWU2 6.47 9.25 12 ms Cyclic Sense/FWU Timing 3 Sleep and Stop Modes CSFWU3 12.9 18.5 24 ms Cyclic Sense/FWU Timing 4 Sleep and Stop Modes CSFWU4 25.9 37 48.1 ms Cyclic Sense/FWU Timing 5 Sleep and Stop Modes CSFWU5 51.8 74 96.2 ms Cyclic Sense/FWU Timing 6 Sleep and Stop Modes CSFWU6 66.8 95.5 124 ms Cyclic Sense/FWU Timing 7 Sleep and Stop Modes CSFWU7 134 191 248 ms Cyclic Sense/FWU Timing 8 Sleep and Stop Modes CSFWU8 271 388 504 ms Cyclic Sense ON Time Sleep and Stop Modes Threshold and Condition to be Added tON 200 350 500 µs Cyclic Sense/FWU Timing Accuracy Sleep and Stop Modes tACC -30 — 30 Delay Between SPI Command and HS1 Turn ON (25) tSHSON — — 22 µs Delay Between SPI Command and HS1 Turn OFF (25) tSHSOFF — — 22 µs Delay Between SPI and V2 Turn ON (25) Standby Mode tSV2ON 9.0 — 22 µs Delay Between SPI and V2 Turn OFF (25) Normal Mode tSV2OFF 9.0 — 22 µs Notes 25. Delay starts at falling edge of clock cycle #8 of the SPI command and start of Turn ON or Turn OFF of HS1 or V2. Table 4. Dynamic Electrical Characteristics (continued) values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.

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DYNAMIC ELECTRICAL CHARACTERISTICS Delay Between Normal Request and Normal Mode After WD Trigger Command Normal Request Mode tSNR2N 15 35 70 µs Delay Between SPI and CAN Normal Mode SBC Normal Mode (26) tSCANN — — 10 µs Delay Between SPI and CAN Normal Mode SBC Normal Mode (26) tSCANS — — 10 µs Delay Between CS Wake-up (CS Low to High) and SBC Normal Request Mode (VDD1 on and Reset High) SBC in Stop Mode tWCS 15 40 90 µs Delay Between CS Wake-up (CS Low to High) and First Accepted API Command SBC in Stop Mode tWSPI 90 — N/A µs Delay Between INT Pulse and First SPI Command Accepted In Stop Mode After Wake-up tS1STSPI 20 — N/A µs INPUT TERMINNALS (L0, L1, L2, AND L3) Wake-up Filter Time tWUF 8.0 20 38 µs CAN MODULE-SIGNAL EDGE RISE AND FALL TIMES (CANH, CANL) Dominant State Timeout tDOUT 200 360 520 µs Propagation Loop Delay TX to RX, Recessive to Dominant Slew Rate 3 Slew Rate 2 Slew Rate 1 Slew Rate 0 tLRD 100 110 140 155 180 220 210 225 255 310 ns Propagation Delay TX to CAN Slew Rate 3 Slew Rate 2 Slew Rate 1 Slew Rate 0 tTRD 100 120 160 110 150 200 300 ns Propagation Delay CAN to RX, Recessive to Dominant tRRD 30 80 140 ns Propagation Loop Delay TX to RX, Dominant to Recessive Slew Rate 3 Slew Rate 2 Slew Rate 1 Slew Rate 0 tLDR 100 130 120 135 160 200 170 180 220 260 ns Propagation Delay TX to CAN Slew Rate 3 Slew Rate 2 Slew Rate 1 Slew Rate 0 tTDR 110 120 150 190 130 150 200 300 ns Propagation Delay CAN to RX, Dominant to Recessive tRDR 20 40 60 Notes 26. Guaranteed by design; however, it is not production tested. values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.

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DYNAMIC ELECTRICAL CHARACTERISTICS Figure 7. Transceiver AC Characteristics

Analog Integrated Circuit Device Data Freescale Semiconductor 17 33989 Figure 8. SPI Timing Characteristics Incoming data at MOSI pin is sampled by the SBC at SCLK falling edge. Outgoing data at MISO pin is set by the SBC at SCLK rising edge (after tVALID delay time).

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The 33989 is an integrated circuit dedicated to automotive applications. Its functions include:

• One full protected voltage regulator with 200 mA total output current capability available at VDD1 external pin
• Driver for an external path transistor for the V2 regulator function
• Reset, programmable watchdog function, interrupt, and four operational modes
• Programmable wake-up input and Cyclic Sense wake-up
• CAN high-speed physical interface FUNCTIONAL PIN DESCRIPTION RECEIVE AND TRANSMIT DATA (RXD AND TXD) The RX and TX pins (receive data and transmit data pins, respectively) are connected to a microcontroller’s CAN protocol handler. TXD is an input and controls the CANH and CANL line state (dominant when TXD is LOW, recessive when TXD is HIGH). RXD is an output and reports the bus state (RXD LOW when CAN bus is dominant, HIGH when CAN bus is recessive). VOLTAGE DIGITAL DRAIN ONE (VDD1) The VDD1 pin is the output pin of the 5.0 V internal regulator. It can deliver up to 200 mA. This output is protected against overcurrent and overtemperature. It includes an overtemperature pre-warning flag, which is set when the internal regulator temperature exceeds 130°C typical. When the temperature exceeds the overtemperature shutdown (170°C typical), the regulator is turned off. VDD1 includes an undervoltage reset circuitry, which sets the RST pin LOW when VDD1 is below the undervoltage reset threshold. RESET (RST) The Reset pin RST is an output that is set LOW when the device is in reset mode. The RST pin is set HIGH when the device is not in reset mode. RST includes an internal pullup current source. When RST is LOW, the sink current capability is limited, allowing RST to be shorted to 5.0 V for software debug or software download purposes. INTERRUPT (INT) The Interrupt pin INT is an output that is set LOW when an interrupt occurs. INT is enabled using the Interrupt Register (INTR). When an interrupt occurs, INT stays LOW until the interrupt source is cleared. INT output also reports a wake-up event by a 10 µs typical pulse when the device is in Stop mode. VOLTAGE SOURCE TWO (V2) The V2 pin is the input sense for the V2 regulator. It is connected to the external series pass transistor. V2 is also the 5.0 V supply of the internal CAN interface. It is possible to connect V2 to an external 5.0 V regulator or to the VDD1 output when no external series pass transistor is used. In this case, the V2CTRL pin must be left open. VOLTAGE SOURCE 2 CONTROL (V2CTRL) The V2CTRL pin is the output drive pin for the V2 regulator connected to the external series pass transistor. VOLTAGE SUPPLY (VSUP) The VSUP pin is the battery supply input of the device. HIGH-SIDE ONE (HS1) The HS1 pin is the internal high-side driver output. It is internally protected against overcurrent and overtemperature. LEVEL 0-3 INPUTS (L0:L3) The L0:L3 pins can be connected to contact switches or the output of other ICs for external inputs. The input states can be read by SPI. These inputs can be used as wake-up events for the SBC when operating in the Sleep or Stop mode. CAN HIGH AND CAN LOW OUTPUTS (CANH AND CANL) The CAN High and CAN Low pins are the interfaces to the CAN bus lines. They are controlled by TX input level, and the state of CANH and CANL is reported through RX output. A 60 Ω termination resistor is connected between CANH and CANL pins. SYSTEM CLOCK (SCLK) SCLK is the System Clock input pin of the serial peripheral interface. MASTER IN SLAVE OUT (MISO) MISO is the Master In Slave Out pin of the serial peripheral interface. Data is sent from the SBC to the microcontroller through the MISO pin.

Analog Integrated Circuit Device Data Freescale Semiconductor 19 33989 FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION MASTER OUT SLAVE IN (MOSI) MOSI is the Master Out Slave In pin of the serial peripheral interface. Control data from a microcontroller is received through this pin. CHIP SELECT (CS) CS is the Chip Select pin of the serial peripheral interface. When this pin is LOW, the SPI port of the device is selected. WATCHDOG (WD) The Watchdog output pin is asserted LOW to flag that the software watchdog has not been properly triggered.

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FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES FUNCTIONAL DEVICE OPERATION DEVICE SUPPLY The device is supplied from the battery line through the VSUP pin. An external diode is required to protect against negative transients and reverse battery. It can operate from 4.5 V and under the jump start condition at 27 Vdc. This pin sustains standard automotive voltage conditions such as load dump at 40 V. When VSUP falls below 3.0 V typical the 33989 detects it and stores the information into the SPI register in a bit called BATFAIL. This detection is available in all operation modes. The device incorporates a battery early warning function, providing a maskable interrupt when the VSUP voltage is below 6.0 V typical. A hysteresis is included. Operation is only in Normal and Standby modes. VSUP low is reported in the Input/Output Register (IOR). VDD1 VOLTAGE REGULATOR The VDD1 Regulator is a 5.0 V output voltage with output current capability up to 200 mA. It includes a voltage monitoring circuitry associated with a reset function. The VDD1 regulator is fully protected against overcurrent and short-circuit. It has over- temperature detection warning flags (bit V DDTEMP in MCR and interrupt registers), and overtemperature shutdown with hysteresis. V2 REGULATOR V2 Regulator circuitry is designed to drive an external path transistor increasing output current flexibility. Two pins are used to achieve the flexibility. Those pins are V2 and V2 control. The output voltage is 5.0 V and is realized by a tracking function of the VDD1 regulator. The recommended ballast transistor is MJD32C. Other transistors can be used; however, depending upon the PNP gain an external resistor- capacitor network might be connected. The V2 is the supply input for the CAN cell. The state of V2 is reported in the IOR (bit V2LOW set to 1 if V2 is below 4.5 V typical). HS1 VBAT SWITCH OUTPUT The HS1 output is a 2.0 Ω typical switch from the VSUP pin. It allows the supply of external switches and their associated pull-up or pull down circuitry, in conjunction with the wake-up input pins, for example. Output current is limited to 200 mA and HS1 is protected against short-circuit and has an overtemperature shutdown (bit HS1OT in IOR and bit HS1OT-V2LOW in INT register). The HS1 output is controlled from the internal register and the SPI. Because of an internal timer, it can be activated at regular intervals in Sleep and Stop modes. It can also be permanently turned on in Normal or Standby modes to drive loads or supply peripheral components. No internal clamping protection circuit is implemented, thus a dedicated external protection circuit is required in case of inductive load drive. BATTERY FALL EARLY WARNING Refer to the discussion under the heading: Device Supply. INTERNAL CLOCK The device has an internal clock used to generate all timings (Reset, Watchdog, Cyclic Wake-up, Filtering Time, etc.). Two oscillators are implemented. A high accuracy (±12 percent) used in Normal Request, Normal and Standby modes, and a low accuracy (±30 percent) used in Sleep and Stop modes. OPERATIONAL MODES FUNCTIONAL MODES The device has four primary operation modes: 1. Standby mode 2. Normal mode 3. Stop mode 4. Sleep mode All modes are controlled by the SPI. An additional temporary mode called Normal Request mode is automatically accessed by the device after reset or wake-up from Stop mode. A Reset ( RST) mode is also implemented. Special modes and configuration are possible for debug and program MCU flash memory. STANDBY MODE Only regulator 1 is ON. Regulator 2 is turned OFF by disabling the V2 control pin. Only the wake-up capability of the CAN interface is available. Other functions available are wake-up input reading through SPI and HS1 activation. The Watchdog is running. NORMAL MODE In this mode both regulators are ON. This corresponds to the normal application operation. All functions are available in this mode (Watchdog, wake-up input reading through SPI, HS1 activation, CAN communication). The software Watchdog is running and must be periodically cleared through SPI. STOP MODE Regulator 2 is turned OFF by disabling the V2 control pin. The regulator 1 is activated in a special low power mode, allowing to deliver few mA. The objective is to maintain the MCU of the application supplied while it is turned into power saving condition (i.e Stop or Wait modes). In Stop mode the device supply current from V BAT is very low.

Analog Integrated Circuit Device Data Freescale Semiconductor 21 33989 FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES When the application is in Stop mode (both MCU and SBC), the application can wake-up from the SBC side (for example: cyclic sense, forced wake-up, CAN message, wake-up inputs and over current on VDD1), or the MCU side (key wake-up, etc.). Stop mode is always selected by the SPI. In Stop mode the software Watchdog can be running or idle depending upon selection by the SPI (RCR, bit WDSTOP). To clear the watchdog, the SBC must be awakened by a CS pin (SPI wake-up). In Stop mode, SBC wake-up capability are identical as in Sleep mode. Please refer to Table 5. SLEEP MODE Regulators 1 and 2 are OFF. The current from VSUP pin is reduced. In this mode, the device can be awakened internally by cyclic sense via the wake-up inputs pins and HS1 output, from the forced wake-up function and from the CAN physical interface. When a wake-up occurs the SBC goes first into reset mode before entering Normal Request mode. RESET MODE In this mode, the Reset (RST) pin is low and a timer is running for a time RSTDUR. After this time is elapsed, the SBC enters Normal Request mode. Reset mode is entered if a reset condition occurs (VDD1 low, watchdog timeout or watchdog trigger in a closed window). NORMAL REQUEST MODE This is a temporary mode automatically accessed by the device after the reset mode, or after the SBC wake-up from Stop mode. After wake-up from the Sleep mode or after the device power-up, the SBC enters the Reset mode before entering the Normal Request mode. After a wake-up from the Stop mode, the SBC enters Normal Request mode directly. In Normal Request mode the VDD1 regulator is ON, V2 is OFF, the reset pin is high. As soon as the device enters the Normal Request mode an internal 350 ms timer is started. During these 350 ms the microcontroller of the application must address the SBC via the SPI, configuring the Watchdog register. This is the condition for the SBC to stop the 350 ms timer and to go into the Normal or Standby mode and to set the watchdog timer according to configuration. NORMAL REQUEST ENTERED AND NO WD CONFIGURATION OCCURS In case the Normal Request mode is entered after SBC power-up, or after a wake-up from Stop mode, and if no WD configuration occurs while the SBC is in Normal Request mode, the SBC goes to Reset mode after the 350 ms time period is expired before again going into Normal Request mode. If no WD configuration is achieved, the SBC alternatively goes from Normal Request into reset, then Normal Request modes etc. In case the Normal Request mode is entered after a wake- up from Sleep mode, and if no WD configuration occurs while the SBC is in Normal Request mode, the SBC goes back to Sleep mode. APPLICATION WAKE-UP FROM SBC SIDE When an application is in Stop mode, it can wake-up from the SBC side. When a wake-up is detected by the SBC (for example, CAN, Wake-up input, etc.) the SBC turns itself into Normal Request mode and generates an interrupt pulse at the INT pin. APPLICATION WAKE-UP FROM MCU SIDE When application is in Stop mode, the wake-up event may come from the MCU side. In this case the MCU signals to the SBC by a low to high transition on the CS pin. Then the SBC goes into Normal Request mode and generates an interrupt pulse at the INT pin. STOP MODE CURRENT MONITOR If the VDD1 output current exceed an internal threshold (IDD1SWU), the SBC goes automatically into Normal Request mode and generates an interrupt at the INT pin. The interrupt is not maskable and the interrupt register will has no flag set. INTERRUPT GENERATION WHEN WAKE-UP FROM STOP MODE When the SBC wakes up from Stop mode, it first enters the Normal Request mode before generating a pulse (10 µs typical) on the INT pin. These interrupts are not maskable, and the wake-up event can be read through the SPI registers (CANWU bit in Reset Control Register (RCR) and LCTRx bit in Wake-Up Register (WUR). In case of wake-up from Stop mode over current or from forced wake-up, no bit is set. After the INT pulse the SBC accept SPI command after a time delay (tS1STSPI parameter). SOFTWARE WATCHDOG IN STOP MODE If Watchdog is enabled, the MCU has to wake-up independently of the SBC before the end of the SBC watchdog time. In order to do this the MCU must signal the wake-up to the SBC through the SPI wake-up ( CS activation). The SBC then wakes up and jumps into the Normal Request mode. MCU has to configured the SBC to go to either Normal or Standby mode. The MCU can then decide to go back again to Stop mode. When there is no MCU wake-up occurring within the watchdog timing, the SBC activates the Reset pin, jumping into the Normal Request mode. The MCU can then be initialized. STOP MODE ENTER COMMAND Stop mode is entered at the end of the SPI message, and at the rising edge of the CS. Please refer to the t CSSTOP data in Dynamic Electrical Characteristics table on page 11. Once Stop mode is entered the SBC could wake-up from the V1 regulator over current detection. In order to allow time for the MCU to complete the last CPU instruction, allowing

22 Freescale Semiconductor

typical 40 µs is implemented. Figure 9 indicates the operation to enter Stop mode. Figure 9. Operation Entering Stop Mode the period. Refer to the SPI TIM register description. Watchdog can only be cleared within the open window time. addressing the TIM1 register. (please refer to Table 5 for reset pin operation).

• V DD1 falling out of range — If V DD1 falls below the reset threshold (parameter RSTTH), the ret pin is pulled low until VDD1 returns to the normal voltage.
• Power-on reset — At device power-on or at device wake- up from Sleep mode, the reset is maintained low until VDD1 is within its operation range. Watchdog timeout — If watchdog is not cleared, the SBC will pull the reset pin low for the duration of the reset time (parameter RSTDUR). In Mode 2, the reset pin is not activated in case of Watchdog timeout. Please refer to Table 6 for more detail. For debug purposes at 25°C, the Reset pin can be shorted to 5.0 V because of its internal limited current drive capability. RESET AND WATCHDOG OPERATION: MODES1 AND 2 Watchdog and Reset functions have two modes of operation: SPI CS SPI Stop/ Sleep Command SBC in Normal or Stand-by mode SBC in Stop mode SBC in Stop mode IDD1DGLTtCSSTOP with IDD1over I wake-upno IDD1 over I wake-up

Table 5. Reset and Watchdog Output Operation

1. WD stays low until the Watchdog register is properly addressed through SPI.

Analog Integrated Circuit Device Data Freescale Semiconductor 23 33989 FUNCTIONAL DEVICE OPERATION RESET AND WATCHDOG PINS, SOFTWARE WATCHDOG OPERATIONS 1. Mode 1 2. Mode 2 (also called Safe mode) These modes are independent of the SBC modes (Normal, Standby, Sleep, and Stop). Modes 1 and 2 selection is achieved through the SPI (register MCR, bit SAFE). Default mode after reset is Mode 1. Table 5 provides Reset and Watchdog output mode of operation. Two modes (modes 1 and 2) are available and can be selected through the SPI Safe bit. Default operation, after reset or power-up, is Mode 1. In both modes reset is active at device power-up and wake-up.

• In mode 1–Reset is activated in case of V DD1 fall or watchdog not triggered. WD output is active low as soon as reset goes low. It remains low as long as the watchdog is not properly re-activated by the SPI.
• In mode 2–(Safe mode) Reset is not activated in case of watchdog fault. WD output has the same behavior as in mode 1–The Watchdog output pin is a push-pull structure driving external components of the application for signal instance of an MCU wrong operation.

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Table 6. Table of Operation

Figure 10. Reset and Watchdog Functions Diagram in Modes 1 and 2 registers. The MCU can then access to the wake-up source. It generates an interrupt if wake-up occurs from Stop mode. Stop modes). The wake-up pins are able to handle 40 V DC. read through SPI (register WUR). cyclic sense) is valid for all 4 wake-up inputs. physical interface operation is accomplished through the SPI. CAN modes are independent of the SBC operation modes. description for detail of wake-up detection.

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moving into Normal Request mode.

• Step 1–Power down the SBC
• Step 2–Power-up the SBC (The BATFAIL bit is set, allowing the SBC to enter Normal Request mode)
• Step 3–Write to TIM1 register allowing SBC entering Normal mode
• Step 4–Write to MCR register with data 0000, enabling the Debug mode. Complete SPI byte: 000 1 0000
• Step 5–Write to MCR register normal debug (0001x101)
• Step 6–To leave the Debug mode, write 0000 to MCR register While in Debug mode, the SBC can be used without having to clear the WD on a regular basis to facilitate software and hardware debug. At Step 2, the SBC is in Normal Request. Steps 3, 4, and 5 should be completed consecutively and within the 350 ms time period of the Normal Request mode. If this step is not accomplished in a timely manner, the SBC will go into Reset mode, entering Normal Request again. When the SBC is in Debug mode, and set in Stop Debug or Sleep Debug, when a wake-up occurs the SBC enters Normal Request mode for a time period of 350 ms. To avoid the SBC generating a reset (enter Reset mode) the desired next Debug mode (Normal Debug or Standby Debug) should be configured within the 350 ms time period of the Normal Request mode. For details, please refer to State Machine in Debug mode, Figure 16. To avoid entering Debug mode after a power-up, first read BATFAIL bit (MCR read) and write 0000 into MCR. Figure 15 illustrates the Debug mode enter.

Figure 11. Debug Mode Enter

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Figure 14. Behavior at SBC Power-Up Figure 15. Transitions to Enter Debug Modes

Figure 16. Simplified State Machine in Debug Modes MCU to SBC, or read back from SBC to MCU. a meaning (content of the accessed register). (1) If Stop mode entered, it is entered without watchdog, no matter the WDSTOP bit. (E) Debug mode entry point (Step 5 of the Debug mode entering sequence). (R) Represents transitions to Reset mode due to VDD1 low. Table 7. Data Format Description

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Table 8. List of Registers

Table 9 provides Mode Control Register data. Table 9. MCR Register

1. Bit BATFAIL cannot be set by SPI. BATFAIL is set when V SUP falls below 3.0 V.

Table 10. MCR Control Bits Debug Mode: Hardware and Software Debug...

1. Watchdog ON or OFF depends on RCR bit D3.
2. Before entering Sleep mode, bit BATFAIL in MCR must be previo usly cleared (MCR read operation), and bit NOSTOP in RCR must be

Table 11. MCR Status Bits

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provides RCR Status Bits data. mode, slew rate, and wake-up. Table 12. RCR Register Table 13. RCR Control Bits Table 14. RCR Status Bits

1 Watchdog Runs in Stop Mode

1 Sleep Mode Allowed, Device Can Enter Sleep Mode

Table 15. CAN Register

• Turn V2 ON (SBC in Normal mode and V2 above V2 threshold) the CAN interface must be set into CAN Sleep
• Return to CAN NORMAL Input/Output Control Register (IOR) Table 18 provides data about HS1 control in Normal and Standby modes, while Table 19 provides control bit data. When HS1 is turned OFF due to an over temperature condition, it can be turned ON again by setting the appropriate control bit to 1. Error bits are latched in the Input/ Output Registers (IOR). Please see Table 20.

Table 16. CAN High-Speed Transceiver Modes Table 17. CAN Status Bits Table 18. IOR Register Table 19. IOR Control Bits

0 HS1 OFF, in Normal and Standby Modes

1 HS1 ON, in Normal and Standby Modes

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as and for waking up the SBC in Sleep or Stop modes. configured together. Please see Table 22. Table 23 provides Status bits data. Table 20. IOR Status Bits Table 21. WUR Register Table 22. WUR Control Bits Table 23. WUR Status Bits threshold, 0 means that LX input is below threshold). only if SBC was in Stop mode.

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Figure 19. HS1 Operation when Cyclic Sense is Selected

• The state of HS1 in Stop and Sleep mode (HS1 permanently off or HS1 cyclic)
• Enable or disable the forced wake-up function (SBC automatic wake-up after time spend in Sleep or Stop modes, time is defined by the TIM2 register)
• Enable or disable the sense of the wake-up inputs (Lx) at sampling point of the Cyclic Sense period (LX2HS1 bit). Please refer to the Cyclic Sense Wake-up discussion for details of the LPC register setup required for proper Cyclic Sense or direct wake-up operation.

Table 27. TIM1 Control Bits Table 28. LPC Register Table 29. LX2HS1 Control Bits

1 Yes, Lx Inputs Sensed at Sampling Point

Table 30. HS1AUTO Control Bits

0 OFF

1 ON, HS1 Cyclic, Period Defined in TIM2 Register

source. A read operation informs about the interrupt source. appropriate condition occurs.

1. Bit D2 = 1: INT source is HS1OT
2. Bit D2 = 0: INT source is V2LOW

HS1OT and V2LOW bits status are available in IOR. (not bit set into the INT register). register the INT register is updated. Errors bits are latched in the CAN register and IOR. Table 31. INT Register Table 32. INT Control Bits Table 33. INT Status Bits

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Figure 20. Typical Application Diagram

Analog Integrated Circuit Device Data Freescale Semiconductor 39 33989 TYPICAL APPLICATIONS SUPPLEMENTAL APPLICATION NOTES SUPPLEMENTAL APPLICATION NOTES MC33989 - GENERAL INFORMATION MC33989 device supply on page 39 Voltage Regulator on page 40 Failure on VDD1, Watchdog, Reset, INT Pins on page 41 WAKE-UP TIMINGS - SLEEP MODE LX Wakes up SBC from Sleep Mode on page 42 CAN Wake-Up on page 42 LX with Cyclic Sense on page 43 WAKE UP TIMING: STOP MODE LX Wake-Up on page 43 CAN Wake-Up on page 44 CS Wake-Up on page 44 Overcurrent Wake-Up on page 44 LX with Cyclic Sense on page 45 MC33989 CAN INTERFACE Block Diagram on page 45 CAN Interface Supply on page 46 Main Operation Modes Description on page 46 CAN Driver Operation in Normal Mode on page 46 CAN Mode versus SBC Modes on page 48 How to Test the MC33989 CAN Interface on page 48 CAN LOW POWER MODE AND WAKE-UP Low Power Mode on page 49 Wake-Up on page 49 FAILURE ON V2 SUPPLY, CAN BUS LINES, AND TX PIN V2LOW on page 51 TX Permanent Dominant on page 51 CAN Driver Overtemperature: on page 52 Overcurrent Detection: on page 52 Protection on page 52 Current in Case of Bus Short Conditions on page 52 SOFTWARE ASPECTS Introduction on page 54 How to Enter in Normal Mode After a Power-Up on page How to Change CAN Slew Rate on page 55 How to Set the CAN Interface in Sleep Mode on page 55 How to Control HS1 Output on page 55 How to Configure Wake-Up Before Going in Low Power Mode on page 56 Disable all Wake-Up on page 56 How to Enter in Sleep Mode on page 57 How to Enter in Stop Mode with Watchdog on page 57 How to Enter in Stop Mode without Watchdog on page 57 How to Recognize and Distinguish the Wake-Up Source on page 58 How to Use the Interrupt Function on page 59 Recognition and Recovery on page 59 How to Distinguish Between V2LOW and HS1 Overtemperature on page 59 GENERAL INFORMATION The parameters given in the application section are for information only. Reference the electrical tables beginning on page 4 for actual operating parameters. MC33989 device supply The MC33989 is supplied from the battery line. A serial diode is necessary to protect the device against negative transient pulses and from reverse battery situation. This is illustrated in the device typical application schematic.

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Figure 21. Device Typical Application Schematic

• C4: 100 nF
• C3: 10 µF < C3 < 22 µF, esr < 1 ohms. 22 µF < C3 < 47 µF, esr < 5 ohms. C3 > = 47 µF, esr < 10 ohms V2 Regulator: Operation with External Ballast Transistor The V2 regulator is a tracking regulator of the V1 output. Its accuracy relative to V1 is ±1%. It requires external decoupling and stabilizing capacitors. The recommended value are: 22 µF esr < 5 ohms, and 47 µF esr < 10 ohms. The V2 pin has two functions: sense input for the V2 regulator and 5 V power supply input to the CAN interface. Ballast transistor selection: PNP or PMOS transistors can be used. A resistor between base and emitter (or source and drain) is necessary to ensure proper operation and optimized performances. Recommended bipolar transistor is MJD32C. V2 Regulator: Operation without Ballast Transistor The external ballast transistor is optional. If the application does not requires more than the maximum output current capability of the V1 regulator, then the ballast transistor can be omitted. The thermal aspects must be analyzed as well. The electrical connections are shown in Figure 22.

Figure 22. V2 Regulator Operation

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and after 100 ms the SBC enters sleep mode. Figure 25. Power up and VDD1 Going Low with Sleep Mode as Default Low Power Mode Selected to high and the MCU is ready to start software operations.

• T1 (LX high level to V DD1 turn on): typ 100 µs.
• T 2 : VDD1 rising time is dependent on the capacitor and the load connected to VDD1. It can be approximated by the capacitor charging time with the regulator output current limitation: T2 = (C x U)/I. With C = 100 mF, IDD1 = 200 mA min., U = 5 V so T2 = 2.5 ms).
• T3 (VDD1>RST-TH (4.6 V by default) to reset high): parameter Rest dur: 4 ms max.
• The total time is 6.6 ms in this example. CAN Wake-Up The following case describes the signal for CAN wake up. Refer to page 49 for more details on CAN wake up signals and the TCAN analysis. SBC in Reset mode (BATFAIL flag must be cl eared) SBC in Sleep mode 100 ms SBC in Normal request mode SBC in Normal mode SBC in RESET mode 350 ms VDD1 SPI (CS) INT WD RST Reset every 350 ms Write Watchdog each X ms No problem on Watchdog period LX VDD1 RST t1 t3t2

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Figure 29. Lx Wake-Up The case below describes the signal for CAN wake-up. Figure 30. CAN Wake-Up

• T CAN: refer to page 49 for more details.
• T1: Third pulse on CAN to INT pulse: typ 80 µs.
• The total time is 113 µs in this case. CS Wake-Up The figure below describes the wake up from a CS signal transition, while the SBC is in stop mode.

Figure 31. CS Wake-Up

• T 1 : CS rising edge to INT pulse: typ 60 µs.
• The total time is 133 µs in this case. Overcurrent Wake-Up The following figure describes the signal when an overcurrent is detected at VDD1. A VDD1 overcurrent condition will lead to a wake-up from stop mode. INT SBC ready to accept SPI command. Wake-up signalled to MCU. tINT + tS-1STSPI (33µs max) tINT + tS-1STSPI (33µs max) CAN INT t1 SBC ready to accept SPI command.Wake-up signalled to MCU. tCAN CS INT T1 SBC ready to accept SPI command.Wake-up signalled to MCU. tINT + tS-1STSPI (33µs max)

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Figure 34. 33989 CAN Interface are controlled by the SPI command. slew rates are available for the user. the remote CAN wake-up capability. reported through the RX pin. divided by 2, approx. 2.5 V. CANH is pulled high toward 5 V (the voltage at V2). threshold, the bus is recessive and RX is set high. Figure 35. CAN Driver Operation in Normal Mode

48 Freescale Semiconductor

Table 34. CAN vs SBC Modes The CAN interface can be easily set up and tested. Figure 38. Testing the CAN Interface

5 V Internal pull up

level. This is illustrated in Figure 39. Figure 39. Low Power Mode CAN bus wake-up is a pattern wake-up. bus traffic will not be detected by the MC33989. occurred while the CAN interface was in sleep mode.

• The CAN interface wake-up receiver must receive a series of 3 consecutive valid dominant pulses, each of them has to be longer than 500 ns and shorter than 500 µs.
• The distance between 2 pulses must be lower than 500 µs and the three pulse must occur within a time frame of 1 ms. CANL CANH TX RX GND 2.5V CANL-DOM CANH-DOM CANL/CANH-REC CAN in Normal mode CAN in Sleep mode (wake-up enable or disable) CAN in TX RX mode (controlled by SPI command)

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Figure 40. Pattern Wake-Up a CAN wake-up occurs in sleep or stop mode. Figure 41. SBC Key Signals

52 Freescale Semiconductor

will be signalled. The GFAIL flag is set in the MCR register. hysteresis, the CAN driver is automatically re-enabled.

• No longer “CAN overtem perature situation” AND
• Read operation of the CAN register. Overcurrent Detection: The CAN interface can detect and signal over current condition, occurring for instance in case of CANL shorted to VBAT. This is signalled by the bit CUR in the CAN register. An INT can be enabled, and GFAIL bit is set. The CUR bit is latched and two conditions are necessary to clear it:
• No longer “CAN over current situation” AND
• Read operation of the CAN register. Protection The MC33989 CAN output is protected for automotive environments. The CAN driver is protected against overtemperature and overcurrent. ISO7637 Transient The CANH and CANL are rated from +40 Vdc to -27 Vdc. This means that the MC33989 CAN output can handle failure situations like the bus directly shorted to the battery line in a load dump situation (+40 V). Ground disconnection of the module will lead to the CANH and CANL line floating high to the VBAT supply. The rest of the network will not be affected. However the CANH and CANL lines of the ungrounded module will see a negative voltage of the VBAT value, with respect to their gnd level. Such situations can be handled by the CAN interface of the MC33989, but also in cases of a jump start (battery at 27 and gnd disconnection. Fast transient pulses, ISO7637-3. During these pulses, the maximum rating of the CANH and CANL lines of +40 Vdc and -27 Vdc must be respected. ESD The CANH and CANL line of the MC33989 are rated at ±4 kV. An external capacitor between CANH and CANL to gnd or a zener diode suppressor can be added to ensure a higher module resistance to ESD. Current in Case of Bus Short Conditions In case of short circuit condition on the CAN bus the current in the CAN supply, the CAN line can be different from the nominal case. The Figure 44 and Table 35 describe the various cases.

Figure 44. Current in Case of Bus Short Conditions

Table 35. Current in Case of Bus Short Conditions

1. For the failure case which leads to loss of communication and current flow for a very short time period as illustrated in Figure 45. So for

figure are placed in a CANH to CANL short circuit condition. Figure 45. CANH to CANL Short Circuit Condition error passive level (TEC=128). the TEC reaches 255: then the node is in the BUS OFF state. order to recover and be able to transmit again. No failure 32 0 0 Normal communication. CANH line to 5 V 55 -55 0 communication OK. CANH line to +VBAT 150 -150 0 communication OK. CANL line to gnd 50 0 50 communication OK.

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Figure 46. Node is in Bus Off State to MC33989 specifications for more details. Node sends one dominant bit. As there is still the fault, the TEC is incremented by 8 each time.

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Figure 50. Wake-Up Configure Before Low Power Mode Figure 51. Enable CAN Wake-Up Figure 52. Enable Wake-Up From LX without Cyclic Sense Figure 53. Enable Wake-Up From LX with Cyclic Sense Figure 54. Force Wake-Up Figure 55. Disable all Wake-Up

• Turn on HS1
• Turn off HS1 Write IOR= $74 Write IOR= $70
• CAN sleep and CAN wake-up enable note: CAN interface will enter sleep mode as soon as this command is sent in Write CAN= $51
• no force wake-up, no cyclic sense, no LX cyclic
• Wake-up levels on LX refer to the specification for details Write LPC =$D0 Write WUR= $9X
• No force wake-up, cyclic sense function, LX cyclic
• Cyclic sense period
• Wake-up levels on LX Write LPC =$D9 Write TIM2= $BX Write WUR =$9X Write LPC= $D4 Write TIM2= $BX
• Force wake-up, no cyclic sense function, LX cyclic
• Force wake-up period
• Disable Force wake-up,LX cyclic
• Disable LX
• CAN sleep and CAN wake-up disable note: can interface will enter sleep mode as soon as $53 is sent Write LPC =$D0 Write WUR =$90 Write CAN =$53

58 Freescale Semiconductor

Figure 59. Recognize and Distinguish the Wake-Up Source

• Wake-up from CAN
• Power-upBatfail in MCR register =»1»? CANWU in CAN register=»1»? NO
• Force wake-up
• Wake-up from LXWUR =XX? NO
• CS wake-up Vsuplow in IOR register =»1»? NO NO NO NO
• Idd1_stop over current (>10 mA) SBC was in stop mode YES YES YES YES YES YES Was FWU enabled? Was any SPI command sent? VBAT undervoltage (<6.1 V) leading a VDD1 undervoltage reset

Analog Integrated Circuit Device Data

60 Freescale Semiconductor

For the most current package revision, visit www.freescale.com and perform a keyword search using the “98A” listed below. DW SUFFIX 28-PIN 98ASB42345B ISSUE G EG SUFFIX (Pb-Free)

Analog Integrated Circuit Device Data Freescale Semiconductor 61 33989 PACKAGING PACKAGE DIMENSIONS DW SUFFIX 28-PIN 98ASB42345B ISSUE G EG SUFFIX (Pb-Free)

62 Freescale Semiconductor

application, and packaging information is provided in the data sheet. simulation according to the standards listed below. Figure 62. Surface Mount for SOIC Wide Body Table 36. Thermal Performance Comparison

1. Per JEDEC JESD51-2 at natural convection, still air
2. 2s2p thermal test board per JEDEC JESD51-7.
3. Per JEDEC JESD51-8, with the board temperature on the

center trace near the center lead.

1. Single layer thermal test board per JEDEC JESD51-3.
2. Thermal resistance between the die junction and the

surface and remaining surfaces insulated.

28 Terminal SOICW

Figure 63. Thermal Test Board

33989 Pin Connections

Table 37. Thermal Resistance Performance

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Figure 64. Device on Thermal Test Board RθJA Figure 65. Transient Thermal Resistance RθJA

1 W Step response, Device on Thermal Test Board Area A = 600 (mm2)

Analog Integrated Circuit Device Data Freescale Semiconductor 65 33989

REVISION HISTORY

REVISION DATE DESCRIPTION OF CHANGES 4.91 7/2002 • Released XC33989: Motorola Format 5.0 8/2005 • Changed document to Freescale format

• Added New Orderable Part Number
• Maximum Rating Table; Added CANH, CANL and ESD ratings
• Static Electrical Characteristics - Table 3
• POWER INPUT (V SUP): (ISUP(STOP2); Max rating changed from 410 to 210 µA)
• POWER OUTPUT(V DD1): VDD1OUT Min rating changed from 4.0 to 4.75 V
• Added CAN SUPPLY, CANH and CANL, TX and RX ratings
• Dynamic Electrical Characteristics - Table 4
• STATE MACHINE TIMING ( CS, SCLK, MOSI, MISO, WD, INT): CSFWU7 max rating changed from 248 to 128 ms
• Added CAN MODULE-SIGNAL EDGE RISE AND FALL TIMES (CANH, CANL) ratings
• Revised Application Section
• Added supplemental Application Notes
• Added Thermal Addendum 6.0 9/2005 • Cosmetic corrections
• CS, INT and WD Pins were changed to CS, INT and WD 7.0 11/2005 • Published in error 8.0 11/2005 • Static Electrical Characteristics - Table 3, added new parameter “VDDst-cap” and Notes 14 and 16, corrected VDD1 output voltage VDD1OUT2 to minimum 4.0 V as previously published in revision 4.91.
• Dynamic Electrical Characteristics - Table 4, Corrected Max Rating of 248 ms for Cyclic Sense/FWU Timing 7 CSFWU7 as previously published in revision 4.91 9.0 1/2006 • Dynamic Electrical Characteristics - Table 4,Corrected “Cyclic Sense ON Time” measurement “Unit” from ms to µs 10.0 6/2006 • Updated to the prevailing Freescale form and style
• Updated from Advance Information to Final documentation
• Removed PC33989EG/R2 and replaced with MCZ33989EG/R2 in the Ordering Information block 11.0 11/2006 • Replaced the label Logic Inputs with Logic Signals (RX, TX, MOSI, MISO, CS, SCLK, RST, WD, and INT) on page 4
• Replaced Logic Output Pins with LOGIC Input PINS (MOSI, SCLK, CS) on page 9
• Reviewed labeling for device pins VDD1, RST, INT, CS, VSUP, TX, RX, V2CTRL, V2, and WD throughout the data sheet, and made corrections as applicable. 12.0 12/2006 • Made changes to Supply Current in Standby Mode (10) (11) on page 6 and Supply Current in Normal Mode (10) on page 6
• Removed Peak Package Reflow Temperature During Reflow (solder reflow) parameter from Maximum Ratings on page 4. Added note with instructions to obtain this information from www.freescale.com. 13.0 3/2007 • Added the EG suffix to the included thermal addendum

Rev. 13.0 RoHS-compliant and/or Pb-free versions of Freescale products have the functionality and electrical characteristics of their non-RoHS-compliant and/or non-Pb-free counterparts. For further information, see http://www.freescale.com or contact your Freescale sales representative. For information on Freescale’s Environmental Products program, go to http:// www.freescale.com/epp. Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”, must be validated for each customer application by customer’s technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc., 2007. All rights reserved. How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. Technical Information Center, EL516

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