33984B

33984B FREESCALE | Alldatasheet

Document overview

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Technical content

Features

• D u a l 4 . 0 mΩ Max High-Side Switch with Parallel Input or SPI Control
• 6 . 0 V to 27 V Operating Voltage with Standby Currents < 5.0 µA
• Output Current Monitoring with Two SPI-Selectable Current Ratios
• SPI Control of Overcurrent Limit, Overcurrent Fault Blanking Time, Output-OFF Open Load Detection, Output ON/OFF Control, Watchdog Timeout, Slew Rates, and Fault Status Reporting
• SPI Status Reporting of Overcurrent, Open and Shorted Loads, Overtemperature, Undervoltage and Overvoltage Shutdown, Fail- Safe Pin Status, and Program Status
• Enhanced -16 V Reverse Polarity VPWR Protection

Figure 1. 33984 Simplified Application Diagram

ORDERING INFORMATION

Range (TA) Package MC33984BPNA/R2 - 40°C to 125°C 16 PQFN BOTTOM VIEW PNA SUFFIX 98ARL10521D 16-PIN PQFN VDD I/O I/O SO SCLK CS SI I/O I/O I/O A/D VPWR FS WAKE SI SCLK CS SO RST INO IN1 CSNS FSI GND HS1 HS0 GND LOAD LOAD 33984B MCU VDDVDDVDD VPWR

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Figure 2. 33984 Simplified Internal Block Diagram

100 A or 75 A

3.0 MHz

Figure 3. 33984 Pin Connections (Transparent Top View) Table 1. Pin Definitions Functional descriptions of many of these pins can be found in the Functional Pin Description section beginning on page 16.

2 WAKE Input Wake This pin is used to input a Logic [1] signal so as to enable the

3 RST Input Reset (Active Low) This input pin is used to initialize the device configuration and fault

registers, as well as place the device in a low current sleep mode. 4 IN0 Input Direct Input 0 This input pin is used to directly control the output HS0. resistor to VDD for fault reporting.

6 FSI Input Fail-Safe Input The value of the resistance connected between this pin and ground

determines the state of the outputs after a watchdog timeout occurs.

7 CS Input Chip Select (Active Low) This input pin is connected to a chip select output of a master

8 SCLK Input Serial Clock This input pin is connected to the MCU providing the required bit shift

clock for SPI communication.

9 SI Input Serial Input This is a command data input pin connected to the SPI Serial Data

10 VDD Input Digital Drain Voltage

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11 SO Output Serial Output This output pin is connected to the SPI Serial Data Input pin of the

MCU or to the SI pin of the next device of a daisy chain of devices. 12 IN1 Input Direct Input 1 This input pin is used to directly control the output HS1. 13 GND Ground Ground This pin is the ground for the logic and analog circuitry of the device. of operational power for the device. 15 HS1 Output High-Side Output 1 Protected 4.0 mΩ high-side power output to the load. 16 HS0 Output High-Side Output 0 Protected 4.0 mΩ high-side power output to the load. Table 1. Pin Definitions (continued) Functional descriptions of many of these pins can be found in the Functional Pin Description section beginning on page 16.

Analog Integrated Circuit Device Data Freescale Semiconductor 5 33984

ELECTRICAL CHARACTERISTICS

Table 2. Maximum Ratings All voltages are with respect to ground unless otherwise noted.

1. Exceeding this voltage limit may c ause permanent damage to the device.
2. Continuous high-side output current rati ng so long as maximum junction temperature is not exceeded. Calculation of maximum output

current using package thermal resistance is required.

1. Active clamp energy using single-pulse method (L = 16 mH, RL = 0, VPWR = 12 V, TJ = 150°C).
2. ESD1 testing is performed in accordance with the Human Body Model (HBM) (C ZAP = 100 pF, RZAP = 1500 Ω); ESD3 testing is

performed in accordance with the Charge Device Model (CDM), Robotic (Czap=4.0pF).

Analog Integrated Circuit Device Data

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• 40 to 125 - 40 to 150 Storage Temperature TSTG - 55 to 150 °C Thermal Resistance (5) Junction-to-Case Junction-to-Ambient RθJC RθJA <1.0 °C/W Peak Package Reflow Temperature During Reflow (6), (7) TPPRT Note 7 °C Notes 5. Device mounted on a 2s2p test board according to JEDEC JESD51-2. 6. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. 7. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), MC33xxxD enter 33xxx), and review parametrics.

All voltages are with respect to ground unless otherwise noted.

Analog Integrated Circuit Device Data Freescale Semiconductor 7 33984 STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TA ≤ 125°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.

3.0 MHz SPI Communication

1. This applies to all intern al device logic supplied by VPWR and assumes the external VDD supply is within specification.
2. This applies when the undervoltage fault is not latched (IN[0 : 1] = 0).

Analog Integrated Circuit Device Data

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STATIC ELECTRICAL CHARACTERISTICS POWER OUTPUT Output Drain-to-Source ON Resistance (IHS[0:1] = 15 A, TJ = 25°C) VPWR = 6.0 V VPWR = 10 V VPWR = 13 V RDS(ON) 6.0 4.0 4.0 mΩ Output Drain-to-Source ON Resistance (IHS[0:1] = 15 A, TJ = 150°C) VPWR = 6.0 V VPWR = 10 V VPWR = 13 V RDS(ON) 10.2 6.8 6.8 mΩ Output Source-to-Drain ON Resistance IHS[0:1] = 15 A, TJ = 25°C (10) VPWR = -12 V RDS(ON) – – 8.0 mΩ Output Overcurrent High Detection Levels (9.0 V < VPWR < 16 V) SOCH = 0 SOCH = 1 IOCH0 IOCH1 100 120 A Overcurrent Low Detection Levels (SOCL[2:0]) 000 001 010 011 100 101 110 111 IOCL0 IOCL1 IOCL2 IOCL3 IOCL4 IOCL5 IOCL6 IOCL7 8.0 6.0 22.5 17.5 12.5 7.5 9.0 A Current Sense Ratio (9.0 V < VPWR < 16 V, CSNS < 4.5 V) DICR D2 = 0 DICR D2 = 1 CSR0 CSR1 Current Sense Ratio (CSR0) Accuracy Output Current 5.0 A 10 A 12.5 A 15 A 20 A 25 A CSR0_ACC - 20 -14 -13 -12 -13 -13 Notes 10. Source-Drain ON Resistance (Reverse Drain-to -Source ON Resistance) with negative polarity VPWR. Table 3. Static Electrical Characteristics (continued) Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TA ≤ 125°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.

Analog Integrated Circuit Device Data Freescale Semiconductor 9 33984 STATIC ELECTRICAL CHARACTERISTICS POWER OUTPUT (CONTINUED) Current Sense Ratio (CSR1) Accuracy Output Current 5.0 A 10 A 12.5 A 15 A 20 A 25 A CSR1_ACC - 25 -19 -18 -17 -18 -18 Current Sense Clamp Voltage CSNS Open; IHS[0:1] = 29 A VCL(CSNS) 4.5 6.0 7.0 V Open Load Detection Current (11) IOLDC 30 – 100 µA Output Fault Detection Threshold Output Programmed OFF VOLD(THRES) 2.0 3.0 4.0 V Output Negative Clamp Voltage 0.5 A < IHS[0:1] < 2.0 A, Output OFF VCL - 20 – -15 V Overtemperature Shutdown (12) TSD 160 175 190 °C Overtemperature Shutdown Hysteresis (12) TSD(HYS) 5.0 – 20 °C Notes 11. Output OFF Open Load Detection Current is the current requir ed to flow through the load for the purpose of detecting the existence of an open load condition when the specific output is commanded OFF. 12. Guaranteed by process monitoring. Not production tested. Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TA ≤ 125°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.

Analog Integrated Circuit Device Data

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STATIC ELECTRICAL CHARACTERISTICS Control Interface Input Logic High Voltage (13) VIH 0.7 VDD – – V Input Logic Low Voltage (13) VIL – – 0.2 VDD V Input Logic Voltage Hysteresis (14) VIN[0:1] (HYS) 100 600 1200 mV Input Logic Pull-down Current (SCLK, IN, SI) IDWN 5.0 – 20 µA RST Input Voltage Range VRST 4.5 5.0 5.5 V SO, FS Tri-State Capacitance (15) CSO – – 20 pF Input Logic Pull-Down Resistor (RST) and WAKE RDWN 100 200 400 kΩ Input Capacitance (15) CIN – 4.0 12 pF WAKE Input Clamp Voltage (16) ICL(WAKE) < 2.5 mA VCL(WAKE) 7.0 – 14 V WAKE Input Forward Voltage ICL(WAKE) = - 2.5 mA VF(WAKE) - 2.0 – - 0.3 V SO High-State Output Voltage IOH = 1.0 mA VSOH

0.8 VDD – –

V FS, SO Low-State Output Voltage IOL = -1.6 mA VSOL – 0.2 0.4 V SO Tri-State Leakage Current CS > 0.7 VDD ISO(LEAK) - 5.0 0 5.0 µA Input Logic Pull-Up Current (17) CS, VIN[0:1] > 0.7 VDD IUP 5.0 – 20 µA FSI Input Pin External Pull-down Resistance FSI Disabled, HS[0:1] Indeterminate FSI Enabled, HS[0:1] OFF FSI Enabled, HS0 ON, HS1 OFF FSI Enabled, HS[0:1] ON RFS RFSdis RFSoffoff RFSonoff RFSonon 6.0 6.5 Infinite 1.0 7.0 kΩ Notes 13. Upper and lower logic thres hold voltage range applies to SI, CS, SCLK, RST, IN[0:1], and WAKE input signals. The WAKE and RST signals may be supplied by a derived voltage reference to VPWR. 14. No hysteresis on FSI and wake pins. Parameter is guar anteed by processing monitoring but is not production tested. 15. Input capacitance of SI, CS, SCLK, RST, and WAKE. This parameter is guaranteed by process monitoring but is not production tested. 16. The current must be limited by a series resistance when using voltages > 7.0 V. 17. Pull-up current is with CS OPEN. CS has an active internal pull-up to VDD. Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TA ≤ 125°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.

Analog Integrated Circuit Device Data Freescale Semiconductor 11 33984 DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 4. Dynamic Electrical Characteristics Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TA ≤ 125°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.

9.0 V < VPWR < 16 V

guaranteed by process monitoring. are guaranteed by process monitoring.

1. Turn-ON delay time measured from rising edge of IN [0:1] signal that would turn the output ON to VHS[0:1] = 0.5 V with RL = 5.0 Ω resistive
2. Turn-OFF delay time measured from falling edge that would turn the output OFF to VHS[0:1] = VPWR - 0.5 V with RL = 5.0 Ω resistive load.

Analog Integrated Circuit Device Data

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DYNAMIC ELECTRICAL CHARACTERISTICS POWER OUTPUT TIMING (CONTINUED) Overcurrent Detection Blanking Time (OCLT [1:0]) t OCL0 t OCL1 t OCL2 t OCL3 108 7.0 0.8 0.08 155 1.2 0.15 202 1.6 0.25 ms Overcurrent High Detection Blanking Time t OCH 1.0 10 20 µs CS to CSNS Valid Time (22) t CNSVAL – – 10 µs HS0 Switching Delay Time (OSD[2:0]) 000 001 010 011 100 101 110 111 t OSD0 t OSD1 t OSD2 t OSD3 t OSD4 t OSD5 t OSD6 t OSD7 110 165 220 275 330 385 150 225 300 375 450 525 190 285 380 475 570 665 ms HS1 Switching Delay Time (OSD[2:0]) 000 001 010 011 100 101 110 111 t OSD0 t OSD1 t OSD2 t OSD3 t OSD4 t OSD5 t OSD6 t OSD7 110 110 220 220 330 330 150 150 300 300 450 450 190 190 380 380 570 570 ms Watchdog Timeout (WD [1:0]) (23) t WDTO0 t WDTO1 t WDTO2 t WDTO3 434 207 1750 875 620 310 2500 1250 806 403 3250 1625 ms Notes 22. Time necessary for the CSNS to be within ±5% of the targeted value. 23. Watchdog timeout delay measured from the rising edge of WAKE to RST from a sleep state condition to output turn-ON with the output driven OFF and FSI floating. The values shown are for WDR setting of [00]. The accuracy of tWDTO is consistent for all configured watchdog time-outs. Table 4. Dynamic Electrical Characteristics (continued) Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TA ≤ 125°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.

Analog Integrated Circuit Device Data Freescale Semiconductor 13 33984 DYNAMIC ELECTRICAL CHARACTERISTICS SPI INTERFACE CHARACTERISTICS Recommended Frequency of SPI Operation f SPI – – 3.0 MHz Required Low State Duration for RST (24) t WRST – 50 350 ns Rising Edge of CS to Falling Edge of CS (Required Setup Time) (25) t CS – – 300 ns Rising Edge of RST to Falling Edge of CS (Required Setup Time) (25) t ENBL – – 5.0 µs Falling Edge of CS to Rising Edge of SCLK (Required Setup Time) (25) t LEAD – 50 167 ns Required High State Duration of SCLK (Required Setup Time) (25) t WSCLKh – – 167 ns Required Low State Duration of SCLK (Required Setup Time) (25) t WSCLKl – – 167 ns Falling Edge of SCLK to Rising Edge of CS (Required Setup Time) (25) t LAG – 50 167 ns SI to Falling Edge of SCLK (Required Setup Time) (26) t SI(SU) – 25 83 ns Falling Edge of SCLK to SI (Required Setup Time) (26) t SI(HOLD) – 25 83 ns SO Rise Time CL = 200 pF t RSO – 25 50 ns SO Fall Time CL = 200 pF t FSO – 25 50 ns SI, CS, SCLK, Incoming Signal Rise Time (26) t RSI – – 50 ns SI, CS, SCLK, Incoming Signal Fall Time (26) t RSI – – 50 ns Time from Falling Edge of CS to SO Low Impedance (27) t SO(EN) – – 145 ns Time from Rising Edge of CS to SO High Impedance (28) t SO(DIS) – 65 145 ns Time from Rising Edge of SCLK to SO Data Valid (29) 0.2 VDD ≤ SO ≤ 0.8 VDD, CL = 200 pF t VALID – 65 105 ns Notes 24. RST low duration measured with outputs enabled and going to OFF or disabled condition. 25. Maximum setup time required for the 33984 is the mi nimum guaranteed time needed from the microcontroller. 26. Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing. 27. Time required for output status data to be available for use at SO. 1.0 k Ω on pull-up on CS. 28. Time required for output status data to be terminated at SO. 1.0 k Ω on pull-up on CS. 29. Time required to obtain valid data out from SO following the rise of SCLK. Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TA ≤ 125°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.

Analog Integrated Circuit Device Data

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Figure 4. Output Slew Rate and Time Delays Figure 5. Overcurrent Shutdown Figure 6. Overcurrent Low and High Detection

Analog Integrated Circuit Device Data Freescale Semiconductor 15 33984 Figure 6 illustrates the overcurrent detection level (Ioclx, Iochx) the device can reach for each overcurrent detection blanking time (tochx, toclx):

• During tochx, the device can reach up to Ioch0 overcurrent level.
• During tocl3 or tocl2 or tocl1 or tocl0, the device can be programmed to detect up to Iocl0.

Figure 7. Input Timing Switching Characteristics Figure 8. SCLK Waveform and Valid SO Data Delay Time

0.7 VDD

0.2 VDD

Analog Integrated Circuit Device Data

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FUNCTIONAL PIN DESCRIPTION FUNCTIONAL DESCRIPTION INTRODUCTION The 33984 is a dual self-protected 4.0 mΩ silicon switch used to replace electromechanical relays, fuses, and discrete devices in power management applications. The 33984 is designed for harsh environments, and it includes self- recovery features. The device is suitable for loads with high inrush current, as well as motors and all types of resistive and inductive loads. Programming, control, and diagnostics are implemented via the Serial Peripheral Interface (SPI). A dedicated parallel input is available for alternate and Pulse Width Modulation (PWM) control of each output. SPI-programmable fault trip thresholds allow the device to be adjusted for optimal performance in the application. The 33984 is packaged in a power-enhanced 12 x 12 nonleaded PQFN package with exposed tabs. FUNCTIONAL PIN DESCRIPTION OUTPUT CURRENT MONITORING (CSNS) This pin is used to output a current proportional to the designated HS0-1 output. That current is fed into a ground- referenced resistor and its voltage is monitored by an MCU's A/D. The channel to be monitored is selected via the SPI. This pin can be tri-stated through SPI. WAKE (WAKE) This pin is used to input a Logic [1] signal so as to enable the watchdog timer function. An internal clamp protects this pin from high damaging voltages when the output is current limited with an external resistor. This input has a passive internal pull-down. RESET (RST) This input pin is used to initialize the device configuration and fault registers, as well as place the device in a low current sleep mode. The pin also starts the watchdog timer when transitioning from Logic LOW to Logic HIGH. This pin should not be allowed to be Logic HIGH until VDD is in regulation. This pin has a passive internal pull-down. DIRECT IN 0 & 1 (INx) This input pin is used to directly control the output HS0 and 1. This input has an active internal pull-down current source and requires CMOS logic levels. This input may be configured via SPI. FAULT STATUS (FS) This is an open drain configured output requiring an external pull-up resistor to VDD for fault reporting. When a device fault condition is detected, this pin is active LOW. Specific device diagnostic faults are reported via the SPI SO pin. FAIL-SAFE INPUT (FSI) The value of the resistance connected between this pin and ground determines the state of the outputs after a watchdog timeout occurs. Depending on the resistance value, either all outputs are OFF, ON, or the output HS0 only is ON. When the FSI pin is connected to GND, the watchdog circuit and fail-safe operation are disabled. This pin incorporates an active internal pull-up current source. CHIP SELECT (CS) This input pin is connected to a chip select output of a master microcontroller (MCU). The MCU determines which device is addressed (selected) to receive data by pulling the CS pin of the selected device Logic LOW, enabling SPI communication with the device. Other unselected devices on the serial link having their CS pins pulled-up Logic HIGH disregard the SPI communication data sent. This pin incorporates an active internal pull-up current source. SERIAL CLOCK (SCLK) This input pin is connected to the MCU providing the required bit shift clock for SPI communication. It transitions one time per bit transferred at an operating frequency, f SPI, defined by the communication interface. The 50 percent duty cycle CMOS-level serial clock signal is idle between command transfers. The signal is used to shift data into and out of the device. This input has an active internal pull-down current source. SERIAL INPUT (SI) This is a command data input pin connected to the SPI Serial Data Output of the MCU or to the SO pin of the previous device of a daisy chain of devices. The input requires CMOS logic-level signals and incorporates an active internal pull-down current source. Device control is facilitated by the input's receiving the MSB first of a serial 8-bit control command. The MCU ensures data is available upon the falling edge of SCLK. The logic state of SI present upon the rising edge of SCLK loads that bit command into the internal command shift register. DIGITAL DRAIN VOLTAGE (VDD) This is an external voltage input pin used to supply power to the SPI circuit. In the event VDD is lost, an internal supply provides power to a portion of the logic, ensuring limited

Analog Integrated Circuit Device Data Freescale Semiconductor 17 33984 FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION functionality of the device. All device configuration registers are reset. SERIAL OUTPUT (SO) This output pin is connected to the SPI Serial Data Input pin of the MCU or to the SI pin of the next device of a daisy chain of devices. This output will remain tri-stated (high impedance OFF condition) so long as the CS pin of the device is Logic HIGH. SO is only active when the CS pin of the device is asserted Logic LOW. The generated SO output signals are CMOS logic levels. SO output data is available on the falling edge of SCLK and transitions immediately on the rising edge of SCLK. POSITIVE POWER SUPPLY (VPWR) This pin connects to the positive power supply and is the source input of operational power for the device. The VPWR pin is a backside surface mount tab of the package. HIGH-SIDE OUTPUT 0 & 1 (HSx) This pin protects 4.0 mΩ high-side power output to the load.

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and RST inputs as defined in Table 5.

• V PWR is within the normal voltage range.
• RST pin is Logic [1].
• No fault has occurred. FAIL-SAFE AND WATCHDOG If the FSI input is not grounded, the watchdog timeout detection is active when either the WAKE or RST input pin transitions from Logic [0] to Logic [1]. The WAKE input is capable of being pulled up to VPWR with a series of limiting resistance that limits the internal clamp current according to the specification. The watchdog timeout is a multiple of an internal oscillator and is specified in Table 14. As long as the WD bit (D7) of an incoming SPI message is toggled within the minimum watchdog timeout period (WDTO), based on the programmed value of the WDR the device will operate normally. If an internal watchdog timeout occurs before the WD bit, the device will revert to a Fail-Safe mode until the device is reinitialized. During the Fail-Safe mode, the outputs will be ON or OFF depending upon the resistor RFS connected to the FSI pin, regardless of the state of the various direct inputs and modes (Table 6). In this mode, the SPI register content is retained except for overcurrent high and low detection levels and timing, which are reset to their default value (SOCL, SOCH, and OCLT). Then the watchdog, overvoltage, overtemperature, and overcurrent circuitry (with default value) are fully operational. The Fail-Safe mode can be detected by monitoring the WDTO bit D2 of the WD register. This bit is Logic [1] when the device is in fail-safe mode. The device can be brought out of the Fail-Safe mode by transitioning the WAKE and RST pins from Logic [1] to Logic [0] or forcing the FSI pin to Logic [0]. Table 5 summarizes the various methods for resetting the device from the latched Fail-Safe mode. If the FSI pin is tied to GND, the Watchdog fail-safe operation is disabled. LOSS OF VDD If the external 5.0 V supply is not within specification, or even disconnected, all register content is reset. The two outputs can still be driven by the direct inputs IN 1:IN0. The 33984 uses the battery input to power the output MOSFET- related current sense circuitry and any other internal logic providing fail-safe device operation with no VDD supplied. In this state, the watchdog, overvoltage, overtemperature, and overcurrent circuitry are fully operational with default values.

Table 5. Fail-Safe Operation and Transitions to Other

33984 Modes

Sleep x 0 0 x Device is in Sleep mode. Table 6. Output State During Fail-Safe Mode

0 Fail-Safe Mode Disabled

6.0 Both HS0 and HS1 OFF

15 HS0 ON, HS1 OFF

30 Both HS0 and HS1 ON

• Overtemperature fault
• Open load fault
• Overcurrent fault (high and low)
• Overvoltage and undervoltage fault The FS pin will automatically return to Logic [1] when the fault condition is removed, except for Overcurrent and in some cases Undervoltage. Fault information is retained in the fault register and is available (and reset) via the SO pin during the first valid SPI communication (refer to Table 16). PROTECTION AND DIAGNOSIS FEATURES OVERTEMPERATURE FAULT (NON-LATCHING) The 33984 incorporates overtemperature detection and shutdown circuitry in each output structure. Overtemperature detection is enabled when an output is in the ON state. For the output, an overtemperature fault (OTF) condition results in the faulted output turning OFF until the temperature falls below the TSD(HYS). This cycle will continue indefinitely until action is taken by the MCU to shut OFF the output, or until the offending load is removed. When experiencing this fault, the OTF fault bit will be set in the status register and cleared after either a valid SPI read or a power reset of the device. OVERVOLTAGE FAULT (NON-LATCHING) The 33984 shuts down the output during an overvoltage fault (OVF) condition on the VPWR pin. The output remains in the OFF state until the overvoltage condition is removed. When experiencing this fault, the OVF fault bit is set in the bit OD1 and cleared after either a valid SPI read or a power reset of the device. The overvoltage protection and diagnostic can be disabled trough SPI (bit OV_dis). UNDERVOLTAGE SHUTDOWN (LATCHING OR NON-LATCHING) The output(s) will latch off at some battery voltage below 6.0 V. As long as the VDD level stays within the normal specified range, the internal logic states within the device will be sustained. In the case where battery voltage drops below the undervoltage threshold (VPWRUV) output will turn off, FS will go to Logic [0], and the fault register UVF bit will be set to 1. Two cases need to be considered when the battery level recovers :
• If output(s) command is (are) low, FS will go to Logic [1] but the UVF bit will remain set to 1 until the next read operation.
• If the output command is ON, then FS will remain at Logic [0]. The output must be turned OFF and ON again to re-enable the state of output and release FS . The UVF bit will remain set to 1 until the next read operation. The undervoltage protection can be disabled through SPI (bit UV_dis = 1). In this case, the FS and UVF bit do not report any undervoltage fault condition and the output state will not be changed as long as battery voltage does not drop any lower than 2.5 V. OPEN LOAD FAULT (NON-LATCHING) The 33984 incorporates open load detection circuitry on each output. Output open load fault (OLF) is detected and reported as a fault condition when that output is disabled (OFF). The open load fault is detected and latched into the status register after the internal gate voltage is pulled low enough to turn OFF the output. The OLF fault bit is set in the status register. If the open load fault is removed, the status register will be cleared after reading the register. The open load protection can be disabled trough SPI (bit OL_dis). It is recommended to disable the open load detection circuitry (OL_dis bit sets to logic [1]) in case of permanent open load fault condition. OVERCURRENT FAULT (LATCHING) The device has eight programmable overcurrent low detection levels (IOCL) and two programmable overcurrent high detection levels (IOCH) for maximum device protection. The two selectable, simultaneously active overcurrent detection levels, defined by IOCH and IOCL, are illustrated in

Figure 6. The eight different overcurrent low detect levels (IOCL0 : IOCL7) are likewise illustrated in Figure 6. device will latch the effected output OFF. the output, regardless of the selected tOCL driver. until the device is commanded OFF and then ON again. enhanced to keep the junction temperature less than 150°C.

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Table 7. Device Behavior in Case of Undervoltage

2.5 V > VPWR > 0V Output State OFF OFF OFF OFF OFF

∗∗ = While VDD remains within specified range.

impedance). See Figure 9 and Figure 10. Table 8. Register addressing and configuration are described Figure 9. Single 8-Bit Word SPI Communication

1. RSTB is in a logic 1 state during the above operation.
2. D0, D1, D2, ..., and D7 relate to the most recent ordered entry of data into the SPSS
3. OD0, OD1, OD2, ..., and OD7 relate to the first 8 bits of ordered fault and status data out
4. RST is a Logic [1] state during the above operation.
5. D7:D0 relate to the most recent ordered entry of data into the device.
6. OD7:OD0 relate to the first 8 bits of ordered fault and status data out of the device.

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Figure 10. Multiple 8-Bit Word SPI Communication with the MSB, D7, and ending with the LSB, D0 (Table 8). control the outputs and their protection features. latch in a message that is not eight bits will be ignored. configure the device and to control the state of the output. addressed via D6 : D4 of the incoming SPI word (Table 8).

1. RSTB i s i n a l ogi c 1 st at e dur i ng t he above oper at i on.
2. O D0, O D1, O D2, . . . , and O D7 r epr esent t he f i r st 8 bi t s of or der ed f aul t and st at us dat a out of t he SPSS
3. RST is a Logic [1] state during the above operation.
4. D7:D0 relate to the most recent ordered entry of data into the device.
5. OD7:OD0 relate to the first 8 bits of ordered fault and status data out of the device.
6. D7*:D0* relate to the previous 8 bits (last command word) of data that was previously shifted into the device.

Table 8. SI Message Bit Assignment MSB D7 Register address bit for output selection. D6 : D4 Register address bits. Table 9. Serial Input Address and Configuration Bit Map Table 8. SI Message Bit Assignment(continued)

addresses and their impact on device operation. D2:D0, determine the content of the first eight bits of SO data. feed the watchdog if enabled. level to one of eight possible levels, as shown in Table 10. levels, which is described inTable 11. open load (OL) detection feature. Table 10. Overcurrent Low Detection Levels Table 11. Overcurrent High Detection Levels Table 12. Overcurrent Low Detection Blanking Time

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Logic [0] will configure the direct input control for the HS0. corresponds to the low speed slew rate. transitions initiated via SPI (not via direct input). to 525 ms. Refer to Table 13. reported in the output fault register. accessible with SPI during normal operation. Table 13. Switching Delay Table 14. Watchdog Timeout

able to accept new fault status information.

• The previous SPI communication was determined to be invalid. In this case, the status will be reported as though the invalid SPI communication never occurred.
• Battery transients below 6.0 V resulting in an under- voltage shutdown of the outputs may result in incorrect data loaded into the status register. The SO data transmitted to the MCU during the first SPI communication following an undervoltage V PWR condition should be ignored.
• T h e RST pin transition from a Logic [0] to Logic [1] while the WAKE pin is at Logic [0] may result in incorrect data loaded into the status register. The SO data transmitted to the MCU during the first SPI communication following this condition should be ignored. SERIAL OUTPUT BIT ASSIGNMENT The 8 bits of serial output data depend on the previous serial input message, as explained in the following paragraphs. Table 15 summarizes the SO register content. Bit OD7 reflects the state of the watchdog bit (D7) addressed during the prior communication. The value of the previous D7 will determine which output the status information applies to for the Fault (FLTR), SOCHLR, CDTOLR, and DICR registers. SO data will represent information ranging from fault status to register contents, user selected by writing to the STATR bits D2:D0. Note that the SO data will continue to reflect the information for each output (depending on the previous D7 state) that was selected during the most recent STATR write until changed with an updated STATR write. Previous Address SOA[2:0] = 000 If the previous three MSBs are 000, bits OD6 : OD0 will reflect the current state of the Fault register (FLTR) corresponding to the output previously selected with the bit OD7 (Table 16). Previous Address SOA[2:0] = 001 Data in bits OD1:OD0 contain CSNS0 EN and IN0_SPI programmed bits, respectively. Data in bits OD3:OD2 contain CSNS0 EN and IN0_SPI programmed bits, respectively. Previous Address SOA[2:0] = 010 The data in bit OD3 contain the programmed overcurrent high detection level (refer to Table 11), and the data in bits OD2:OD0 contain the programmed overcurrent low detection levels (refer to Table 12).

Table 15. Serial Output Bit Map Description s = Selection of output: Logic [0] = HS0, Logic [1] = HS1.

26 Freescale Semiconductor

active. OD3 reports if the open load circuitry is active.

• SOA3 = 0. The returned data contain the programmed values in the OSDR. Bit OD3 (FSM_HS0) reflects the state of the output HS0 in the Fail-Safe mode after a watchdog timeout occurs.
• SOA3 = 1. The returned data contain the programmed values in the WDR. Bit OD2 (WDTO) reflects the status of the watchdog circuitry. If WDTO bit is Logic [1], the watchdog has timed out and the device is in Fail-Safe mode. If WDTO is Logic [0], the device is in Normal mode (assuming the device is powered and not in Sleep mode), with the watchdog either enabled or disabled. Bit OD3 (FSM_HS1) reflects the state of the output HS1 in the Fail-Safe mode after a watchdog timeout occurs. Previous Address SOA[2:0] = 110
• SOA3 = 0. OD3:OD0 return t he state of the IN1, IN0, FSI, and WAKE pins, respectively (Table 17).
• SOA3 = 1. The returned data contain the programmed values in the UOVR. Bit OD1 reflects the state of the undervoltage protection and bit OD0 reflects the state of the overvoltage protection. Refer to Table 15). Previous Address SOA[2:0] =111 Null Data. No previous register Read Back command received, so bits OD2:OD0 are null, or 000.

Table 16. Fault Register OD7 (s) = Selection of output: Logic [0] = HS0, Logic [1] = HS1. OD6 (OTF) = Overtemperature Flag. OD3 (OLFs) = Open Load Flag. OD1 (OVF) = Overvoltage Flag. a new Switch ON command (via SPI or direct input IN). Table 17. Pin Register

28 Freescale Semiconductor

Figure 12. CSR0 ratio deviation in function all tolerance without battery variation effect. Figure 13. CSR0 ratio deviation in function contributors are considered. Figure 14. CSR0 ratio deviation in function test in order to take into account the ageing of devices. Table 18 summaries test results covering 99.74% of parts.

Analog Integrated Circuit Device Data Freescale Semiconductor 29 33984 PACKAGING SOLDERING INFORMATION PACKAGING SOLDERING INFORMATION SOLDERING INFORMATION The 33984 is packaged in a surface mount power package intended to be soldered directly on the printed circuit board. The 33984 was qualified in accordance with JEDEC standards JESD22-A113-B and J-STD-020A. The recommended reflow conditions are as follows:

• Convection: 225°C +5 .0/ -0°C
• Vapor Phase Reflow (VPR): 215°C to 219°C
• Infrared (IR) / Convection: 225°C +5.0 / -0°C The maximum peak temperature during the soldering process should not exceed 230°C. The time at maximum temperature should range from 10 s to 40 s maximum.

Analog Integrated Circuit Device Data

30 Freescale Semiconductor

For the most current revision of the package, visit www.freescale.com and perform a keyword search on 98ARL10521D. PNA SUFFIX 16-PIN PQFN NONLEADED PACKAGE 98ARL10521D ISSUE C

Analog Integrated Circuit Device Data Freescale Semiconductor 31 33984 PACKAGING PACKAGE DIMENSIONS

32 Freescale Semiconductor

application, and packaging information is provided in the datasheet. TJ1 and TJ2, and a thermal resistance matrix with RθJAmn. temperature while only heat source 1 is heating with P1. The stated values are solely for a thermal performance comparison of one package to another in a standardized environment. values were obtained by measurement and simulation according to the standards listed below. Figure 1. Surface Mount for Power PQFN Table 1. Thermal Performance Comparison

1. Per JEDEC JESD51-2 at natural convection, still air
2. 2s2p thermal test board per JEDEC JESD51-7 and
3. Per JEDEC JESD51-8, with the board temperature on the

center trace near the power outputs.

1. Single layer thermal test board per JEDEC JESD51-3 and
2. Thermal resistance between the die junction and the

exposed pad; “infinite” heat sink attached to exposed pad.

Figure 2. Thermal Test Board where the junction temperature is sensed.

33984 Pin Connections

Table 2. Thermal Resistance Performance

34 Freescale Semiconductor

Figure 3. Device on Thermal Test Board RθJA Figure 4. Transient Thermal Resistance RθJA (1 W Step Response)

Analog Integrated Circuit Device Data Freescale Semiconductor 35 33984

REVISION HISTORY

REVISION DATE DESCRIPTION OF CHANGES 6.0 2/2006 • Implemented Revision History page

• Deletion of MC33984 part number, replaced with MC33984B. 7.0 5/2006 • Corrected Pin Connections to the proper case outline
• Added final sentence to Open Load Fault (Non-Latching)
• Corrected heading labels on Input Timing Switching Characteristics
• Changed labels in the Typical Applications drawing
• Corrected Package Dimensions to Revision C
• Added Thermal Addendum (rev 2.0). 8.0 1/2007 • Added RoHS logo 9.0 1/2007 • Changed several names on the Typical Applications on page 27
• Added section Output current monitoring on page 27

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