33984

MC33984 NXP | Alldatasheet

Document overview

• Manufacturer or author: NXP B.V.
• PDF pages: 57

Technical content

Features

• Dual 4.0 m  max. high-side switch with parallel input or SPI control
• 6.0 V to 27 V operating voltage with standby currents < 5.0 A
• Output current monitoring with two SPI-selectable current ratios
• SPI control of overcurrent limit, over current fault blanking time, output OFF open load detection, output ON/OFF control, watchdog timeout, slew-rates, and fault status reporting
• SPI status reportin g of overcurrent, open and shorted loads, overtemperature, undervoltage and overvoltage shutdown, fail-safe pin status, and program status
• Enhanced -16 V reverse polarity V PWR protection

Figure 1. 33984 simplified application diagram

Applications

• DC motor or solenoid
• Resistive or inductive loads
• Low-voltage lighting BOTTOM VIEW FK SUFFIX 98ARL10521D 98ASA00815D 16-PIN PQFN VDD I/O I/O SO SCLK CS SI I/O I/O I/O A/D VPWR FS WAKE SI SCLK CS SO RST INO IN1 CSNS FSI GND HS1 HS0 GND LOAD LOAD 33984 MCU VDDVDDVDD VPWR

2 NXP Semiconductors

Table 1. Orderable part variations (1)

1. To order parts in Tape & Reel, add the R2 suffix to the part number.

Figure 2. 33984 simplified internal block diagram

7.5 A to 25 A

100 A or 75 A

3.0 MHz

4 NXP Semiconductors

Figure 3. 33984 pin connections (transparent top view) Functional descriptions of many of these pins can be found in the Functional Pin Description section beginning on page 19. Table 2. Pin definitions 1 CSNS Output Output Current Monitoring This pin is used to output a current proportional to the designated HS0-1 output.

2 WAKE Input Wake This pin is used to input a logic [1] signal so as to enable the watchdog timer

well as place the device in a low current Sleep mode. 4 IN0 Input Direct Input 0 This input pin is used to directly control the output HS0. the state of the outputs after a watchdog timeout occurs.

9 SI Input Serial Input This is a command data input pin connected to the SPI serial data output of the

MCU or to the SO pin of the previous device of a daisy chain of devices.

10 VDD Input Digital Drain Voltage

(Power) This is an external voltage input pin used to supply power to the SPI circuit. SI pin of the next device of a daisy chain of devices. 12 IN1 Input Direct Input 1 This input pin is used to directly control the output HS1. 13 GND Ground Ground This pin is the ground for the logic and analog circuitry of the device.

operational power for the device. 15 HS1 Output High-side Output 1 Protected 4.0 m high-side power output to the load. 16 HS0 Output High-side Output 0 Protected 4.0 m high-side power output to the load. Table 2. Pin definitions (continued)

6 NXP Semiconductors

ELECTRICAL CHARACTERISTICS

Table 3. Maximum ratings All voltages are with respect to ground unless otherwise noted.

1. Exceeding this voltage limit may cause permanent damage to the device.
2. Continuous high-side output current rating so long as maximum junction temperature is not exceeded. Calculation of maximum output current using

package thermal resistance is required.

1. Active clamp energy using single-pulse method (L = 16 mH, R L = 0, VPWR = 12 V, TJ = 150 °C).
2. ESD1 testing is performed in accordance with the Human Body Model (HBM) (C ZAP = 100 pF, RZAP = 1500 ESD3 testing is performed in

accordance with the Charge Device Model (CDM), Robotic (CZAP = 4.0 pF).

-40 to 125 -40 to 150 TSTG Storage Temperature -55 to 150 C RJC RJA Thermal Resistance Junction-to-Case Junction-to-Ambient <1.0 C/W (5) TPPRT Peak Package Reflow Temperature During Reflow Note 7 °C (6), (7) Notes 5. Device mounted on a 2s2p test board according to JEDEC JESD51-2. 6. Pin soldering temperature limit is for 40 seconds maximum dur ation. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. 7. NXP’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), Go to www.nxp.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics. Table 3. Maximum ratings (continued) All voltages are with respect to ground unless otherwise noted.

8 NXP Semiconductors

Static electrical characteristics Table 4. Static electrical characteristics values noted reflect the approximate parameter mean at TA = 25 C under nominal conditions, unless otherwise noted.

3.0 MHz SPI Communication

1. This applies to all inter nal device logic supplied by VPWR and assumes the external VDD supply is within specification.
2. This applies when the undervoltage fault is not latched (IN[0:1] = 0).
3. Source-Drain ON Resistance (Reverse Drain-to -Source ON Resistance) with negative polarity VPWR.

POWER OUTPUT (CONTINUED) IOCH0 IOCH1 Output Overcurrent High Detection Levels (9.0 V < VPWR < 16 V) SOCH = 0 SOCH = 1 100 120 A I OCL0 IOCL1 IOCL2 IOCL3 IOCL4 IOCL5 IOCL6 IOCL7 IOCL0 IOCL1 IOCL2 IOCL3 IOCL4 IOCL5 IOCL6 IOCL7 Overcurrent Low Detection Levels (SOCL[2:0]) MC33984CHFK 000 001 010 011 100 101 110 111 MC33984EHFK 000 001 010 011 100 101 110 111 8.0 6.0 8.5 6.5 22.5 17.5 12.5 7.5 20.5 15.5 10.5 9.0 12.5 9.5 A C SR0 CSR1 Current Sense Ratio (9.0 V < VPWR < 16 V, CSNS < 4.5 V) DICR D2 = 0 MC33984CHFK MC33984EHFK DICR D2 = 1 MC33984CHFK MC33984EHFK C SR0_ACC Current Sense Ratio (CSR0) Accuracy Output Current 5.0 A 10 A 12.5 A 15 A 20 A 25 A -20 -14 -13 -12 -13 -13 C SR1_ACC Current Sense Ratio (CSR1) Accuracy Output Current 5.0 A 10 A 12.5 A 15 A 20 A 25 A -25 -19 -18 -17 -18 -18 V CL(CSNS) Current Sense Clamp Voltage CSNS Open; IHS[0:1] = 29 A 4.5 6.0 7.0 V IOLDC Open Load Detection Current 30 – 100 A (11) Table 4. Static electrical characteristics (continued) values noted reflect the approximate parameter mean at TA = 25 C under nominal conditions, unless otherwise noted.

10 NXP Semiconductors

VOLD(THRES) Output Fault Detection Threshold Output Programmed OFF 2.0 3.0 4.0 V VCL Output Negative Clamp Voltage 0.5 A < IHS[0:1] < 2.0 A, Output OFF -20 – -15 V TSD Overtemperature Shutdown 160 175 190 C (12) TSD(HYS) Overtemperature Shutdown Hysteresis 5.0 – 20 C (12) Notes 11. Output OFF Open Load Detection Current is the current requir ed to flow through the load for the purpose of detecting the existence of an open load condition when the specific output is commanded OFF. 12. Guaranteed by process monitoring. Not production tested. values noted reflect the approximate parameter mean at TA = 25 C under nominal conditions, unless otherwise noted.

VIH Input Logic High-voltage 0.7 x VDD – – V (13) VIL Input Logic Low-voltage – – 0.2 x VDD V (13) VIN0:1 Input Logic Voltage Hysteresis 100 600 1200 mV (14) IDWN Input Logic Pull-down Current (SCLK, IN, SI) 5.0 – 20 A VRST RST Input Voltage Range 4.5 5.0 5.5 V CSO SO, FS Tri-state Capacitance – – 20 pF (15) RDWN Input Logic Pull-down Resistor (RST) and WAKE 100 200 400 k CIN Input Capacitance – 4.0 12 pF (15) VCL(WAKE) WAKE Input Clamp Voltage ICL(WAKE) < 2.5 mA 7.0 – 14 V (16) VF(WAKE) WAKE Input Forward Voltage ICL(WAKE) = -2.5 mA -2.0 – -0.3 V VSOH SO High-state Output Voltage IOH = 1.0 mA 0.8 x VDD – – V VSOL FS, SO Low-state Output Voltage IOL = -1.6 mA – 0.2 0.4 V ISO(LEAK) SO Tri-state Leakage Current CS > 0.7 VDD -5.0 0.0 5.0 A IUP Input Logic Pull-up Current RFS RFSDIS RFSOFFOFF RFSONOFF RFSONON FSI Input Pin External Pull-down Resistance FSI Disabled, HS[0:1] Indeterminate FSI Enabled, HS[0:1] OFF FSI Enabled, HS0 ON, HS1 OFF FSI Enabled, HS[0:1] ON 6.0 6.5 Infinite 1.0 7.0 Notes 13. Upper and lower logic threshold voltage range applies to SI, CS, SCLK, RST, IN[0:1], and WAKE input signals. The WAKE and RST signals may be supplied by a derived voltage reference to VPWR. 14. No hysteresis on FSI and WAKE pins. Parameter is guarant eed by processing monitoring but is not production tested. 15. Input capacitance of SI, CS, SCLK, RST, and WAKE. This parameter is guaranteed by process monitoring but is not production tested. 16. The current must be limited by a seri es resistance when using voltages > 7.0 V. 17. Pull-up current is with CS OPEN. CS has an active internal pull-up to VDD. values noted reflect the approximate parameter mean at TA = 25 C under nominal conditions, unless otherwise noted.

12 NXP Semiconductors

Dynamic electrical characteristics Table 5. Dynamic electrical characteristics values noted reflect the approximate parameter mean at TA = 25 C under nominal conditions, unless otherwise noted.

9.0 V < VPWR < 16 V

tOCH Overcurrent High Detection Blanking Time 1.0 10 20 s tCNSVAL CS to CSNS Valid Time – – 10 s (22) Notes by process monitoring. guaranteed by process monitoring. 20. Turn-ON delay time measured from rising edge of IN [0:1] signal would turn the output ON to VHS[0:1] = 0.5 V with RL = 5.0  resistive load. 21. Turn-OFF delay time measured from fall ing edge would turn the output OFF to VHS[0:1] = VPWR -0.5 V with RL =5 . 0 resistive load. 22. Time necessary for the CSNS to be within ±5.0% of the targeted value. Table 5. Dynamic electrical characteristics (continued) values noted reflect the approximate parameter mean at TA = 25 C under nominal conditions, unless otherwise noted.

14 NXP Semiconductors

POWER OUTPUT TIMING (CONTINUED) tOSD0 tOSD1 tOSD2 tOSD3 tOSD4 tOSD5 tOSD6 tOSD7 HS1 Switching Delay Time (OSD[2:0]) 000 001 010 011 100 101 110 111 110 165 220 275 330 385 150 225 300 375 450 525 190 285 380 475 570 665 ms tOSD0 tOSD1 tOSD2 tOSD3 tOSD4 tOSD5 tOSD6 tOSD7 HS0 Switching Delay Time (OSD[2:0]) 000 001 010 011 100 101 110 111 110 110 220 220 330 330 150 150 300 300 450 450 190 190 380 380 570 570 ms tWDTO0 tWDTO1 tWDTO2 tWDTO3 tWDTO0 tWDTO1 tWDTO2 tWDTO3 Watchdog Timeout (WD[1:0]) MC33984CHFK MC33984EHFK 434 207 1750 875 434 207 1750 875 620 310 2500 1250 620 310 2500 1250 806 403 3250 1625 1344 672 5377 2688 ms (23) fSPI Recommended Frequency of SPI Operation – – 3.0 MHz tWRST Required Low State Duration for RST – 50 350 ns (24) tCS Rising Edge of CS to Falling Edge of CS (Required Setup Time) – – 300 ns (25) tENBL Rising Edge of RST to Falling Edge of CS (Required Setup Time) – – 5.0 s (25) tLEAD Falling Edge of CS to Rising Edge of SCLK (Required Setup Time) – 50 167 ns (25) tWSCLKh Required High State Duration of SCLK (Required Setup Time) – – 167 ns (25) tWSCLKl Required Low State Duration of SCLK (Required Setup Time) – – 167 ns (25) tLAG Falling Edge of SCLK to Rising Edge of CS (Required Setup Time) – 50 167 ns (25) tSI(SU) SI to Falling Edge of SCLK (Required Setup Time) – 25 83 ns (26) tSI(HOLD) Falling Edge of SCLK to SI (Required Setup Time) – 25 83 ns (27) tRSO SO Rise Time CL = 200 pF – 25 50 ns tFSO SO Fall Time CL = 200 pF – 25 50 ns values noted reflect the approximate parameter mean at TA = 25 C under nominal conditions, unless otherwise noted.

1. Watchdog timeout delay measured from the rising edge of WAKE to RST from a sleep-state condition to output turn-ON with the output driven OFF and FSI floating. The values shown are for WDR setting of [00]. The accuracy of tWDTO is consistent for all configured watchdog timeouts. 24. RST low duration measured with outputs enabled and going to OFF or disabled condition. 25. Maximum setup time required for the 33984 is the mi nimum guaranteed time needed from the microcontroller. 26. Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.

values noted reflect the approximate parameter mean at TA = 25 C under nominal conditions, unless otherwise noted.

16 NXP Semiconductors

Figure 4. Output slew rate and time delays Figure 5. Overcurrent shutdown

1. Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
2. Time required for output status dat a to be available for use at SO. 1.0 kon pull-up on CS.
3. Time required for output status data to be terminated at SO. 1.0 k on pull-up on CS.
4. Time required to obtain valid data out from SO following the rise of SCLK.

values noted reflect the approximate parameter mean at TA = 25 C under nominal conditions, unless otherwise noted.

Figure 6. Overcurrent low and high detection

• During tochx, the device can reach up to Ioch0 overcurrent level.
• During tocl3 or tocl2 or tocl1 or tocl0, the de vice can be programmed to detect up to Iocl0.

Figure 7. Input timing switching characteristics

0.7 VDD

0.2 VDD

18 NXP Semiconductors

Figure 8. SCLK waveform and valid SO data delay time

The 33984 is a dual self-protected 4.0 m silicon switch used to replace electromechanical relays, fuses, and discrete devices in power management applications. The 33984 is designed for harsh environments, and it includes self-recovery features. The device is suitable for loads with high inrush current, as well as motors and all types of resistive and inductive loads. Programming, control, and diagnostics are implemented via the serial peripheral interface (SPI). A dedicated parallel input is available for alternate and pulse width modulation (PWM) control of each output. SPI-programmable fault trip thresholds allow the device to be adjusted for optimal performance in the application. The 33984 is packaged in a power-enhanced 12 mm x 12 mm non-leaded PQFN package with exposed tabs. Functional pin description OUTPUT CURRENT MONITORING (CSNS) This pin is used to output a current proportional to the designated HS0-1 output. The current is fed into a ground-referenced resistor and its voltage is monitored by an MCU's A/D. The channel to be monitored is selected via the SPI. This pin can be tri-stated through the SPI. WAKE (WAKE) This pin is used to input a logic [1] signal so as to enable the watchdog timer function. An internal clamp protects this pin from high damaging voltages when the output is current limited with an external resistor. This input has a passive internal pull-down. RESET (RST) This input pin is used to initialize the device configuration and fault registers, as well as place the device in a low-current Sleep mode. The pin also starts the watchdog timer when transitioning from logic Low to logic High. This pin should not be allowed to be logic High until VDD is in regulation. This pin has a passive internal pull-down. DIRECT IN 0 & 1 (INx) This input pin is used to directly control the output HS0 and 1. This input has an active internal pull-down current source and requires CMOS logic levels. This input may be configured via the SPI. FAULT STATUS (FS) This is an open drain configured output requiring an external pull-up resistor to VDD for fault reporting. When a device fault condition is detected, this pin is active Low. Specific device diagnostic faults are reported via the SPI SO pin. FAIL-SAFE INPUT (FSI) The value of the resistance connected between this pin and ground determines the state of the outputs after a watchdog timeout occurs. Depending on the resistance value, either all outputs are OFF, ON, or the output HS0 only is ON. When the FSI pin is connected to GND, the watchdog circuit and fail-safe operation are disabled. This pin incorporates an active internal pull-up current source. CHIP SELECT (CS) This input pin is connected to a chip select output of a master microcontroller (MCU). The MCU determines which device is addressed (selected) to receive data by pulling the CS pin of the selected device logic Low, enabling SPI communication with the device. Other unselected devices on the serial link having their CS pins pulled-up logic High disregard the SPI communication data sent. This pin incorporates an active internal pull-up current source. SERIAL CLOCK (SCLK) This input pin is connected to the MCU providing the required bit shift clock for SPI communication. It transitions one time per bit transferred at an operating frequency, fSPI, defined by the communication interface. The 50 percent duty cycle CMOS-level serial clock signal is idle between command transfers. The signal is used to shift data into and out of the device. This input has an active internal pull- down current source.

20 NXP Semiconductors

SERIAL INPUT (SI) This is a command data input pin connected to the SPI Serial Data Output of the MCU or to the SO pin of the previous device of a daisy chain of devices. The input requires CMOS logic-level signals and incorporates an active internal pull-down current source. Device control is facilitated by the input's receiving the MSB first of a serial 8-bit control command. The MCU ensures data is available upon the falling edge of SCLK. The logic state of SI present upon the rising edge of SCLK loads this bit command into the internal command shift register. DIGITAL DRAIN VOLTAGE (VDD) This is an external voltage input pin used to supply power to the SPI circuit. In the event VDD is lost, an internal supply provides power to a portion of the logic, ensuring limited functionality of the device. All device configuration registers are reset. SERIAL OUTPUT (SO) This output pin is connected to the SPI Serial Data Input pin of the MCU or to the SI pin of the next device of a daisy chain of devices. This output remains tri-stated (high-impedance OFF condition) so long as the CS pin of the device is logic HIGH. SO is only active when the CS pin of the device is asserted logic Low. The generated SO output signals are CMOS logic levels. SO output data is available on the falling edge of SCLK and transitions immediately on the rising edge of SCLK. POSITIVE POWER SUPPLY (VPWR) This pin connects to the positive power supply and is the source input of operational power for the device. The VPWR pin is a backside surface mount tab of the package. HIGH-SIDE OUTPUT 0 & 1 (HSx) This pin protects 4.0 m high-side power output to the load.

Functional internal block description POWER SUPPLY The 33984 is designed to operate from 4.0 V to 28 V on the VPWR pin. Characteristics are provided from 6.0 V to 20 V for the device. The VPWR pin supplies power to internal regulator, analog, and logic circuit blocks. The VDD supply is used for serial peripheral interface (SPI) communication in order to configure and diagnose the device. This IC architecture provides a low quiescent current sleep mode. Applying VPWR and VDD to the device places the device in the Normal mode. The device transits to Fail-safe mode in case of failures on the SPI (watchdog timeout). HIGH-SIDE SWITCH: HS[0:1] Those pins are the high-side outputs controlling multiple automotive loads with high inrush current, as well as motors and all types of resistive and inductive loads. This N-channel MOSFET with 4.0 m RDS(ON), is self-protected and each N-channel presents extended diagnostics in order to detect load disconnections and short-circuit fault conditions. The HS[0:1] outputs are actively clamped during a turn-off of inductive loads. MCU INTERFACE AND OUTPUT CONTROL In Normal mode, the loads are controlled directly from the MCU through the SPI. With a dedicated SPI command, it is possible to independently turn on and off several loads are PWMed at the same frequency, and duty cycles with only one PWM signal. An analog feedback output provides a current proportional to each load current. The SPI is used to configure and to read the diagnostic status (faults) of the high-side output. The reported fault conditions are: open load, short-circuit to ground (OCLO-resistive and OCHI-severe short- circuit), thermal shutdown, and under/overvoltage. In Fail-safe mode, the loads are controlled with dedicated parallel input pins. The device is configured in default mode. MCU INTERFACE MCU INTERFACE AND OUTPUT CONTROL SPI INTERFACE PARALLEL CONTROL INPUTS POWER SUPPLY SELF-PROTECTED HIGH-SIDE SWITCH HS [0:1]

22 NXP Semiconductors

• V PWR is within the normal voltage range.
• RST pin is logic [1].
• No fault has occurred. FAIL-SAFE AND WATCHDOG If the FSI input is not grounded, the watchdog timeout detection is active when either the WAKE or RST input pin transitions from logic [0] to logic [1]. The WAKE input is capable of being pulled up to VPWR with a series of limiting resistance limits the internal clamp current according to the specification. The watchdog timeout is a multiple of an internal oscillator and is specified in Table 15. As long as the WD bit (D7) of an incoming SPI message is toggled within the minimum watchdog timeout period (WDTO), based on the programmed value of the WDR the device operates normally. If an internal watchdog timeout occurs before the WD bit, the device reverts to a Fail-safe mode until the device is reinitialized. During the Fail-safe mode, the outputs are ON or OFF depending upon the resistor RFS connected to the FSI pin, regardless of the state of the various direct inputs and modes (Table 7). In this mode, the SPI register content is retained except for overcurrent high and low detection levels and timing, which are reset to their default value (SOCL, SOCH, and OCLT). Then the watchdog, overvoltage, overtemperature, and overcurrent circuitry (with default value) are fully operational.

Table 6. Fail-safe operation and transitions to other 33984 modes Sleep x 0 0 x Device is in Sleep mode. All outputs are OFF. Normal 1 x 1 No Normal mode. Watchdog is active if enabled. No The device is currently in Fault mode. The faulted output(s) is (are) OFF. device out of the Fail-safe mode or momentarily tied the FSI pin to ground.

tied to GND, the watchdog Fail-safe operation is disabled. overcurrent circuitry are fully operational with default values.

• Overtemperature fault
• Open load fault
• Overcurrent faul t (high and low)
• Overvoltage and undervoltage fault The FS pin automatically returns to logic [1] when the fault condition is removed, except for overcurrent and in some cases undervoltage. fault information is retained in the fault register and is available (and reset) via the SO pin during the first valid SPI communication (refer to Table 17). Protection and diagnostic features OVERTEMPERATURE FAULT (NON-LATCHING) The 33984 incorporates overtemperature detection and shutdown circuitry in each output structure. Overtemperature detection is enabled when an output is in the ON state. For the output, an overtemperature fault (OTF) condition results in the faulted output turning OFF until the temperature falls below the TSD(HYS). This cycle continues indefinitely until action is taken by the MCU to shut OFF the output, or until the offending load is removed. When experiencing this fault, the OTF fault bit is set in the status register and cleared after either a valid SPI read or a power reset of the device. OVERVOLTAGE FAULT (NON-LATCHING) The 33984 shuts down the output during an overvoltage fault (OVF) condition on the VPWR pin. The output remains in the OFF state until the overvoltage condition is removed. When experiencing this fault, the OVF fault bit is set in the bit OD1 and cleared after either a valid SPI read or a power reset of the device. The overvoltage protection and diagnostic can be disabled trough the SPI (bit OV_dis). UNDERVOLTAGE SHUTDOWN (LATCHING OR NON-LATCHING) The output(s) latches off at some battery voltage below 6.0 V. As long as the VDD level stays within the normal specified range, the internal logic states within the device is sustained. In the case where battery voltage drops below the undervoltage threshold (VPWRUV) output turns off, FS goes to logic [0], and the fault register UVF bit is set to 1. Two cases need to be considered when the battery level recovers :
• If output(s) command is (are) low, FS goes to logic [1] but the UVF bit remains set to 1 until the next read operation.
• If the output command is ON, then FS remains at logic [0]. The output must be turned OFF and ON again to re-enable the state of output and release FS . The UVF bit remains set to 1 until the next read operation. The undervoltage protection can be disabled through the SPI (bit UV_dis = 1). In this case, the FS and UVF bits do not report any undervoltage fault condition and the output state is not changed as long as battery voltage does not drop any lower than 2.5 V.

Table 7. Output state during fail-safe mode

0 Fail-safe mode Disabled

6.0 Both HS0 and HS1 OFF

15 HS0 ON, HS1 OFF

30 Both HS0 and HS1 ON

24 NXP Semiconductors

status register is cleared after reading the register. bit sets to logic [1]) in case of permanent open load fault condition. are illustrated in Figure 6. The eight different overcurrent low detect levels (IOCL0:IOCL7) are likewise illustrated in Figure 6. stays off indefinitely until the device is commanded OFF and then ON again. order to ensure the device turns off in case of ground disconnect, and to prevent this pin from exceeding its maximum ratings. Table 8. Device behavior in case of undervoltage

2.5 V > VPWR >

the SCLK pin be in a logic [0] state whenever the device is not accessed (CS logic [1] state). SCLK has an active internal pull-down, IDWN. When CS is logic [1], signals at the SCLK and SI pins are ignored and SO is tri-stated (high-impedance). See Figure 9 and Figure 10. SCLK is a logic [0]. CS has an active internal pull-up, IUP.  While VDD remains within specified range. = IN is equivalent to IN direct input or IN_spi SPI input. Table 8. Device behavior in case of undervoltage (continued)

26 NXP Semiconductors

Figure 9. Single 8-Bit Word SPI Communication Figure 10. Multiple 8-bit word SPI communication and their protection features. transmitted data, as long as the messages are all multiples of eight bits. Any attempt made to latch in a message is not eight bits is ignored. SI registers. The registers are addressed via D6:D4 of the incoming SPI word (Table 9). Table 9. SI message bit assignment watchdog: toggled to satisfy watchdog requirements. D6:D4 Register address bits. features and SO status content. features and SO status content.

1. RSTB is in a logic 1 state during the above operation.
2. D0, D1, D2, ..., and D7 relate to the most recent ordered entry of data into the SPSS
3. OD0, OD1, OD2, ..., and OD7 relate to the first 8 bits of ordered fault and status data out
4. RST is a logic [1] state during the above operation.
5. D7:D0 relate to the most recent ordered entry of data into the device.
6. OD7:OD0 relate to the first 8 bits of ordered fault and status data out of the device.
7. RSTB i s i n a l ogi c 1 st at e dur i ng t he above oper at i on.
8. O D0, O D1, O D2, . . . , and O D7 r epr esent t he f i r st 8 bi t s of or der ed f aul t and st at us dat a out of t he SPSS
9. RST is a logic [1] state during the above operation.
10. D7:D0 relate to the most recent ordered entry of data into the device.
11. OD7:OD0 relate to the first 8 bits of ordered fault and status data out of the device.
12. D7*:D0* relate to the previous 8 bits (last command word) of data was previously shifted into the device.

The following section describes the possible register addresses and their impact on device operation. entitled Serial Output Communication (Device Status Return Data)). is enabled for both outputs, the current is summed. Bit D7 is used to feed the watchdog if enabled. matching system characteristics. Bits D2:D0 set the overcurrent low detection level to one of eight possible levels, as shown in Table 11. Bit D3 sets the overcurrent high detection level to one of two levels, which is described inTable 12. Table 10. Serial input address and configuration bit map s (SOA3 bit) = Selection of output: logic [0] = HS0, logic [1] = HS1.

28 NXP Semiconductors

low detection levels. If the selected overcurrent high level is reached, the device latches off within 20 s. the HS0. Similarly, if D7 is logic [1] when this register is written, then HS1 is configured. pin with the corresponding message bits when addressing the OCR register. bit can now be used to enable and disable the common PWM signal from controlling its assigned output. value [0] corresponds to the low speed slew rate. Table 11. Overcurrent low detection levels Table 12. Overcurrent high detection levels Table 13. Overcurrent Low Detection Blanking Time

switching delay times ranging from 0 ms to 525 ms. Refer to Table 14. is programmed at the beginning of a new count sequence. Refer to Table 15. continues to be reset while no programming or data readback functions are being requested from the device. are active. When disabled, an undervoltage or overvoltage condition fault is not reported in the output fault register. The TEST register is reserved for test and is not accessible with SPI during normal operation. upon the previously written SPI word. first transitioned to a logic [0]. This feature is useful for daisy chaining devices as well as message verification. Table 14. Switching delay Table 15. Watchdog Timeout

30 NXP Semiconductors

register is now able to accept new fault status information.

• The previous SPI communication was determined to be invalid. In this case, the status is reported as though the invalid SPI communication never occurred.
• Battery transients below 6.0 V resulting in an undervoltage shutdown of the outputs may result in incorrect data loaded into the status register. The SO data transmitted to the MCU during the first SPI communication following an undervoltage VPWR condition should be ignored.
• T h e RST pin transition from a logic [0] to logic [1] while the WAKE pin is at logic [0] may result in incorrect data loaded into the status register. The SO data transmitted to the MCU during the first SPI communication following this condition should be ignored. SERIAL OUTPUT BIT ASSIGNMENT The 8 bits of serial output data depend on the previous serial input message, as explained in the following paragraphs. Table 16 summarizes the SO register content. Bit OD7 reflects the state of the watchdog bit (D7) addressed during the prior communication. The value of the previous D7 determines which output the status information applies to for the Fault (FLTR), SOCHLR, CDTOLR, and DICR registers. SO data represents information ranging from fault status to register contents, user selected by writing to the STATR bits D2:D0. Note that the SO data continues to reflect the information for each output (depending on the previous D7 state) was selected during the most recent STATR write until changed with an updated STATR write. Previous Address SOA[2:0]=000 If the previous three MSBs are 000, bits OD6:OD0 reflects the current state of the Fault register (FLTR) corresponding to the output previously selected with the bit OD7 (Table 17). Previous Address SOA[2:0]=001 Data in bits OD1:OD0 contain CSNS0 EN and IN0_SPI programmed bits, respectively. Data in bits OD3:OD2 contain CSNS0 EN and IN0_SPI programmed bits, respectively. Previous Address SOA[2:0]=010 The data in bit OD3 contain the programmed overcurrent high detection level (refer to Table 12), and the data in bits OD2:OD0 contain the programmed overcurrent low detection levels (refer to Table 13).

Table 16. Serial output bit map description s = Selection of output: Logic [0] = HS0, Logic [1] = HS1.

overcurrent detection timeout feature is active. OD3 reports if the open load circuitry is active. The returned data contain the programmed values in the DICR.

• SOA3 = 0. The returned data contain the programmed values in the OSDR. Bit OD3 (FSM_HS0) reflects the state of the output HS0 in the Fail-safe mode after a watchdog timeout occurs.
• SOA3 = 1. The returned data contain the programmed values in th e WDR. Bit OD2 (WDTO) reflects the status of the watchdog circuitry. If WDTO bit is logic [1], the watchdog has timed out and the device is in Fail-safe mode. If WDTO is logic [0], the device is in Normal mode (assuming the device is powered and not in Sleep mode), with the watchdog either enabled or disabled. Bit OD3 (FSM_HS1) reflects the state of the output HS1 in the Fail-safe mode after a watchdog timeout occurs. Previous Address SOA[2:0] =110
• SOA3 = 0. OD3:OD0 return the state of the IN1, IN0, FSI, and WAKE pins, respectively (Table 18).
• SOA3 = 1. The returned data contain the programmed values in the UOVR. Bit OD1 reflects the state of the undervoltage protection and bit OD0 reflects the state of the overvoltage protection. Refer to Table 16). Previous Address SOA[2:0]=111 Null Data. No previous register Read Back command received, so bits OD2:OD0 are null, or 000.

Table 17. Fault register OD7 (s) = Selection of Output: Logic [0] = HS0, Logic [1] = HS1. OD6 (OTF) = Overtemperature Flag. OD3 (OLFs) = Open Load Flag. OD1 (OVF) = Overvoltage Flag. OD0 (FAULT) = This flag reports a fault and is reset by a read operation. command (via SPI or direct input IN). Table 18. Pin Register

32 NXP Semiconductors

Figure 11. Typical applications The loads must be chosen in order to guarantee the device normal operating conditions for junction temperatures from -40 °C to 150 °C. external recirculation device must be used to maintain the device in its safe operating area.

• AN3274, which proposes safe configurations of the eXtreme switch devices in case of application faults, and to protect all circuitry with minimum external components.
• AN2469, which provides guidelines for prin ted circuit board (PCB) design and assembly. Development effort is required by the end users to optimize the board design and PCB layout, in order to reach electromagnetic compatibility standards (emission and immunity). A/D MCU I/O I/O SI SO SCLK I/O CS SI FS VDD FSI CSNS RST CS IN0 SCLK WAKE NC VPWR 33984 100 nF 10 µF VDD VDD GND HS1 HS0 VPWR VPWR 2.5 µF 10 nF LOAD RFSI1k 2.2 k 10 k VDD 131 LOAD Voltage Regulator VDD VPWR IN1 I/O SO11 10 k 10 k 10 k 10 k 10 k 10 k

34 NXP Semiconductors

versus 10% when all contributors are considered. Figure 14. CSR0 ratio deviation in function manufacturing ageing of devices. Table 19 summaries test results covering 99.74% of parts. Table 19. CSR0 precision for several output current values with one calibration point at 5.0 A

0.5 A -25% 25%

1.0 A -12% 12%

The 33984 is packaged in a surface mount power package (PQFN), intended to be soldered directly on the printed circuit board. The AN2467 provides guidelines for Printed Circuit Board design and assembly. For the most current revision of the package, visit www.nxp.com and perform a keyword search on 98ARL10521D and 98ASA00815D. Dimensions shown are provided for reference ONLY. Table 20. Part keywords

36 NXP Semiconductors

38 NXP Semiconductors

40 NXP Semiconductors

42 NXP Semiconductors

Figure 15.

44 NXP Semiconductors

46 NXP Semiconductors

48 NXP Semiconductors

50 NXP Semiconductors

52 NXP Semiconductors

information is provided in the datasheet. TJ2, and a thermal resistance matrix with RJAmn. while only heat source 1 is heating with P1. application-specific environment. Stated values were obtained by measurement and simulation according to the standards listed below. Table 21. Thermal performance comparison

1. Per JEDEC JESD51-2 at natural convection, still air condition.
2. 2s2p thermal test board per JEDEC JESD51-7 and JESD51-5.
3. Per JEDEC JESD51-8, with the board temperature on the center trace near the
4. Single layer thermal test board per JEDEC JESD51-3 and JESD51-5.
5. Thermal resistance between the die junc tion and the exposed pad; “infinite” heat

sink attached to exposed pad.

Figure 16. Surface mount for power PQFN with exposed pads Figure 17. Thermal test board

33984 Pin Connections

54 NXP Semiconductors

heated. Index n refers to the number of the die where the junction temperature is sensed. Figure 18. Device on thermal test board RJA Table 22. Device on thermal test board Table 23. Thermal resistance performance

Figure 19. Transient thermal resistance RJA (1.0 W step response)

56 NXP Semiconductors

REVISION HISTORY

Revision Date Description of Changes 6.0 2/2006 • Implemented Revision History page

• Deletion of MC33984 part number, replaced with MC33984B. 7.0 5/2006
• Corrected Pin connections to the proper case outline
• Added final sentence to Open Load Fault (Non-Latching)
• Corrected heading labels on Input timing switching characteristics
• Changed labels in the Typical applications drawing
• Corrected Package dimensions to Revision C
• Added Thermal Addendum (rev 3.0). 8.0 1/2007 • Added RoHS logo 9.0 1/2007 • Changed several names on the Typical applications on page 32
• Added section Output current monitoring on page 33 10.0 8/2007
• Updated Freescale format and style
• Updated Thermal Rating (R JA) Junction-to-Ambient (from 20 to 30C/W)
• Changes label for HS1 Switching Delay Time (OSD[2:0]) and HS0 Switching Delay Time (OSD[2:0])
• Added Functional internal block description
• Updated Device behavior in case of undervoltage 11.0 10/2009 • Added MC33984C to the ordering information
• Added a Device Variation table 12.0 4/2010 • Corrected link from Device Variation Table to Table 3. No technical changes. 13.0 6/2010 • Corrected typo in Tables 16 and 17 (Faults to Fa ult) and added “FAULT report of any fault on HS0 or HS1” to Table 17. 14.0 5/2012
• Removed MC33984BPNA
• Updated orderable part number from MC33984CPNA to MC33984CHFK
• Updated (6)
• Updated Soldering information
• Updated Freescale form and style 15.0 8/2012 • Updated values in Table 14.
• Documented with PB15287. 16.0 10/2012 • Made limit changes to Dynamic electrical characteristics min, typ, and max.
• Corrected Orderable Part number information.
• Updated Freescale form and style
• Updated back page 10/2016 • Updated document to NXP form and style 17.0 07/2023
• Updated under CIN 202306024I
• Updated copyright from 2016 to 2023 on Page 45.
• Added package outline drawing number 98ASA00815D to page 1.
• Added row for MC33984EHFK to Table 1.
• Added rows for MC33984EHFK/MC33984CHFK under Characteristic for I OCL0. Parameters added for MC33984CHFK in Table 4.
• Added rows for MC33984EHFK/MC33984CHFK under Characteristic for C SR0 ... and associated parameters in Table 4.
• Added rows for MC33984EHFK/MC33984CHFK under Characteristic for SRRA_SLOW, SRFA_SLOW,
• Updated text on page 35 to include “and 98ASA00815D”, added Table 20.
• Added package outline drawing number 98ASA00815D and “and 98ASA00815D” to Note on page 53.
• Added figures for 98ASA00815D package dimensions.

Information in this document is provided solely to enable system and software implementers to use NXP products. There are no expressed or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. NXP reserves the right to make changes without further notice to any products herein. NXP makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does NXP assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation, consequential or incidental damages. "Typical" parameters that may be provided in NXP data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including "typicals," must be validated for each customer application by the customer's technical experts. NXP does not convey any license under its patent rights nor the rights of others. NXP sells products pursuant to standard terms and conditions of sale, which can be found at the following address: http://www.nxp.com/terms-of-use.html. How to Reach Us: Home Page: NXP.com Web Support: http://www.nxp.com/support NXP , the NXP logo, Freescale, the Freescale logo and SMARTMOS are trademarks of NXP B.V. All other product or service names are the property of their respective owners. All rights reserved. © 2023 NXP B.V. Document Number: MC33984 Rev. 17.0