MC33984 MOTOROLA | Alldatasheet

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Technical content

Features

•D u a l 4 . 0 mΩ Max High-Side Switch with Parallel Input or SPI Control • 6.0 V to 27 V Operating Voltage with Standby Currents < 5.0 µA • Output Current Monitoring with Two SPI-Selectable Current Ratios • SPI Control of Overcurrent Limit, Overcurrent Fault Blanking Time, Output-OFF Open Load Detection, Output ON/OFF Control, Watchdog Timeout, Slew Rates, and Fault Status Reporting • SPI Status Reporting of Overcurrent, Open and Shorted Loads, Overtemperature, Undervoltage and Overvoltage Shutdown, Fail-Safe Pin Status, and Program Status • Enhanced -16 V Reverse Polarity V PWR Protection DUAL HIGH-SIDE SWITCH 4.0 mΩ

ORDERING INFORMATION

Range (TA) Package MC33984PNA/R2 -40°C to 125°C 16 PQFN

33984 Simplified Application Diagram

SCALE 1:1 Bottom View PNA SUFFIX CASE 1402-02 16-TERMINAL PQFN (12 x 12) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

33984 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

Figure 1. 33984 Simplified Internal Block Diagram

100 A or 75 A

3.0 MHz

Freescale Semiconductor, Inc.

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33984 CSNS IN0 FS FSI CS SCLK RST WAKE SI VDD SO IN1 HS0 HS1 VPWR Transparent Top View of Package GND TERMINAL DEFINITIONS Functional descriptions of many of these terminals can be found in the System/Application Information section beginning on page 15. Terminal Terminal Name Formal Name Definition 1 CSNS Output Current Monitoring This term inal is used to output a current proportional to the designated HS0-1 output. That current is fed into a ground-referenced resistor and its voltage is monitored by an MCU's A/D. The channel to be monitored is selected via the SPI. This terminal can be tri-stated through SPI.

2 WAKE Wake This terminal is used to input a logi c [1] signal so as to enable the watchdog timer

function. An internal clamp protects this terminal from high damaging voltages when the output is current limited with an external resistor. This input has a passive internal pulldown. 3 RST Reset (Active Low) This input terminal is used to initia lize the device configuration and fault registers, as well as place the device in a low current sleep mode. The terminal also starts the watchdog timer when transitioning from logic LOW to logic HIGH. This terminal should not be allowed to be logic HIGH until VDD is in regulation. This terminal has a passive internal pulldown. 4 IN0 Serial Input This input terminal is used to directly control the output HS0. This input has an active internal pulldown current source and requires CMOS logic levels. This input may be configured via SPI. 5 FS Fault Status (Active Low) This is an open drain configured output requiring an external pullup resistor to VDD for fault reporting. When a device fault condition is detected, this terminal is active LOW. Specific device diagnostic faults are reported via the SPI SO terminal. 6 FSI Fail-Safe Input The value of the resistance c onnected between this terminal and ground determines the state of the outputs after a watchdog timeout occurs. Depending on the resistance value, either all outputs are OFF, ON, or the output HSO only is ON. When the FSI terminal is connected to GND, the watchdog circuit and fail-safe operation are disabled. This terminal incorporates an active internal pullup current source. 7 CS Chip Select (Active Low) This input te rminal is connected to a chip select output of a master microcontroller (MCU). The MCU determines which device is addressed (selected) to receive data by pulling the CS terminal of the selected device logic LOW, enabling SPI communication with the device. Other unselected devices on the serial link having their CS terminals pulled-up logic HIGH disregard the SPI communication data sent. This terminal incorporates an active internal pullup current source. 8 SCLK Serial Clock This input terminal is connected to the MCU providing the required bit shift clock for SPI communication. It transitions one time per bit transferred at an operating frequency, f SPI, defined by the communication interface. The 50 percent duty cycle CMOS-level serial clock signal is idle between command transfers. The signal is used to shift data into and out of the device. This input has an active internal pulldown current source. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

9 SI Serial Input This is a command data input terminal connected to the SPI Serial Data Output of the

MCU or to the SO terminal of the previous device of a daisy chain of devices. The input requires CMOS logic-level signals and incorporates an active internal pulldown current source. Device control is facilitated by the input's receiving the MSB first of a serial 8- bit control command. The MCU ensures data is available upon the falling edge of SCLK. The logic state of SI present upon the rising edge of SCLK loads that bit command into the internal command shift register.

10 V DD Digital Drain Voltage

(Power) This is an external voltage input terminal used to supply power to the SPI circuit. In the event VDD is lost, an internal supply provides power to a portion of the logic, ensuring limited functionality of the device. 11 SO Serial Output This output terminal is connected to the SPI Serial Data Input terminal of the MCU or to the SI terminal of the next device of a daisy chain of devices. This output will remain tri-stated (high impedance OFF condition) so long as the CS terminal of the device is logic HIGH. SO is only active when the CS terminal of the device is asserted logic LOW. The generated SO output signals are CMOS logic levels. SO output data is available on the falling edge of SCLK and transitions immediately on the rising edge of SCLK. 12 IN1 Serial Input This input terminal is used to directly control the output HS1. This input has an active internal pulldown current source and requires CMOS logic levels. This input may be configured via SPI. 13 GND Ground This terminal is the ground for the logic and analog circuitry of the device. 14 V PWR Positive Power Supply This terminal connects to the positive power supply and is the source input of operational power for the device. The VPWR terminal is a backside surface mount tab of the package. 15 HS1 High-Side Output 1 Protected 4.0 m Ω high-side power output to the load. 16 HS0 High-Side Output 0 Protected 4.0 m Ω high-side power output to the load. TERMINAL DEFINITIONS (continued) Functional descriptions of many of these terminals can be found in the System/Application Information section beginning on page 15. Terminal Terminal Name Formal Name Definition Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33984 MAXIMUM RATINGS All voltages are with respect to ground unless otherwise noted. Rating Symbol Value Unit ELECTRICAL RATINGS Operating Voltage Range Steady-State VPWR -16 to 41 V VDD Supply Voltage V DD 0 to 5.5 V Input/Output Voltage (Note 1) VIN[0:1], RST, FSI CSNS, SI, SCLK, CS, FS -0.3 to 7.0 V SO Output Voltage (Note 1) VSO -0.3 to VDD+0.3 V WAKE Input Clamp Current I CL(WAKE) 2.5 mA CSNS Input Clamp Current I CL(CSNS) 10 mA Output Current (Note 2) I HS[0:1] 30 A Output Clamp Energy (Note 3) ECL[0:1] 0.75 J ESD Voltage Human Body Model (Note 4) Machine Model (Note 5) VESD1 VESD2 ±2000 ±200 V THERMAL RATINGS Operating Temperature Ambient Junction TA TJ -40 to 125 -40 to 150 Storage Temperature T STG -55 to 150 °C Thermal Resistance (Note 6) Junction to Case Junction to Ambient RθJC RθJA <1.0 °C/W Peak Terminal Reflow Temperature During Solder Mounting (Note 7) T SOLDER 230 °C Notes 1. Exceeding voltage limits on RST, IN[0:1], or FSI terminals may cause a malfunction or permanent damage to the device. 2. Continuous high-side output current rati ng so long as maximum junction temperature is not exceeded. Calculation of maximum output current using package thermal resistance is required. 3. Active clamp energy using single-pulse method (L = 16 mH, R L = 0, VPWR = 12 V, TJ = 150°C). 4. ESD1 testing is performed in accordance with the Human Body Model (C ZAP = 100 pF, RZAP = 1500 Ω). 5. ESD2 testing is performed in ac cordance with the Machine Model (CZAP = 200 pF, RZAP = 0 Ω). 6. Device mounted on a 2s2p test board according to JEDEC JESD51-2. 7. Terminal soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

STATIC ELECTRICAL CHARACTERISTICS Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit POWER INPUT Battery Supply Voltage Range Full Operational VPWR 6.0 – 27 V VPWR Operating Supply Current Output ON, IHS0 and IHS1 = 0 A IPWR(ON) –– 2 0 mA VPWR Supply Current Output OFF, Open Load Detection Disabled, WAKE > 0.7 VDD, RST = VLOGIC HIGH IPWR(SBY) –– 5 . 0 mA Sleep State Supply Current (VPWR < 14 V, RST < 0.5 V, WAKE < 0.5 V) TJ = 25°C TJ = 85°C IPWR(SLEEP) µA VDD Supply Voltage V DD(ON) 4.5 5.0 5.5 V VDD Supply Current No SPI Communication

3.0 MHz SPI Communication

IDD(ON) 1.0 5.0 mA VDD Sleep State Current I DD(SLEEP) –– 5 . 0 µA Overvoltage Shutdown Threshold V PWR(OV) 28 32 36 V Overvoltage Shutdown Hysteresis V PWR(OVHYS) 0.2 0.8 1.5 V Undervoltage Output Shutdown Threshold (Note 8) VPWR(UV) 5.0 5.5 6.0 V Undervoltage Hysteresis (Note 9) VPWR(UVHYS) –0 . 2 5 – V Undervoltage Power-ON Reset V PWR(UVPOR) –– 5 . 0 V Notes 8. Output will automatically recover to instructed state when V PWR voltage is restored to normal so long as the VPWR degradation level did not go below the undervoltage power-ON reset threshold. This applies to all internal device logic that is supplied by VPWR and assumes that the external VDD supply is within specification. 9. This applies when the undervoltage fault is not latched (IN[0:1] = 0). Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33984 STATIC ELECTRICAL CHARACTERISTICS (continued) Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit POWER OUTPUT Output Drain-to-Source ON Resistance (IHS[0:1] = 30 A, TJ = 25°C) VPWR = 6.0 V VPWR = 10 V VPWR = 13 V RDS(ON) 6.0 4.0 4.0 mΩ Output Drain-to-Source ON Resistance (IHS[0:1] = 30 A, TJ = 150°C) VPWR = 6.0 V VPWR = 10 V VPWR = 13 V RDS(ON) 10.2 6.8 6.8 mΩ Output Source-to-Drain ON Resistance I HS[0:1] = 15 A, TJ = 25°C (Note 10) VPWR = -12 V RDS(ON) –– 8 . 0 mΩ Output Overcurrent High Detection Levels (9.0 V < VPWR < 16 V) SOCH = 0 SOCH = 1 IOCH0 IOCH1 100 120 A Overcurrent Low Detection Levels (SOCL[2:0]) 000 001 010 011 100 101 110 111 I OCL0 IOCL1 IOCL2 IOCL3 IOCL4 IOCL5 IOCL6 IOCL7 8.0 6.0 22.5 17.5 12.5 7.5 9.0 A Current Sense Ratio (9.0 V < VPWR < 16 V, CSNS < 4.5 V) DICR D2 = 0 DICR D2 = 1 CSR0 CSR1 Current Sense Ratio (CSR0) Accuracy Output Current 5.0 A 10 A 12.5 A 15 A 20 A 25 A C SR0_ACC -20 -14 -13 -12 -13 -13 Notes 10. Source-Drain ON Resistance (Reverse Drain-to -Source ON Resistance) with negative polarity V PWR. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

STATIC ELECTRICAL CHARACTERISTICS (continued) Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit POWER OUTPUT (continued) Current Sense Ratio (CSR1) Accuracy Output Current 5.0 A 10 A 12.5 A 15 A 20 A 25 A C SR1_ACC -25 -19 -18 -17 -18 -18 Current Sense Clamp Voltage CSNS Open; I HS[0:1] =2 9A VCL(CSNS) 4.5 6.0 7.0 V Open Load Detection Current (Note 11) I OLDC 30 – 100 µA Output Fault Detection Threshold Output Programmed OFF VOLD(THRES) 2.0 3.0 4.0 V Output Negative Clamp Voltage 0.5 A < IHS[0:1] < 2.0 A, Output OFF VCL -20 – – V Overtemperature Shutdown (Note 12) T SD 160 175 190 °C Overtemperature Shutdown Hysteresis (Note 12) T SD(HYS) 5.0 – 20 °C Notes 11. Output OFF Open Load Detection Current is the current required to flow through the load for the purpose of detecting the existence of an open load condition when the specific output is commanded OFF. 12. Guaranteed by process monitoring. Not production tested. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33984 STATIC ELECTRICAL CHARACTERISTICS (continued) Characteristics noted under conditions 4.5 V≤ VDD ≤ 5 . 5V , 6 . 0V ≤ VPWR ≤ 27 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit CONTROL INTERFACE Input Logic High Voltage (Note 13) VIH 0.7VDD – – V Input Logic Low Voltage (Note 13) VIL – – 0.2VDD V Input Logic Voltage Hysteresis (Note 14) VIN0:1 100 350 750 mV Input Logic Pulldown Current (SCLK, IN, SI) IDWN 5.0 – 20 µA RST Input Voltage Range VRST 4.5 5.0 5.5 V SO, FS Tri-State Capacitance (Note 15) CSO – – 20 pF Input Logic Pulldown Resistor (RST) and WAKE RDWN 100 200 400 kΩ Input Capacitance (Note 15) CIN – 4.0 12 pF WAKE Input Clamp Voltage (Note 16) ICL(WAKE) <2 . 5m A VCL(WAKE) 7.0 – 14 V WAKE Input Forward Voltage ICL(WAKE) = -2.5 mA VF(WAKE) -2.0 – -0.3 V SO High-State Output Voltage IOH = 1.0 mA VSOH

0.8 VDD – –

V FS, SO Low-State Output Voltage IOL = -1.6 mA VSOL – 0.2 0.4 V SO Tri-State Leakage Current CS > 0.7 VDD ISO(LEAK) -5.0 0 5.0 µA Input Logic Pullup Current (Note 17) CS, VIN[0:1] > 0.7 VDD IUP 5.0 – 20 µA FSI Input Terminal External Pulldown Resistance FSI Disabled, HS[0:1] Indeterminate FSI Enabled, HS[0:1] OFF FSI Enabled, HS0 ON, HS1 OFF FSI Enabled, HS[0:1] ON RFS RFSdis RFSoffoff RFSonoff RFSonon 6.0 6.5 Infinite 1.0 7.0 kΩ Notes 13. Upper and lower logic threshold voltage range applies to SI, CS, SCLK, RST, IN[0:1], and WAKE input signals. The WAKE and RST signals may be supplied by a derived voltage reference to VPWR. 14. Parameter is guaranteed by processi ng monitoring but is not production tested. 15. Input capacitance of SI, CS, SCLK, RST, and WAKE. This parameter is guaranteed by process monitoring but is not production tested. 16. The current must be limited by a series resistance when using voltages > 7.0 V. 17. Pullup current is with CS OPEN. CS has an active internal pullup to VDD. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

DYNAMIC ELECTRICAL CHARACTERISTICS Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit POWER OUTPUT TIMING Output Rising Slow Slew Rate A (DICR D3 = 0) (Note 18)

9.0 V < VPWR < 16 V

SRRA_SLOW 0.2 0.6 1.2 V/µs Output Rising Slow Slew Rate B (DICR D3 = 0) (Note 19) SRRB_SLOW 0.03 0.1 0.3 V/µs Output Rising Fast Slew Rate A (DICR D3 = 1) (Note 18) SRRA_FAST 0.4 1.0 4.0 V/µs Output Rising Fast Slew Rate B (DICR D3 = 1) (Note 19) SRRB_FAST 0.03 0.1 1.2 V/µs Output Falling Slow Slew Rate A (DICR D3 = 0) (Note 18) SRFA_SLOW 0.2 0.6 1.2 V/µs Output Falling Slow Slew Rate B (DICR D3 = 0) (Note 19) SRFB_SLOW 0.03 0.1 0.3 V/µs Output Falling Fast Slew Rate A (DICR D3 = 1) (Note 18) SRFA_FAST 0.8 2.0 4.0 V/µs Output Falling Fast Slew Rate B (DICR D3 = 1) (Note 19) SRFB_FAST 0.1 0.35 1.2 V/µs Output Turn-ON Delay Time in Fast/Slow Slew Rate (Note 20) DICR = 0, DICR = 1 tDLY(ON) 1.0 15 100 µs Output Turn-OFF Delay Time in Slow Slew Rate Mode (Note 21) DICR = 0 tDLY_SLOW(OFF) 20 230 500 µs Output Turn-OFF Delay Time in Fast Slew Rate Mode (Note 21) DICR = 1 tDLY_FAST(OFF) 10 60 200 µs Direct Input Switching Frequency (DICR D3 = 0) fPWM – 300 – Hz Notes guaranteed by process monitoring. guaranteed by process monitoring. 20. Turn-ON delay time measured from rising edge of IN [0:1] signal that would turn the output ON to VHS[0:1] = 0.5 V with RL = 5.0 Ω resistive load. 21. Turn-OFF delay time measured from falli ng edge that would turn the output OFF to VHS[0:1] = VPWR -0.5 V with RL =5 . 0Ω resistive load. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33984 POWER OUTPUT TIMING (continued) Overcurrent Detection Blanking Time (OCLT[1:0]) tOCL0 tOCL1 tOCL2 tOCL3 108 7.0 0.8 0.08 155 1.2 0.15 202 1.6 0.25 ms Overcurrent High Detection Blanking Time tOCH 1.0 10 20 µs CS to CSNS Valid Time (Note 22) tCNSVAL – – 10 µs HS0 Switching Delay Time (OSD[2:0]) 000 001 010 011 100 101 110 111 tOSD0 tOSD1 tOSD2 tOSD3 tOSD4 tOSD5 tOSD6 tOSD7 110 165 220 275 330 385 150 225 300 375 450 525 190 285 380 475 570 665 ms HS1 Switching Delay Time (OSD[2:0]) 000 001 010 011 100 101 110 111 tOSD0 tOSD1 tOSD2 tOSD3 tOSD4 tOSD5 tOSD6 tOSD7 110 110 220 220 330 330 150 150 300 300 450 450 190 190 380 380 570 570 ms Watchdog Timeout (WD[1:0]) (Note 23) tWDTO0 tWDTO1 tWDTO2 tWDTO3 434 207 1750 875 620 310 2500 1250 806 403 3250 1625 ms Notes 22. Time necessary for the CSNS to be within ±5% of the targeted value. 23. Watchdog timeout delay measured from the rising edge of WAKE to RST from a sleep state condition to output turn-ON with the output driven OFF and FSI floating. The values shown are for WDR setting of [00]. The accuracy of tWDTO is consistent for all configured watchdog timeouts. DYNAMIC ELECTRICAL CHARACTERISTICS (continued) Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

DYNAMIC ELECTRICAL CHARACTERISTICS (continued) Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit SPI INTERFACE CHARACTERISTICS Recommended Frequency of SPI Operation fSPI – – 3.0 MHz Required Low State Duration for RST (Note 24) tWRST – 50 350 ns Rising Edge of CS to Falling Edge of CS (Required Setup Time) (Note 25) tCS – – 300 ns Rising Edge of RST to Falling Edge of CS (Required Setup Time) (Note 25) tENBL – – 5.0 µs Falling Edge of CS to Rising Edge of SCLK (Required Setup Time) (Note 25) tLEAD – 50 167 ns Required High State Duration of SCLK (Required Setup Time) (Note 25) tWSCLKh – – 167 ns Required Low State Duration of SCLK (Required Setup Time) (Note 25) tWSCLKl – – 167 ns Falling Edge of SCLK to Rising Edge of CS (Required Setup Time) (Note 25) tLAG – 50 167 ns SI to Falling Edge of SCLK (Required Setup Time) (Note 26) tSI(SU) – 25 83 ns Falling Edge of SCLK to SI (Required Setup Time) (Note 26) tSI(HOLD) – 25 83 ns SO Rise Time CL = 200 pF tRSO – 25 50 ns SO Fall Time CL = 200 pF tFSO – 25 50 ns SI, CS, SCLK, Incoming Signal Rise Time (Note 26) tRSI – – 50 ns SI, CS, SCLK, Incoming Signal Fall Time (Note 26) tRSI – – 50 ns Time from Falling Edge of CS to SO Low Impedance (Note 27) tSO(EN) – – 145 ns Time from Rising Edge of CS to SO High Impedance (Note 28) tSO(DIS) – 65 145 ns Time from Rising Edge of SCLK to SO Data Valid (Note 29) 0.2 VDD ≤ SO ≥ 0.8 VDD, CL = 200 pF tVALID – 65 105 ns Notes 24. RST low duration measured with outputs enabled and going to OFF or disabled condition. 25. Maximum setup time required for the 33984 is the minimum guaranteed time needed from the microcontroller. 26. Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing. 27. Time required for output status data to be available for use at SO. 1.0 k Ω on pullup on CS. 28. Time required for output status data to be terminated at SO. 1.0 k Ω on pullup on CS. 29. Time required to obtain valid data out from SO following the rise of SCLK. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Figure 5. Input Timing Switching Characteristics Figure 6. SCLK Waveform and Valid SO Data Delay Time

0.7 VDD

0.2 VDD

Freescale Semiconductor, Inc.

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33984 SYSTEM/APPLICATION INFORMATION INTRODUCTION The 33984 is a dual self-protected 4.0 mΩ silicon switch used to replace electromechanical relays, fuses, and discrete devices in power management applications. The 33984 is designed for harsh environments, and it includes self-recovery features. The device is suitable for loads with high inrush current, as well as motors and all types of resistive and inductive loads. Programming, control, and diagnostics are implemented via the Serial Peripheral Interface (SPI). A dedicated parallel input is available for alternate and Pulse Width Modulation (PWM) control of each output. SPI-programmable fault trip thresholds allow the device to be adjusted for optimal performance in the application. The 33984 is packaged in a power-enhanced 12 x 12 nonleaded PQFN package with exposed tabs. FUNCTIONAL DESCRIPTION SPI Protocol Description The SPI interface has a full duplex, three-wire synchronous data transfer with four I/O lines associated with it: Serial Clock (SCLK), Serial Input (SI), Serial Output (SO), and Chip Select (CS). The SI/SO terminals of the 33984 follow a first-in first-out (D7/D0) protocol with both input and output words transferring the most significant bit (MSB) first. All inputs are compatible with 5.0 V CMOS logic levels. The SPI lines perform the following functions: Serial Clock (SCLK) Serial clocks (SCLK) the internal shift registers of the 33984 device. The serial input (SI) terminal accepts data into the input shift register on the falling edge of the SCLK signal while the serial output (SO) terminal shifts data information out of the SO line driver on the rising edge of the SCLK signal. It is important that the SCLK terminal be in a logic low state whenever CS makes any transition. For this reason, it is recommended that the SCLK terminal be in a logic [0] state whenever the device is not accessed (CS logic [1] state). SCLK has an active internal pulldown, IDWN. When CS is logic [1], signals at the SCLK and SI terminals are ignored and SO is tri-stated (high impedance). (See Figure 7 and Figure 8 on page 16.) Serial Input (SI) This is a serial interface (SI) command data input terminal. SI instruction is read on the falling edge of SCLK. An 8-bit stream of serial data is required on the SI terminal, starting with D7 to D0. The internal registers of the 33984 are configured and controlled using a 4-bit addressing scheme, as shown in Table 1, page 16. Register addressing and configuration are described in Table 2, page 17. The SI input has an active internal pulldown, IDWN. Serial Output (SO) The SO data terminal is a tri-stateable output from the shift register. The SO terminal remains in a high impedance state until the CS terminal is put into a logic [0] state. The SO data is capable of reporting the status of the output, the device configuration, and the state of the key inputs. The SO terminal changes states on the rising edge of SCLK and reads out on the falling edge of SCLK. Fault and Input Status descriptions are provided in Table 11, page 21. Chip Select (CS) The CS terminal enables communication with the master microcontroller (MCU). When this terminal is in a logic [0] state, the device is capable of transferring information to, and receiving information from, the MCU. The 33984 device latches in data from the Input shift registers to the addressed registers on the rising edge of CS. The device transfers status information from the power output to the shift register on the falling edge of CS. The SO output driver is enabled when CS is logic [0]. CS should transition from a logic [1] to a logic [0] state only when SCLK is a logic [0]. CS has an active internal pullup, IUP. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Figure 7. Single 8-Bit Word SPI Communication Figure 8. Multiple 8-Bit Word SPI Communication SPI communication is accomplished using 8-bit messages. latch in a message that is not eight bits will be ignored. configure the device and to control the state of the output. are addressed via D6:D4 of the incoming SPI word (Table 1).

  1. RSTB is in a logic 1 state during the above operation.
  2. D0, D1, D2, ..., and D7 relate to the most recent ordered entry of data into the SPSS
  3. OD0, OD1, OD2, ..., and OD7 relate to the first 8 bits of ordered fault and status data out

RST1. RST is a logic [1] state during the above operation.

  1. D7:D0 relate to the most recent ordered entry of data into the device.
  2. OD7:OD0 relate to the first 8 bits of ordered fault and status data out of the device.
  3. RSTB i s i n a l ogi c 1 st at e dur i ng t he above oper at i on.
  4. O D 0, O D 1, O D 2, . . . , and O D 7 r epr esent t he f i r st 8 bi t s of or der ed f aul t and st at us dat a out of t he SPSS

RST1. RST is a logic [1] state during the above operation.

  1. D7:D0 relate to the most recent ordered entry of data into the device.
  2. OD7:OD0 relate to the first 8 bits of ordered fault and status data out of the device.
  3. D7*:D0* relate to the previous 8 bits (last command word) of data that was previously shifted into the device.

Table 1. SI Message Bit Assignment D6:D4 Register address bits. Freescale Semiconductor, Inc.

addresses and their impact on device operation. D2:D0, determine the content of the first eight bits of SO data. summed. Bit D7 is used to feed the watchdog if enabled. output overcurrent low and high detection levels, respectively. logic [0] will configure the current detection levels for the HS0. Table 3. Bit D3 sets the overcurrent high detection level to one of two levels, which is described in Table 4. high level is reached, the device will latch off within 20 µs. Table 2. Serial Input Address and Configuration Bit Map s = Selection of output: logic [0] = HS0, logic [1] = HS1. Table 3. Overcurrent Low Detection Levels Table 4. Overcurrent High Detection Levels Freescale Semiconductor, Inc.

load (OL) detection feature. logic [1] when this register is written, then HS1 is configured. the same frequency and duty cycle with only one PWM signal. outputs with the dedicated SPI bit that also controls the output. the common PWM signal from controlling its assigned output. default value [0] is used to select the low ratio (CSR0, 1/20500). transitions initiated via SPI (not via direct input). beginning of a new count sequence (refer to Table 7). Table 5. Overcurrent Low Detection Table 6. Switching Delay Table 7. Watchdog Timeout Freescale Semiconductor, Inc.

in the output fault register. with SPI during normal operation. transition, are dependant upon the previously written SPI word. terminal since the CS terminal first transitioned to a logic [0]. accept new fault status information. the invalid SPI communication never occurred. following this condition should be ignored. input message, as explained in the following paragraphs. Table 8 summarizes the SO register content. until changed with an updated STATR write. Table 8. Serial Output Bit Map Description s = Selection of output: logic [0] = HS0, logic [1] = HS1. Freescale Semiconductor, Inc.

the output previously selected with the bit OD7 (Table 9). CSNS0 EN and IN0_SPI programmed bits, respectively. detection levels (refer to Table 3, page 17). overcurrent fault blanking time, illustrated in Table 5, page 18. active. OD3 reports if the open load circuitry is active. Safe mode after a watchdog timeout occurs. received, so bits OD2:OD0 are null, or 000. Table 9. Fault Register OD7 (s) = Selection of output: logic [0] = HS0, logic [1] = HS1. OD6 (OTF) = Overtemperature Flag. OD3 (OLFs) = Open Load Flag. OD1 (OVF) = Overvoltage Flag. is reset by a new Switch ON command (via SPI or direct input IN). Table 10. Terminal Register Freescale Semiconductor, Inc.

SPI-configurable features of the device are as if set to logic [0]. •V PWR is within the normal voltage range. • RST terminal is logic [1]. revert to a Fail-Safe mode until the device is reinitialized. overcurrent circuitry (with default value) are fully operational. from logic [1] to logic [0] or forcing the FSI terminal to logic [0]. device from the latched Fail-Safe mode. circuitry are fully operational with default values. Table 11. Fail-Safe Operation and Sleep x 0 0 x Device is in Sleep mode. Table 12. Output State During Fail-Safe Mode

0 Fail-Safe Mode Disabled

6.0 Both HS0 and HS1 OFF

15 HS0 ON, HS1 OFF

30 Both HS0 and HS1 ON

Freescale Semiconductor, Inc.

The 33984 indicates the following faults as they occur by driving the FS terminal to logic [0]: • Overtemperature fault • Open load fault • Overcurrent fault (high and low) • Overvoltage and undervoltage fault The FS terminal will automatically return to logic [1] when the fault condition is removed, except for Overcurrent and in some cases Undervoltage. Fault information is retained in the fault register and is available (and reset) via the SO terminal during the first valid SPI communication (refer to Table 9, page 20). Overtemperature Fault (Non-Latching) The 33984 incorporates overtemperature detection and shutdown circuitry in each output structure. Overtemperature detection is enabled when an output is in the ON state. For the output, an overtemperature fault (OTF) condition results in the faulted output turning OFF until the temperature falls below the TSD(HYS). This cycle will continue indefinitely until action is taken by the MCU to shut OFF the output, or until the offending load is removed. When experiencing this fault, the OTF fault bit will be set in the status register and cleared after either a valid SPI read or a power reset of the device. Overvoltage Fault (Non-Latching) The 33984 shuts down the output during an overvoltage fault (OVF) condition on the VPWR terminal. The output remains in the OFF state until the overvoltage condition is removed. When experiencing this fault, the OVF fault bit is set in the bit OD1 and cleared after either a valid SPI read or a power reset of the device. The overvoltage protection and diagnostic can be disabled trough SPI (bit OV_dis). Undervoltage Shutdown (Latching or Non-Latching) The output latches OFF at some battery voltage between 5.0 V and 6.0 V. As long as the VDD level stays within the normal specified range, the internal logic states within the device will be sustained. This ensures that when the battery level then returns above 6.0 V, the device can be returned to the state that it was in prior to the low VPWR excursion. Once the output latches OFF, the outputs must be turned OFF and ON again to re-enable them. In the case IN1:IN0 = 0, this fault is non-latched. The undervoltage protection and diagnostic can be disabled through SPI (bit UV_dis). Open Load Fault (Non-Latching) The 33984 incorporates open load detection circuitry on each output. Output open load fault (OLF) is detected and reported as a fault condition when that output is disabled (OFF). The open load fault is detected and latched into the status register after the internal gate voltage is pulled low enough to turn OFF the output. The OLF fault bit is set in the status register. If the open load fault is removed, the status register will be cleared after reading the register. The open load protection can be disabled trough SPI (bit OL_dis). Overcurrent Fault (Latching) The device has eight programmable overcurrent low detection levels (IOCL) and two programmable overcurrent high detection levels (IOCH) for maximum device protection. The two selectable, simultaneously active overcurrent detection levels, defined by IOCH and IOCL, are illustrated in Figure 4, page 13. The eight different overcurrent low detect levels (IOCL0:IOCL7) are likewise illustrated in Figure 4. If the load current level ever reaches the selected overcurrent low detect level and the overcurrent condition exceeds the programmed overcurrent time period (tOCx), the device will latch the effected output OFF. If at any time the current reaches the selected IOCH level, then the device will immediately latch the fault and turn OFF the output, regardless of the selected tOCL driver. For both cases, the device output will stay off indefinitely until the device is commanded OFF and then ON again. Reverse Battery The output survives the application of reverse voltage as low as -16 V. Under these conditions, the output’s gates are enhanced to keep the junction temperature less than 150°C. The ON resistance of the output is fairly similar to that in the Normal mode. No additional passive components are required. Ground Disconnect Protection In the event the 33984 ground is disconnected from load ground, the device protects itself and safely turns OFF the output regardless the state of the output at the time of disconnection. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33984 Soldering Information The 33984 is packaged in a surface mount power package intended to be soldered directly on the printed circuit board. The 33984 was qualified in accordance with JEDEC standards JESD22-A113-B and J-STD-020A. The recommended reflow conditions are as follows: • Convection: 225°C +5.0/-0°C • Vapor Phase Reflow (VPR): 215°C to 219°C • Infrared (IR)/Convection: 225°C +5.0/-0°C The maximum peak temperature during the soldering process should not exceed 230°C. The time at maximum temperature should range from 10 s to 40 s maximum. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

M M 2.2 2.20 0.05 C0.1 C0.05 C SEATING PLANE 42.0 1.95 0.00 121 (10X 0.4) M0.1 C M0.05 C A B C A B0.1 4.6 5.0 C0.1 A B 9X 0.9 2X 1.075 6X 2.05 1.55 1.85 3.55 (2) 6X 0.8 0.4 2X 1.28 0.88

6 PLACES

0.15 0.05(10X 0.5) (0.5) 10.7 10.3 C0.1 A B 11.2 10.8 (2X 0.75) 4X 1.45 1.05 C0.1 A B 5.5 5.1 C0.1 A B 2.25 1.75 (10X 0.25) 2.5 2.1 6X 1.1 0.6 2X 0.95 0.55 M0.1 C M0.05 C A B 10X 0.6 0.2 1516 PIN 1 INDEX AREA B C0.1 2X C0.1 A12 112 1615 PIN NUMBER REF . ONL Y DET AIL G NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETERS. 2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 3. THE COMPLETE JEDEC DESIGNA TOR FOR THIS 5. MINIMUM MET AL GAP SHOULD BE 0.25MM. P ACKAGE IS: HF-PQFP-N. 4. COPLANARITY APPLIES TO LEADS AND CORNER LEADS. DETAIL G VIEW ROTATED 90˚ CLOCKWISE VIEW M-M Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33984 NOTES Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33984 NOTES Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

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