33982C

33982B_09 FREESCALE | Alldatasheet

Document overview

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Technical content

Features

• Single 2.0 m Ω max high side switch with parallel input or SPI control
• 6.0 V to 27 V operating voltage with standby currents < 5.0 μA
• Output current monitoring with two SPI-selectable current ratios
• SPI control of over-current limit, over-current fault blanking time, output-OFF open load detection, output ON/OFF control, watchdog timeout, slew rates, and fault status reporting
• SPI status reporting of over-cu rrent, open and shorted loads, over-temperature shutdown, under-voltage and over-voltage shutdown, fail-safe pin status, and program status
• Enhanced -16 V reverse polarity V PWR protection

Figure 1. 33982 Simplified Application Diagram

ORDERING INFORMATION

Range (TA) Package MC33982BPNA/R2 -40°C to 125°C 16 PQFN MC33982CPNA/R2 SCALE 1:1 Bottom View PNA SUFFIX 98ARL10521D 16-PIN PQFN VDD I/O I/O SO SCLK CS SI I/O I/O A/D VPWR FS WAKE SI SCLK CS SO RST IN CSNS FSI GND HS GND LOAD 33982 MCU VDDVDDVDD VPWR GND PWR GND

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Table 1. Device Variations

Figure 2. 33982 Simplified Internal Block Diagram

3.0 MHz

150 A or 100 A

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Figure 3. 33982 Pin Connections Table 2. Pin Definitions Functional descriptions of many of these pins can be found in the Functional Pin Description section beginning on page 16.

1 CSNS Output Output Current

the microcontroller to monitor output current.

2 WAKE Input Wake This pin is used to input a Logic [1] signal in order to enable the watchdog

registers, as well as place the device in a low current sleep mode. 4 IN Input Direct Input The Input pin is used to directly control the output. resistor to VDD for fault reporting.

6 FSI Input Fail-Safe Input The value of the resistance connected between this pin and ground

determines the state of the output after a watchdog timeout occurs.

8 SCLK Input Serial Clock This input pin is connected to the MCU providing the required bit shift

clock for SPI communication.

9 SI Input Serial Input This is a command data input pin connected to the SPI Serial Data

10 VDD Input Digital Drain Voltage

11 SO Output Serial Output This output pin is connected to the SPI Serial Data Input pin of the MCU

or to the SI pin of the next device in a daisy chain of devices. 12 NC NC No Connect This pin may not be connected. 13 GND Ground Ground This pin is the ground for the logic and analog circuitry of the device.

14 VPWR Input Positive Power

operational power for the device. connected in parallel for operation. Table 2. Pin Definitions (continued) Functional descriptions of many of these pins can be found in the Functional Pin Description section beginning on page 16.

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ELECTRICAL CHARACTERISTICS

Table 3. Maximum Ratings All voltages are with respect to ground unless otherwise noted.

1. Exceeding this voltage limit may cause permanent damage to the device.
2. Continuous high side output current rating so long as maximum junction temperature is not exceeded. Calculation of maximum output

current using package thermal resistance is required.

1. Active clamp energy using single-pulse method (L = 16 mH, R L = 0, VPWR = 12 V, TJ = 150°C).
2. ESD1 testing is performed in accordance with the Human Body Model (HBM) (C ZAP = 100 pF, RZAP = 1500 Ω); ESD3 testing is

performed in accordance with the Charge Device Model (CDM), Robotic (Czap = 4.0 pF).

Analog Integrated Circuit Device Data Freescale Semiconductor 7 33982

• 40 to 125 - 40 to 150 Storage Temperature TSTG - 55 to 150 °C Thermal Resistance(5) Junction-to-Case Junction-to-Ambient RθJC RθJA <1.0 °C/W Peak Package Reflow Temperature During Reflow(6), (7) TPPRT Note 7 °C Notes 5. Device mounted on a 2s2p test board per JEDEC JESD51-2. 6. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. 7. Freescale’s Package Reflow capability meets Pb-free requir ements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.

All voltages are with respect to ground unless otherwise noted.

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STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 4. Static Electrical Characteristics Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TA ≤ 125°C, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted.

3.0 MHz SPI Communication

1. This applies to all internal dev ice logic that is supplied by VPWR and assumes that the external VDD supply is within specification.
2. This applies when the under-voltage fault is not latched (IN = 0).
3. Source-Drain ON Resistance (Reverse Drain-to -Source ON Resistance) with negative polarity VPWR.

Analog Integrated Circuit Device Data Freescale Semiconductor 9 33982 STATIC ELECTRICAL CHARACTERISTICS POWER OUTPUT (CONTINUED) Output Over-current High Detection Levels (9.0 V < VPWR < 16 V) SOCH = 0 SOCH = 1 IOCH0 IOCH1 120 150 100 180 120 A Over-current Low Detection Levels (SOCL[2:0]) 000 001 010 011 100 101 110 111 I OCL0 IOCL1 IOCL2 IOCL3 IOCL4 IOCL5 IOCL6 IOCL7 A Current Sense Ratio (9.0 V < VPWR < 16 V, CSNS < 4.5 V) DICR D2 = 0 DICR D2 = 1 CSR0 CSR1 Current Sense Ratio (CSR0) Accuracy Output Current 10 A 20 A 25 A 30 A 40 A 50 A C SR0_ACC - 20 -14 -13 -12 -13 -13 Current Sense Ratio (C SR1) Accuracy Output Current 10 A 20 A 25 A 30 A 40 A 50 A C SR1_ACC - 25 -19 -18 -17 -18 -18 Current Sense Clamp Voltage CSNS Open, I HS = 59.0 A VCL(CSNS) 4.5 6.0 7.0 V Current Sense Leakage(11) IN=1 with OUT opened of load or IN=0 ILEAK(CSNS) 01 0 2 0 μA Open Load Detection Current(12) IOLDC 30 – 100 μA Output Fault Detection Threshold Output Programmed OFF VOLD(THRES) 2.0 3.0 4.0 V Notes 11. This parameter is achieved by the design c haracterization by measuring a statistically relevant sample size across process variations but, not tested in production. 12. Output OFF Open Load Detection Current is the current requir ed to flow through the load for the purpose of detecting the existence of an open load condition when the specific output is commanded OFF. Table 4. Static Electrical Characteristics (continued) Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TA ≤ 125°C, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted.

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STATIC ELECTRICAL CHARACTERISTICS POWER OUTPUT (CONTINUED) Output Negative Clamp Voltage 0.5 A < IHS < 2.0 A, Output OFF VCL - 20 – -15 V Over-temperature Shutdown(13) TSD 160 175 190 °C Over-temperature Shutdown Hysteresis(13) TSD(HYS) 5.0 – 20 °C CONTROL INTERFACE Input Logic High-voltage(14) VIH 0.7 x VDD – – V Input Logic Low-voltage(14) VIL – – 0.2 x VDD V Input Logic Voltage Hysteresis(15) VIN(HYS) 100 600 1200 mV Input Logic Pull-down Current (SCLK, IN, SI) IDWN 5.0 – 20 μA RST Input Voltage Range VRST 4.5 5.0 5.5 V SO, FS Tri-state Capacitance(16) CSO – – 20 pF Input Logic Pull-down Resistor (RST) and WAKE RDWN 100 200 400 kΩ Input Capacitance(16) CIN – 4.0 12 pF WAKE Input Clamp Voltage(17) ICL(WAKE) < 2.5 mA VCL(WAKE) 7.0 – 14 V WAKE Input Forward Voltage ICL(WAKE) = -2.5 mA VF(WAKE) - 2.0 – -0.3 V SO High-state Output Voltage IOH = 1.0 mA VSOH 0.8 x VDD – – V FS, SO Low-state Output Voltage IOL = -1.6 mA VSOL – 0.2 0.4 V SO Tri-state Leakage Current CS > 0.7 x VDD ISO(LEAK) -5.0 0.0 5.0 μA Input Logic Pull-up Current (18) CS, VIN > 0.7 x VDD IUP 5.0 – 20 μA FSI Input Pin External Pull-down Resistance FSI Disabled, HS Indeterminate FSI Enabled, HS OFF FSI Enabled, HS ON RFS RFSDIS RFSOFF RFSON 6.0 0.0 1.0 kΩ Notes 13. Guaranteed by process monitoring. Not production tested. 14. Upper and lower logic threshold voltage range applies to SI, CS , SCLK, RST, IN, and WAKE input signals. The WAKE and RST signals may be supplied by a derived voltage reference to VPWR. 15. No hysteresis on FSI and wake pins. Parameter is guaran teed by process monitoring but is not production tested. 16. Input capacitance of SI, CS , SCLK, RST, and WAKE. This parameter is guaranteed by process monitoring but is not production tested. 17. The current must be limited by a series resistance when using voltages > 7.0 V. 18. Pull-up current is with CS OPEN. CS has an active internal pull-up to VDD. Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TA ≤ 125°C, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted.

Analog Integrated Circuit Device Data Freescale Semiconductor 11 33982 DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 5. Dynamic Electrical Characteristics Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TA ≤ 125°C, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted.

9.0 V < VPWR < 16 V

guaranteed by process monitoring. parameters are guaranteed by process monitoring.

1. Turn-ON delay time measured from rising edge of any signal (IN, SCLK, CS) that would turn the output ON to VHS = 0.5 V with
2. Turn-OFF delay time measured from fa lling edge of any signal (IN, SCLK, CS) that would turn the output OFF to VHS = VPWR - 0.5 V

with RL = 5.0 Ω resistive load.

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DYNAMIC ELECTRICAL CHARACTERISTICS POWER OUTPUT TIMING (CONTINUED) Over-current Low Detection Blanking Time (OCLT [1:0]) t OCL0 t OCL1 t OCL2 t OCL3 108 7.0 0.8 0.08 155 1.2 0.15 202 1.6 0.25 ms Over-current High Detection Blanking Time t OCH 1.0 10 20 μs CS to CSNS Valid Time(23) t CNSVAL – – 10 μs Output Switching Delay Time (OSD [2:0]) 000 001 010 011 100 101 110 111 t OSD0 t OSD1 t OSD2 t OSD3 t OSD4 t OSD5 t OSD6 t OSD7 105 157 210 262 315 367 0.0 150 225 300 375 450 525 195 293 390 488 585 683 ms Watchdog Timeout (WD [1:0])(24) t WDTO0 t WDTO1 t WDTO2 t WDTO3 434 207 1750 875 620 310 2500 1250 806 403 3250 1625 ms SPI INTERFACE CHARACTERISTICS Recommended Frequency of SPI Operation f SPI – – 3.0 MHz Required Low-state Duration for RST(25) t WRST – 50 167 ns Notes 23. Time necessary for the CSNS to be within ±5% of the targeted value. 24. Watchdog timeout delay measured from the rising edge of WAKE to RST from a sleep state condition to output turn-ON with the output driven OFF and FSI floating. The values shown are for WDR setting of [00]. The accuracy of tWDTO is consistent for all configured watchdog timeouts. 25. RST low duration measured with outputs enabled and going to OFF or disabled condition. Table 5. Dynamic Electrical Characteristics (continued) Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TA ≤ 125°C, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted.

Analog Integrated Circuit Device Data Freescale Semiconductor 13 33982 DYNAMIC ELECTRICAL CHARACTERISTICS SPI INTERFACE CHARACTERISTICS Rising Edge of CS to Falling Edge of CS (Required Setup Time)(26) t CS – – 300 ns Rising Edge of RST to Falling Edge of CS (Required Setup Time)(26) t ENBL – – 5.0 μs Falling Edge of CS to Rising Edge of SCLK (Required Setup Time)(26) t LEAD – 50 167 ns Required High-state Duration of SCLK (Required Setup Time)(26) t WSCLKH – – 167 ns Required Low-state Duration of SCLK (Required Setup Time)(26) t WSCLKL – – 167 ns Falling Edge of SCLK to Rising Edge of CS (Required Setup Time)(26) t LAG – 50 167 ns SI to Falling Edge of SCLK (Required Setup Time)(27) t SI(SU) – 25 83 ns Falling Edge of SCLK to SI (Required Setup Time)(27) t SI(HOLD) – 25 83 ns SO Rise Time CL = 200 pF t RSO – 25 50 ns SO Fall Time CL = 200 pF t FSO – 25 50 ns SI, CS, SCLK, Incoming Signal Rise Time(27) t RSI – – 50 ns SI, CS, SCLK, Incoming Signal Fall Time(27) t FSI – – 50 ns Time from Falling Edge of CS to SO Low-impedance(28) t SO(EN) – – 145 ns Time from Rising Edge of CS to SO High-impedance(29) t SO(DIS) – 65 145 ns Time from Rising Edge of SCLK to SO Data Valid(30) 0.2 VDD ≤ SO ≤ 0.8 VDD, CL = 200 pF t VALID – 65 105 ns Notes 26. Maximum setup time required for the 33982 is the mi nimum guaranteed time needed from the microcontroller. 27. Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing. 28. Time required for output status data to be available for use at SO. 1.0 k Ω on pull-up on CS. 29. Time required for output status data to be terminated at SO. 1.0 k Ω on pull-up on CS. 30. Time required to obtain valid data out from SO following the rise of SCLK. Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TA ≤ 125°C, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted.

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Figure 4. Output Slew Rate and Time Delays Figure 5. Over-current Shutdown Figure 6. Over-current Low and High Detection

Analog Integrated Circuit Device Data Freescale Semiconductor 15 33982 Figure 6 illustrates the over-current detection level (IOCLX, IOCHX) the device can reach for each over-current detection blanking time (tOCHX, tOCLX):

• During t OCHX, the device can reach up to Ioch0 over- current level.
• During t OCL3 or tOCL2 or tOCL1 or tOCL0, the device can be programmed to detect up to Iocl0.

Figure 7. Input Timing Switching Characteristics Figure 8. SCLK Waveform and Valid SO Data Delay Time

0.7 VDD

0.2 VDD

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The 33982 is a self-protected silicon 2.0 mΩ high side switch used to replace electromechanical relays, fuses, and discrete devices in power management applications. The 33982 is designed for harsh environments, including self- recovery features. The device is suitable for loads with high inrush current, as well as motors and all types of resistive and inductive loads. Programming, control, and diagnostics are implemented via the Serial Peripheral Interface (SPI). A dedicated parallel input is available for alternate and pulse width modulation (PWM) control of the output. SPI programmable fault trip thresholds allow the device to be adjusted for optimal performance in the application. The 33982 is packaged in a power-enhanced 12 x 12 nonleaded PQFN package with exposed tabs. FUNCTIONAL PIN DESCRIPTION OUTPUT CURRENT MONITORING (CSNS) The CSNS pin outputs a current proportional to the high side output current and used externally to generate a ground- referenced voltage for the microcontroller to monitor output current. WAKE (WAKE) This pin is used to input a Logic [1] signal in order to enable the watchdog timer function. An internal clamp protects this pin from high damaging voltages when the output is current limited with an external resistor. This input has a passive internal pull-down. RESET (RST) This input pin is used to initialize the device configuration and fault registers, as well as place the device in a low- current sleep mode. The pin also starts the watchdog timer when transitioning from logic LOW to logic HIGH. This pin should not be allowed to be logic HIGH until V DD is in regulation. This pin has a passive internal pull-down. DIRECT IN (IN) The Input pin is used to directly control the output. This input has an active internal pulldown current source and requires CMOS logic levels. This input may be configured via SPI. FAULT STATUS (FS) This is an open drain configured output requiring an external pull-up resistor to VDD for fault reporting. When a device fault condition is detected, this pin is active LOW. Specific device diagnostic faults are reported via the SPI SO pin. FAIL-SAFE INPUT (FSI) The value of the resistance connected between this pin and ground determines the state of the output after a watchdog timeout occurs. Depending on the resistance value, either the output is OFF or ON. When the FSI pin is connected to GND, the watchdog circuit and fail-safe operation are disabled. This pin incorporates an active internal pull-up current source. CHIP SELECT (CS) This input pin is connected to a chip select output of a master microcontroller (MCU). The MCU determines which device is addressed (selected) to receive data by pulling the CS pin of the selected device logic LOW, enabling SPI communication with the device. Other unselected devices on the serial link having their CS pins pulled up logic HIGH disregard the SPI communication data sent. This pin incorporates an active internal pull-up current source. SERIAL CLOCK (SCLK) This input pin is connected to the MCU providing the required bit shift clock for SPI communication. It transitions one time per bit transferred at an operating frequency, fSPI, defined by the communication interface. The 50 percent duty cycle CMOS-level serial clock signal is idle between command transfers. The signal is used to shift data into and out of the device. This input has an active internal pull-down current source. SERIAL INTERFACE (SI) This is a command data input pin connected to the SPI Serial Data Output of the MCU or to the SO pin of the previous device in a daisy chain of devices. The input requires CMOS logic level signals and incorporates an active internal pull-down current source. Device control is facilitated by the input's receiving the MSB first of a serial 8-bit control command. The MCU ensures data is available upon the falling edge of SCLK. The logic state of SI present upon the rising edge of SCLK loads that bit command into the internal command shift register. DIGITAL DRAIN VOLTAGE POWER (VDD) This is an external voltage input pin used to supply power to the SPI circuit. In the event VDD is lost, an internal supply provides power to a portion of the logic, ensuring limited functionality of the device. All device configuration registers are reset.

Analog Integrated Circuit Device Data Freescale Semiconductor 17 33982 FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION SERIAL OUTPUT (SO) This output pin is connected to the SPI Serial Data Input pin of the MCU or to the SI pin of the next device in a daisy chain of devices. This output will remain tri-stated (high- impedance OFF condition) so long as the CS pin of the device is logic HIGH. SO is only active when the CS pin of the device is asserted logic LOW. The generated SO output signals are CMOS logic levels. SO output data is available on the falling edge of SCLK and transitions immediately on the rising edge of SCLK. POSITIVE POWER SUPPLY (VPWR) This pin connects to the positive power supply and is the source input of operational power for the device. The VPWR pin is a backside surface mount tab of the package. HIGH-SIDE OUTPUT (HS) This pin protects high side power output to the load. Output pins must be connected in parallel for operation.

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Figure 9. Functional Internal Block Diagram architecture provides a low quiescent current sleep mode. case of failures on the SPI (watchdog timeout). output is actively clamped during a turn-off of inductive loads. short-circuit), thermal shutdown, and under/over-voltage. parallel input pins. The device is configured in default mode.

RST inputs as defined in Table 6.

• V PWR is within the normal voltage range.
• RST pin is Logic [1].
• No fault has occurred. FAIL-SAFE MODE AND WATCHDOG If the FSI input is not grounded, the watchdog timeout detection is active when either the WAKE or RST input pin transitions from Logic [0] to Logic [1]. The WAKE input is capable of being pulled up to VPWR with a series of limiting resistance that limits the internal clamp current. The watchdog timeout is a multiple of an internal oscillator and is specified in Table 15. As long as the WD bit (D7) of an incoming SPI message is toggled within the minimum watchdog timeout period (WDTO), based on the programmed value of the WDR the device will operate normally. If an internal watchdog timeout occurs before the WD bit, the device will revert to a Fail-safe mode until the device is reinitialized. During the Fail-safe mode, the output will be ON or OFF depending upon the resistor RFS connected to the FSI pin, regardless of the state of the various direct inputs and modes (Table 7 ). In this mode, the SPI register content is retained except for over-current high and low detection levels and timing, which are reset to their default value (SOCL, SOCH, OCLT). The watchdog, over-voltage, over-temperature, and over-current circuitry (with default value for this one) are fully operational. The Fail-safe mode can be detected by monitoring the WDTO bit D2 of the WDR register. This bit is Logic [1] when the device is in Fail-safe mode. The device can be brought out of the Fail-safe mode by transitioning the WAKE and RST pins from Logic [1] to Logic [0] or forcing the FSI pin to Logic [0]. Table 6 summarizes the various methods for resetting the device from the latched Fail-safe mode. If the FSI pin is tied to GND, the Watchdog Fail-safe operation is disabled. LOSS OF VDD If the external 5.0 V supply is not within specification, or even disconnected, all register content is reset. The output can still be driven by the direct input IN. The 33982 uses the battery input to power the output MOSFET related current sense circuitry, and any other internal Logic, providing fail- safe device operation with no V DD supplied. In this state, the watchdog, over-voltage, over-temperature, and over-current circuitry are fully operational with default values. Current recopy is active with the default current recopy value.

Table 6. Fail-safe Operation and Transitions to Other

33982 Modes

Sleep x 0 0 x Device is in Sleep mode. Table 7. Output State During Fail-safe Mode

0 Fail-safe Mode Disabled

10 HS OFF

30 HS ON

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• Over-temperature fault
• Over-voltage and under-voltage fault
• Open load fault
• Over-current fault (high and low) The FS pin will automatically return to Logic [1] when the fault condition is removed, except for over-current and in some cases under-voltage. Fault information is retained in the fault register and is available (and reset) via the SO pin during the first valid SPI communication (refer to Table 17). PROTECTION AND DIAGNOSIS FEATURES OVER-TEMPERATURE FAULT (NON-LATCHING) The 33982 incorporates over-temperature detection and shutdown circuitry in the output structure. Over-temperature detection is enabled when the output is in the ON state. For the output, an over-temperature fault (OTF) condition results in the faulted output turning OFF until the temperature falls below the TSD(HYS). This cycle will continue indefinitely until action is taken by the MCU to shut OFF the output, or until the offending load is removed. When experiencing this fault, the OTF fault bit will be set in the status register and cleared after either a valid SPI read or a power reset of the device. OVER-VOLTAGE FAULT (NON-LATCHING) The 33982 shuts down the output during an over-voltage fault (OVF) condition on the VPWR pin. The output remains in the OFF state until the over-voltage condition is removed. When experiencing this fault, the OVF fault bit is set in bit OD1 and cleared after either a valid SPI read or a power reset of the device. The over-voltage protection and diagnostic can be disabled through the SPI (bit OV_dis). UNDER-VOLTAGE SHUTDOWN (LATCHING OR NON-LATCHING) The output(s) will latch off at some battery voltage below 6.0 V. As long as the VDD level stays within the normal specified range, the internal logic states within the device will be sustained. In the cases where the battery voltage drops below the under-voltage threshold, (VPWRUV) the output will turn off, FS will go to Logic [0], and the fault register UVF bit will be set to 1. Two cases need to be considered when the battery level recovers:
• If the output(s) command is (are) low, FS will go to Logic [1], but the UVF bit will remain set to 1 until the next read operation.
• If the output command is ON, then FS will remain at Logic [0]. The output must be turned OFF and ON again to re-enable the state of output and release FS. The UVF bit will remain set to 1 until the next read operation. The under-voltage protection can be disabled through the SPI (bit UV_dis = 1). In this case, the FS and UVF bits do not report any under-voltage fault condition and the output state will not be changed as long as the battery voltage does not drop any lower than 2.5 V. OPEN LOAD FAULT (NON-LATCHING) The 33982 incorporates open load detection circuitry on the output. Output open load fault (OLF) is detected and reported as a fault condition when the output is disabled (OFF). The open load fault is detected and latched into the status register after the internal gate voltage is pulled low enough to turn OFF the output. The OLF fault bit is set in the status register. If the open load fault is removed, the status register will be cleared after reading the register. The open load protection can be disabled through the SPI (bit OL_dis). It is recommended to disable the open load detection circuitry (OL_dis bit sets to logic [1]) in case of a permanent open load fault condition. OVER-CURRENT FAULT (LATCHING) The 33982 has eight programmable over-current low detection levels (IOCL) and two programmable over-current high detection levels (IOCH) for maximum device protection. The two selectable, simultaneously active over-current detection levels, defined by IOCH and IOCL, are illustrated in

Figure 6. The eight different over-current low detection levels (IOCL0 : IOCL7) are likewise illustrated in Figure 6. device will latch the output OFF. until the device is commanded OFF and then ON again.

enhanced to keep the junction temperature less than 150°C. prevent this pin to exceed its maximum ratings. Table 8. Device Behavior in Case of Under-voltage

2.5 V > VPWR >

∗∗ While VDD remains within specified range. ∗∗∗ = IN is equivalent to IN direct input or IN_spi SPI input.

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Table 9. Register addressing and configuration are described The SO pin is a tri-stateable output from the shift register. Figure 10. Single 8-Bit Word SPI Communication

1. RSTB is in a logic 1 state during the above operation.
2. D0, D1, D2, ..., and D7 relate to the most recent ordered entry of data into the SPSS
3. OD0, OD1, OD2, ..., and OD7 relate to the first 8 bits of ordered fault and status data out

RST1. RST is a Logic [1] state during the above operation.

1. D7:D0 relate to the most recent ordered entry of data into the device.
2. OD7:OD0 relate to the first 8 bits of ordered fault and status data out of the device.

Figure 11. Multiple 8-Bit Word SPI Communication with the MSB, D7, and ending with the LSB, D0 (Table 9). configure and control the output and its protection features. latch in a message that is not eight bits will be ignored. configure the device and to control the state of the output. addressed via D6 : D4 of the incoming SPI word (Table 9).

1. RSTB i s i n a l ogi c 1 st at e dur i ng t he above oper at i on.
2. O D0, O D1, O D2, . . . , and O D7 r epr esent t he f i r st 8 bi t s of or der ed f aul t and st at us dat a out of t he SPSS
3. RST is a Logic [1] state during the above operation.
4. D7:D0 relate to the most recent ordered entry of data into the device.
5. OD7:OD0 relate to the first 8 bits of ordered fault and status data out of the device.
6. D7*:D0* relate to the previous 8 bits (last command word) of data that was previously shifted into the device.

Table 9. SI Message Bit Assignment D6 : D4 Register address bits.

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addresses and their impact on device operation. CDTOLR, DICR, OSDR, WDR, NAR, and UOVR registers. disables the open load (OL) detection feature. on bit D1 will enable the output for direct control by the IN pin. A Logic [1] on bit D1 will disable the output from direct control. Table 10. Serial Input Address and Configuration Bit Table 11. Over-current Low Detection Levels Table 12. Over-current High Detection Levels Table 13. Over-current Low Detection Blanking Time

corresponds to the low-speed slew rate. transitions that are initiated via the SPI (not via direct input). delay configured in the OSDR register. times, which range from 0 to 525 ms. Table 14. Switching Delay Table 15. Watchdog Timeout

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and D0 of the output fault register. accessible with SPI during normal operation. able to accept new fault status information.

• The previous SPI communication was determined to be invalid. In this case, the status will be reported as though the invalid SPI communication never occurred.
• Battery transients below 6. 0 V resulting in an under- voltage shutdown of the outputs may result in incorrect data loaded into the status register. The SO data transmitted to the MCU during the first SPI communication following an under-voltage VPWR condition should be ignored.
• The RST pin transition from a Logic [0] to Logic [1] while the WAKE pin is at Logic [0] may result in incorrect data loaded into the status register. The SO data transmitted to the MCU during the first SPI communication following this condition should be ignored. SERIAL OUTPUT BIT ASSIGNMENT The eight bits of serial output data depend on the previous serial input message, as explained in the following paragraphs. Table 16 summarizes the SO register content. Bit OD7 reflects the state of the watchdog bit (D7) addressed during the prior communication. The contents of bits OD6 : OD0 depend upon the bits D2 : D0 from the most recent STATR command SOA2 : SOA0. Previous Address SOA[2:0] = 000 If the previous three MSBs are 000, bits OD6 : OD0 reflect the current state of the Fault register (FLTR) (Table 17). Previous Address SOA[2:0] = 001 The data in bits OD1 and OD0 contain CSNS EN and IN_SPI programmed bits, respectively.

Table 16. Serial Output Bit Map Descriptions

low detection levels (refer to Table 11). for the over-current fault blanking time, illustrated in Table 13.

• SOA3 = 0. The returned data contain the programmed values in the OSDR. Bit OD3 (FSM_HS) reflects the state of the output in the Fail-safe mode after a watchdog timeout occurs.
• SOA3 = 1. The returned data contain the programmed values in the WDR. Bit OD2 (WDTO) reflects the status of the watchdog circuitry. If WDTO bit is Logic [1], the watchdog has timed out and the device is in Fail-safe mode. If WDTO is Logic [0], the device is in Normal mode (assuming device is powered and not in the Sleep mode), with the watchdog either enabled or disabled. Previous Address SOA[2:0] =110
• SOA3 = 0. OD2, OD1, and OD0 return the state of the IN, FSI, and WAKE pins, respectively (Table 18).
• SOA3 = 1. The returned data contains the programmed values in the UOVR register. Bit OD1 reflects the state of the under-voltage protection, while bit OD0 reflects the state of the over-voltage protection (refer to Table 16). Previous Address SOA[2:0] = 111 Null Data. No previous register Read Back command received, so bits OD2, OD1, and OD0 are null, or 000.

Table 17. Fault Register OD6 (OTF) = Over-temperature Flag. OD1 (OVF) = Over-voltage Flag. command (via SPI or direct input IN). Table 18. Pin Register

28 Freescale Semiconductor

Figure 12. Typical Applications

• AN3274, which proposes sa fe configurations of the eXtreme Switch devices in case of application faults, and to protect all circuitry with minimum external components.
• AN2469, which provides guidelines for Printed Circuit Board (PCB) design and assembly. Development effort will be required by the end users to optimize the board design and PCB layout, in order to reach electromagnetic compatibility standards (emission and immunity). A/D MCU I/O I/O SI SO SCLK I/O CS SO SI FS VDD FSI CSNS RST CS IN SCLK NC WAKE NC VPWR 33982 100nF 10µF VDD VDD GND HS HS VPWR VPWR 2.5µF 10nF LOAD RFS1k 10 k 10 k VDD Voltage Regulator VDD VPWR NC 10k 10k 10k 10k 10k

Analog Integrated Circuit Device Data Freescale Semiconductor 29 33982 PACKAGING SOLDERING INFORMATION PACKAGING SOLDERING INFORMATION SOLDERING INFORMATION The 33982 is packaged in a surface mount power package intended to be soldered directly on the printed circuit board. The 33982 was qualified in accordance with JEDEC standards JESD22-A113-B and J-STD-020A. The recommended reflow conditions are as follows:

• Convection: 225°C +5 .0/ -0°C
• Vapor Phase Reflow (VPR): 215°C to 219°C
• Infrared (IR) / Convection: 225°C +5.0 / -0°C The maximum peak temperature during the soldering process should not exceed 230°C. The time at maximum temperature should range from 10 to 40 s maximum.

Analog Integrated Circuit Device Data

30 Freescale Semiconductor

For the most current revision of the package, visit www.freescale.com and perform a keyword search on 98ARL10596D. PNA SUFFIX 16-PIN PQFN NONLEADED PACKAGE 98ARL10521D ISSUE C

Analog Integrated Circuit Device Data Freescale Semiconductor 31 33982 PACKAGING PACKAGE DIMENSIONS PACKAGE DIMENSIONS (CONTINUED) PNA SUFFIX 16-PIN PQFN NONLEADED PACKAGE 98ARL10521D ISSUE C

32 Freescale Semiconductor

application, and packaging information is provided in the datasheet. TJ1 and TJ2, and a thermal resistance matrix with RθJAmn. temperature while only heat source 1 is heating with P1. Figure 13. Surface Mount for Power PQFN Table 19. Thermal Performance Comparison

1. Per JEDEC JESD51-2 at natural convection, still air
2. 2s2p thermal test board per JEDEC JESD51-7and
3. Per JEDEC JESD51-8, with the board temperature on the

center trace near the power outputs.

1. Single layer thermal test board per JEDEC JESD51-3 and
2. Thermal resistance betw een the die junction and the

exposed pad, “infinite” heat sink attached to exposed pad.

Figure 14. Thermal Test Board where the junction temperature is sensed.

33982 Pin Connections

Table 20. Thermal Resistance Performance

34 Freescale Semiconductor

Figure 15. Device on Thermal Test Board RθJA Figure 16. Transient Thermal Resistance RθJA (1.0 W Step Response)

Analog Integrated Circuit Device Data Freescale Semiconductor 35 33982

REVISION HISTORY

REVISION DATE DESCRIPTION OF CHANGES 10 2/2006 • Implemented Revision History page

• Deletion of MC33982 part number, replaced with MC33982B. 11 5/2006 • Corrected Pin Connections to the proper case outline
• Added final sentence to Open Load Fault (Non-Latching)
• Corrected heading labels on Input Timing Switching Characteristics
• Changed labels in the Typical Applications drawing
• Corrected Package Dimensions to Revision C
• Added Thermal Addendum (Rev 3.0). 12 1/2007 • Added RoHS logo to the data sheet 13 7/2007 • Added Functional Internal Block Description
• Minor corrections to Serial Output Bit Map Descriptions and Device Behavior in Case of Under- voltage 14 6/2008 • Changed the labeling header on DYNAMIC Electrical Characteristics from 150 to 125 degrees C
• Updated Freescale form and style 15.0 7/2009 • Added Current Sense Leakage to Static Electr ical Characteristics table (Table 3). 16.0 10/2009 • Added MC33982C to the ordering information
• Added a Device Variations table

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