33982_V01 FREESCALE | Alldatasheet

Document overview

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Technical content

Features

  • Single 2.0 m  max high-side switch with parallel input or SPI control
  • 6.0 V to 27 V operating voltage with standby currents < 5.0 A
  • Output current monitoring with two SPI-selectable current ratios
  • SPI control of overcurrent limit, overcurrent fault blanking time, output OFF open load detection, output ON/OFF control, watchdog timeout, slew rates, and fault status reporting
  • SPI status reportin g of overcurrent, open and shorted loads, overtemperature shutdown, undervoltage and overvoltage shutdown, Fail-safe pin status, and program status
  • Enhanced -16 V reverse polarity V PWR protection

Figure 1. 33982 Simplified Application Diagram

Applications

  • DC motor or solenoid
  • Resistive and inductive loads
  • Low-voltage lighting SCALE 1:1 Bottom View FK SUFFIX 98ARL10521D 16-PIN PQFN VDD I/O I/O SO SCLK CS SI I/O I/O A/D VPWR FS WAKE SI SCLK CS SO RST IN CSNS FSI GND HS GND LOAD 33982 MCU VDDVDDVDD VPWR GND PWR GND

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Table 1. Orderable Part Variations (1)

  1. To order parts in Tape & Reel, add the R2 suffix to the part number.

Figure 2. 33982 Simplified Internal Block Diagram

3.0 MHz

15 A to 50 A

150 A or 100 A

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Figure 3. 33982 Pin Connections Functional descriptions of many of these pins can be found in the Functional Pin Description section beginning on page 16. Table 2. Pin Definitions

1 CSNS Output Output Current

microcontroller to monitor output current.

2 WAKE Input Wake This pin is used to input a logic [1] signal in order to enable the watchdog timer

well as place the device in a low current sleep mode. 4 IN Input Direct Input The Input pin is used to directly control the output. the state of the output after a watchdog timeout occurs.

9 SI Input Serial Input This is a command data input pin connected to the SPI Serial Data Output of the

MCU or to the SO pin of the previous device in a daisy chain of devices.

10 VDD Input Digital Drain Voltage

(Power) This is an external voltage input pin used to supply power to the SPI circuit. SI pin of the next device in a daisy chain of devices. 12 NC NC No Connect This pin may not be connected.

13 GND Ground Ground This pin is the ground for the logic and analog circuitry of the device.

14 VPWR Input Positive Power

operational power for the device. Table 2. Pin Definitions (continued)

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ELECTRICAL CHARACTERISTICS

Table 3. Maximum Ratings All voltages are with respect to ground unless otherwise noted.

  1. Exceeding this voltage limit may cause permanent damage to the device.
  2. Continuous high-side output current rating so long as maximum junction temperature is not exceeded. Calculation of maximum output current

using package thermal resistance is required.

  1. Active clamp energy using singl e-pulse method (L = 16 mH, RL = 0, VPWR = 12 V, TJ = 150°C).
  2. ESD1 testing is performed in accordanc e with the Human Body Model (HBM) (CZAP = 100 pF, RZAP = 1500 ESD3 testing is performed in

accordance with the Charge Device Model (CDM), Robotic (Czap = 4.0 pF).

Analog Integrated Circuit Device Data Freescale Semiconductor 7 33982

  • 40 to 125 - 40 to 150 TSTG Storage Temperature - 55 to 150 C RJC RJA Thermal Resistance Junction-to-Case Junction-to-Ambient <1.0 C/W (6) TPPRT Peak Package Reflow Temperature During Reflow Note 8 °C (7), (8) Notes 6. Device mounted on a 2s2p test board per JEDEC JESD51-2. 7. Pin soldering temperature limit is for 40 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. 8. Freescale’s Package Reflow capabi lity meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.

All voltages are with respect to ground unless otherwise noted.

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STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 4. Static Electrical Characteristics values noted reflect the approximate parameter mean at TA = 25 C under nominal conditions, unless otherwise noted.

3.0 MHz SPI Communication

  1. This applies to all internal devi ce logic that is supplied by V

PWR and assumes that the external VDD supply is within specification.

  1. This applies when the undervoltage fault is not latched (IN = 0).
  2. Source-Drain ON Resistance (Reverse Drain-to -Source ON Resistance) with negative polarity VPWR.

Analog Integrated Circuit Device Data Freescale Semiconductor 9 33982 STATIC ELECTRICAL CHARACTERISTICS POWER OUTPUT (CONTINUED) IOCL0 IOCL1 IOCL2 IOCL3 IOCL4 IOCL5 IOCL6 IOCL7 Overcurrent Low Detection Levels (SOCL[2:0]) 000 001 010 011 100 101 110 111 A C SR0 CSR1 Current Sense Ratio (9.0 V < VPWR < 16 V, CSNS < 4.5 V) DICR D2 = 0 DICR D2 = 1 C SR0_ACC Current Sense Ratio (CSR0) Accuracy Output Current 10 A 20 A 25 A 30 A 40 A 50 A - 20 -14 -13 -12 -13 -13 C SR1_ACC Current Sense Ratio (CSR1) Accuracy Output Current 10 A 20 A 25 A 30 A 40 A 50 A - 25 -19 -18 -17 -18 -18 V CL(CSNS) Current Sense Clamp Voltage CSNS Open, IHS = 59.0 A 4.5 6.0 7.0 V ILEAK(CSNS) Current Sense Leakage IN = 1 with OUT opened of load or IN = 0 0.0 10 20 A (12) IOLDC Open Load Detection Current 30 – 100 A (13) VOLD(THRES) Output Fault Detection Threshold Output Programmed OFF 2.0 3.0 4.0 V VCL Output Negative Clamp Voltage 0.5 A < IHS < 2.0 A, Output OFF - 20 – -15 V TSD Overtemperature Shutdown 160 175 190 C (14) TSD(HYS) Overtemperature Shutdown Hysteresis 5.0 – 20 C (14) Notes 12. This parameter is achieved by the design characterization by measuring a statistically relevant sample size across process variations but, not tested in production. 13. Output OFF open load detection current is the current required to flow through the load for the purpose of detecting the existence of an open load condition when the specific output is commanded OFF. 14. Guaranteed by process monitoring. Not production tested. Table 4. Static Electrical Characteristics (continued) values noted reflect the approximate parameter mean at TA = 25 C under nominal conditions, unless otherwise noted.

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STATIC ELECTRICAL CHARACTERISTICS CONTROL INTERFACE VIH Input Logic High-voltage 0.7 x VDD – – V (15) VIL Input Logic Low-voltage – – 0.2 x VDD V (15) VIN(HYS) Input Logic Voltage Hysteresis 100 600 1200 mV (16) IDWN Input Logic Pull-down Current (SCLK, IN, SI) 5.0 – 20 A VRST RST Input Voltage Range 4.5 5.0 5.5 V CSO SO, FS Tri-state Capacitance – – 20 pF (17) RDWN Input Logic Pull-down Resistor (RST) and WAKE 100 200 400 k CIN Input Capacitance – 4.0 12 pF (17) VCL(WAKE) WAKE Input Clamp Voltage ICL(WAKE) < 2.5 mA 7.0 – 14 V (18) VF(WAKE) WAKE Input Forward Voltage ICL(WAKE) = -2.5 mA - 2.0 – -0.3 V VSOH SO High-state Output Voltage IOH = 1.0 mA 0.8 x VDD – – V VSOL FS, SO Low-state Output Voltage IOL = -1.6 mA – 0.2 0.4 V ISO(LEAK) SO Tri-state Leakage Current CS > 0.7 x VDD -5.0 0.0 5.0 A IUP Input Logic Pull-up Current CS, VIN > 0.7 x VDD 5.0 – 20 A (19) RFS RFSDIS RFSOFF RFSON FSI Input Pin External Pull-down Resistance FSI Disabled, HS Indeterminate FSI Enabled, HS OFF FSI Enabled, HS ON 6.0 0.0 1.0 Notes 15. Upper and lower logic threshold voltage range applies to SI, CS , SCLK, RST, IN, and WAKE input signals. The WAKE and RST signals may be supplied by a derived voltage reference to VPWR. 16. No hysteresis on FSI and wake pins. Parameter is guar anteed by process monitoring but is not production tested. 17. Input capacitance of SI, CS , SCLK, RST, and WAKE. This parameter is guaranteed by process monitoring but is not production tested. 18. The current must be limited by a series resistance when using voltages > 7.0 V. 19. Pull-up current is with CS OPEN. CS has an active internal pull-up to VDD. values noted reflect the approximate parameter mean at TA = 25 C under nominal conditions, unless otherwise noted.

Analog Integrated Circuit Device Data Freescale Semiconductor 11 33982 DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 5. Dynamic Electrical Characteristics values noted reflect the approximate parameter mean at TA = 25C under nominal conditions, unless otherwise noted. are guaranteed by process monitoring.

  1. Turn-ON delay time measured from rising edge of any signal (IN, SCLK, CS ) that would turn the output ON to VHS = 0.5 V with 
  2. Turn-OFF delay time measured from fa lling edge of any signal (IN, SCLK, CS) that would turn the output OFF to VHS = VPWR - 0.5 V with RL =

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DYNAMIC ELECTRICAL CHARACTERISTICS POWER OUTPUT TIMING (CONTINUED) t CNSVAL CS to CSNS Valid Time – – 10 s (24) t OSD0 t OSD1 t OSD2 t OSD3 t OSD4 t OSD5 t OSD6 t OSD7 Output Switching Delay Time (OSD [2:0]) 000 001 010 011 100 101 110 111 105 157 210 262 315 367 0.0 150 225 300 375 450 525 195 293 390 488 585 683 ms t WDTO0 t WDTO1 t WDTO2 t WDTO3 Watchdog Timeout (WD [1:0]) 434 207 1750 875 620 310 2500 1250 806 403 3250 1625 ms (25) SPI INTERFACE CHARACTERISTICS f SPI Recommended Frequency of SPI Operation – – 3.0 MHz t WRST Required Low-state Duration for RST – 50 167 ns (26) Notes 24. Time necessary for the CSNS to be within ±5% of the targeted value. 25. Watchdog timeout delay measured from the rising edge of WAKE to RST from a sleep state condition to output turn-ON with the output driven OFF and FSI floating. The values shown are for WDR setting of [00]. The accuracy of tWDTO is consistent for all configured watchdog timeouts. 26. RST low duration measured with outputs enabled and going to OFF or disabled condition. Table 5. Dynamic Electrical Characteristics (continued) values noted reflect the approximate parameter mean at TA = 25C under nominal conditions, unless otherwise noted.

Analog Integrated Circuit Device Data Freescale Semiconductor 13 33982 Figure 4. Output Slew Rate and Time Delays

  1. Maximum setup time required for the 33982 is the mi nimum guaranteed time needed from the microcontroller.
  2. Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
  3. Time required for output status data to be available for use at SO. 1.0 k on pull-up on CS.
  4. Time required for output status data to be terminated at SO. 1.0 k on pull-up on CS.
  5. Time required to obtain valid data out from SO following the rise of SCLK.

values noted reflect the approximate parameter mean at TA = 25C under nominal conditions, unless otherwise noted.

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Figure 5. Overcurrent Shutdown Figure 6. Overcurrent Low and High Detection

  • During t OCHX, the device can reach up to Ioch0 overcurrent level.
  • During t OCL3 or tOCL2 or tOCL1 or tOCL0, the device can be programmed to detect up to Iocl0. IOCLx IOCHx t OCLx t OCH Time Load Current IOCH0 t OCL0t OCL1t OCL2t OCL3t OCHx Time Load Current IOCH1 IOCL0 IOCL2 IOCL3 IOCL4 IOCL5 IOCL6 IOCL7 IOCL1

Analog Integrated Circuit Device Data Freescale Semiconductor 15 33982 Figure 7. Input Timing Switching Characteristics Figure 8. SCLK Waveform and Valid SO Data Delay Time

0.7 VDD

0.2 VDD

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The 33982 is a self-protected silicon 2.0 m high-side switch used to replace electromechanical relays, fuses, and discrete devices in power management applications. The 33982 is designed for harsh environments, including self-recovery features. The device is suitable for loads with high inrush current, as well as motors and all types of resistive and inductive loads. Programming, control, and diagnostics are implemented via the Serial Peripheral Interface (SPI). A dedicated parallel input is available for alternate and pulse width modulation (PWM) control of the output. SPI programmable fault trip thresholds allow the device to be adjusted for optimal performance in the application. The 33982 is packaged in a power-enhanced 12 mm x 12 mm non-leaded PQFN package with exposed tabs. FUNCTIONAL PIN DESCRIPTION OUTPUT CURRENT MONITORING (CSNS) The CSNS pin outputs a current proportional to the high-side output current and used externally to generate a ground-referenced voltage for the microcontroller to monitor output current. WAKE (WAKE) This pin is used to input a logic [1] signal in order to enable the watchdog timer function. An internal clamp protects this pin from high damaging voltages when the output is current limited with an external resistor. This input has a passive internal pull-down. RESET (RST) This input pin is used to initialize the device configuration and fault registers, as well as place the device in a low-current sleep mode. The pin also starts the watchdog timer when transitioning from logic LOW to logic HIGH. This pin should not be allowed to be logic High until VDD is in regulation. This pin has a passive internal pull-down. DIRECT IN (IN) The Input pin is used to directly control the output. This input has an active internal pull-down current source and requires CMOS logic levels. This input may be configured via the SPI. FAULT STATUS (FS) This is an open drain configured output requiring an external pull-up resistor to VDD for fault reporting. When a device fault condition is detected, this pin is active LOW. Specific device diagnostic faults are reported via the SPI SO pin. FAIL-SAFE INPUT (FSI) The value of the resistance connected between this pin and ground determines the state of the output after a watchdog timeout occurs. Depending on the resistance value, either the output is OFF or ON. When the FSI pin is connected to GND, the watchdog circuit and Fail- safe operation are disabled. This pin incorporates an active internal pull-up current source. CHIP SELECT (CS) This input pin is connected to a chip select output of a master microcontroller (MCU). The MCU determines which device is addressed (selected) to receive data by pulling the CS pin of the selected device logic Low, enabling SPI communication with the device. Other unselected devices on the serial link having their CS pins pulled up logic High disregard the SPI communication data sent. This pin incorporates an active internal pull-up current source. SERIAL CLOCK (SCLK) This input pin is connected to the MCU providing the required bit shift clock for SPI communication. It transitions one time per bit transferred at an operating frequency, fSPI, defined by the communication interface. The 50 percent duty cycle CMOS-level serial clock signal is idle between command transfers. The signal is used to shift data into and out of the device. This input has an active internal pull-down current source. SERIAL INTERFACE (SI) This is a command data input pin connected to the SPI Serial Data Output of the MCU or to the SO pin of the previous device in a daisy chain of devices. The input requires CMOS logic level signals and incorporates an active internal pull-down current source. Device control is facilitated by the input's receiving the MSB first of a serial 8-bit control command. The MCU ensures data is available upon the falling edge of SCLK. The logic state of SI present upon the rising edge of SCLK loads that bit command into the internal command shift register.

Analog Integrated Circuit Device Data Freescale Semiconductor 17 33982 FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION DIGITAL DRAIN VOLTAGE POWER (VDD) This is an external voltage input pin used to supply power to the SPI circuit. In the event VDD is lost, an internal supply provides power to a portion of the logic, ensuring limited functionality of the device. All device configuration registers are reset. SERIAL OUTPUT (SO) This output pin is connected to the SPI Serial Data Input pin of the MCU or to the SI pin of the next device in a daisy chain of devices. This output remains tri-stated (high-impedance OFF condition) so long as the CS pin of the device is logic High. SO is only active when the CS pin of the device is asserted logic Low. The generated SO output signals are CMOS logic levels. SO output data is available on the falling edge of SCLK and transitions immediately on the rising edge of SCLK. POSITIVE POWER SUPPLY (VPWR) This pin connects to the positive power supply and is the source input of operational power for the device. The VPWR pin is a backside surface mount tab of the package. HIGH-SIDE OUTPUT (HS) This pin protects high-side power output to the load. Output pins must be connected in parallel for operation.

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Figure 9. Functional Internal Block Diagram disconnections and short-circuit fault conditions. The HS output is actively clamped during a turn-off of inductive loads. thermal shutdown, and under/overvoltage. In Fail-safe mode, the load is controlled with dedicated parallel input pins. The device is configured in default mode.

  • V PWR is within the normal voltage range.
  • RST pin is logic [1].
  • No fault has occurred. FAIL-SAFE MODE AND WATCHDOG If the FSI input is not grounded, the watchdog timeout detection is active when either the WAKE or RST input pin transitions from logic [0] to logic [1]. The WAKE input is capable of being pulled up to VPWR with a series of limiting resistance that limits the internal clamp current. The watchdog timeout is a multiple of an internal oscillator and is specified in Table 15. As long as the WD bit (D7) of an incoming SPI message is toggled within the minimum watchdog timeout period (WDTO), based on the programmed value of the WDR the device operates normally. If an internal watchdog timeout occurs before the WD bit, the device reverts to a Fail-safe mode until the device is reinitialized. During the Fail-safe mode, the output is ON or OFF depending upon the resistor RFS connected to the FSI pin, regardless of the state of the various direct inputs and modes (Table 7). In this mode, the SPI register content is retained except for overcurrent high and low detection levels and timing, which are reset to their default value (SOCL, SOCH, OCLT). The watchdog, overvoltage, overtemperature, and overcurrent circuitry (with default value for this one) are fully operational. The Fail-safe mode can be detected by monitoring the WDTO bit D2 of the WDR register. This bit is logic [1] when the device is in Fail- safe mode. The device can be brought out of the Fail-safe mode by transitioning the WAKE and RST pins from logic [1] to logic [0] or forcing the FSI pin to logic [0]. Table 6 summarizes the various methods for resetting the device from the latched Fail-safe mode.

Table 6. Fail-safe Operation and Transitions to Other 33982 Modes Sleep x 0 0 x Device is in Sleep mode. All outputs are OFF. Normal 1 x 1 No Normal mode. Watchdog is active if enabled. No The device is currently in Fault mode. The faulted output is OFF. device out of the Fail-safe mode or momentarily tied the FSI pin to ground. Table 7. Output State During Fail-safe Mode

0 Fail-safe Mode Disabled

10 HS OFF

30 HS ON

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FUNCTIONAL DEVICE OPERATION PROTECTION AND DIAGNOSTIC FEATURES If the FSI pin is tied to GND, the Watchdog Fail-safe operation is disabled. LOSS OF VDD If the external 5.0 V supply is not within specification, or even disconnected, all register content is reset. The output can still be driven by the direct input IN. The 33982 uses the battery input to power the output MOSFET related current sense circuitry, and any other internal logic, providing fail-safe device operation with no VDD supplied. In this state, the watchdog, overvoltage, overtemperature, and overcurrent circuitry are fully operational with default values. Current recopy is active with the default current recopy value. FAULT MODE The 33982 indicates the following faults as they occur by driving the FS pin to logic [0]:

  • Overtemperature fault
  • Overvoltage and undervoltage fault
  • Open load fault
  • Overcurrent fault (high and low) The FS pin automatically returns to logic [1] when the fault condition is removed, except for overcurrent and in some cases undervoltage. Fault information is retained in the fault register and is available (and reset) via the SO pin during the first valid SPI communication (refer to Table 17). PROTECTION AND DIAGNOSTIC FEATURES OVERTEMPERATURE FAULT (NON-LATCHING) The 33982 incorporates overtemperature detection and shutdown circuitry in the output structure. Overtemperature detection is enabled when the output is in the ON state. For the output, an overtemperature fault (OTF) condition results in the faulted output turning OFF until the temperature falls below the TSD(HYS). This cycle continues indefinitely until action is taken by the MCU to shut OFF the output, or until the offending load is removed. When experiencing this fault, the OTF fault bit is set in the status register and cleared after either a valid SPI read or a power reset of the device. OVERVOLTAGE FAULT (NON-LATCHING) The 33982 shuts down the output during an overvoltage fault (OVF) condition on the VPWR pin. The output remains in the OFF state until the overvoltage condition is removed. When experiencing this fault, the OVF fault bit is set in bit OD1 and cleared after either a valid SPI read or a power reset of the device. The overvoltage protection and diagnostic can be disabled through the SPI (bit OV_dis). UNDERVOLTAGE SHUTDOWN (LATCHING OR NON-LATCHING) The output(s) latches off at some battery voltage below 6.0 V. As long as the VDD level stays within the normal specified range, the internal logic states within the device is sustained. In cases where the battery voltage drops below the undervoltage threshold, (VPWRUV) the output turns off, FS goes to logic [0], and the fault register UVF bit is set to 1. Two cases need to be considered when the battery level recovers:
  • If the output(s) command is (are) low, FS goes to logic [1], but the UVF bit remains set to 1 until the next read operation.
  • If the output command is ON, then FS remains at logic [0]. The output must be turned OFF and ON again to re-enable the state of output and release FS. The UVF bit remains set to 1 until the next read operation. The undervoltage protection can be disabled through the SPI (bit UV_dis = 1). In this case, the FS and UVF bits do not report any undervoltage fault condition and the output state is not changed as long as the battery voltage does not drop any lower than 2.5 V. OPEN LOAD FAULT (NON-LATCHING) The 33982 incorporates open load detection circuitry on the output. Output open load fault (OLF) is detected and reported as a fault condition when the output is disabled (OFF). The open load fault is detected and latched into the status register after the internal gate voltage is pulled low enough to turn OFF the output. The OLF fault bit is set in the status register. If the open load fault is removed, the status register is cleared after reading the register. The open load protection can be disabled through the SPI (bit OL_dis). It is recommended to disable the open load detection circuitry: (OL_dis bit sets to logic [1]) in case of a permanent open load fault condition. OVERCURRENT FAULT (LATCHING) The 33982 has eight programmable overcurrent low detection levels (IOCL) and two programmable overcurrent high detection levels (IOCH) for maximum device protection. The two selectable, simultaneously active overcurrent detection levels, defined by IOCH and IOCL, are illustrated in Figure 6. The eight different overcurrent low detection levels (IOCL0 : IOCL7) are likewise illustrated in Figure 6.

overcurrent time period (tOCx), the device latches the output OFF. of the selected tOCL driver. For both cases, the device output stays off indefinitely until the device is commanded OFF and then ON again. order to ensure that the device turns off in case of a ground disconnect and to prevent this pin to exceed its maximum ratings. Table 8. Device Behavior in Case of Undervoltage

2.5 V > VPWR >

 While VDD remains within specified range. = IN is equivalent to IN direct input or IN_spi SPI input.

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Input (SI), Serial Output (SO), and Chip Select (CS). SCLK is a logic [0]. CS has an active internal pull-up, IUP. Figure 10. Single 8-Bit Word SPI Communication

  1. RSTB is in a logic 1 state during the above operation.
  2. D0, D1, D2, ..., and D7 relate to the most recent ordered entry of data into the SPSS
  3. OD0, OD1, OD2, ..., and OD7 relate to the first 8 bits of ordered fault and status data out

RST1. RST is a logic [1] state during the above operation.

  1. D7:D0 relate to the most recent ordered entry of data into the device.
  2. OD7:OD0 relate to the first 8 bits of ordered fault and status data out of the device.

Figure 11. Multiple 8-Bit Word SPI Communication register; and the remaining four bits, D3 : D0, are used to configure and control the output and its protection features. summarizes the SI registers. The registers are addressed via D6 : D4 of the incoming SPI word (Table 9). Table 9. SI Message Bit Assignment D6 : D4 Register address bits. features and SO status content. features and SO status content. Table 10. Serial Input Address and Configuration Bit Map

  1. R STB i s i n a l ogi c 1 st at e dur i ng t he above oper at i on.
  2. O D0, O D1, O D2, . . . , and O D7 r epr esent t he f i r st 8 bi t s of or der ed f aul t and st at us dat a out of t he SPSS
  3. RST is a logic [1] state during the above operation.
  4. D7:D0 relate to the most recent or dered entry of data into the device.
  5. OD7:OD0 relate to the first 8 bits of ordered fault and status data out of the device.
  6. D7*:D0* relate to the previous 8 bits (last command word) of data that was previously shifted into the device.

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The following section describes the possible register addresses and their impact on device operation. Sense (CSNS) pin. Bits D2 and D3 must be logic [0]. Bit D7 is used to feed the watchdog if enabled. protecting the device, this slow blow fuse emulation feature can be used to optimize the load requirements to match system characteristics. the overcurrent high detection level to one of two levels as defined in Table 12. apply only to the overcurrent low detection levels. If the selected overcurrent high level is reached, the device latchs off within 20 s. Table 11. Overcurrent Low Detection Levels Table 12. Overcurrent High Detection Levels Table 13. Overcurrent Low Detection Blanking Time

message bits when addressing the OCR register. configured SPI bit can now be used to enable and disable the common PWM signal from controlling its assigned output. for the time delay configured in the OSDR register. switching delay times, which range from 0 ms to 525 ms. ensure that the new timeout period is programmed at the beginning of a new count sequence. continues to be reset while no programming or data readback functions are being requested from the device. Table 14. Switching Delay Table 15. Watchdog Timeout

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active. When disabled, an undervoltage or overvoltage condition fault is not reported in bits D1 and D0 of the output fault register. The TEST register is reserved for test and is not accessible with SPI during normal operation. upon the previously written SPI word. first transitioned to a logic [0]. This feature is useful for daisy chaining devices as well as message verification. register is now able to accept new fault status information.

  • The previous SPI communication was determined to be invalid. In this case, the status reports as though the invalid SPI communication never occurred.
  • Battery transients below 6.0 V resulting in an undervoltage shutdown of the outputs may result in incorrect data loaded into the status register. The SO data transmitted to the MCU during the first SPI communication following an undervoltage VPWR condition should be ignored.
  • T h e RST pin transition from a logic [0] to logic [1] while the WAKE pin is at logic [0] may result in incorrect data loaded into the status register. The SO data transmitted to the MCU during the first SPI communication following this condition should be ignored. SERIAL OUTPUT BIT ASSIGNMENT The eight bits of serial output data depend on the previous serial input message, as explained in the following paragraphs. Table 16 summarizes the SO register content. Bit OD7 reflects the state of the watchdog bit (D7) addressed during the prior communication. The contents of bits OD6 : OD0 depend upon the bits D2 : D0 from the most recent STATR command SOA2 : SOA0. Previous Address SOA[2:0] = 000 If the previous three MSBs are 000, bits OD6 : OD0 reflect the current state of the Fault register (FLTR) (Table 17).

Table 16. Serial Output Bit Map Descriptions

The data in bits OD1 and OD0 contain CSNS EN and IN_SPI programmed bits, respectively. contain the programmed overcurrent low detection levels (refer to Table 11). when the overcurrent detection timeout feature is active. OD3 reports whether the open load circuitry is active. The returned data contain the programmed values in the DICR.

  • SOA3 = 0. The returned data contain the programmed values in the OSDR. Bit OD3 (FSM_HS) reflects the state of the output in the Fail-safe mode after a watchdog timeout occurs.
  • SOA3 = 1. The returned data contain the programmed values in the WDR. Bit OD2 (WDTO) reflects the status of the watchdog circuitry. If WDTO bit is logic [1], the watchdog has timed out and the device is in Fail-safe mode. If WDTO is logic [0], the device is in Normal mode (assuming device is powered and not in the Sleep mode), with the watchdog either enabled or disabled. Previous Address SOA[2:0] =110
  • SOA3 = 0. OD2, OD1, and OD0 return the state of the IN, FSI, and WAKE pins, respectively (Table 18).
  • SOA3 = 1. The returned data contains the programmed values in th e UOVR register. Bit OD1 reflects the state of the undervoltage protection, while bit OD0 reflects the state of the overvoltage protection (refer to Table 16). Previous Address SOA[2:0] = 111 Null Data. No previous register Read Back command received, so bits OD2, OD1, and OD0 are null, or 000.

Table 17. Fault Register OD6 (OTF) = Overtemperature Flag. OD1 (OVF) = Overvoltage Flag. OD0 (FAULT) = This flag reports a fault and is reset by a read operation. Table 18. Pin Register

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Figure 12. Typical Applications The loads must be chosen in order to guarantee the device normal operating condition for junction temperatures from -40 °C to 150 °C. external recirculation device must be used to maintain the device in its safe operating area.

  • AN3274, which proposes safe configurations of the eXtreme switch devices in case of application faults, and to protect all circuitry with minimum external components.
  • AN2469, which provides guidelines for prin ted circuit board (PCB) design and assembly. Development effort is required by the end users to optimize the board design and PCB layout, in order to reach electromagnetic compatibility standards (emission and immunity). A/D MCU I/O I/O SI SO SCLK I/O CS SO SI FS VDD FSI CSNS RST CS IN SCLK NC WAKE NC VPWR 33982 100nF 10µF VDD VDD GND HS HS VPWR VPWR 2.5µF 10nF LOAD RFS1k 10 k 10 k VDD Voltage Regulator VDD VPWR NC 10k 10k 10k 10k 10k

Analog Integrated Circuit Device Data Freescale Semiconductor 29 33982 PACKAGING SOLDERING INFORMATION PACKAGING SOLDERING INFORMATION SOLDERING INFORMATION The 33982 is packaged in a surface mount power package (PQFN), intended to be soldered directly on the printed circuit board. The AN2467 provides guidelines for Printed Circuit Board design and assembly. PACKAGE DIMENSIONS For the most current revision of the package, visit www.freescale.com and perform a keyword search on 98ARL10596D. Dimensions shown are provided for reference ONLY.

Analog Integrated Circuit Device Data

30 Freescale Semiconductor

Analog Integrated Circuit Device Data Freescale Semiconductor 31 33982 PACKAGING PACKAGE DIMENSIONS

32 Freescale Semiconductor

is provided in the datasheet. TJ2, and a thermal resistance matrix with RJAmn. while only heat source 1 is heating with P1. were obtained by measurement and simulation according to the standards listed below. Table 19. Thermal Performance Comparison

  1. Per JEDEC JESD51-2 at natura l convection, still air condition.
  2. 2s2p thermal test board per JEDEC JESD51-7and 
  3. Per JEDEC JESD51-8, with the board temperature on the center trace near the
  4. Single layer thermal test board per JEDEC JESD51-3 and JESD51-5.
  5. Thermal resistance between the die junc tion and the exposed pad, “infinite” heat

sink attached to exposed pad.

Figure 13. Surface Mount for Power PQFN Figure 14. Thermal Test Board

33982 Pin Connections

34 Freescale Semiconductor

heated. Index n refers to the number of the die where the junction temperature is sensed. Figure 15. Device on Thermal Test Board RJA Table 20. Device on Thermal Test Board Table 21. Thermal Resistance Performance

Figure 16. Transient Thermal Resistance RJA (1.0 W Step Response)

Analog Integrated Circuit Device Data

36 Freescale Semiconductor

REVISION HISTORY

REVISION DATE DESCRIPTION OF CHANGES 10.0 2/2006 • Implemented Revision History page

  • Deletion of MC33982 part number, replaced with MC33982B. 11.0 5/2006
  • Corrected Pin Connections to the proper case outline
  • Added final sentence to Open Load Fault (Non-Latching)
  • Corrected heading labels on Input Timing Switching Characteristics
  • Changed labels in the Typical Applications drawing
  • Corrected Package Dimensions to Revision C
  • Added Thermal Addendum (Rev 4.0). 12.0 1/2007 • Added RoHS logo to the data sheet 13.0 7/2007 • Added Functional Internal Block Description
  • Minor corrections to Serial Output Bit Map Descriptions and Device Behavior in Case of Undervoltage 14.0 6/2008 • Changed the labeling header on Dynamic Electrical Characteristics from 150 to 125 degrees C
  • Updated Freescale form and style 15.0 7/2009 • Added Current Sense Leakage to Static Electr ical Characteristics table (Table 3). 16.0 10/2009 • Added MC33982C to the ordering information
  • Added a Device Variations table 17.0 5/2012
  • Removed MC33982BPNA
  • Updated orderable part number from MC33982CPNA to MC33982CHFK
  • Updated (7)
  • Updated Soldering Information
  • Updated Freescale form and style 18.0 10/2012 • Made limit changes to Dynamic Electrical Characteristics min, typ, and max.
  • Corrected Orderable Part number information.
  • Updated Freescale form and style
  • Updated back page

Document Number: MC33982 Rev. 18.0 Information in this document is provided solely to enable system and software implementers to use Freescale products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. Freescale reserves the right to make changes without further notice to any products herein. Freescale makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including “typicals,” must be validated for each customer application by customer’s technical experts. Freescale does not convey any license under its patent rights nor the rights of others. Freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: freescale.com/SalesTermsandConditions. SMARTMOS is a trademark of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2014 Freescale Semiconductor, Inc. How to Reach Us: Home Page: freescale.com Web Support: freescale.com/support