MC33981 NXP | Alldatasheet
Document overview
- Manufacturer or author: NXP B.V.
- PDF pages: 51
Technical content
Features
- Single 4.0 m RDS(ON) maximum high side switch
- PWM capability up to 60 kHz with duty cycle from 5 % to 100 %
- Very low standby current
- Slew-rate control with external capacitor
- Over-current and over-temperature protection, under-voltage shutdown, and fault reporting
- Reverse battery protection
- Gate drive signal for external low side N-channel MOSFET with protection features
- Output current monitoring
- Temperature feedback
Figure 1. 33981 Simplified Application Diagram
ORDERING INFORMATION
(Add R2 Suffix for Tape and Reel) Temperature Range (TA) Package MC33981BHFK - 40 to 125 °C 16 PQFNMC33981ABHFK MC33981ADHFK Bottom View FK (Pb-Free Suffix) 98ARL10521D 16-PIN PQFN (12 X 12) 98ASA00815D VDD I/O I/O I/O I/O A/D A/D MCU CONF FS INLS EN INHS TEMP CSNS OCLS SR GND VPWR CBOOT OUT DLS GLS VDD M VPWR 33981
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Table 1. Device Peak Solder Temperature MC33981BHFK Original BOM and lower Peak Package Temperature solderability. MC33981ABHFK Improved BOM and higher Peak Package Temperature solderability. MC33981ADHFK Improved BOM and higher Peak Package Temperature solderability.
- PPT values can be found on NXP’s web site, or contact sales. Reference Peak Package Reflow Temperature
Figure 2. 33981 Simplified Internal Block Diagram
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Figure 3. Pin Connections Table 2. PIN DEFINITIONS Descriptions of the pins listed in the table below can be found in the Functional Description section located on page 16. microcontroller (MCU) to monitor output current. 2 TEMP Reports Temperature Feedback This pin is used by the MCU to monitor board temperature.
3 EN Input Enable
This pin is used to place the device in a low-current Sleep mode. 4 INHS Input Serial Input High Side This input pin is used to control the output of the device.
5 FS Reports Fault Status
This pin monitors fault conditions and is active LOW. 6 INLS Input Serial Input Low Side This pin is used to control an external low side N-channel MOSFET. 7 CONF Input Configuration Input This input manages MOSFET N-channel cross-conduction. 8 OCLS Input Low Side Overload This pin sets the VDS protection level of the external low side MOSFET. 9 DLS Input Drain Low Side This pin is the drain of the external low side N-channel MOSFET.
10 GLS Output Low Side Gate This output pin drives the gate of the external low side N-channel
11 SR Input Slew Rate Control This pin controls the output slew rate. 12 CBOOT Input Bootstrap Capacitor This pin provides the high pulse current to drive the device. 13 GND Ground Ground This is the ground pin of the device. 14 VPWR Input Positive Power Supply This pin is the source input of operational power for the device.
Analog Integrated Circuit Device Data (Preliminary) NXP Semiconductors 5 33981
ELECTRICAL CHARACTERISTICS
Table 3. Maximum Ratings All voltages are with respect to ground unless otherwise noted.
- Exceeding voltage limits on INHS, INLS, CONF, CSNS, FS, TEMP, and EN pins may cause a malfunction or permanent damage to the
- Continuous high side output rating as long as maximum junction temperature is not exceeded. Calculation of maximum output current
using package thermal resistance is required.
- ESD testing is performed in accordance with the Human Body Model (HBM) (C ZAP = 100 pF, RZAP = 1500 ) and the Charge Device
Model (CDM), Robotic (CZAP = 4.0 pF).
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- 40 to 125 - 40 to 150 Storage Temperature TSTG - 55 to 150 C Thermal Resistance(5) Junction to Power Die Case Junction to Ambient RJC RJA 1.0 30.0 C/W Peak Package Reflow Temperature During Reflow(6), (7) TPPRT Note 7 °C Notes 5. Device mounted on a 2s2p test board per JEDEC JESD51-2. 6. Pin soldering temperature limit is for 40 seconds maximum dur ation. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. 7. NXP’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), Go to www.nxp.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.
All voltages are with respect to ground unless otherwise noted.
Analog Integrated Circuit Device Data (Preliminary) NXP Semiconductors 7 33981 STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 4. Static Electrical Characteristics noted reflect the approximate parameter mean at TA = 25 C under nominal conditions, unless otherwise noted.
9.0 V < VPWR < 16 V
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STATIC ELECTRICAL CHARACTERISTICS Current Sense Ratio (CSR) Accuracy 9.0 V < VPWR < 16 V, CSNS < 4.5 V Output Current MC33981BHFK and M33981ABHFK 5.0 A
15 A, 20 A, and 30 A
5.0 A, 15 A, 20 A, and 30 A
CSR_ACC -20 -15 -25 Notes 8. OUT can be commanded fully on, PWM is avai lable at room. Low Side Gate driver is available. Protections and Diagnosis are not available. Min/max parameters are not guaranteed. 9. Source-Drain ON Resistance (Reverse Drain-to -Source ON Resistance) with negative polarity VPWR. POWER OUTPUT (VPWR) (continued) Current Sense Voltage Clamp I CSNS = 15 mA VCL(CSNS) 4.5 6.0 7.0 V Current Sense Leakage(10) I NHS = 1 with OUT opened of load or INHS = 0 ILEAK(CSNS) 0 13 17 Over-temperature Shutdown TSD 160 175 190 °C Over-temperature Shutdown Hysteresis(11) TSDHYS 5.0 – 20 C LOW SIDE GATE DRIVER (VPWR, VGLS, VOCLS) Low Side Gate Voltage VPWR = 6.0 V VPWR = 9.0 V VPWR = 13 V VPWR = 27 V VGLS 5.0 8.0 12.0 12.0 5.4 8.4 12.4 12.4 6.0 9.0 13.0 13.0 V Low Side Gate Sinked Current VGLS = 2.0 V, VPWR = 13 V I GLSNEG – 100 – mA Low Side Gate Sourced Current VGLS = 2.0 V, VPWR = 13 V I GLSPOS – 100 – mA Low Side Overload Detection Level versus Low Side Drain Voltage MC33981BHFK and M33981ABHFK MC33981ADHFK VDS_LS -50 -75 mV CONTROL INTERFACE (CONF, INHS, INLS, EN, OCLS) Input Logic High-voltage (CONF, INHS, INLS) VIH 3.3 – – V Input Logic Low-voltage (CONF, INHS, INLS) VIL – – 1.0 V Input Logic Voltage Hysteresis (CONF, INHS, INLS) VINHYS 100 600 1200 mV Input Logic Active Pull-down Current (INHS, INLS) IDWN 5.0 10 20 A Enable Pull-down Resistor (EN) RDWN 100 200 400 k Enable Voltage Threshold (EN) VEN 2.5 V Table 4. Static Electrical Characteristics (continued) noted reflect the approximate parameter mean at TA = 25 C under nominal conditions, unless otherwise noted.
Analog Integrated Circuit Device Data (Preliminary) NXP Semiconductors 9 33981 STATIC ELECTRICAL CHARACTERISTICS Input Clamp Voltage (EN) IEN < 2.5 mA VCLEN 7.0 – 14 V Input Forward Voltage (EN) VF(EN) -2.0 – -0.3 V Input Active Pull-up Current (OCLS) IOCLS p 50 100 200 A Input Active Pull-up Current (CONF) I CONF 5.0 10 20 A Notes 10. This parameter is achieved by the design characterization by measuring a statistically relevant sample size across process variations but not tested in production. 11. Parameter is guaranteed by process monitoring but is not production tested. noted reflect the approximate parameter mean at TA = 25 C under nominal conditions, unless otherwise noted.
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STATIC ELECTRICAL CHARACTERISTICS CONTROL INTERFACE (CONF, INHS, INLS, EN, OCLS) (continued) FS Tri-state Capacitance(12) CFS – – 20 pF FS Low-state Output Voltage IFS = -1.6 mA VFSL – 0.2 0.4 V Temperature Feedback TA = 25°C for VPWR = 14 V MC33981BHFK and M33981ABHFK MC33981ADHFK VTFEED 3.35 3.35 3.45 3.45 3.55 3.63 V Temperature Feedback Derating(12) DTFEED -8.5 -8.9 -9.3 mV/°C Notes 12. Parameter is guaranteed by process monitoring but is not production tested. noted reflect the approximate parameter mean at TA = 25 C under nominal conditions, unless otherwise noted.
Analog Integrated Circuit Device Data (Preliminary) NXP Semiconductors 11 33981 DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 5. Dynamic Electrical Characteristics noted reflect the approximate parameter mean at TA = 25 C under nominal conditions, unless otherwise noted.
- The MC33981 fully operates down to DC. To reset a latched Fault the INHS pin must go low for the “Time to reset Fault Diagno sis”
- Values for CBOOT=100 nF. Refer to Sleep Mode on page 17. Parameter is guaranteed by design and not production tested.
- Turn-ON delay time measured from rising edge of INHS that turns the output ON to V OUT = 0.5 V with RL= 5.0 resistive load.
- Turn-OFF delay time measured from falling edge of INHS that turns the output OFF to VOUT = VPWR -0.5 V with RL= 5.0 resistive load.
- The ratio is measured at V OUT = 50% VPWR without SR capacitor. The device is capable of 100% duty cycle.
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Figure 4. Time Delays Functional Diagrams Figure 5. Normal Mode, Cross-Conduction Management
Analog Integrated Circuit Device Data (Preliminary) NXP Semiconductors 13 33981 Figure 6. Normal Mode, Independent High Side and Low Side
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ELECTRICAL PERFORMANCE CURVES ELECTRICAL PERFORMANCE CURVES Figure 7. Typical RDS(ON) vs. Temperature at VPWR = 13 V Figure 8. Typical Sleep-state Supply Current vs. VPWR at 150 °C Figure 9. VOUT Rise Time vs. SR Capacitor From 10% to 90% of VOUT at 25 °C and VPWR = 13 V
Analog Integrated Circuit Device Data (Preliminary) NXP Semiconductors 15 33981 ELECTRICAL PERFORMANCE CURVES Figure 10. VOUT Fall Time vs. SR Capacitor From 10% to 90% of VOUT at 25 °C and VPWR = 13 V
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The 33981 is a high-frequency self-protected silicon 4.0 mRDS(ON) high side switch used to replace electromechanical relays, fuses, and discrete devices in power management applications. The 33981 can be controlled by pulse-width modulation (PWM) with a frequency up to 60 kHz. It is designed for harsh environments, and it includes self-recovery features. The 33981 is suitable for loads with high inrush current, as well as motors and all types of resistive and inductive loads. A dedicated parallel input is available for an external low side control with protection features and cross-conduction management. FUNCTIONAL PIN DESCRIPTIONS OUTPUT CURRENT MONITORING (CSNS) This pin is used to output a current proportional to the high side OUT current and is used externally to generate a ground-referenced voltage for the microcontroller (MCU) to monitor OUT current. TEMPERATURE FEEDBACK (TEMP) This pin reports an analog value proportional to the temperature of the GND flag (pin 13). It is used by the MCU to monitor board temperature. ENABLE [ACTIVE HIGH] (EN) This is an input used to place the device in a low-current Sleep Mode. This pin has an active passive internal pull- down. INPUT HIGH SIDE (INHS) The input pin is used to directly control the OUT. This input has an active internal pull-down current source and requires CMOS logic levels. FAULT STATUS (FS) This pin is an open drain-configured output requiring an external pull-up resistor to VDD (5.0 V) for fault reporting. When a device fault condition is detected, this pin is active LOW. INPUT LOW SIDE (INLS) This input pin is used to directly control an external low side N-channel MOSFET and has an active internal pull- down current source and requires CMOS logic levels. It can be controlled independently of the INHS depending of CONF pin. CONFIGURATION INPUT (CONF) This input pin is used to manage the cross-conduction between the internal high side N-channel MOSFET and the external low side N-channel MOSFET. The pin has an active internal pull-up current source. When CONF is at 0 V, the two MOSFETs are controlled independently. When CONF is at VDD 5.0 V, the two MOSFETs cannot be on at the same time. LOW SIDE OVERLOAD (OCLS) This pin sets the VDS protection level of the external low side MOSFET. This pin has an active internal pull-up current source. It must be connected to an external resistor. DRAIN LOW SIDE (DLS) This pin is the drain of the external low side N-channel MOSFET. Its monitoring allows protection features: low side short protection and V PWR short protection. LOW SIDE GATE (GLS) This pin is an output used to drive the gate of the external low side N-channel MOSFET. SLEW RATE CONTROL (SR) A capacitor connected between this pin and ground is used to control the output slew rate. BOOTSTRAP CAPACITOR (CBOOT) A capacitor connected between this pin and OUT is used to switch the OUT in PWM mode. GROUND (GND) This pin is the ground for the logic and analog circuitry of the device. POSITIVE POWER SUPPLY (VPWR) This pin connects to the positive power supply and is the source input of operational power for the device. The VPWR pin is a backside surface mount tab of the package. OUTPUT (OUT) Protected high side power output to the load. Output pins must be connected in parallel for operation.
charge of the bootstrap capacitor. GLS is at high or low level. Over-temperature faults force the TEMP pin to 0 V. [0] at the INHS pin for at least t RST(DIAG). When INHS goes to 0 V, CSNS goes to 5.0 V. owing to internal logic circuit. Table 6. Operating Modes Sleep x x x x x H L Device is in Sleep Mode. The OUT and low side gate are OFF. independently. The high side and the low side are both on. independently. The high side and the low side are both off. Normal H PWM H PWM PWM_bar H H Normal mode. Cross-conduction management is activated. PWM_bar = Opposite of pulse-width modulation signal.
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FUNCTIONAL DEVICE OPERATION PROTECTION AND DIAGNOSTIC FEATURES directly but rather its effects on the low side MOSFET. When VDLS > VOCLS, the GLS pin goes to 0 V and the OCLS internal current source is disconnected and OCLS goes to 0 V. The GLS pin and the OCLS pin are reset (and the fault is delatched) by a logic [0] at the INLS pin for at least t RST(DIAG). Figure 13 and Figure 14 illustrate the behavior in case of overload on the low side gate driver. When connected to an external resistor, the OCLS pin with its internal current source sets the VOCLS level. By changing the external resistance, the protection level can be adjusted depending on low side characteristics. A 33 k resistor gives a VDS level of 3.3 V typical. This protection circuitry measures the voltage between the drain of the low side (DLS pin) and the 33981 ground (GND pin). For this reason it is key that the low side source, the 33981 ground, and the external resistance ground connection are connected together in order to prevent false error detection due to ground shifts. The maximum OCLS voltage being 4.0 V, a resistor bridge on DLS must be used to detect a higher voltage across the low side. CONFIGURATION The CONF pin manages the cross-conduction between the internal MOSFET and the external low side MOSFET. With the CONF pin at 0 V, the two MOSFETs can be independently controlled. A load can be placed between the high side and the low side. With the CONF pin at 5.0 V, the two MOSFETs cannot be on at the same time. They are in half-bridge configuration as shown in the 33981 Simplified Application Diagram. If INHS and INLS are at 5.0 V at the same time, INHS has priority and OUT will be at VPWR. If INHS changes from 5.0 V to 0 V with INLS at 5.0 V, GLS will go to high state as soon as the VGS of the internal MOSFET is lower than 2.0 V typically. A half- bridge application could consist in sending PWM signal to the INHS pin and 5.0 V to the INLS pin with the CONF pin at 5.0 V. Figure 20, illustrates the simplified application diagram in the 33981 Simplified Application Diagram with a DC motor and external low side. The CONF and INLS pins are at 5.0 V. When INHS is at 5.0 V, current is flowing in the motor. When INHS goes to 0 V, the load current recirculates in the external low side. BOOTSTRAP SUPPLY Bootstrap supply provides current to charge the bootstrap capacitor through the VPWR pin. A short time is required after the application of power to the device to charge the bootstrap capacitor. A typical value for this capacitor is 100 nF. An internal charge pump allows continuous MOSFET drive. When the device is in the sleep mode, this bootstrap supply is off to minimize current consumption. HIGH SIDE GATE DRIVER The high side gate driver switches the bootstrap capacitor voltage to the gate of the MOSFET. The driver circuit has a low-impedance drive to ensure that the MOSFET remains OFF in the presence of fast falling dV/dt transients on the OUT pin. This bootstrap capacitor connected between the power supply and the CBOOT pin provides the high pulse current to drive the device. The voltage across this capacitor is limited to about 13 V typical. An external capacitor connected between pins SR and GND is used to control the slew rate at the OUT pin. Figure 9 and Figure 10 give VOUT rise and fall time versus different SR capacitors. LOW SIDE GATE DRIVER The low side control circuitry is PWM capable. It can drive a standard MOSFET with an RDS(ON) as low as 10.0 m at a frequency up to 60 kHz. The VGS is internally clamped at 12 V typically to protect the gate of the MOSFET. The GLS pin is protected against short by a local over-temperature sensor. THERMAL FEEDBACK The 33981 has an analog feedback output (TEMP pin) that provides a value in inverse proportion to the temperature of the GND flag (pin 13). The controlling microcontroller can “read” the temperature proportional voltage with its analog- to-digital converter (ADC). This can be used to provide real- time monitoring of the PC board temperature to optimize the motor speed and to protect the whole electronic system. TEMP pin value is V TFEED with a negative temperature coefficient of DTFEED. REVERSE BATTERY The 33981 survives the application of reverse battery voltage as low as -16 V. Under these conditions, the output’s gate is enhanced to decrease device power dissipation. No additional passive components are required. The 33981 survives these conditions until the maximum junction rating is reached. In the case of reverse battery in a half-bridge application, a direct current passes through the external freewheeling diode and the internal high side. As Figure 11 shows, it is essential to protect this power line. The proposed solution is an external N-channel low side with its gate tied to battery voltage through a resistor. A high side in the V PWR line could be another solution.
Figure 11. Reverse Battery Protection exceeding this pin’s maximum ratings.
- Over-temperature fault
- Over-current fault on OUT
- Overload fault on the external low side MOSFET The FS pin will return to logic [1] when the over temperature fault condition is removed. The two other faults are latched. MVPWR VDD VPWR MCU 33981 No current GND OUT Diode 10.0 k
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Table 7. Functional Truth Table in Fault Mode x x x L H L H L x x The 33981 is currently in Fault mode. x x x L L L H L x x The 33981 is currently in Fault mode. The OUT is OFF and GLS is at 0V. x H L L x L H x L x The 33981 is currently in Fault mode. [0] at INHS for at least t RST(DIAG). L L H x L L H x x L The 33981 is currently in Fault mode. and GND pin will pull OCLS pin to 0V.
Figure 12. Over-temperature on Output
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Figure 13. Overload on Low Side Gate Drive, Case 1 Figure 14. Overload on Low Side Gate Drive, Case 2
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Figure 17. Cross-Conduction with Low Side Figure 18. Over-temperature on OUT
Figure 19. Maximum Operating Frequency for SR Capacitor of 4.7 nF
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used for the freewheeling phase. Typical values for external capacitors and resistors are given. Figure 20. 33981 Typical Application Diagram electromagnetic emission are described. extended diagnostics, able to drive DC motors up to 60 kHz. (100 A typical) with an innovative over-current strategy. to facilitate closed-loop operation for motor speed control. protects the IC against high overload condition. Figure 21 illustrates the typical application diagram.
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- 0 . 1 5 MHz to 30 MHz: 1.0 m vertical monopole in vertical polarization.
- 3 0 MHz to 200 MHz: a biconical antenna used in vertical and horizontal polarization.
- 200 MHz to 1,000 MHz: a log-periodic antenna used in vertical and horizontal polarization.
Figure 24. Test Bench for Radiated Emission the load was 17 A continuous. 1000 F is connected between VPWR and GND. Figure 25. 33981 Initial Configuration Figure 26. Conducted Emission Test Setup
1 EUT (grounded locally if
8 Biconical antenna
2 Test harness – –
3 Load simulator (placement
10 High quality double-
4 Power supply (location
11 Bulkhead connector
5 Artificial Network (AN) 12 Measuring instrument
6 Ground plane (bonded to
13 RF absorber material
7 Low relative permittivity
14 Stimulation and monitoring
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Figure 31. Radiated Emission Test Set-up Figure 32. The enhanced board is in accordance with the Class 3 limits of the CISPR25 standard for radiated emission. Figure 32. Radiated Emission Spectrum for 33981 limits. The same method can be used with other PC boards. power management applications. extended diagnostics, able to drive DC motors up to 60 kHz. (100 A typical) with an innovative over-current strategy. to facilitate closed-loop operation for motor speed control. protects the IC against high overload condition. Figure 33 illustrates the typical application diagram. Figure 33. Typical Application Diagram
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Figure 36. Positive and Negative Slew Rate Figure 37. OUT switching vs. SR Capacitor where RDS(ON)_ls is the on resistance of the low side. Figure 38. The parameters to enter temperature, and thermal impedance. Figure 38. Excel Tool
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Figure 43. Junction Temperature vs. Duty Cycle
board. The AN2467 provides guidelines for Printed Circuit Board design and assembly. “98ASA00815D”. Dimensions shown are provided for reference ONLY. Table 8. Part keywords
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Analog Integrated Circuit Device Data (Preliminary) NXP Semiconductors 37 33981 PACKAGING PACKAGING DIMENSIONS
Analog Integrated Circuit Device Data (Preliminary)
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Analog Integrated Circuit Device Data (Preliminary) NXP Semiconductors 39 33981 PACKAGING DIMENSIONS
Analog Integrated Circuit Device Data (Preliminary)
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Analog Integrated Circuit Device Data (Preliminary) NXP Semiconductors 41 33981 PACKAGING DIMENSIONS
Analog Integrated Circuit Device Data (Preliminary)
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Analog Integrated Circuit Device Data (Preliminary) NXP Semiconductors 43 33981 PACKAGING DIMENSIONS
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Analog Integrated Circuit Device Data (Preliminary) NXP Semiconductors 45 33981 PACKAGING DIMENSIONS
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application, and packaging information is provided in the datasheet. TJ1 and TJ2, and a thermal resistance matrix with RJAmn. temperature while only heat source 1 is heating with P1. RJ21 and RJ22, respectively. The stated values are solely for a thermal performance comparison of one package to another in a standardized environment. values were obtained by measurement and simulation according to the standards listed below. Figure 44. Surface mount for power PQFN
12 MM X 12 MM
Table 9. Thermal Performance Comparison
- Per JEDEC JESD51-2 at natural convection, still air
- 2s2p thermal test board per JEDEC JESD51-7and
- Per JEDEC JESD51-8, with the board temperature on the
center trace near the power outputs.
- Single layer thermal test board per JEDEC JESD51-3 and
- Thermal resistance between the die junction and the
exposed pad, “infinite” heat sink attached to exposed pad.
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Figure 45. Thermal Test Board where the junction temperature is sensed.
33981 Pin Connections
Table 10. Thermal Resistance Performance
Figure 46. Device on Thermal Test Board RJA Figure 47. Transient Thermal Resistance RJA,
1 W Step response,Device on Thermal Test Board Area A = 600(mm2)
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REVISION HISTORY
Revision Date Description of Changes 3.0 1/2006 • Implemented Revision History page
- Made content updates and changes
- Converted to Freescale format
- Added Thermal Addendum 4.0 3/2006 • Made minor content changes to pages 6 and 7.
- Updated to Product Preview status 5.0 5/2006 • Changed Part Number from PC33981PNA to MC33981BPNA in the ordering information
- Changed Electrical Characteristics, Maximum Ra tings, Table 2, Maximum Ratings, Electrical
- Changed Electrical Characteristics, Static Electric al Characteristics, Table 3, Static Electrical Characteristics, Low Side Gate Driver (VPWR, VGLS, VOCLS), Low-Side Overload Detection Level versus Low-Side Drain Voltage Minimum, from “-75” to “-50” and Maximum from “+75” to “+50” (page 8).
- Changed Electrical Characteristics, Dynamic Electrical Characteristics, Table 4, Dynamic Electrical Characteristics, Control Interface and Power Output Timing (CBOOT, VPWR), Input Switching Frequency, Minimum from “20” to “-” and Typical from “-” to “20” (page 11).
- Updated to Advanced status 6.0 5/2007 • Changed CSNS Input Clamp Current in MAXIMUM RATINGS
- Changed Figure 11, Reverse Battery Protection
- Removed unnecessary line in Figure 14, Overload on Low Side Gate Drive, Case 2
- Corrected label in Figure 28, 33981 with Filter 7.0 10/2008 • Updated Freescale form and style
- Minor text corrections.
- Added Current Sense Leakage(10) 8.0 6/2009 • Corrected Reference to Figure 15 on page 13. 9.0 10/2010 • Reworded Notes 5 and 11. 10.0 5/2012 • Updated Orderable part number from MC33981BPNA to MC33981BHFK
- Updated (6)
- Updated soldering information
- Updated Freescale form and style 11.0 7/2012 • Added MC33981ABHFK to the ordering information
- Added Device Variations table 12.0 7/2023 • Updated under CIN 202306024I
- Added package outline drawing number 98ASA00815D under Bottom View and part number MC33981ADHFK to the ordering information on page 1.
- Device Variations, Device Peak Solder Temperature, Table 1: Added part number on page 2.
- Electrical characteristics, Ma ximum ratings, Table 3, footnote [7]: Changed “Freescale’s Package
- Static Electrical Characte ristics, Static Electrical Characteristics, Table 4: Added two rows for part numbers, MC33981BHFK and M33981ABHFK, and MC33981ADHFK, and associated Min/Typ/ Max values, throughout, on pages 7, 8, and 9.
- Dynamic Electrical Characteristic s, Dynamic Electrical Characteristics, Table 5: Added two rows for part numbers, MC33981BHFK and M33981ABHFK, and MC33981ADHFK, and associated Min/ Typ/Max values, throughout, on page 10.
- Added Table 8 to page 35.
- Removed text below Mechanical Outline figures of pages 36 and 37.
- Added figures for 98ASA00815D package dimensions.
- Changed “www.freescale.com” to “www.nxp.com”, added “and "98ASA00815D”, added Table in Packaging, Packaging Dimensions on page 36.
- Added package outline drawing number 98ASA00815D and “and 98ASA00815D” to the Note on page 47.
Document Number: MC33981 Rev. 12.0 Information in this document is provided solely to enable system and software implementers to use NXP products. There are no expressed or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. NXP reserves the right to make changes without further notice to any products herein. NXP makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does NXP assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation, consequential or incidental damages. "Typical" parameters that may be provided in NXP data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including "typicals," must be validated for each customer application by the customer's technical experts. NXP does not convey any license under its patent rights nor the rights of others. NXP sells products pursuant to standard terms and conditions of sale, which can be found at the following address: http://www.nxp.com/terms-of-use.html. NXP, the NXP logo, Freescale, the Freescale logo and SMARTMOS are trademarks of NXP Semiconductors B.V. All other product or service names are the property of their respective owners. All rights reserved. © NXP B.V. 2023. How to Reach Us: Home Page: NXP.com Web Support: http://www.nxp.com/support