33975

33975_V01 FREESCALE | Alldatasheet

Document overview

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• PDF pages: 32

Technical content

Features

• Designed to operate from 5.5 V  V PWR  28 V
• Switch input voltage: (33975: - 14 to 38 V) (33975A: -14 to 40 V)
• Interfaces to microprocessor using 3.3 V/5.0 V SPI protocol
• Selectable wake-up on change of state
• 14 switch-to-ground inputs
• 8 programmable inputs (switches to battery or ground)
• Selectable wetting current (32 mA or 4.0 mA for switch-to-ground inputs)
• Sleep State current V PWR 100 A, VDD 20 A

Figure 1. 33975 Simplified Application Diagram

Applications

• Automotive systems
• Industrial control systems
• Process control systems
• Security systems
• Systems requiring switch status verification for safety, operation, or process control purposes VBAT SP0 SP1 SP7 SG0 SG1 SG12 SG13 VPWR VDD WAKE SI CS SO INT AMUX GND MOSI SCLK CS MISO INT AN0 33975 MCU SCLK POWER SUPPLY LVI ENABLE WATCHDOG RESET VDD VBAT VDD VBAT

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1 Orderable Parts

Table 1. Orderable Part Variations

Figure 2. 33975 Simplified Internal Block Diagram

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Figure 3. 33975 Pin Connections Table 2. Pin Definitions A functional description of each Pin can be found in the Functional Pin Description section on page 12.

1 GND Ground Ground for logic, analog, and switch-to-battery inputs

2 SI SPI Slave In SPI control data input pin from MCU to 33975

3 SCLK Serial Clock SPI control clock input pin

16 VPWR Battery Input Battery supply input pin. This pin requires external reverse battery protection.

17 WAKE Wake-up Open drain wake-up output is designed to control a power supply enable pin

29 INT Interrupt Open-drain output to MCU is used to indicate input switch change of state

30 AMUX Analog Multiplex Output Analog multiplex output

32 SO SPI Slave Out Provides digital data from 33975 to the MCU

Analog Integrated Circuit Device Data Freescale Semiconductor 5 33975

ELECTRICAL CHARACTERISTICS

Table 3. Maximum Ratings

1. ESD testing is performed in accord ance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 ), the Machine Model (CZAP =

200 pF, RZAP = 0 ), and the Charge Device Model.

1. All Programmable Switches (SP) and Switch-to- Ground (SG) input pins when tested individually.
2. Maximum power dissipation at T J =150 C junction temperature with no heatsink used.
3. Thermal resistance between the die and the exposed die pad.

Analog Integrated Circuit Device Data

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Between the die and the exposed die pad(4) RJA RJC 1.2 C/W Peak Package Reflow Temperature During Reflow(5), (6) TPPRT Note 6 °C Notes 5. Pin soldering temperature limit is for 10 seconds maximum durat ion. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. 6. Freescale’s Package Reflow capability meets Pb-free requirem ents for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.

Analog Integrated Circuit Device Data Freescale Semiconductor 7 33975 STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 4. Static Electrical Characteristics noted. Where applicable, typical values reflect the parameter’s approximate average value with VPWR = 13 V, TA = 25 C.

5.5 V  VPWR  28 V

8.0 V  VPWR  28 V

1. Thermal considerations must be ta ken when operating the device above 28 V.

Analog Integrated Circuit Device Data

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STATIC ELECTRICAL CHARACTERISTICS SWITCH INPUT (CONTINUED) Input Offset Current when Selected as Analog IOFFSET -2.0 1.4 2.0 A Input Offset Voltage when Selected as Analog V(SP&SGINPUTS) to AMUX output VOFFSET -10 2.5 10 mV Analog Operational Amplifier Output Voltage Sink 250 A VOL – 10 30 mV Analog Operational Amplifier Output Voltage Source 250 A VOH VDD - 0.1 – – V Switch Detection Threshold VTH 3.70 4.0 4.3 V Temperature Monitor(9), (10) TLIM 155 – 185 C Temperature Monitor Hysteresis(10) TLIM(HYS) 5.0 10 15 C Notes 9. Thermal shutdown of 16mA and 32mA pull-up and pull-down current sources only. 4.0mA and 2.0mA current source/sink and all other functions remain active. 10. This parameter is guaranteed by design; however it is not production tested. Table 4. Static Electrical Characteristics (continued) noted. Where applicable, typical values reflect the parameter’s approximate average value with VPWR = 13 V, TA = 25 C.

Analog Integrated Circuit Device Data Freescale Semiconductor 9 33975 DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Input Logic High Voltage Thresholds(11) VIH 0.7 x VDD –V DD + 0.3 V Input Logic Low Voltage Thresholds(11) VIL GND - 0.3 – 0.2 x V DD V SCLK, SI, Tri-state SO Input Current

0.0 V to VDD

ISCLK, ISI, ISO(TRI) -10 – 10 CS Input Current CS = VDD ICS -10 – 10 CS Pull-up Current CS = 0.0 V ICS 30 – 100 SO High State Output Voltage ISO(HIGH) = -200 A VSO(HIGH) VDD - 0.8 – VDD V SO Low State Output Voltage ISO(HIGH) = 1.6 mA VSO(LOW) – – 0.4 V Input Capacitance on SCLK, SI, Tri-state SO(12) CIN – – 20 pF INT Internal Pull-up Current – 15 40 100 A INT Voltage INT = Open Circuit VINT(HIGH) VDD - 0.5 – VDD V INT Voltage IINT = 1.0 mA VINT(LOW) – 0.2 0.4 V WAKE Internal Pull-Up current IWAKE(PU) 20 40 100 A WAKE Voltage WAKE = Open Circuit VWAKE(HIGH) 4.0 4.3 5.3 V WAKE Voltage IWAKE = 1.0 mA VWAKE(LOW) – 0.2 0.4 V WAKE Voltage(12) Maximum Voltage Applied to WAKE Through External Pull-up VWAKE(MAX) – – 40 V Notes 11. Upper and lower logic threshol d voltage levels apply to SI, CS, and SCLK. 12. This parameter is guaranteed by desig n however, is not production tested. noted. Where applicable, typical values reflect the parameter’s approximate average value with VPWR = 13 V, TA = 25 C. Table 5. Dynamic Electrical Characteristics Characteristics noted under conditions of 3.0V  VDD  5.5V, 8.0V  VPWR  28V, -40C  TC  125C, unless otherwise noted. Where applicable, typical values reflect the parameter’s approximate average value with VPWR = 13 V, TA = 25C.

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DYNAMIC ELECTRICAL CHARACTERISTICS Pulse Wetting Current Time tPULSE(ON) 15 16 22 ms Interrupt Delay Time Normal Mode tINT-DLY – 5.0 16 Sleep Mode Switch Scan Time tSCAN 100 200 300 s Calibrated Scan Timer Accuracy Sleep Mode tSCAN TIMER – – 10 Calibrated Interrupt Timer Accuracy Sleep Mode tINT TIMER – – 10 DIGITAL INTERFACE TIMING(13) Required Low State Duration on VPWR for Reset(14) VPWR  0.2V tRESET – – 10 Falling Edge of CS to Rising Edge of SCLK Required Setup Time tLEAD 100 – – ns Falling Edge of SCLK to Rising Edge of CS Required Setup Time tLAG 50 – – ns SI to Falling Edge of SCLK Required Setup Time tSI(SU) 16 – – ns Falling Edge of SCLK to SI Required Hold Time tSI(HOLD) 20 – – ns SI, CS, SCLK Signal Rise Time(15) tR(SI) – 5.0 – ns SI, CS, SCLK Signal Fall Time(15) tF(SI) – 5.0 – ns Time from Falling Edge of CS to SO Low Impedance(16) tSO(EN) – – 55 ns Time from Rising Edge of CS to SO High Impedance(17) tSO(DIS) – – 55 ns Time from Rising Edge of SCLK to SO Data Valid(18) tVALID – 25 55 ns Notes 14. This parameter is guaranteed by design but not production tested. 15. Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing. 16. Time required for valid output status data to be available on the SO pin. 17. Time required for output states data to be terminated at the SO pin. 18. Time required to obtain valid data out from SO following the rise of SCLK with a 200pF load. Characteristics noted under conditions of 3.0V  VDD  5.5V, 8.0V  VPWR  28V, -40C  TC  125C, unless otherwise noted. Where applicable, typical values reflect the parameter’s approximate average value with VPWR = 13 V, TA = 25C.

Analog Integrated Circuit Device Data Freescale Semiconductor 11 33975 Figure 4. SPI Timing Characteristics Figure 5. Sleep Mode to Normal Mode Operation Figure 6. Normal Mode Interrupt Operation

0.7 VDD

0.2 VDD

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The 33975 device is an integrated circuit designed to provide systems with ultra-low quiescent sleep/wake-up modes and a robust interface between switch contacts and a microprocessor. The 33975 replaces many of the discrete components required when interfacing to microprocessor- based systems while providing switch ground offset protection, contact wetting current, and system wake-up. The 33975 features 8-programmable switch-to-ground or switch-to-battery inputs and 14 switch-to-ground inputs. All switch inputs may be read as analog inputs through the analog multiplexer (AMUX). Other features include a programmable wake-up timer, programmable interrupt timer, programmable wake-up/interrupt bits, and programmable wetting current settings. This device is designed primarily for automotive applications but may be used in a variety of other applications such as computer, telecommunications, and industrial controls. FUNCTIONAL PIN DESCRIPTION CHIP SELECT (CS) The system MCU selects the 33975 to receive communication using the chip select (CS) pin. With CS in a logic low state, command words may be sent to the 33975 via the serial input (SI) pin, and switch status information can be received by the MCU via the serial output (SO) pin. The falling edge of CS enables the SO output, latches the state of the INT pin, and the state of the external switch inputs. Rising edge of the CS initiates the following sequence: 1. Disables the SO driver (high-impedance) 2. INT pin is reset to logic [1], except when additional switch changes occur during CS low (see Figure 6, page 11). 3. Activates the received command word, allowing the 33975 to act upon new data from switch inputs. To avoid any spurious data, it is essential the high-to-low and low-to-high transitions of the CS signal occur only when SCLK is in a logic low state. A clean CS signal is needed to ensure no incomplete SPI words are sent to the device. Internal to the 33975 device is an active pull-up to VDD on CS. In Sleep Mode the negative edge of CS (VDD applied) will wake up the 33975 device. Data received from the device during CS wake-up may not be accurate. SERIAL CLOCK (SCLK) The system clock (SCLK) pin clocks the internal shift register of the 33975. The SI data is latched into the input shift register on the falling edge of SCLK signal. The SO pin shifts the switch status bits out on the rising edge of SCLK. The SO data is available for the MCU to read on the falling edge of SCLK. False clocking of the shift register must be avoided to ensure validity of data. It is essential the SCLK pin be in a logic low state whenever CS makes any transition. For this reason, it is recommended, though not necessary, that the SCLK pin is commanded to a low logic state as long as the device is not accessed and CS is in a logic high state. When the CS is in a logic high state, any signal on the SCLK and SI pin will be ignored and the SO pin is tri-state. SERIAL INPUT (SI) The SI pin is used for serial instruction data input. SI information is latched into the input register on the falling edge of SCLK. A logic high state present on SI will program a one in the command word on the rising edge of the CS signal. To program a complete word, 24 bits of information must be entered into the device. SERIAL OUTPUT (SO) The SO pin is the output from the shift register. The SO pin remains tri-stated until the CS pin transitions to a logic low state. All open switches are reported as a zero, all closed switches are reported as a one. The negative transition of CS enables the SO driver. The first positive transition of SCLK will make the status data bit 24 available on the SO pin. Each successive positive clock will make the next status data bit available for the MCU to read on the falling edge of SCLK. The SI/SO shifting of the data follows a first-in-first-out protocol, with both input and output words transferring the most significant bit (MSB) first. INTERRUPT OUTPUT (INT) The INT pin is an interrupt output from the 33975 device. The INT pin is an open-drain output with an internal pull-up to VDD. In Normal mode, a switch state change will trigger the INT pin (when enabled). The INT pin is latched on the falling edge of CS, and cleared on the rising edge of CS. The INT pin will not clear with rising edge of CS if a switch contact change has occurred while the CS was low. In a multiple 33975 device system with WAKE high and VDD in (Sleep mode), the falling edge of INT will place all 33975s in Normal mode. WAKE INPUT (WAKE) The WAKE pin is an open-drain output and a wake-up input. The pin is designed to control a power supply Enable pin. In the Normal mode, the WAKE pin is low. In the Sleep mode, the WAKE pin is high. The WAKE pin has a pull-up to the internal +5.0 V supply.

Analog Integrated Circuit Device Data Freescale Semiconductor 13 33975 FUNCTIONAL DESCRIPTIONS FUNCTIONAL PIN DESCRIPTION In Sleep mode with the WAKE pin high, the falling edge of WAKE will place the 33975 in Normal mode. In Sleep mode with VDD applied, the INT pin must be high for a negative edge of WAKE to wake up the device. If VDD is not applied to the device in Sleep mode, INT does not affect the WAKE operation. LOAD SUPPLY VOLTAGE (VPWR) The VPWR pin is battery input and Power-ON Reset to the 33975 IC. The VPWR pin requires external reverse battery and transient protection. The maximum input voltage on V PWR is 50 V. All wetting, sustain, and internal logic current is provided from the VPWR pin. LOGIC VOLTAGE (VDD) The VDD input pin is used to determine logic levels on the microprocessor interface (SPI) pins. Current from VDD is used to drive the SO output, and the pull-up current for CS and INT pins. VDD must be applied for a wake-up from the negative edge of CS or INT. GROUND (GND) The GND pin provides ground for the IC as well as ground for inputs programmed as switch-to-battery inputs. PROGRAMMABLE SWITCHES (SP0–SP7) The 33975 device has 8 switch inputs capable of being programmed to read switch-to-ground or switch-to-battery contacts. The input is compared with a 4.0 V reference. When programmed to be switch-to-battery, voltages greater than 4.0 V are considered closed. Voltages less than 4.0 V are considered open. The opposite holds true when inputs are programmed as switch-to-ground. Programming features are defined in Table 6 through Table 11 in the Functional Device Operation section of this datasheet beginning on page 16. Voltages greater than the VPWR supply voltage will source current through the SP inputs to the VPWR pin. Transient battery voltages greater than 38/40 V must be clamped by an external device. SWITCH-TO-GROUND (SG0–SG13) The SGn pins are switch-to-ground inputs only. The input is compared with a 4.0 V reference. Voltages greater than 4.0 V are considered open. Voltages less than 4.0 V are considered closed. Programming features are defined in Table 6 through Table 11 in the Functional Device Operation section of this datasheet beginning on page 16. Voltages greater than the VPWR supply voltage will source current through the SG inputs to the VPWR pin. Transient battery voltages greater than 38/40 V must be clamped by an external device.

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Figure 7. Functional Internal Block Description temperature monitor is active in the Normal Mode. (MCU) through a serial peripheral interface (SPI). of operation, Normal and Sleep. contacts. The input is compared with a 4.0 V reference. are programmed as switch-to-ground. sensors external to a module.

6.0 MHz may be used for programming and reading switch

illustrates the configuration between an MCU and one 33975. information between the 33975 and the MCU. Figure 8. SPI Interface with Microprocessor transfer data in/out of the ICs. Figure 9. SPI Parallel Interface with Microprocessor Figure 10. SPI Serial Interface with Microprocessor

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switch input or interrupt timer expires). and place the device in Normal mode.

• Programmable switch – Set to switch-to-battery
• All inputs set as wake-up
• Wetting current on (16 mA pull-down, 32 mA pull-up)
• Wetting current timer on (20 ms)
• All inputs tri-state
• Analog select 00000 (no input channel selected) Note The 33975 device provides indication that a reset has occurred by placing a logic [1] in bit 22 of the SO buffer. The reset bit is cleared on rising edge of CS. OPERATIONAL MODES The 33975 has two operating modes, Normal mode and Sleep mode. A discussion on Normal mode begins below. A discussion on Sleep Mode begins on page 21. NORMAL MODE Normal mode may be entered by the following events:
• Application of VPWR to the IC
• Change-of-switch state (when enabled)
• Falling edge of WAKE
• Falling edge of INT (with VDD = 5.0 V and WAKE at Logic [1])
• Falling edge of CS (with VDD = 5.0 V)
• Interrupt timer expires Only in Normal mode with VDD applied can the registers of the 33975 be programmed through the SPI. The registers that may be programmed in Normal mode are listed below. Further explanation of each register is provided in subsequent paragraphs.
• Programmable Switch Register (Settings Command)
• Wake-up/Interrupt Register (Wake-up/Interrupt Command)
• Wetting Current Register (Metallic Command)
• Wetting Current Timer Register (Wetting Current Timer Enable Command)
• Tri-state Register (Tri-state Command)
• Analog Select Register (Analog Command)
• Calibration of Timers (Calibration Command)
• Reset (Reset Command) Figure 6, page 11, is a graphical description of the device operation in Normal mode. Switch states are latched into the input register on the falling edge of CS. The INT to the MCU is cleared on the rising edge of CS. However, INT will not clear on the rising edge of CS if a switch has closed during SPI communication (CS low). This prevents switch states from being missed by the MCU. PROGRAMMABLE SWITCH REGISTER Inputs SP0 to SP7 may be programmable for switch-to- battery or switch-to-ground. These inputs types are defined using the settings command (refer to Table 6). To set an SPn input for switch-to-battery, a logic [1] for the appropriate bit must be set. To set an SPn input for switch-to-ground, a logic [0] for the appropriate bit must be set. The MCU may change or update the Programmable Switch Register via software at any time in Normal mode. Regardless of the setting, when the SPn input switch is closed a logic [1] will be placed in the Serial Output Response Register (refer to Table 17 , page 21).

Table 6. Settings Command

Figure 11. Contact Wetting and Sustain Current wetting current timer may be disabled for a specific input. Table 7. Wake-Up /Interrupt Command Table 8. Metallic Command

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Register via software at any time in Normal mode. will place the input as an analog input with high-impedance. Select Register via software at any time in Normal mode. Table 9. Wetting Current Timer Enable Command Table 10. Tri-state Command Table 11. Analog Command

Table 12. Analog Channel

00000 No Input Selected

00001 SG0

00010 SG1

00011 SG2

00100 SG3

00101 SG4

00110 SG5

00111 SG6

01000 SG7

01001 SG8

01010 SG9

01011 SG10

01100 SG11

01101 SG12

01110 SG13

01111 SP0

10000 SP1

10001 SP2

10010 SP3

10011 SP4

10100 SP5

10101 SP6

10110 SP7

Table 13. Calibration Command

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logic [0], closed switches are indicated with logic [1]. Table 14. Reset Command Table 15. SPI Command Summar

• Programmable switch – set to switch-to-ground
• All inputs set as wake-up
• Wetting current on (32 mA)
• Wetting current timer on (20 ms)
• All inputs tri-state-disabled (comparator is active)
• Analog select 00000 (no input channel selected) With the device programmed as above, an interrupt will be generated with each switch contact change of state (open-to- close or close-to-open) and 32mA of contact wetting current will be source for 20 ms. The INT pin will remain low until switch status is acknowledged by the microprocessor. It is critical to understand INT will not be cleared on the rising edge of CS if a switch closure occurs while the CS is low. The maximum duration a switch state change can exist without acknowledgement depends on the software response time to the interrupt. Figure 6, page 11, shows the interaction between changing input states and the INT and CS pins. If desired the user may disable interrupts (wake-up/interrupt command) from the 33975 device and read the switch states on a periodic basis. Switch activation and deactivation faster than the MCU read rate will not be acknowledged. The 33975 device will exit the Normal mode and enter the Sleep mode only with a valid sleep command. SLEEP MODE Sleep mode is used to reduce system quiescent currents. Sleep mode may be entered only by sending the sleep command. All register settings programmed in Normal mode will be maintained in Sleep mode. The 33975 will exit Sleep mode and enter Normal mode when any of the following events occur:
• Input switch change of state (when enabled)
• Interrupt timer expire
• Falling edge of WAKE
• Falling edge of INT (with VDD = 5.0 V and WAKE at Logic [1])
• Falling edge of CS (with VDD = 5.0 V)
• Power-on reset (POR) The VDD supply may be removed from the device during Sleep mode. However removing VDD from the device in Sleep mode will disable a wake-up from falling edge of INT and CS. Note: In cases where CS is used to wake the device, the first SO data message is not valid. The sleep command contains settings for two programmable timers for Sleep mode, the interrupt timer and the scan timer, as shown in Table 18.

Table 16. Serial Output (SO) Bit Data Table 17. Serial Output (SO) Response Register Table 18. Sleep Command

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disabled by programming the interrupt bits to logic [1 1 1]. the scan timer expires again. 33975 device exits Sleep mode and enters Normal mode. INT triggers the MCU to wake from Sleep state. Figure 12. Sleep Current Waveform

• Generate an interrupt.
• Force all wetting current s ources to revert to 2.0 mA/ 4.0 mA sustain currents
• Maintain the 2.0 mA/4.0 mA sustain currents and all other functionality.
• Set the thermal fl ag bit in the SPI output register. The thermal flag bit in the SPI word will be cleared on the rising edge of CS provided the die temperature has cooled below the thermal limit. When die temperature has cooled below thermal limit, the device will resume previously programmed settings.

Table 19. Interrupt Timer

111 No interrupt wake-up

Table 20. Scan Timer

000 No Scan

that allow the device to be used in a variety of applications.

• Sensor power supply
• Switch monitor for metallic or elastomeric switches
• Analog sensor inputs (Ratiometric)
• Power MOSFET/LED driver and monitor
• Multiple 33975 devices in a module system The following paragraphs describe the applications in detail. SENSOR POWER SUPPLY Each input may be used to supply current to sensors external to a module. Many sensors such as Hall effect, pressure sensors, and temperature sensors require a supply voltage to power the sensor, and provide an open collector or analog output. Figure 13 shows how the 33975 may be used to supply power and interface to these types of sensors. In an application where the input makes continuous transitions, consider using the wake-up/interrupt command to disable the interrupt for the particular input.

Figure 13. Sensor Power Supply switch may be achieved by paralleling SGn or SPn inputs. data stream will be logic [0].

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Figure 14. Analog Ratiometric Conversion represent the position of the sensor. calculated A/D conversion may be obtained. calibrated error correction factor. the drain-to-source voltage is approximately 1.0 V.

Figure 15. MOSFET or LED Driver Output

• wetting current timer enable command –Disable SPn wetting current timer (refer to Table 9, page 18).
• metallic command –Set SPn to 16/32 mA or 2.0/4.0 mA gate drive current (refer to Table 8, page 17).
• settings command –Set SPn as switch-to-battery (refer to Table 6, page 16).
• tri-state command –Disable tri-state for SPn (refer to Table 10, page 18). After the tri-state command has been sent (tri-state disable), the MOSFET gate will be pulled to ground. From this point forward the MOSFET may be turned on and off by sending the settings command:
• settings command –SPn as switch-to-ground (MOSFET ON).
• settings command –SPn as switch-to-battery (MOSFET OFF). Monitoring of the MOSFET drain in the OFF state provides open load detection. This is done by using an input comparator. With the SGn input in tri-state, the load will pull up the input to battery. With the load open, the SGn pin is pulled down to ground through an external resistor. The open load is indicated by a logic [1] in the SO data bit. The analog command may be used to monitor the drain voltage in the MOSFET ON state. By sourcing 4.0 mA of current to the 750 resistor, the analog voltage on the SGn pin will be approximately: As the voltage on the drain of the MOSFET increases, so does the voltage on the SGn pin. With the SGn pin selected as analog, the MCU may perform the A/D conversion. Using this method for controlling unclamped inductive loads is not recommended. Inductive fly-back voltages greater than V PWR may damage the IC. The SP0–SP7 pins of this device may also be used to send signals from one module to another. Operation is similar to the gate control of a MOSFET. For LED applications a resistor in series with the LED is recommended but not required. The switch-to-ground inputs are recommended for LED application. To drive the LED use the following commands:
• wetting current timer enable command –Disable SGn wetting current timer.
• metallic command –Set SGn to 32 mA. From this point forward the LED may be turned on and off using the tri-state command:
• tri-state command –Disable tri-state for SGn (LED ON).
• tri-state command –Enable tri-state for SGn (LED OFF). These parameters are easily programmed via SPI commands in Normal mode. Multiple 33975 Devices in a Module System Connecting power to the 33975 and the MCU for Sleep mode operation may be done in several ways. Table 21 shows several system configurations for power between the MCU and the 33975 and their specific requirements for functionality. Multiple 33975 devices may be used in a module system. SPI control may be done in parallel or serial. However when parallel mode is used, each device is addressed independently (refer to MCU Interface Description, page 15 SP0 SG0 SG13 32 4.0

4.0 V Ref +

Table 21. Sleep Mode Power Supply 5.0V 0V SPI wake-up is not possible. CS will put 33975 in Normal mode. 0V 0V SPI wake-up is not possible.

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Therefore, when sending the sleep command, one device will enter sleep before the other. For multiple devices in a system, it is recommended that the devices are controlled in serial (S0 from first device is connected to SI of second device). With two devices, 48 clock pulses are required to shift data in. When the WAKE feature is used to enable the power supply, both WAKE pins should be connected to the enable pin on the power supply. The INT pins may be connected to one interrupt pin on the MCU, or may have their own dedicated interrupt to the MCU. The transition from Normal to Sleep mode is done by sending the sleep command. With the devices connected in serial and the sleep command sent, both will enter Sleep mode on the rising edge of CS. When Sleep mode is entered, the WAKE pin will be logic [1]. If either device wakes up, the WAKE pin will transition low, waking the other device. A condition exists where the MCU is sending the sleep command (CS logic [0]) and a switch input changes state. With this event, the device that detects this input will not transition to Sleep mode, while the second device will enter Sleep mode. In this case, two switch status commands must be sent to receive accurate switch status data. The first switch status command will wake the device in Sleep mode. Switch status data may not be valid from the first switch status command because of the time required for the input voltage to rise above the 4.0 V input comparator threshold. This time is dependant on the impedance of SGn or SPn node. The second switch status command will provide accurate switch status information. It is recommended that the software wait 10 to 20 ms between the two switch status commands, allowing time for switch input voltages to stabilize. With all switch states acknowledged by the MCU, the sleep sequence may be initiated. All parameters for Sleep mode should be updated prior to sending the sleep command. The 33975 IC has an internal 5.0 V supply from the VPWR pin. A POR circuit monitors the internal 5.0 V supply. In the event of transients on the VPWR pin, an internal reset may occur. Upon reset the 33975 will enter Normal mode with the internal registers as defined in Table , page 20. Therefore it is recommended that the MCU periodically update all registers internal to the IC. USING THE WAKE FEATURE The 33975 provides a WAKE output and wake-up input designed to control an enable pin on system power supply. While in the Normal mode, the WAKE output is low, enabling the power supply. In the Sleep mode, the WAKE pin is high, disabling the power supply. The WAKE pin has a passive pull- up to the internal 5.0 V supply but may be pulled up through a resistor to VPWR supply (see Figure 17, page 27). When the WAKE output is not used the pin should be pulled up to the VDD supply through a resistor, as shown in Figure 16, page 27). During the Sleep mode, a switch closure will set the WAKE pin low, causing the 33975 to enter the Normal mode. The power supply will then be activated, supplying power to the VDD pin and the microprocessor and the 33975. The microprocessor can determine the source of the wake-up by reading the interrupt flag. COST AND FLEXIBILITY Systems requiring a significant number of switch interfaces have many discrete components. Discrete components on standard PWB consume board space and must be checked for solder joint integrity. An integrated approach reduces solder joints, consumes less board space, and offers wider operating voltage, analog interface capability, and greater interfacing flexibility.

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Important: For the most current revision of the package, visit www.freescale.com and perform a “keyword” search on the “98A” number listed below. EK SUFFIX 32-PIN EXPOSED PAD 98ASA10556D REVISION D

Analog Integrated Circuit Device Data Freescale Semiconductor 29 33975 PACKAGING PACKAGE DIMENSIONS (CONTINUED) PACKAGE DIMENSIONS (Continued) EK SUFFIX 32-PIN EXPOSED PAD 98ASA10556D REVISION D

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PACKAGE DIMENSIONS (CONTINUED) EK SUFFIX 32-PIN EXPOSED PAD 98ASA10556D REVISION D

Analog Integrated Circuit Device Data Freescale Semiconductor 31 33975

REVISION HISTORY

Revision Date Description of Changes 5.0 6/2007

• Implemented Revision History page
• Updated to Freescale form and style
• Added MCZ33975EK/R2 and MCZ33975AEK/R2
• Removed Peak Package Reflow Temperature During Reflow, and added Peak Package Reflow Temperature During Reflow (5), (6) 6.0 11/2007
• Removed MC33975AEK/R2 from the Ordering Information
• Replaced figures for 33975 Simplified Application Diagram, Power Supply Active in Sleep Mode, and Power Supply Shutdown in Sleep Mode.
• Adjusted ESD voltages for Human Body Model(2) and Applies to all non-input Pins.
• Updated document form and style. 7.0 2/2008 • Minor changes to text 8.0 8/2008 • Updated package drawing 9.0 8/2008 • Revised wording of Features on Page 1 - No parameter /technical changes. 10.0 8/2011
• Revised Ordering Information table by adding part numbers MC33975TEK/R2 and MC33975ATEK/R2, and removing part numbers MC33975EK/R2, MCZ33975EK/R2 and MCZ33975AEK/R2.
• Updated document form and style. 11.0 01/2014 • No technical changes. Revised back page. Updated document properties. Added SMARTMOS sentence to last paragraph.

Document Number: MC33975 Rev 11.0 Information in this document is provided solely to enable system and software implementers to use Freescale products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. Freescale reserves the right to make changes without further notice to any products herein. Freescale makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including “typicals,” must be validated for each customer application by customer’s technical experts. Freescale does not convey any license under its patent rights nor the rights of others. Freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: freescale.com/SalesTermsandConditions. SMARTMOS is a trademark of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2014 Freescale Semiconductor, Inc. How to Reach Us: Home Page: freescale.com Web Support: freescale.com/support