33975 FREESCALE | Alldatasheet
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Technical content
Features
Designed to Operate 5.5 V ≤ VPWR ≤ 28 V Switch Input Voltage Range -14 V to V PWR Interfaces Directly to Micr oprocessor Using 3.3 V/5.0 V SPI Protocol Selectable Wake-Up on Change of State Selectable Wetting Current (32 mA or 4.0 mA for switch-to-ground inputs) 8 Programmable Inputs (Switches to Battery or Ground) 14 Switch-to-Ground Inputs PWR Standby Current 100 µA Typical, VDD Standby Current 20 µA Typical Pb-free 32-terminal suffix EK Figure 1. 33975 Simplified Application Diagram
ORDERING INFORMATION
Range (TA) Package MC33975EK/R2 -40°C to 125°C 32 SOICW-EP PC33975AEK/R2 EK Suffix (Pb-Free) 98ARL10543D 32-TERMINAL SOICW EP 33975 33975A MULTIPLE SWITCH DETECTION INTERFACE WITH SUPPRESSED WAKE-UP 33975 VBAT VBAT SP0 SP1 SP7 SG0 SG1 SG12 SG13 VPWR VDD AMUX WAKE GND INT SO SI SCLK CS MCU AN0 INT MISO MOSI SCLK CS Power Supply LVI Watchdog Reset Enable VBAT VDD VDD
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Table 1. Device Variations
Figure 2. 33975 Simplified Internal Block Diagram
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Figure 3. 33975 Terminal Connections Table 2. Terminal Definitions A functional description of each terminal can be found in the Functional Terminal Description section on page 11. 1 GND Ground Ground for logic, analog, and switch-to-battery inputs. 2 SI SPI Slave In SPI control data input terminal from MCU to 33975. 3 SCLK Serial Clock SPI control clock input terminal. Programmable switch-to-battery or switch-to-ground input terminals. Switch-to-ground input terminals.
17 WAKE Wake-Up Open drain wake-up output is designed to control a power supply enable
29 INT Interrupt Open-drain output to MCU is used to indicate input switch change of state. 30 AMUX Analog Multiplex Output Analog multiplex output. 31 VDD Voltage Drain Supply 3.3/5.0 V supply sets SPI commu nication level for SO driver. 32 SO SPI Slave Out Provides digital data from 33975 to MCU.
Table 3. Maximum Ratings
- ESD testing is performed in acco rdance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω), the Machine Model (CZAP = 200
pF, RZAP = 0 Ω), and the Charge Device Model.
- All Programmable Switches (SP) and Switch-to-Gr ound (SG) input terminals when tested individually.
- Maximum power dissipation at T J =150°C junction temperature with no heatsink used.
- Thermal resistance between the die and the exposed die pad.
- Terminal soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits
may cause malfunction or permanent damage to the device.
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Table 4. Static Electrical Characteristics noted. Where applicable, typical values reflect the parameters approximate average value with VPWR = 13 V, TA = 25°C.
5.5 V ≤ VPWR ≤ 28 V
8.0 V ≤ VPWR ≤ 28 V
- Thermal considerations must be ta ken when operating the device above 28 V.
- Thermal shutdown of 16 mA and 32 mA pull-up and pull-down current sources only. 4.0 mA and 2.0 mA current source/sink and all
other functions remain active.
- This parameter is guaranteed by design; however it is not production tested.
Table 4. Static Electrical Characteristics (continued) noted. Where applicable, typical values reflect the parameters approximate average value with VPWR = 13 V, TA = 25°C.
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0.0 V to VDD
- Upper and lower logic threshol d voltage levels apply to SI, CS, and SCLK.
- This parameter is guaranteed by desig n however, is not production tested.
noted. Where applicable, typical values reflect the parameters approximate average value with VPWR = 13 V, TA = 25°C.
Table 5. Dynamic Electrical Characteristics noted. Where applicable, typical values reflect the parameters approximate average value with VPWR = 13 V, TA = 25°C.
- This parameter is guaranteed by design but not production tested.
- Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
- Time required for valid output status data to be available on SO terminal.
- Time required for output states data to be terminated at SO terminal.
- Time required to obtain valid data out from SO following the rise of SCLK with 200 pF load.
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Figure 4. SPI Timing Characteristics Figure 5. Sleep Mode to Normal Mode Operation Figure 6. Normal Mode Interrupt Operation
0.7 VDD
0.2 VDD
Analog Integrated Circuit Device Data Freescale Semiconductor 11 33975 FUNCTIONAL DESCRIPTIONS INTRODUCTION FUNCTIONAL DESCRIPTIONS INTRODUCTION The 33975 device is an integrated circuit designed to provide systems with ultra-low quiescent sleep/wake-up modes and a robust interface between switch contacts and a microprocessor. The 33975 replaces many of the discrete components required when interfacing to microprocessor- based systems while providing switch ground offset protection, contact wetting current, and system wake-up. The 33975 features 8-programmable switch-to-ground or switch-to-battery inputs and 14 switch-to-ground inputs. All switch inputs may be read as analog inputs through the analog multiplexer (AMUX). Other features include a programmable wake-up timer, programmable interrupt timer, programmable wake-up/interrupt bits, and programmable wetting current settings. This device is designed primarily for automotive applications but may be used in a variety of other applications such as computer, telecommunications, and industrial controls. FUNCTIONAL TERMINAL DESCRIPTION CHIP SELECT (CS) The system MCU selects the 33975 to receive communication using the chip select (CS) terminal. With the CS in a logic low state, command words may be sent to the 33975 via the serial input (SI) terminal, and switch status information can be received by the MCU via the serial output (SO) terminal. The falling edge of CS enables the SO output, latches the state of the INT terminal, and the state of the external switch inputs. Rising edge of the CS initiates the following operation: 1. Disables the SO driver (high impedance) 1. INT terminal is reset to logic [1], except when additional switch changes occur during CS low (see Figure 6, page 10). 1. Activates the received command word, allowing the 33975 to act upon new data from switch inputs. To avoid any spurious data, it is essential the high-to-low and low-to-high transitions of the CS signal occur only when SCLK is in a logic low state. Internal to the 33975 device is an active pull-up to VDD on CS. In Sleep mode the negative edge of CS (VDD applied) will wake up the 33975 device. Data received from the device during CS wake-up may not be accurate. SERIAL CLOCK (SCLK) The system clock (SCLK) terminal clocks the internal shift register of the 33975. The SI data is latched into the input shift register on the falling edge of SCLK signal. The SO terminal shifts the switch status bits out on the rising edge of SCLK. The SO data is available for the MCU to read on the falling edge of SCLK. False clocking of the shift register must be avoided to ensure validity of data. It is essential the SCLK terminal be in a logic low state whenever CS makes any transition. For this reason, it is recommended, though not necessary, that the SCLK terminal is commanded to a low logic state as long as the device is not accessed and CS is in a logic high state. When the CS is in a logic high state, any signal on the SCLK and SI terminals will be ignored and the SO terminal is tri-state. SERIAL INPUT (SI) The SI terminal is used for serial instruction data input. SI information is latched into the input register on the falling edge of SCLK. A logic high state present on SI will program a one in the command word on the rising edge of the CS signal. To program a complete word, 24 bits of information must be entered into the device. SERIAL OUTPUT (SO) The SO terminal is the output from the shift register. The SO terminal remains tri-stated until the CS terminal transitions to a logic low state. All open switches are reported as zero, all closed switches are reported as one. The negative transition of CS enables the SO driver. The first positive transition of SCLK will make the status data bit 24 available on the SO terminal. Each successive positive clock will make the next status data bit available for the MCU to read on the falling edge of SCLK. The SI/SO shifting of the data follows a first-in-first-out protocol, with both input and output words transferring the most significant bit (MSB) first. INTERRUPT OUTPUT (INT) The INT terminal is an interrupt output from the 33975 device. The INT terminal is an open-drain output with an internal pull-up to VDD. In Normal mode, a switch state change will trigger the INT terminal (when enabled). The INT terminal is latched on the falling edge of CS. and cleared on the rising edge of CS. The INT terminal will not clear with rising edge of CS if a switch contact change has occurred while CS was low. In a multiple 33975 device system with WAKE high and VDD on (Sleep mode), the falling edge of INT will place all 33975s in Normal mode.
Analog Integrated Circuit Device Data
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FUNCTIONAL TERMINAL DESCRIPTION WAKE INPUT (WAKE) The WAKE terminal is an open-drain output and a wake-up input. The terminal is designed to control a power supply Enable terminal. In the Normal mode, the WAKE terminal is low. In the Sleep mode, the WAKE terminal is high. The WAKE terminal has a pull-up to the internal +5.0 V supply. In Sleep mode with the WAKE terminal high, falling edge of WAKE will place the 33975 in Normal mode. In Sleep mode with VDD applied, the INT terminal must be high for negative edge of WAKE to wake up the device. If VDD is not applied to the device in Sleep mode, INT does not affect WAKE operation. LOAD SUPPLY VOLTAGE (VPWR) The VPWR terminal is battery input and Power-ON Reset to the 33975 IC. The VPWR terminal requires external reverse battery and transient protection. Maximum input voltage on VPWR is 50 V. All wetting, sustain, and internal logic current is provided from the VPWR terminal. LOGIC VOLTAGE (VDD) The VDD input terminal is used to determine logic levels on the microprocessor interface (SPI) terminals. Current from VDD is used to drive SO output and the pull-up current for CS and INT terminals. VDD must be applied for wake-up from negative edge of CS or INT. GROUND (GND) The GND terminal provides ground for the IC as well as ground for inputs programmed as switch-to-battery inputs. PROGRAMMABLE SWITCHES (SP0SP7) The 33975 device has 8 switch inputs capable of being programmed to read switch-to-ground or switch-to-battery contacts. The input is compared with a 4.0 V reference. When programmed to be switch-to-battery, voltages greater than 4.0 V are considered closed. Voltages less than 4.0 V are considered open. The opposite holds true when inputs are programmed as switch-to-ground. Programming features are defined in Table 6 through Table 11 in the Functional Device Operation section of this datasheet beginning on page 14. Voltages greater than the VPWR supply voltage will source current through the SP inputs to the VPWR terminal. Transient battery voltages greater than 38/40 V must be clamped by an external device. SWITCH-TO-GROUND (SG0SG13) The SGn terminals are switch-to-ground inputs only. The input is compared with a 4.0 V reference. Voltages greater than 4.0 V are considered open. Voltages less than 4.0 V are considered closed. Programming features are defined in Table 6 through Table 11 in the Functional Device Operation section of this datasheet beginning on page 14. Voltages greater than the VPWR supply voltage will source current through the SG inputs to the VPWR terminal. Transient battery voltages greater than 38/40 V must be clamped by an external device.
6.0 MHz may be used for programming and reading switch
illustrates the configuration between an MCU and one 33975. register on the falling edge of the chip select (CS) terminal. information between the 33975 and the MCU. Figure 7. SPI Interface with Microprocessor transfer data in/out of the ICs. Figure 8. SPI Parallel Interface with Microprocessor Figure 9. SPI Serial Interface with Microprocessor
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internal logic supply are generated from the VPWR terminal. driver, and pull-up current on INT and CS. switch input or interrupt timer expires). Reset and place the device in Normal mode. has occurred by placing a logic [1] in bit 22 of the SO buffer. The reset bit is cleared on rising edge of CS. Sleep mode. A discussion on Normal mode begins below. A discussion on Sleep Mode begins on page 20. of the 33975 be programmed through the SPI. provided in subsequent paragraphs. Table 6. Settings Command
software at any time in Normal mode. battery contact current, 16 mA and 2.0 mA (see Figure 10). software at any time in Normal mode. form on the switch contact surface. Figure 10. Contact Wetting and Sustain Current wetting current timer may be disabled for a specific input. will enable the wetting current timer (refer to Table 9). Table 7. Wake-Up /Interrupt Command Table 8. Metallic Command
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Register via software at any time in Normal mode. Table 9. Wetting Current Timer Enable Command Table 10. Tri-State Command
Table 11. Analog Command Table 12. Analog Channel
00000 No Input Selected
00001 SG0
00010 SG1
00011 SG2
00100 SG3
00101 SG4
00110 SG5
00111 SG6
01000 SG7
01001 SG8
01010 SG9
01011 SG10
01100 SG11
01101 SG12
01110 SG13
01111 SP0
10000 SP1
10001 SP2
10010 SP3
10011 SP4
10100 SP5
10101 SP6
10110 SP7
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should transition during this 512 µs calibration pulse. logic [0], closed switches are indicated with logic [1]. Table 15. SPI Command Summary Table 13. Calibration Command Table 14. Reset Command
00000000 XXXXXXXXXXXXXXXX
00000001 XXXXXXXX S P 7 S P 6 S P 5 S P 4 S P 3 S P 2 S P 1 S P 0
00000010 XXXXXXXX S P 7 S P 6 S P 5 S P 4 S P 3 S P 2 S P 1 S P 0
00000100 XXXXXXXX S P 7 S P 6 S P 5 S P 4 S P 3 S P 2 S P 1 S P 0
00000111 XXXXXXXX S P 7 S P 6 S P 5 S P 4 S P 3 S P 2 S P 1 S P 0
00001001 XXXXXXXX S P 7 S P 6 S P 5 S P 4 S P 3 S P 2 S P 1 S P 0
00001011 XXXXXXXXXXXXXXXX
00001100 XXXXXXXXXX i n t
Table 16. Serial Output (SO) Bit Data Table 17. Serial Output (SO) Response Register
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between changing input states and the INT and CS terminals. Sleep mode only with a valid sleep command. Sleep mode is used to reduce system quiescent currents. will be maintained in Sleep mode. first SO data message is not valid. interrupt is generated and the device enters Normal mode. disabled by programming the interrupt bits to logic [1 1 1]. command and may be set to 000 (no period) to 111 (64 ms). compared with the switch state prior to sleep command. page 15) is generated and the device enters Normal mode. until the scan timer expires again. Table 18. Sleep Command Table 19. Interrupt Timer
111 No interrupt wake-up
Table 20. Scan Timer
000 No Scan
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that allow the device to be used in a variety of applications. the interrupt for the particular input. Figure 12. Sensor Power Supply switch may be achieved by paralleling SGn or SPn inputs. a high contact resistance. Resistance of 1.0 kΩ is common. multiplexer connects a requested input to the AMUX terminal. corresponding bit in the next SO data stream will be logic [0]. ratiometric reading of variable resistive input.
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Figure 14. MOSFET or LED Driver Output wetting current timer (refer to Table 9, page 16). gate drive current (refer to Table 8, page 15). open load is indicated by a logic [1] in the SO data bit. similar to the gate control of a MOSFET. metallic command Set SGn to 32 mA. tri-state command Disable tri-state for SGn (LED ON).
4.0 V Ref +
Table 21. Sleep Mode Power Supply 5.0 V 0V SPI wake-up is not possible. 0V 0V SPI wake-up is not possible.
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Figure 15. Power Supply Active in Sleep Mode Figure 16. Power Supply Shutdown in Sleep Mode
Analog Integrated Circuit Device Data Freescale Semiconductor 27 33975 PACKAGE DIMENSIONS PACKAGE DIMENSIONS The silicon device is packaged in the 32 terminal SOIC with an exposed pad. The exposed pad is thermally conductive and electrically isolated to the die. It is recommended that the exposed pad be electrically connected to ground. Important: For the most current revision of the package, visit www.freescale.com and perform a keyword search on the 98A number listed below.
Analog Integrated Circuit Device Data
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PACKAGE DIMENSIONS (CONTINUED) PACKAGE DIMENSIONS (CONTINUED)
Analog Integrated Circuit Device Data Freescale Semiconductor 29 33975 PACKAGE DIMENSIONS (CONTINUED) PACKAGE DIMENSIONS (CONTINUED)
Analog Integrated Circuit Device Data
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Analog Integrated Circuit Device Data Freescale Semiconductor 31 33975 NOTES
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