33972T

33972_09 FREESCALE | Alldatasheet

Document overview

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• PDF pages: 32

Technical content

Features

• Designed to operate 5.5 V ≤ VPWR ≤ 26 V
• Switch input voltage range -14 V to VPWR, 40 V Max
• Interfaces directly to MPU using 3.3 V / 5.0 V SPI protocol
• Selectable wake-up on change of state
• Selectable wetting current (16 or 2.0 mA)
• 8 programmable inputs (switches to battery or ground)
• 14 switch-to-ground inputs
• Typical standby current - V PWR = 100 μA and VDD = 20 μA
• Active interrupt ( INT) on change-of-switch state
• Pb-free packaging designated by suffix code EW
• Exposed pad packaging designated by suffix code EK

Figure 1. 33972 Simplified Application Diagram

ORDERING INFORMATION

Range (TA) Package MC33972DWB/R2 -40°C to 125°C

32 SOICW

MCZ33972AEK/R2 32 SOICW EP 33972/A/T EK SUFFIX (Pb-FREE) 98ASA10556D 32-PIN SOICW EP VBAT SP0 SP1 SP7 SG0 SG1 SG12 SG13 VPWR VDD WAKE SI CS SO INT AMUX GND MOSI SCLK CS MISO INT AN0 33972 MCU SCLK POWER SUPPLY LVI ENABLE WATCHDOG RESET VDD VBAT VDD VBAT

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Table 1. Device Variations

Figure 2. 33972 Simplified Internal Block Diagram

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Figure 3. 33972 Pin Connections Table 2. 33972 Pin Definitions A functional description of each pin can be found in the Functional Pin Description section beginning on page 10. 1 GND Ground Ground Ground for logic, analog, and switch to battery inputs. 2 SI Input SPI Slave In SPI control data input pin from the MCU to the 33972. 3 SCLK Input Serial Clock SPI control clock input pin. allows data to be transferred in. Programmable switch-to-battery or switch-to-ground input pins. Switch-to-ground input pins. 30 AMUX Output Analog Multiplex Output Analog multiplex output. 31 VDD Input Voltage Drain Supply 3.3 / 5.0V supply. Sets SPI communication level for the SO driver. 32 SO Output SPI Slave Out Provides digital data from the 33972 to the MCU. the exposed pad unterminated (floating).

Analog Integrated Circuit Device Data Freescale Semiconductor 5 33972

ELECTRICAL CHARACTERISTICS

Table 3. Maximum Ratings permanent damage to the device.

1. Exceeding these limits may cause malf unction or permanent damage to the device.
2. ESD data available upon request.
3. ESD1 testing is performed in accordance with the Human Body Model (C ZAP = 100 pF, RZAP = 1500 Ω), and ESD2 testing is performed

in accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 Ω).

1. Maximum power dissipation at T J = 150°C junction temperature with no heat sink used.
2. Pin soldering temperature limit is for 10 seconds maximum dura tion. Not designed for immersion soldering. Exceeding these limits may

cause malfunction or permanent damage to the device.

1. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow

and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.

Analog Integrated Circuit Device Data

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STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 4. Static Electrical Characteristics noted.(7) Where applicable, typical values reflect the parameter’s approximate average value with VPWR = 13 V, TA = 25°C.

1. T C is the TCASE of the package
2. Device operational. Table paramet ers may be out of specification.
3. Thermal shutdown of 16 mA pull-up and pulldown current sources only. 2.0 mA current source / sink and all other functions remain active.
4. This parameter is guaranteed by design but is not production tested.

Analog Integrated Circuit Device Data Freescale Semiconductor 7 33972 STATIC ELECTRICAL CHARACTERISTICS DIGITAL INTERFACE Input Logic Voltage Thresholds(11) VINLOGIC 0.8 – 2.2 V SCLK, SI, Tri-state SO Input Current

0 V to VDD

ISCLK, ISI, ISO (TRI) -10 – 10 μA CS Input Current CS = VDD ICS -10 – 10 μA CS Pull-up Current CS = 0 V ICS 30 – 100 μA SO High-state Output Voltage I SO (HIGH) = -200 μA VSO (HIGH) VDD -0.8 – VDD V SO Low-state Output Voltage I SO (HIGH) = 1.6mA VSO (LOW) – – 0.4 V Input Capacitance on SCLK, SI, Tri-state SO(12) CIN – – 20 pF INT Internal Pull-up Current – 15 40 100 μA INT Voltage INT = Open Circuit V INT (HIGH) VDD -0.5 – VDD V INT Voltage I INT = 1.0 mA V INT (LOW) – 0.2 0.4 V WAKE Internal Pull-up Current I WAKE (PU) 20 40 100 μA WAKE Voltage WAKE = Open Circuit V WAKE (HIGH) 4.0 4.3 5.3 V WAKE Voltage I WAKE = 1.0 mA V WAKE(LOW) – 0.2 0.4 V WAKE Voltage Maximum Voltage Applied to WAKE Through External Pull-up V WAKE(MAX) – – 40 V Notes 11. Upper and lower logic threshold voltage levels apply to SI, CS, and SCLK. 12. This parameter is guaranteed by design but is not production tested. Table 4. Static Electrical Characteristics (continued) noted.(7) Where applicable, typical values reflect the parameter’s approximate average value with VPWR = 13 V, TA = 25°C.

Analog Integrated Circuit Device Data

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DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 5. Dynamic Electrical Characteristics noted. Where applicable, typical values reflect the parameter’s approximate average value with VPWR = 13 V, TA = 25°C.

1. This parameter is guaranteed by design but not production tested.
2. Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
3. Time required for valid output status data to be available on SO pin.
4. Time required for output states data to be terminated at SO pin.
5. Time required to obtain valid data out from SO following the rise of SCLK with 200 pF load.

Analog Integrated Circuit Device Data Freescale Semiconductor 9 33972 Figure 4. SPI Timing Characteristics Figure 5. Sleep Mode to Normal Mode Operation Figure 6. Normal Mode Interrupt Operation

0.7 VDD

0.2 VDD

Analog Integrated Circuit Device Data

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The 33972 device is an integrated circuit designed to provide systems with ultra-low quiescent sleep / wake-up modes, and a robust interface between switch contacts and a microprocessor. The 33972 replaces many of the discrete components required when interfacing to microprocessor- based systems, while providing switch ground offset protection, contact wetting current, and a system wake-up. The 33972 features 8-programmable switch-to-ground or switch-to-battery inputs and 14 switch-to-ground inputs. All switch inputs may be read as analog inputs through the analog multiplexer (AMUX). Other features include a programmable wake-up timer, programmable interrupt timer, programmable wake-up /interrupt bits, and programmable wetting current settings. This device is designed primarily for automotive applications, but may be used in a variety of other applications such as computer, telecommunications, and industrial controls. FUNCTIONAL PIN DESCRIPTION CHIP SELECT (CS) The system MCU selects the 33972 to receive communication using the chip select (CS) pin. With the CS in a logic LOW state, command words may be sent to the 33972 via the serial input (SI) pin, and switch status information can be received by the MCU via the serial output (SO) pin. The falling edge of CS enables the SO output, latches the state of the INT pin, and the state of the external switch inputs. Rising edge of the CS initiates the following operation: 1. Disables the SO driver (high-impedance) 2. INT pin is reset to logic [1], except when additional switch changes occur during CS LOW. (See Figure 6 on page 9.) 3. Activates the received command word, allowing the 33972 to act upon new data from switch inputs. To avoid any spurious data, it is essential the HIGH-to- LOW and LOW-to-HIGH transitions of the CS signal occur only when SCLK is in a logic LOW state. A clean CS is needed to ensure no incomplete SPI words are sent to the device. Internal to the 33972 device is an active pull-up to VDD on CS. In Sleep mode, the negative edge of CS (VDD applied) will wake up the 33972 device. Data received from the device during CS wake-up may not be accurate. SYSTEM CLOCK (SCLK) The system clock (SCLK) pin clocks the internal shift register of the 33972. The SI data is latched into the input shift register on the falling edge of SCLK signal. The SO pin shifts the switch status bits out on the rising edge of SCLK. The SO data is available for the MCU to read on the falling edge of SCLK. False clocking of the shift register must be avoided to ensure validity of data. It is essential the SCLK pin be in a logic LOW state whenever CS makes any transition. For this reason, it is recommended, that the SCLK pin is commanded to a logic LOW state as long as the device is not accessed and CS is in a logic HIGH state. When the CS is in a logic HIGH state, any signal on the SCLK and SI pins will be ignored and the SO pin is tri-state. SPI SLAVE IN (SI) The SI pin is used for serial instruction data input. SI information is latched into the input register on the falling edge of SCLK. A logic HIGH state present on SI will program a one in the command word on the rising edge of the CS signal. To program a complete word, 24 bits of information must be entered into the device. SPI SLAVE OUT (SO) The SO pin is the output from the shift register. The SO pin remains tri-stated until the CS pin transitions to a logic LOW state. All open switches are reported as zero, all closed switches are reported as one. The negative transition of CS enables the SO driver. The first positive transition of SCLK will make the status data bit 24 available on the SO pin. Each successive positive clock will make the next status data bit available for the MCU to read on the falling edge of SCLK. The SI / SO shifting of the data follows a first-in, first-out protocol, with both input and output words transferring the most significant bit (MSB) first. iNTERRUPT (INT) The INT pin is an interrupt output from the 33972 device. The INT pin is an open-drain output with an internal pull-up to VDD. In Normal mode, a switch state change will trigger the INT pin (when enabled). The INT pin and INT bit in the SPI register are latched on the falling edge of CS. This permits the MCU to determine the origin of the interrupt. When two 33972 devices are used, only the device initiating the interrupt will have the INT bit set. The INT pin is cleared on the rising edge of CS. The INT pin will not clear with rising edge of CS if a switch contact change has occurred while CS was LOW. In a multiple 33972 device system with WAKE HIGH and VDD in (Sleep Mode), the falling edge of INT will place all 33972s in Normal mode.

Analog Integrated Circuit Device Data Freescale Semiconductor 11 33972 FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION WAKE-UP (WAKE) The WAKE pin is an open-drain output and a wake-up input. The pin is designed to control a power supply Enable pin. In the Normal mode, the WAKE pin is LOW. In the Sleep mode, the WAKE pin is HIGH. The WAKE pin has a pull-up to the internal + 5.0 V supply. In Sleep mode with the WAKE pin HIGH, the falling edge of WAKE will place the 33972 in Normal mode. In Sleep mode with VDD applied, the INT pin must be HIGH for negative edge of WAKE to wake up the device. If VDD is not applied to the device in Sleep mode, INT does not affect WAKE operation. BATTERY INPUT (VPWR) The VPWR pin is battery input and Power-ON Reset to the 33972 IC. The VPWR pin requires external reverse battery and transient protection. Maximum input voltage on VPWR is 50 V. All wetting, sustain, and internal logic current is provided from the VPWR pin. VOLTAGE DRAIN SUPPLY (VDD) The VDD input pin is used to determine logic levels on the microprocessor interface (SPI) pins. Current from VDD is used to drive SO output and the pull-up current for CS and INT pins. VDD must be applied for wake-up from negative edge of CS or INT. GROUND (GND) The GND pin provides ground for the IC as well as ground for inputs programmed as switch-to-battery inputs. PROGRAMMABLE SWITCHES (SP0 : SP7) The 33972 device has 8 switch inputs capable of being programmed to read switch-to-ground or switch-to-battery contacts. The input is compared with a 4.0 V reference. When programmed to be switch-to-battery, voltages greater than 4.0 V are considered closed. Voltages less than 4.0 V are considered open. The opposite holds true when inputs are programmed as switch-to-ground. Programming features are defined in Table 6 through Table 11 in the Functional Device Operation section of this datasheet beginning on page 13. Voltages greater than the VPWR supply voltage will source current through the SP inputs to the VPWR pin. Transient battery voltages greater than 38/40 V must be clamped by an external device. SWITCH-TO-GROUND INPUTS (SG0 : SG13) The SGn pins are switch-to-ground inputs only. The input is compared with a 4.0 V reference. Voltages greater than 4.0 V are considered open. Voltages less than 4.0 V are considered closed. Programming features are defined in Table 6 through Table 11 in the Functional Device Operation section of this datasheet beginning on page 13. Voltages greater than the VPWR supply voltage will source current through the SG inputs to the VPWR pin. Transient battery voltages greater than 40 V must be clamped by an external device.

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Figure 7. Functional Internal Block Description temperature monitor is active in the Normal mode. (MCU) through a serial peripheral interface (SPI). of operation, Normal and Sleep. are programmed as switch-to-ground. current to sensors external to a module.

6.0 MHz may be used for programming and reading switch

illustrates the configuration between an MCU and one 33972. information between the 33972 and the MCU. Figure 8. SPI Interface with Microprocessor transfer data in / out of the ICs. Figure 9. SPI Parallel Interface with Microprocessor Figure 10. SPI Serial Interface with Microprocessor

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LOW, switch input or interrupt timer expires). and place the device in Normal mode.

• Programmable switch – set to switch to battery
• All inputs set as wake-up
• Wetting current on (16 mA)
• Wetting current timer on (20 ms)
• All inputs tri-state
• Analog select 00000 (no input channel selected) NORMAL AND SLEEP MODES The 33972 has two operating modes, Normal mode and Sleep mode. A discussion on Normal mode begins below. A discussion on Sleep mode begins on page 19. Normal Mode Normal mode may be entered by the following events:
• Application of V PWR to the IC
• Change-of-switch state (when enabled)
• Falling edge of WAKE
• Falling edge of INT (with VDD = 5.0 V and WAKE at Logic [1])
• Falling edge of CS (with VDD = 5.0 V)
• Interrupt timer expires Only in Normal mode with VDD applied can the registers of the 33972 be programmed through the SPI. The registers that may be programmed in Normal mode are listed below. Further explanation of each register is provided in subsequent paragraphs.
• Programmable Switch Register (Settings Command )
• Wake-Up / Interrupt Register (Wake-up / Interrupt Command )
• Wetting Current Register (Metallic Command )
• Wetting Current Timer Register (Wetting Current Timer Enable Command )
• Tri-State Register (Tri-state Command )
• Analog Select Register (Analog Command )
• Calibration of Timers (Calibration Command )
• Reset (Reset Command ) Figure 6, page 9, is a graphical description of the device operation in Normal mode. Switch states are latched into the input register on the falling edge of CS. The INT to the MCU is cleared on the rising edge of CS. However, INT will not clear on rising edge of CS if a switch has closed during SPI communication (CS LOW). This prevents switch states from being missed by the MCU. PROGRAMMABLE SWITCH REGISTER Inputs SP0 to SP7 may be programmable for switch-to- battery or switch-to-ground. These inputs types are defined using the settings command (Table 6). To set an SPn input for switch-to-battery, a logic [1] for the appropriate bit must be set. To set an SPn input for switch-to-ground, a logic [0] for the appropriate bit must be set. The MCU may change or update the programmable switch register via software at any time in Normal mode. Regardless of the setting, when the SPn input switch is closed a logic [1] will be placed in the serial output response register (Table 17, page 19). WAKE-UP / INTERRUPT REGISTER The wake-up / interrupt register defines the inputs that are allowed to wake the 33972 from Sleep Mode or set the INT pin LOW in Normal mode. Programming the wake-up / interrupt bit to logic [0] will disable the specific input from generating an interrupt and will disable the specific input from waking the IC in Sleep mode (Table 7). Programming the wake-up /interrupt bit to logic [1] will enable the specific input to generate an interrupt with switch change of state and will enable the specific input as wake-up. The MCU may change or update the wake-up / interrupt register via software at any time in Normal mode.

Table 6. Settings Command

form on the switch contact surface. Figure 11. Contact Wetting and Sustain Current disabled, power dissipation for the IC must be considered. will enable the wetting current timer (Table 9). Table 7. Wake-up / Interrupt Command Table 8. Metallic Command Table 9. Wetting Current Timer Enable Command

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place the input as an analog input with high-impedance. register via software at any time in Normal mode. Table 10. Tri-State Command Table 11. Analog Command

Table 12. Analog Channel

00000 No Input Selected

00001 SG0

00010 SG1

00011 SG2

00100 SG3

00101 SG4

00110 SG5

00111 SG6

01000 SG7

01001 SG8

01010 SG9

01011 SG10

01100 SG11

01101 SG12

01110 SG13

01111 SP0

10000 SP1

10001 SP2

10010 SP3

10011 SP4

10100 SP5

10101 SP6

10110 SP7

Table 13. Calibration Command

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[0], closed switches are indicated with logic [1]. Table 14. Reset Command Table 15. SPI Command Summary

• Programmable switch – set to switch-to-ground
• All inputs set as wake-up
• Wetting current on (16 mA)
• Wetting current timer on (20 ms)
• All inputs tri-state-disabled (comparator is active)
• Analog select 00000 (no input channel selected) With the device programmed as above, an interrupt will be generated with each switch contact change of state (open-to- close or close-to-open) and 16 mA of contact wetting current will be source for 20 ms. The INT pin will remain LOW until switch status is acknowledged by the microprocessor. It is critical to understand INT will not be cleared on the rising edge of CS if a switch closure occurs while CS is LOW. The maximum duration a switch state change can exist without acknowledgement depends on the software response time to the interrupt. Figure 6, page 9, shows the interaction between changing input states and the INT and CS pins. If desired the user may disable interrupts (wake up/ interrupt command) from the 33972 device and read the switch states on a periodic basis. Switch activation and deactivation faster than the MCU read rate will not be acknowledged. The 33972 device will exit the Normal mode and enter the Sleep mode only with a valid sleep command. SLEEP MODE Sleep mode is used to reduce system quiescent currents. Sleep mode may be entered only by sending the sleep command. All register settings programmed in Normal mode will be maintained in Sleep mode. The 33972 will exit Sleep mode and enter Normal mode when any of the following events occur:
• Input switch change of state (when enabled)
• Interrupt timer expire
• Falling edge of WAKE
• Falling edge of INT (with VDD = 5.0 V and WAKE at Logic [1])
• Falling edge of CS (with VDD = 5.0 V)
• Power-ON Reset (POR) The VDD supply may be removed from the device during Sleep mode. However removing VDD from the device in Sleep mode will disable a wake-up from falling edge of INT and CS. Note In cases where CS is used to wake the device, the first SO data message is not valid. The sleep command contains settings for two programmable timers for Sleep mode, the interrupt timer and the scan timer, as shown in Table 18 The interrupt timer is used as a periodic wake-up timer. When the timer expires, an interrupt is generated and the device enters Normal mode. Note The interrupt timer in the 33972 device may be disabled by programming the interrupt bits to logic [1 1 1]. Table 19 shows the programmable settings of the Interrupt timer.

Table 16. Serial Output (SO) Bit Data Table 17. Serial Output (SO) Response Register Table 18. Sleep Command

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command and may be set to 000 (no period) to 111 (64 ms). compared with the switch state prior to sleep command. mode continues until the scan timer expires again. 33972 device exits Sleep mode and enters Normal mode. Figure 12. Sleep Current Waveform

• Generate an interrupt.
• Force all 16 mA pull-up and pull-down current sources to revert to 2.0 mA current sources.
• Maintain the 2.0 mA current source and all other functionality.
• Set the thermal fl ag bit in the SPI output register. The thermal flag bit in the SPI word will be cleared on rising edge of CS provided the die temperature has cooled below the thermal limit. When die temperature has cooled below thermal limit, the device will resume previously programmed settings.

Table 19. Interrupt Timer

111 No interrupt wake-up

Table 20. Scan Timer

000 No Scan

that allow the device to be used in a variety of applications. the interrupt for the particular input. Figure 13. Sensor Power Supply switch may be achieved by paralleling SGn or SPn inputs. a high contact resistance. Resistance of 1.0 kΩ is common. ratiometric reading of variable resistive input.

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Figure 14. Analog Ratiometric Conversion represent the position of the sensor. memory and used in the A / D calculation for the specific input. dedicated calibrated error correction factor. the drain-to-source voltage is approximately 1.0 V.

Figure 15. MOSFET or LED Driver Output

• wetting current timer enable command – Disable SPn wetting current timer (refer to Table 9, page 15).
• metallic command – Set SPn to 16 or 2.0 mA gate drive current (refer to Table 8, page 15).
• settings command – Set SPn as switch-to-battery (refer to Table 6, page 14).
• tri-state command – Disable tri-state for SPn (refer to Table 10, page 16). After the tri-state command has been sent (tri-state disable), the MOSFET gate will be pulled to ground. From this point forward the MOSFET may be turned on and off by sending the settings command :
• settings command – SPn as switch-to-ground (MOSFET ON).
• settings command – SPn as switch-to-battery (MOSFET OFF). Monitoring of the MOSFET drain in the OFF state provides open load detection. This is done by using an SGn input comparator. With the SGn input in tri-state, the load will pull up the SGn input to battery. With open load the SGn pin is pulled down to ground through an external resistor. The open load is indicated by a logic [1] in the SO data bit. The analog command may be used to monitor the drain voltage in the MOSFET ON state. By sourcing 2.0 mA of current to the 1.5 kΩ resistor, the analog voltage on the SGn pin will be approximately: As the voltage on the drain of the MOSFET increases, so does the voltage on the SGn pin. With the SGn pin selected as analog, the MCU may perform the A / D conversion. Using this method for controlling unclamped inductive loads is not recommended. Inductive flyback voltages greater than VPWR may damage the IC. The SP0 : SP7 pins of this device may also be used to send signals from one module to another. Operation is similar to the gate control of a MOSFET.
• For LED applications a resistor in series with the LED is recommended but not required. The switch-to-ground inputs are recommended for LED application. To drive the LED use the following commands:
• wetting current timer enable command – Disable SGn wetting current timer.
• metallic command – Set SGn to 16 mA. From this point forward the LED may be turned on and off using the tri-state command :
• tri-state command – Disable tri-state for SGn (LED ON).
• tri-state command – Enable tri-state for SGn (LED OFF). These parameters are easily programmed via SPI commands in Normal mode. MULTIPLE 33972 DEVICES IN A MODULE SYSTEM Connecting power to the 33972 and the MCU for Sleep mode operation may be done in several ways. Table 21 shows several system configurations for power between the MCU and the 33972 and their specific requirements for functionality. Multiple 33972 devices may be used in a module system. SPI control may be done in parallel or serial. However when parallel mode is used, each device is addressed independently (refer to MCU Interface Description, page 13). Therefore when sending the sleep command, one device will enter sleep before the other. For multiple devices in a system, it is recommended that the devices are controlled in serial (S0 SP0 SG0 SG13 16 2.0 4.0V Ref + Comparator To SPI VPWR SG0 1.5kΩ LOAD VBAT AMUX 100kΩ mA VPWR Comparator To SPI4.0V Ref 2.0 2.0mA mA mA VPWRVPWR SG0 16 2.0 VPWR mA VPWR Comparator To SPI4.0V Ref SG13 mA mA mA

Table 21. Sleep Mode Power Supply 5.0 V 0 V SPI wake-up is not possible. 0 V 0 V SPI wake-up is not possible.

Analog Integrated Circuit Device Data

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from first device is connected to SI of second device). With two devices, 48 clock pulses are required to shift data in. When the WAKE feature is used to enable the power supply, both WAKE pins should be connected to the enable pin on the power supply. The INT pins may be connected to one interrupt pin on the MCU or may have their own dedicated interrupt to the MCU. The transition from Normal to Sleep mode is done by sending the sleep command. With the devices connected in serial and the sleep command sent, both will enter Sleep mode on the rising edge of CS. When Sleep mode is entered, the WAKE pin will be logic [1]. If either device wakes up, the WAKE pin will transition LOW, waking the other device. A condition exists where the MCU is sending the sleep command (CS logic [0]) and a switch input changes state. With this event the device that detects this input will not transition to Sleep mode, while the second device will enter Sleep mode. In this case two switch status commands must be sent to receive accurate switch status data. The first switch status command will wake the device in Sleep mode. Switch status data may not be valid from the first switch status command because of the time required for the input voltage to rise above the 4.0 V input comparator threshold. This time is dependant on the impedance of SGn or SPn node. The second switch status command will provide accurate switch status information. It is recommended that software wait 10 to 20 ms between the two switch status commands, allowing time for switch input voltages to stabilize. With all switch states acknowledged by the MCU, the sleep sequence may be initiated. All parameters for Sleep mode should be updated prior to sending the sleep command. The 33972 IC has an internal 5.0 V supply from the VPWR pin. A POR circuit monitors the internal 5.0 V supply. In the event of transients on the VPWR pin, an internal reset may occur. Upon reset the 33972 will enter Normal mode with the internal registers as defined in Table 15, page 18. Therefore it is recommended that the MCU periodically update all registers internal to the IC. USING THE WAKE FEATURE The 33972 provides a WAKE output and wake-up input designed to control an enable pin on system power supply. While in the Normal mode, the WAKE output is LOW, enabling the power supply. In the Sleep mode, the WAKE pin is high, disabling the power supply. The WAKE pin has a passive pull-up to the internal 5.0 V supply but may be pulled up through a resistor to the VPWR supply (see Figure 17, page 25) When the WAKE output is not used, the pin should be pulled up to the VDD supply through a resistor as shown in Figure 16, page 25. During the Sleep mode, a switch closure will set the WAKE pin LOW, causing the 33972 to enter the Normal mode. The power supply will then be activated, supplying power to the VDD pin and the microprocessor and the 33972. The microprocessor can determine the source of the wake-up by reading the interrupt flag. COST AND FLEXIBILITY Systems requiring a significant number of switch interfaces have many discrete components. Discrete components on standard PWB consume board space and must be checked for solder joint integrity. An integrated approach reduces solder joints, consumes less board space, and offers wider operating voltage, analog interface capability, and greater interfacing flexibility.

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For the most current package revision, visit www.freescale.com and perform a keyword search using the 98A listed below. DWB SUFFIX EW SUFFIX (Pb-FREE) 32-LEAD SOIC WIDE BODY 98ARH99137A ISSUE B

Analog Integrated Circuit Device Data Freescale Semiconductor 27 33972 PACKAGING PACKAGE DIMENSIONS (CONTINUED) PACKAGE DIMENSIONS (CONTINUED) DWB SUFFIX EW SUFFIX (Pb-FREE) 32-LEAD SOIC WIDE BODY 98ARH99137A ISSUE B

Analog Integrated Circuit Device Data

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PACKAGE DIMENSIONS (CONTINUED) EK SUFFIX (Pb-FREE) 32-LEAD SOIC WIDE BODY EXPOSED PAD 98ASA10556D ISSUE D

Analog Integrated Circuit Device Data Freescale Semiconductor 29 33972 PACKAGING PACKAGE DIMENSIONS (CONTINUED) EK SUFFIX (Pb-FREE) 32-LEAD SOIC WIDE BODY EXPOSED PAD 98ASA10556D ISSUE D

Analog Integrated Circuit Device Data

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PACKAGE DIMENSIONS (CONTINUED) EK SUFFIX (Pb-FREE) 32-LEAD SOIC WIDE BODY EXPOSED PAD 98ASA10556D ISSUE D

Analog Integrated Circuit Device Data Freescale Semiconductor 31 33972

REVISION HISTORY

REVISION DATE DESCRIPTION OF CHANGES 4.0 2/2006 • Converted to Freescale format

• Added PC33972A version
• Changed Figure 15, Power Supply Active in Sleep Mode
• Changed Figure 16, Power Supply Shutdown in Sleep Mode
• Updated Outline Drawing for package 5.0 6/2006 • Update to the prevailing Freescale form and style. 6.0 7/2006 • Added MC33972T devices.
• Updated StatiC Electrical Characteristics on page 6 with 33972T parameters. 7.0 11/2006 • Changed Human Body Model parameters in Maximum Ratings table.
• Replaced Part Number MC33972TEW/R2 with MCZ33972TEW/R2
• Removed Peak Package Reflow Temperature During Reflow (solder reflow) parameter from Maximum Ratings on page 5. Added note with instructions to obtain this information from www.freescale.com. 8.0 12/2006 • Restated note (6)
• Changed Part Number MCZ33972TEW/R2 with MC33972TEW/R2 9.0 4/2007 • Removed all references to the 33972T device.
• Removed the MC33972TDWB/R2, MC33972TEW/R2, and PC33972AEW/R2 from the ordering information.
• Added MCZ33972AEW/R2 to the ordering information. 10.0 6/2007 • Added MC33972EW/R2, MC33972TDWB/R2, MC33972TEW/R2, and MCZ33972TEW/ R2 to the ordering information. 11.0 11/2007 • Updated to the current Freescale form and style
• Added MC33972AEK/R2 to th e ordering information.
• Included device specific information relevant to the EK suffix on pages 1, 2, 4, 5, 6, 27, and 28.
• Added sentence to CHIP SELECT (CS) on page 10
• Made calculation corrections to Analog Sensor Inputs (Ratiometric) 12.0 12/2007 • Corrected Device Variation Table on page 2. 13.0 12/2007 • Replaced Outline Drawing 98ARL10543D with 98ASA10556D. 14 6/2008 • Added Note 7, “ TC is the TCASE of the package” to Electrical Characteristics Table. 15 8/2008 • Updated package drawing 98ASA10556D 16 10/2009 • Updated data sheet status from Advance Information to Technical Data
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