33970

33970 FREESCALE | Alldatasheet

Document overview

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Technical content

Features

• MMT-Licensed Two-Phase Step Motor Compatible
• Minimal Processor Overhead Required
• Fully Integrated Pointer Movement and Position State Machine with Air Core Movement Emulation
• 4096 Possible Steady State Pointer Positions
• 340° Maximum Pointer Sweep
• Fixed Maximum Acceleration and Deceleration of 4500°/s 2
• Maximum Pointer Velocity of 400°/s
• Analog Microstepping (12 Steps/Degree of Pointer Movement)
• Pointer Calibration and Return to Zero
• SPI-Controlled 16-Bit Word
• Calibratable Internal Clock
• Low Sleep Mode Current
• Backward Compatible with MC33991
• Improved Pointer Movement, Diagnos tics, and Return to Zero (RTZ)
• Pb-Free Packaging Designated by Suffix Code EG

Figure 1. 33970 Simplified Application Diagram

ORDERING INFORMATION

Range (TA) Package MC33970DW/R2 -40°C to 125°C 24 SOICW MCZ33970EG/R2 5.0 V Regulator MCU VPWR VPWR 33970 VDD VDD RTZ RST CS SCLK SI SO GND Motor 0 SIN0+ SIN0- COS0+ COS0- Motor 1 SIN1+ SIN1- COS1+ COS1-

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Figure 2. 33970 Simplified Internal Block Diagram

Figure 3. 33970 Pin Connections Table 1. 33970 Pin Definitions A functional description of each pin can be found in the Functional Pin Description section beginning on page 10. transistors as well as the logic portion of the device. 9 CS Input Chip Select This pin is connected to a chip select output of a LSI IC.

10 SCLK Input Serial Clock This pin is connected to the SCLK pin of the master device and acts as a

11 SO Output Serial Output This pin is connected to the SPI Serial Data Input pin of the master

device, or to the SI pin of the next device in a daisy chain.

12 SI Input Serial Input This pin is connected to the SPI Serial Data Output pin of the master

device from which it receives output command data. 14 VDD Input Voltage This SPI and logic power supply input will work with 5.0 V supplies. 15 RST Input Reset This input has an internal active pull-up. 16 VPWR Input Battery Voltage Power supply.

Analog Integrated Circuit Device Data

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ELECTRICAL CHARACTERISTICS

Table 2. Maximum Ratings permanent damage to the device.

1. Exceeding voltage limits on Input pins may cause permanent damage to the device.
2. Output continuous output rating so long as maximum junction temperature is not exceeded. Operation at 125°C ambient temperature

will require maximum output current computation using package thermal resistances.

1. ESD1 testing is performed in accordance with the Human Body Model (C ZAP = 100 pF, RZAP = 1500 Ω), ESD2 testing is performed in

accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 Ω).

1. Pin soldering temperature limit is for 10 seconds maximum dura tion. Not designed for immersion soldering. Exceeding these limits may

cause malfunction or permanent damage to the device.

1. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow

MC33xxxD enter 33xxx), and review parametrics.

Analog Integrated Circuit Device Data Freescale Semiconductor 5 33970 STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.

0.94 VST6

0.84 VST6

0.68 VST6

0.47 VST6

0.23 VST6

0.97 VST6

0.87 VST6

0.71 VST6

0.50 VST6

0.26 VST6

1.0 VST6

0.96 VST6

0.8 VST6

0.57 VST6

0.31 VST6

1. Outputs and logic remain active; however, the larger coil volt age levels may be clipped. The reduction in drive voltage may result in a
2. The logic will reset at some level below the specified Limited Operational minimum.
3. Outputs will disable and must be re-enabled via the PECCR command.
4. Outputs remain active; however, the reduction in drive voltage may result in a loss of position control.

Analog Integrated Circuit Device Data

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STATIC ELECTRICAL CHARACTERISTICS POWER OUTPUTS (continued) Output Flyback Clamp (10) VFB – VST6 + 0.5 VST6 + 1.0 V Output Current Limit (Output = VST6) ILIM 40 100 170 mA Overtemperature Shutdown (10) OTSD 155 – 180 °C Overtemperature Hysteresis (10) OTHYST 8.0 – 16 °C CONTROL I/O Input Logic High Voltage (11) VIH 2.0 – – V Input Logic Low Voltage (11) VIL – – 0.8 V Input Logic Voltage Hysteresis (10) VIN(HYST) – 100 – mV Input Logic Pull Down Current (SI, SCLK) IDWN 3.0 – 20 µA Input Logic Pull-Up Current (CS, RST) IUP 5.0 – 20 µA SO High-State Output Voltage (IOH = 1.0 mA) VSOH 0.8 VDD – – V SO Low-State Output Voltage (IOL = -1.6 mA) VSOL – 0.2 0.4 V SO Tri-State Leakage Current (CS ≥ 3.5 V) ISOLK -5.0 0 5.0 µA Input Capacitance (12) CIN – 4.0 12 pF SO Tri-State Capacitance (12) CSO – – 20 pF ANALOG TO DIGITAL CONVERTER (RTZ ACCUMULATOR COUNT) ADC Gain (10), (13) GADC 100 188 270 Counts/V/ ms Notes 10. This parameter is guaranteed by desi gn; however, it is not production tested. 11. V DD = 5.0 V. 12. Capacitance not measured. This parameter is guarant eed by design; however, it is not production tested. 13. Reference Figure 8, RTZ Accumulator (Typical) Table 3. Static Electrical Characteristics (continued) values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.

Analog Integrated Circuit Device Data Freescale Semiconductor 7 33970 DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 4. Dynamic Electrical Characteristics values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.

1. Maximum specified time for t he 33970 is the minimum guaranteed time needed from the microcontroller.
2. The minimum and maximum value will vary proportionally to th e internal clock tolerance. These numbers are based on an ideally

calibrated clock frequency of 1.0 MHz. These are not 100 percent tested.

1. The device shall meet all SPI interface timing requirements specified in the SPI Interface Timing section of this table, over the temperature

be fully functional for slower clock speeds. See Figure 4 and 5.

1. The maximum setup time specified for the 33970 is the mini mum time needed from the microcontroller to guarantee correct operation.
2. Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
3. The value is for a 1.0 MHz calibrated internal clock. The value will change proportionally as the internal clock frequency changes

Analog Integrated Circuit Device Data

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DYNAMIC ELECTRICAL CHARACTERISTICS Time from Falling Edge of CS to SO Low Impedance (20) tSO(EN) – – 145 ns Time from Rising Edge of CS to SO High Impedance (21) tSO(DIS) – 1.3 4.0 µs Time from Rising Edge of SCLK to SO Data Valid (22) 0.2 VDD ≤ SO ≥ 0.8 VDD, CL = 200 pF tVALID – 65 105 ns Notes 20. Time required for output status data to be terminated at SO. 1.0 k Ω load on SO 21. Time required for output status data to be available for use at SO. 1.0 k Ω load on SO. 22. Time required to obtain valid data out from SO following the rise of SCLK. values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.

Analog Integrated Circuit Device Data Freescale Semiconductor 9 33970 Figure 4. Input Timing Switching Characteristics Figure 5. Valid Data Delay Time and Valid Time Waveforms

0.2 VDD

0.7 VDD

Analog Integrated Circuit Device Data

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This 33970 is a single-packaged, Serial Peripheral Interface (SPI) controlled, dual step motor gauge driver integrated circuit (IC). This monolithic IC consists of four dual output H-Bridge coil drivers and the associated control logic. Each pair of H-Bridge drivers is used to automatically control the speed, direction, and magnitude of current through the two coils of a two-phase instrumentation step motor, similar to an MMT-licensed AFIC 6405. The 33970 is ideal for use in automotive instrumentation systems requiring distributed and flexible step motor gauge driving. The device also eases the transition to step motors from air core motors by emulating the air core pointer movement with little additional processor bandwidth utilization. FUNCTIONAL PIN DESCRIPTION H-Bridge Outputs 0 (COS0+, COS0-, SIN0+, SIN0-) Each pin is the output pin of a half bridge, designed to source or sink current. The H-Bridge pins linearly drive the sine and cosine coils of two separate step motors to provide four-quadrant operation. GROUND (GND) These pins serve as the ground for the source of the low- side output transistors as well as the logic portion of the device. They also help dissipate heat from the device. CHIP SELECT (CS) The CS pin enables communication with the master device. When this pin is in a logic [0] state, the 33970 is capable of transferring information to, and receiving information from, the master. The 33970 latches data in from the Input Shift registers to the addressed registers on the rising edge of CS. The output driver on the SO pin is enabled when CS is logic [0]. When CS is logic high, signals at the SCLK and SI pins are ignored and the SO pin is tri-stated (high impedance). CS will only be transitioned from a logic [1] state to a logic [0] state when SCLK is a logic [0]. CS has an internal pull-up (lUP) connected to the pin, as specified in the section of the Static Electrical Characteristics table entitled CONTROL I/O, which is found on page 6. SERIAL CLOCK (SCLK) SCLK clocks the Internal Shift registers of the 33970 device. The Serial Input (SI) pin accepts data into the Input Shift register on the falling edge of the SCLK signal, while the Serial Output pin (SO) shifts data information out of the SO Line Driver on the rising edge of the SCLK signal. It is important that the SCLK pin be in a logic [0] state whenever the CS makes any transition. SCLK has an internal pull down (lDWN), as specified in the section of the Static Electrical Characteristics table entitled CONTROL I/O, which is found on page 6. When CS is logic [1], signals at the SCLK and SI pins are ignored and SO is tri-stated (high impedance). Refer to the data transfer timing diagrams in Figure 6 and Figure 7 on page 12. SERIAL OUTPUT (SO) The SO data pin is a tri-stateable output from the Shift register. The Status register bits are the first 16 bits shifted out. Those bits are followed by the message bits clocked in FIFO, when the device is in a daisy chain connection or being sent words that are multiples of 16 bits. Data is shifted on the rising edge of the SCLK signal. The SO pin will remain in a high impedance state until the CS pin is put into a logic low state. SERIAL INPUT (SI) The SI pin is the input of the Serial Peripheral Interface (SPI). Serial Input (SI) information is read on the falling edge of SCLK. A 16-bit stream of serial data is required on the SI pin, beginning with the most significant bit (MSB). Messages that are not multiples of 16 bits (e.g., daisy chained device messages) are ignored. After transmitting a 16-bit word, the CS pin must be de-asserted (logic [1]) before transmitting a new word. SI information is ignored when CS is in a logic high state. Multiplexed Output (RTZ) This is a multiplexed output pin, for the non-driven coil, during a Return to Zero (RTZ) event. Voltage (VDD) This SPI and logic power supply input will work with 5.0 V supplies. RESET (RST) If the master decides to reset the device, or place it into a sleep state, the RST pin is driven to a logic [0]. A logic [0] on the RST pin will force all internal logic to the known default state. This input has an internal active pull-up. BATTERY VOLTAGE (VPWR) Power supply.

Analog Integrated Circuit Device Data Freescale Semiconductor 11 33970 FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION H-BRIDGE OUTPUTS 1 (SIN1-, SIN1+, COS1-, COS1+) Each of this pins is the output pin of a half bridge, designed to source or sink current. The H-Bridge pins linearly drive the sine and cosine coils of two separate step motors to provide four-quadrant operation.

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compatible with 5.0 V CMOS logic levels. timing diagrams shown in Figure 6 and Figure 7. Figure 6. Single 16-Bit Word SPI Communication Figure 7. Multiple 16-Bit Word SPI Communication Table 5. Data Transfer Timing CS (1-to-0) SO pin is enabled. SO Will change state on the rising edge of the SCLK pin signal. SI Will accept data on the falling edge of the SCLK pin signal. Output shift register is loaded here. Note SO is tri-stated when CS is logic [1].

1. SO is tri-stated when CS is logic [1].

the Input Shift register and transfer it to the internal registers. control the behavior of this device. in a message smaller than 16 bits wide, it is ignored. incoming SPI word (refer to Table 6). by the three MSBs of the 16-bit word received serially.

• Individual gauge drive enabling
• Power-up/down
• Internal clock calibration
• Gauge pointer position and velocity
• Gauge pointer zeroing
• Air core motor movement emulation
• Status information Status reporting includes:
• Individual gauge overte mperature condition
• Battery overvoltage
• Battery undervoltage
• Pointer zeroing status
• Internal clock status
• Confirmation of coil output changes that should result in pointer movement
• Real time pointer position information
• Real time pointer velocity step information
• Pointer movement direction
• Command pointer position status
• RTZ accumulator value Table 6 provides the registers available to control the above functions. REGISTER DESCRIPTIONS The following section describes the registers, their addresses, and their impact on device operation. Address 000 — Power, Enable, Calibration, and Configuration Register (PECCR) The Power, Enable, Calibration, and Configuration Register is illustrated in Table 7, page 14. A write to the 33970 using this register allows the master to (1) independently enable or disable the output drivers of the two-gauge controllers, (2) calibrate the internal clock, (3) disable the air core emulation, (4) select the direction of the pointer movement during pointer positioning and zeroing, (5) configure the device for the desired status information to be clocked out into the SO pin, or (6) send a null command for the purpose of reading the status bits. This register is also used to place the 33970 into a low current consumption mode. Each of the gauge drivers can be enabled by writing a logic [1] to their assigned address bits, PE0 and PE1 respectively. This feature could be used to disable a driver if

Table 6. Module Memory Map

000 Power, Enable, Calibration,

001 Maximum Velocity Register VELR Page 15

010 Gauge 0 Position Register POS0R Page 15

011 Gauge 1 Position Register POS1R Page 15

100 Gauge Return to 0 Register RTZR Page 16

101 Gauge Return to 0

110 Not Used – –

111 Reserved for Test – –

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motor is directly related to the accuracy of the internal clock. independent, the non-calibrated tolerance is +70% to -35%. section, beginning on page 26. the counter and generate a CAL fault indication. than is provided with the air core motor emulation feature. deceleration at the maximum rate. Bit D6 is logic [0] during a PECCR commands.

• Accumulator information and detection status during the RTZ (PE10 logic [0])
• Real time pointer position location at the time CS goes low (PE10 logic [1] and PE9 logic [0]), or
• The real time step position of the pointer as described in the velocity Table 21, page 24 (PE10, PE9, and PE8 logic [1]). Additional details are provided in the SO Communication section beginning on page 18. If bit PE12 is logic [1] during a PECCR command, the state of PE11:PE0 is ignored. This is referred to as the null command and can be used to read device status without affecting device operation. The bits in Table 7 are write-only. PE12 (D12) — Null Command for Status Read
• 0 = Disable
• 1 = Enable PE11 (D11) — Status Select bit. This bit selects the information clocked out of the SO pin.
• 0 = Device Status (the logi c states of PE10, PE9, and PE8 don’t cares)
• 1 = RTZ Accumulator Value, Gauge 0 or 1 Pointer position, or Gauge 0 and 1 Velocity ramp position (depending upon the logic states of PE10, PE9, and PE8) PE10 (D10) — RTZ Accumulator or Pointer Status Select bit. This bit is recognized only when PE11 = 1.
• 0 = RTZ Accumulator Value and status
• 1 = Pointer Position or Speed

Table 7. Power, Enable, Calibration, and Configuration Register (PECCR)

PE9 (D9) — Pointer Position or Pointer Speed Select bit. This bit is recognized only if PE11 and PE10 = 1.

• 0 = Gauge 0 or Gauge 1 Pointer Position
• 1 = Gauge 0 and Gauge 1 Pointer Speed PE8 (D8) — Pointer Position Gauge Select bit. Also the Position 0 of the selected gauge is determined by the PE7 selection. This bit is recognized only if PE11 and PE10 = 1 and PE9 = 0.
• 0 = Gauge 0 position
• 1 = Gauge 1 position PE7 (D7) — Position 0 Location Select bit. This bit determines the Position 0 of the gauge selected by PE8. RTZ direction will always be to the position 0.
• 0 = Position 0 is the most CCW (counterclockwise) position
• 1 = Position 0 is the mo st CW (clockwise) position PE6 (D6) — This bit must be transmitted as logic [0] for valid PECCR commands. PE5 (D5) — Air Core Motor Emulation bit. This bit is enabled or disabled (acceleration and deceleration is constant if disabled).
• 0 = Enable
• 1 = Disable PE4 (D4) — Clock Calibration Frequency Selector
• 0 = Maximum f =1.0 MHz (for 8.0 µs calibration pulse)
• 1 = Nominal f =1.0 MHz (for 8.0 µs calibration pulse) PE3 (D3) — Clock Calibration Enable bit. This bit enables or disables the clock calibration.
• 0 = Disable
• 1 = E n a b l e PE2 (D2) — Oscillator Adjustment
• 0 = tCLU
• 1 = 0.66 x t CLU PE1 (D1) — Gauge 1 Enable bit. This bit enables or disables the output driver of Gauge 1.
• 0 = Disable
• 1 = E n a b l e PE0 (D0) — Gauge 0 Enable bit. This bit enables or disables the output driver of Gauge 0.
• 0 = Disable
• 1 = E n a b l e Address 001 — Maximum Velocity Register (VELR) The Gauge Maximum Velocity Register is used to set a maximum velocity for each gauge (refer to Table 8). Bits V7:V0 contain a position value from 1– 225 that is representative of the velocity position value described in Table 21, page 24. The table value becomes the maximum velocity until it is changed to another value. If a maximum value is chosen greater than the maximum velocity in the acceleration table, the maximum table value becomes the maximum velocity. If the motor is turning at a speed greater than the new maximum, the motor immediately moves down the velocity ramp until the speed falls equal to or below it. Velocity for each motor can be changed simultaneously or independently by writing V8 and/or V9 to a logic [1]. Bits V12:V10 must be at logic [0] for valid VELR commands. The bits in Table 8 are write-only. V12:V10 (D12:D10) — These bits must be transmitted as logic [0] for valid VELR commands V9 (D9) — Gauge 1 Velocity. Specifies whether the maximum velocity determined in the V7: V0 field will apply to Gauge 1.
• 0 = Velocity does not apply to Gauge 1
• 1 = Velocity applies to Gauge 1 V8 (D8) — Gauge 0 Velocity. Specifies whether the maximum velocity specified in the V7: V0 field will apply to Gauge 0.
• 0 = Velocity does not apply to Gauge 0
• 1 = Velocity applies to Gauge 0 V7:V0 (D7:D0) — Maximum Velocity. Specifies the maximum velocity position from Table 21. This velocity will remain the maximum of the intended gauge until changed by command. Velocities can range from position 1 (00000001) to position 225 (11111111). Addresses 010 and 011 — Gauge 0/1 Position Registers (POS0R, POS1R) Gauge 0 Position Register (SI Addresses 010) bits P0 11: P0 0 are written to when communicating the desired pointer positions, and Gauge 1 Position Register (SI Address 011) bits P1 11: P1 0 are written to when communicating the desired pointer positions. Commanded positions can range from 0 to 4095. The D12 bit must be at logic [0] for valid POS0R and POS1R commands.

Table 8. Maximum Velocity Register (VELR)

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The bits in Table 9 are write-only. movement, the maximum pointer sweep is 341.25°. The bits in Table 10 are write-only. is written to return the gauge pointers to the zero position. Gauge 1 when RZ0 is logic [1], respectively. and characterization of RTZ requirements. The register bits in Table 11 are write-only. logic [0] for valid commands.

• 0 = Automatic Return to Zero
• 1 = Unconditional Return to Zero RZ3 (D3) — This bit must be transmitted as logic [0] for valid commands. RZ2 (D2) — Return to Zero Direction bit. This bit is used to properly sequence the integrator, depending upon the desired zeroing direction.
• 0 = Return to Zero will occur in the CCW direction (PE7 = 0)
• 1 = Return to Zero will occur in the CW direction (PE7 = 1)

Table 9. Gauge 0 Position Register (POS0R) Table 10. Gauge 1 Position Register (POS1R) Table 11. Return to Zero Register (RTZR)

the selected gauge to return the pointer to zero position.

• 0 = Return to Zero Disabled
• 1 = Return to Zero Enabled RZ0 (D0) — Gauge Select: Gauge 0/Gauge 1. This bit selects the gauge to be commanded.
• 0 = Selects Gauge 0
• 1 = Selects Gauge 1 Address 101 — Gauge Return to Zero Configuration Register Gauge Return to Zero Configuration Register (RTZCR) is used to configure the Return to Zero Event (refer to Table 12). It is written to modify the step time, or rate; at which the pointer moves during an RTZ event. Also, the integration blanking time, which is the time immediately following the transition of a coil from a driven state to an open state in the RTZ mode, is adjustable with this command. Finally, this command is used to adjust the threshold of the RTZ integration register. The values used for this register should be selected during development to optimize the RTZ for each application. Selecting an RTZ step rate resulting in consistently successful zero detections depends on a clear understanding of the motor characteristics. Specifically, resonant frequencies exist due to the interaction between the motor and the pointer. This command allows movement of the RTZ pointer speed away from these frequencies. Also, some motors require a significant amount of time for the pointer to settle to a steady state position when moving from one full step position to the next. Consistent and accurate integration values require the pointer be stationary at the end of the full step time. Bits RC3:RC0, RC12:RC11, and RC4 determine the time spent at each full step during an RTZ event. Bits RC3:RC0 are used to select a ∆t ranging from 0 ms (0000) to 61.44 ms (1111) in increments of 4.096 ms (refer to Table 13). The ∆t is multiplied by the factor M, which is defined by bits RC12:RC11. The product is then added to the blanking time, selected using bit RC4, to generate the full step time. The multiplier selected with RC12:RC11 will be 1 (00), 2 (01), or 4 (10) as illustrated in the equations below. Note that the RC12:RC11 value of 8 (11) is not recommended for use in a product design application, because of the potential for an RTZ accumulator internal overflow, due to the long time step. The blanking time is either 512 µs when RC4 is logic [0], or 768 µs when it is logic [1].The full step time is generated using the following equations: When D3:D0 (RC3:RC0) ≠ 0000 Full Step (t) = ∆t x M + blanking (t)(1) When D3:D0 (RC3:RC0) = 0000 Full Step (t) = blanking (t) + 2.048 ms(2) Note In equation (2), a 2.048 ms offset is added to the full step time when the RC:3:RC0 = 0000. The full step time default value after a logic reset is 12.80 ms (RC12:RC11 = 00, RC4 = 0, and RC3:RC0 = 0011). If there are two full steps per degree of pointer movement, the pointer speed is 1/(FullStep x 2) deg/s. Detecting pointer movement is accomplished by integrating the EMF present in the non-driven coil during the RTZ event. The integration circuitry is implemented using a Sigma-Delta converter resulting in the placement of a value in the 15-bit RTZ accumulator at the end of each full step. The value in the RTZ accumulator represents the change in flux and is compared to a threshold. Values above the threshold indicate a pointer is moving. Values below the threshold indicate a stalled pointer, thereby resulting in the cessation of the RTZ event. The RTZ accumulator bits are signed and represented in two’s complement. After a full step of integration, a sign bit of 0 is the indicator of an accumulator exceeding the decision threshold of 0, and the pointer is assumed to still be moving. Similarly, if the sign bit is logic [1] after a full step of integration, the accumulator value is negative and the pointer is assumed to be stopped. The integrator and accumulator are initialized after each full step. If the PECCR command is written to clock out the RTZ accumulator values via the SO, the OD14 bit corresponds to the sign bit of the RTZ accumulator. Accurate pointer stall detection depends on a correctly preloaded accumulator for specific gauge, pointer, and full step combinations. Bits RC10:RC5 are used to offset the initial RTZ accumulator value, properly detecting a stalled motor. The initial accumulator value at the start of a full step of integration is negative. If the accumulator was correctly preloaded, a free-moving pointer will result in a positive value at the end of the integration time, and a stalled pointer will result in a negative value. The preloaded values associated with each combination of bits RC10:RC5 are illustrated in

Table 14. The accumulator should be loaded with a value the 33970 device sets the accumulator value to -1. Table 12. RTZCR SI Register Assignment

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The bits in Table 12 are write-only.

• 00 = 1
• 01 = 2
• 10 = 4
• 11 = 8 (Not to be used for design) RC10:RC5 (D10:D5) — These bits determine the value preloaded into the RTZ integration accumulator to adjust the detection threshold. Values range from -1 (00000000) to - 1099 (11111111) as shown in Table 14. RC4 (D4) — This bit determines the RTZ blanking time (blanking (t)).
• 0 = 512 µs
• 1 = 768 µs RC3:RC0 (D3:D0) — These bits, along with RC12:RC11 (D12:D11) and RC4 (D4), determine the time variables used to calculate the full step times with equations (1) or (2) illustrated above. RC3:RC0 determines the ∆t time. The ∆t values range from 0 (0000) to 61.440 ms (1111) and are shown in

Table 13. The default ∆t is 0 (0011). equation (1) for all other combinations of RC3:RC0. status) will always reflect the real time state of the pointer. Table 13. RTZCR Full Step Time Table 14. RTZCR Accumulator Offset

data that is clocked out of the SO pin.

1. Device Status (refer to Table 15 below)
2. RTZ Accumulator Status (refer to Table 16, page 20)
3. Gauge 0 Pointer Position Status (refer to Table 17,
4. Gauge 1 Pointer Position Status (refer to Table 18,
5. Gauge 1 and 2 Pointer Velocity Status (refer to

The bits in Table 15 are read-only bits.

• 0 = Toward position 0
• 1 = Away from position 0 DIR0 (OD14) — This bit indicates the direction Gauge 0 pointer is moving.
• 0 = Toward position 0
• 1 = Away from position 0 0POS1 (OD13) — This bit indicates the configured Position 0 for Gauge 1.
• 0 = Farthest CCW
• 1 = F a r t h e s t C W 0POS0 (OD12) — This bit indicates the configured Position 0 for Gauge 0.
• 0 = Farthest CCW
• 1 = F a r t h e s t C W CMD1 (OD11) — This bit indicates whether Gauge 1 is at the most recently commanded position.
• 0 = At commanded position
• 1 = Not at commanded position CMD0 (OD10) — This bit indicates whether Gauge 0 is at the most recently commanded position.
• 0 = At commanded position
• 1 = Not at commanded position OV (OD9) — Overvoltage Indication. A logic [1] on this bit indicates VPWR voltage exceeded the upper limit of VPWROV since the last SPI communication (refer to the Static Electrical Characteristics table under POWER INPUT, page 5). An overvoltage event will automatically disable the driver outputs. Because the pointer may not be in the expected position, the master may want to re-calibrate the pointer position with an RTZ command after the voltage returns to a normal level. For an overvoltage event, both gauges must be re-enabled as quickly as this flag returns to logic [0]. The state machine will continue to operate properly as long as VDD is within the normal range.
• 0 = Normal range
• 1 = Battery voltage exceeded V PWROV UV (OD8) — Undervoltage Indication. A logic 1] on this bit indicates the VPWR voltage fell below VPWRUV since the last SPI communication (refer to the Static Electrical Characteristics table under POWER INPUT, page 5). An undervoltage event is just flagged; however, at some voltage level below 4.0 V, the outputs turn OFF and the state machine resets. Because the pointer may not be in the expected position, the master may want to re-calibrate the pointer position with an RTZ command after the voltage returns to a normal level. For an undervoltage event, both gauges may need to be re-enabled as quickly as this flag returns to logic [0]. The state machine will continue to operate properly as long as VDD is within the normal range.
• 0 = Normal range
• 1 = Battery voltage fell below V PWRUV CAL (OD7) — Calibrated Clock out of Specification. A logic [1] on this bit indicates the clock count calibrated to a value outside the expected range given the tolerance specified by t CLC in the Dynamic Electrical Characteristics D11 D10 D9 D8 0 x x x x = Don’t care.

Table 15. Device Status Output Register

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• 0 = Clock within spec
• 1 = Clock out of spec OVUV (OD6) — Undervoltage or Overvoltage Indication. A logic [1] on this bit indicates the VPWR voltage fell to a level below the VPWRUV since the last SPI communication (refer to the Static Electrical Characteristics table under POWER INPUT, page 5). An undervoltage event is just flagged, while an overvoltage event automatically disables the drive outputs. Because the pointer may not be in the expected position, the master may want to re-calibrate the pointer with an RTZ command after the voltage returns to normal level. For an overvoltage event, both gauges must be re-enabled as soon as this flag returns to logic [0]. The state machine will continue to operate properly as long as VDD is within the normal range.
• 0 = Normal range
• 1 = Battery voltage fell below V PWRUV or exceeded VPWROV MOV1 (OD5) — This bit identifies Gauge 1 Movement since last SPI communication. A logic [1] on this bit indicates the Gauge 1 pointer position changed since the last SPI command. This information allows the master to confirm the pointer is moving as commanded.
• 0 = Gauge 1 position has not changed since the last SPI command
• 1 = Gauge 1 pointer position has changed since the last SPI command MOV0 (OD4) — Gauge 0 Movement Since last SPI Communication. A logic [1] on this bit indicates the Gauge 0 pointer position has changed since the last SPI command. This information allows the master to confirm the pointer is moving as commanded.
• 0 = Gauge 0 position has not changed since the last SPI command
• 1 = Gauge 0 pointer position has changed since the last SPI command RTZ1 (OD3) — RTZ1 Is Enabled or Disabled. A logic [1] on this bit indicates Gauge 1 is in the process of returning to the zero position as requested with the RTZ command. This bit will continue to indicate a logic [1] until the SPI message following a detection of the zero position, or the RTZ feature is commanded OFF using the RTZ message.
• 0 = Return to Zero disabled
• 1 = Return to Zero enabled successfully RTZ0 (OD2) — RTZ0 Is Enabled or Disabled. A logic [1] on this bit indicates Gauge 0 is in the process of returning to the zero position as requested with the RTZ command. This bit continues to indicate a logic [1] until the SPI message following a detection of the zero position, or the RTZ feature is commanded OFF using the RTZ message.
• 0 = Return to Zero disabled
• 1 = Return to Zero enabled successfully OT1 (OD1) — Gauge 1 Junction Overtemperature. A logic [1] on this bit indicates that the coil drive circuitry dedicated to drive Gauge 1 has exceeded the maximum allowable junction temperature since the last SPI communication and that Gauge 1 has been disabled. It is recommended that the pointer be re-calibrated using the RTZ command after re-enabling the gauge using the PECCR command. This bit remains logic [1] until the gauge is enabled.
• 0 = Temperature within range
• 1 = Gauge 1 maximum allo wable junction temperature condition has been reached OT0 (OD0) — Gauge 0 Junction Overtemperature. A logic [1] on this bit indicates that the coil drive circuitry dedicated to drive Gauge 0 has exceeded the maximum allowable junction temperature since the last SPI communication and that Gauge 0 has been disabled. It is recommended that the pointer be re-calibrated using the RTZ command after re-enabling the gauge using the PECCR command. This bit remains logic [1] until the gauge is re- enabled.
• 0 = Temperature within range
• 1 = Gauge 0 maximum allo wable junction temperature condition is reached RTZ Accumulator Status Information Most recent valid PECCR command resulting in the RTZ Accumulator status output: The bits in Table 16 are read-only bits. RTZ (OD15) — RTZ Bit Is Enabled or Disabled. A logic [1] on this bit indicates that the Gauge is in the process of returning to the zero position as requested with the RTZ command. This bit will continue to indicate a logic [1] until the SPI message following a detection of the zero position, or the RTZ feature is commanded OFF using the RTZ message.
• 0 = Return to Zero disabled D11 D10 D9 D8 1 0 x x x = Don’t care.

Table 16. RTZ Accumulator Status Output Register

22 Freescale Semiconductor

The bits in Table 18 are read-only bits. ENB1 (OD15) — This bit indicates if Gauge 1 is enabled.

• 0 = Disabled
• 1 = Enabled DIR1 (OD14) — This bit indicates the direction Gauge 1 pointer is moving.
• 0 = Toward position 0
• 1 = Away from position 0 DIRC1 (OD13) — This bit determines if the direction of the most recent pointer movement is toward, or away from, the last commanded position.
• 0 = Direction of the pointer movement is toward the commanded position
• 1 = Direction of the pointer movement is away from the commanded position CMD1 (OD12) — This bit indicates if Gauge 1 is at the most recently commanded position.
• 0 = At commanded position
• 1 = Not at commanded position POS11:POS0 (OD11:OD0) — These 12 bits represent the actual position of the pointer at the time CS transitions to a logic [0]. Gauge 0 and 1 Pointer Velocity Status Information Most recent valid PECCR command resulting in the Gauge 0 and 1 Pointer Velocity status output: The bits in Table 19 are read-only bits. 1V7:1V0 (OD15:OD8) — These eight bits represent the velocity position value (refer to Table 21, page 24) indicating the actual velocity of Gauge 1 pointer at the time CS transitions to a logic [0]. 0V7:0V0 (OD7:OD0) — These eight bits represent the velocity position value (refer to Table 21) indicating the actual velocity of Gauge 0 pointer at the time CS transitions to a logic [0]. STATE MACHINE OPERATION The two-phase step motor has maximum allowable velocities and acceleration and deceleration.The purpose of the step motor state machine is to drive the motor with maximum performance while remaining within the motor’s voltage, velocity, and acceleration constraints. A requirement of the state machine is to ensure the deceleration phase begins at the correct time and pointer position. When commanded, the motor will accelerate constantly to the maximum velocity, then move toward the commanded position. Eventually, the pointer will reach the calculated location where the movement has to decelerate, slowing safely to a stop at the desired position. During the deceleration phase, the motor will not exceed the maximum deceleration. During normal operation, both step motor rotors are microstepped with 24 steps per electrical revolution (see Figure 9). A complete electrical revolution results in two degrees of pointer movement. There is a second (smaller) state machine in the IC controlling these microsteps. This state machine receives clockwise or counter-clockwise index commands at intervals, stepping the motor in the appropriate direction by adjusting the current in each coil. Normalized values are provided in Table 20, page 23. D11 D10 D9 D8 1 1 1 x x = Don’t care.

Table 19. Gauge 0 and 1 Pointer Velocity Status Output Register

Figure 9. Clockwise Microsteps Table 20. Coil Step Value

24 Freescale Semiconductor

and the changing time defines the motor acceleration. motor to stop at the desired position. The motor equations of motion are generated as follows. the time step actually used. quantized value obtained above. is generated giving the time step ∆t at an index position n. where indicates rounding up. also equal to the current value of n.

1. The pointer is at the previously commanded position
2. A command to move to a pointer position (other than

commanded position efficiently. quantized to a 1.0 MHz clock.

• Denotes normalized values.

Table 21. Velocity Table

Table 21. Velocity Table (continued)

26 Freescale Semiconductor

the use of an additional crystal or resonator.

28 Freescale Semiconductor

Figure 11. Deceleration Ramp automatic RTZ is initiated using the RZ0, RZ1, and RZ2 bits. back via the SO pin that an RTZ is underway. too long), it can disable the command via the RTZR bit RZ1. be turned OFF using the RTZR bit RZ1. while essentially grounding the other end.

Figure 12. Full Steps Counterclockwise integration value potentially interpreted as a stalled pointer. commanded, position before starting the RTZ event. microsteps clockwise to the nearest full step location. device status bits CMD1 and CMD2. calibrating them sequentially. prior to initiating the RTZ.

Analog Integrated Circuit Device Data

30 Freescale Semiconductor

FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS DEFAULT MODE Default mode refers to the state of the 33970 after an internal or external reset prior to SPI communication. An internal reset occurs during VDD power-up or if VPWR falls below 4.0 V. An external reset is initiated by the RST pin driven to a logic [0]. With the exception of the RTZCR full step time, all of the specific pin functions and internal registers will operate as though all of the addressable configuration register bits were set to logic [0]. This means, for example, all of the outputs will be disabled after a power-up or external reset, and SO flag ST6 is set, indicating an undervoltage event. Anytime an external reset is exerted and the default is restored, all configuration parameters (e.g., clock calibration, maximum speed, RTZ parameters, etc.) are lost and must be reloaded. FAULT LOGIC REQUIREMENTS The 33970 device indicates each of the following faults as they occur:

• Overtemperature fault
• Undervoltage V PWR
• Overvoltage V PWR
• Clock out of spec These fault bits remain enabled until they are clocked out of the SO pin with a valid SPI message. Overcurrent faults are not reported directly; however, it is likely an overcurrent condition will become a thermal issue and be reported. OVERTEMPERATURE FAULT REQUIREMENTS The 33970 incorporates overtemperature protection circuitry, which shuts off the affected gauge driver when excessive temperatures are detected. In the event of a thermal overload, the affected gauge driver is automatically disabled. The overtemperature fault is flagged via the OT0 and/or OT1 device status bits. The indicating flag continues to be set until the affected gauge is successfully re-enabled, provided the junction temperature has fallen to a temperature below the hysteresis level. OVERVOLTAGE FAULT REQUIREMENTS The device is capable of surviving VPWR voltages within the maximum specified in Table 2. VPWR levels resulting in an Overvoltage Shutdown condition can result in uncertain pointer positions. Therefore, the pointer position should be re-calibrated. The master will be notified of an overvoltage event via the SO pin if the device status is selected. Overvoltage detection and notification occurs regardless of whether the gauge(s) are enabled or disabled. OVERCURRENT FAULT REQUIREMENTS Output currents are limited to safe levels allowing the device to rely on thermal shutdown to protect itself. UNDERVOLTAGE FAULT REQUIREMENTS Undervoltage VPWR conditions may result in uncertain pointer positions. Therefore, the internal clock and the pointer position may require re-calibration. The state machine continues with VPWR voltage levels as low as 4.0 V; however, the coil voltages may be clipped. The master can be notified of an undervoltage event via the SO pin. Undervoltage detection and notification are disabled if both outputs are disabled. RESET (SLEEP MODE) The device can reset internally or externally. If the VDD level falls below the VDDUV level (refer to the Static Electrical Characteristics table under POWER INPUT, page 5), the device resets and powers up in the Default mode. Similarly, If the RST pin is driven to a logic [0], the device resets to its default state. The device consumes the least amount of current (IDD and IPWR) when the RST pin is logic 0]. This is also referred to as the Sleep mode.

users with some of its capabilities. Table 22. 33970 Setup, Configuration, and Usage Example

1 PECCR (a) Enable Gauges

2 RTZCR (a) Set RTZ Full Step Time

3 POS0R (a) Move pointer to position 12 prior to RTZ Table 9 (page 16)

4 POS1R (a) Move pointer to position 12 prior to RTZ Table 10 (page 16)

5 PECCR (a) Send null command to see if gauges have moved

6 RTZ (a) Return one gauge at a time to the zero stop using RTZ command

will be used if characterizing the RTZ.

32 Freescale Semiconductor

7 PECCR (a) Check the Status of the RTZ by sending t he null command to monitor SO bit RTZ0, RTZ1

than the first, a new RTZCR command may be required to change the Full Step time.

9 PECCR (a) Check the Status of the RTZ by sending t he null command to monitor SO, bit RTZ1 (OD3)

10 VELR (a) Change the maximum velocity of the gauge

11 POS0R (a) Position Gauge 0 pointer

12 POS1R (a) Position Gauge 1 pointer

13 POS0R (a) Return the pointers close to zero position using POS0R Table 9 (page 16)

14 POS1R (c) Return the pointers close to zero position using POS1R Table 10 (page 16)

Table 22. 33970 Setup, Configuration, and Usage Example (continued)

15 PECCR (f) Send null command to see if gauges have moved

16 RTZ (a) Return one gauge at a time to the zero stop using RTZ command

17 PECCR (a) Check the status of the RTZ by sendi ng the null command to monitor SO bit RTZ0

19 PECCR (a) Check the status of the RTZ by sendi ng the null command to monitor SO bit RTZ1

20 PECCR (a) Disable both gauges and go to standby

Analog Integrated Circuit Device Data

34 Freescale Semiconductor

For the most current package revision, visit www.freescale.com and perform a keyword search using the “98A” listed below. DW SUFFIX 24-PIN PLASTIC PACKAGE 98ASB42344B ISSUE F EG SUFFIX (Pb-FREE)

Analog Integrated Circuit Device Data Freescale Semiconductor 35 33970

REVISION HISTORY

REVISION DATE DESCRIPTION OF CHANGES 2.0 8/2006 • Implemented Revision History page

• Converted to Freescale format
• Corrected Symbol notation for Microstep Output (Measured Across Coil Outputs) SIN0,1, ± (COS0,1, ±) (refer to Table 1) and Output Flyback Clamp (10)
• Added maximum pointer calculation on page 16
• Corrected detect threshold upper range from 4081 to 1009
• Changed internal clock variation from 35% to 70%
• Changed EMF to flux on page 28
• Added MCZ33970EG/R2 to the Ordering Information block 3.0 1/2007 • Revised Internal Block Diagram to enhance readability
• Added parameter Peak Package Reflow Temperature During Reflow (4), (5) on page 4 and notes (4) and (5)
• Added ADC Gain (10), (13) to Static Elecrtrical Characteristics table.
• Made wording additions to Address 101 — Gauge Return to Zero Configuration Register on page 17 and RC12:RC11 = M on page 18
• Added RTZ Accumulator (Typical) on page 21 and accompanying text

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