33931 FREESCALE | Alldatasheet

Document overview

  • Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 21

Technical content

Features

  • 8 . 0 V to 28 V continuous operation (transient operation from

5.0 V to 40 V)

  • 235 mΩ maximum RDS(ON) @ Tj=150°C (each H-bridge MOSFET)
  • 3 . 0 V and 5.0 V TTL / CMOS logic compatible inputs
  • Over-current limiting (regulation) via internal constant-off-time PWM
  • Output short-circuit protection (short to VPWR or GND)
  • Temperature-dependant current-limit threshold reduction
  • All inputs have an internal source/sink to define the default (floating input) states
  • Sleep mode with current draw < 50 µA (each half with inputs floating or set to match default logic states)

Figure 1. MC33931 Simplified Application Diagram

ORDERING INFORMATION

Range (TA) Package MC33931VW/R2 -40°C to 125°C 44 HSOP VW SUFFIX (PB-FREE) 98ARH98330A 44-PIN HSOP WITH PROTRUDING HEAT SINK SF FB IN1 IN2 EN/D2 VPWR CCP OUT1 OUT2 PGND AGND MCU 33931 VPWRVDD MOTOR

2 Freescale Semiconductor

Figure 2. 33931 Simplified Internal Block Diagram

Figure 3. 33931 Pin Connections Table 1. 33931 Pin Definitions A functional description of each pin can be found in the Functional Description section beginning on page 11.

1 D1 Logic Input Disable Input 1

input with ~80 μA source so default condition = disabled.

2 FB Analog

directly soldered down to a wide, thick, low resistance supply plane on the PCB. H-bridge Output 1 Source of high side MOSFET1 and drain of low side MOSFET1. H-bridge Output 2 Source of high side MOSFET2 and drain of low side MOSFET2.

23 N/C

4 Freescale Semiconductor

41 CCP Analog

capacitor is required for the proper performance of the device.

44 SF Logic

heatsinking path for the device. Table 1. 33931 Pin Definitions (continued) A functional description of each pin can be found in the Functional Description section beginning on page 11.

Analog Integrated Circuit Device Data Freescale Semiconductor 5 33931

ELECTRICAL CHARACTERISTICS

Table 2. Maximum Ratings permanent damage to the device. These parameters are not production tested.

  1. Device will survive repetitive transient over-v oltage conditions for durations not to exceed 500 ms @ duty cycle not to exceed 10%.

External protection is required to prevent device damage in case of a reverse battery condition.

  1. Exceeding the maximum input voltage on IN1, IN2, EN/ D2 or D1 may cause a malfunction or permanent damage to the device.
  2. Exceeding the pull-up resistor voltage on the open drain SF pin may cause permanent damage to the device.
  3. Continuous output current capability is dependent on suffi cient package heatsinking to keep junction temperature ≤ 150°C.
  4. ESD testing is performed in accordance with the Human Body Model (C ZAP = 100 pF, RZAP = 1500 Ω), Machine Model (CZAP = 200 pF,

RZAP = 0 Ω), and the Charge Device Model (CDM), Robotic (CZAP = 4.0 pF).

  1. The limiting factor is junction temperatur e, taking into account the power dissipation, thermal resistance, and heat sinking provided. Brief
  2. Pin soldering temperature limit is for 10 seconds maximum dura tion. Not designed for immersion soldering. Exceeding these limits may

cause malfunction or permanent damage to the device.

  1. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow

and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.

  1. Exposed heatsink pad plus the power and ground pins comprise the main heat conduction paths. The actual RθJB (junction-to-PC board)

< 5.0°C/W for maximum current at 70°C ambient. Module thermal design must be planned accordingly.

Analog Integrated Circuit Device Data

6 Freescale Semiconductor

STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics values noted reflect the approximate parameter means at TA = 25°C under nominal conditions, unless otherwise noted.

  1. Device specifications are char acterized over the range of 8.0 V ≤ VPWR ≤ 28 V. Continuous operation above 28 V may degrade device

reliability. Device is operational down to 5.0 V, but below 8.0 V the output resistance may increase by 50 percent.

  1. Device will survive the tr ansient over-voltage indicated for a maximum duration of 500 ms. Transient not to be repeated more than once
  2. I PWR(SLEEP) is with Sleep Mode activated and EN/ D2, = logic [0], and IN1, IN2, D1 = logic [1] or with these inputs left floating.

Analog Integrated Circuit Device Data Freescale Semiconductor 7 33931 STATIC ELECTRICAL CHARACTERISTICS POWER OUTPUTS OUT1, OUT2 Output-ON Resistance(14), ILOAD = 3.0 A VPWR = 8.0 V, TJ = 25°C VPWR = 8.0 V, TJ = 150°C VPWR = 5.0 V, TJ = 150°C RDS(ON) 120 235 325 mΩ Output Current Regulation Threshold TJ < TFB TJ ≥ TFB (Foldback Region - see Figure 9 and Figure 11)(13) ILIM 5.2 6.5 4.2 8.0 A High Side Short Circuit Detection Threshold (Short Circuit to Ground)(13) ISCH 11 13 16 A Low Side Short Circuit Detection Threshold (Short Circuit to VPWR)(13) ISCL 9.0 11 14 A Output Leakage Current(15), Outputs off, VPWR = 28 V VOUT = VPWR VOUT = Ground IOUTLEAK –60 100 μA Output MOSFET Body Diode Forward Voltage Drop, IOUT = 3.0 A VF – – 2.0 V Over-temperature Shutdown(13) Thermal Limit @ TJ Hysteresis @ TJ TLIM THYS 175 200 Current Foldback at TJ (13) TFB 165 – 185 °C Current Foldback to Thermal Shutdown Separation(13) TSEP 10 – 15 °C HIGH SIDE CURRENT SENSE FEEDBACK Feedback Current (pin FB sourcing current)(16) I OUT = 0 mA I OUT = 300 mA I OUT = 500 mA I OUT = 1.5 A I OUT = 3.0 A I OUT = 6.0 A I FB 0.0 0.0 0.35 2.86 5.71 11.43 270 0.775 3.57 7.14 14.29 750 1.56 4.28 8.57 17.15 μA μA mA mA mA mA STATUS FLAG(17) Status Flag Leakage Current(18) V SF = 5.0 V ISFLEAK – – 5.0 μA Status Flag SET Voltage(19) I SF = 300 µA VSFLOW – – 0.4 V Notes 13. This parameter is Guaranteed By Design. 14. Output-ON resistance as measured from output to VPWR and from output to GND. 15. Outputs switched OFF via D1 or EN/ D2. 17. Status Flag output is an open drain output requiring a pull-up resistor to logic VDD. 18. Status Flag Leakage Current is measured with Status Flag HIGH and not SET. 19. Status Flag Set Voltage measured with Status Flag LOW and SET with I SF = 300 μA. Maximum allowable sink current from this pin is < 500 μA . Maximum allowable pull-up voltage < 7.0 V. Table 3. Static Electrical Characteristics (continued) values noted reflect the approximate parameter means at TA = 25°C under nominal conditions, unless otherwise noted.

Analog Integrated Circuit Device Data

8 Freescale Semiconductor

DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 4. Dynamic Electrical Characteristics values noted reflect the approximate parameter means at TA = 25°C under nominal conditions, unless otherwise noted.

  1. The maximum PWM frequency should be limited to frequencies < 11 kHz in order to allow the internal high side driver circuitry time to

fully enhance the high side MOSFETs.

  1. The internal current limit circuitry produces a constant-OFF -time Pulse Width Modulation of the output current. The output load’s

frequency during current limit.

  1. * Output Delay is the time duration from 1.5 V on the IN1 or IN2 input signal to the 20% or 80% point (dependent on the transition direction)

output response signal. See Figure 4, page 9.

  1. The time during which the internal constant-OFF time PWM current regulation circuit has tri-stated the output bridge.
  2. The time during which the current regulation threshold is i gnored so that the short-circuit detection threshold comparators may have time
  3. * Disable Delay Time measurement is defined in Figure 5, page 9.
  4. Rise Time is from the 10% to the 90% level and Fall Time is from the 90% to the 10% level of the output signal with VPWR = 14 V, RLOAD

= 3.0 ohm. See Figure 6, page 9.

  1. Load currents ramping up to the current r egulation threshold become limited at the ILIM value (see Figure 7). The short-circuit currents

is limited to non-repetitive transient events of duration not to exceed 30 seconds (see Figure 9).

  1. Parameter is Guaranteed By Design.

Analog Integrated Circuit Device Data

10 Freescale Semiconductor

Figure 8. Short-circuit Detection Turn-OFF Time tFAULT Figure 9. Output Current Limiting Foldback Region Current Limit Threshold Foldback.

Analog Integrated Circuit Device Data Freescale Semiconductor 11 33931 FUNCTIONAL DESCRIPTION INTRODUCTION FUNCTIONAL DESCRIPTION INTRODUCTION Numerous protection and operational features (speed, torque, direction, dynamic breaking, PWM control, and closed-loop control) make the 33931 a very attractive, cost- effective solution for controlling a broad range of small DC motors. The 33931 outputs are capable of supporting peak DC load currents of up to 5.0 A from a 28 V VPWR source. An internal charge pump and gate drive circuitry are provided that can support external PWM frequencies up to 11 kHz. The 33931 has an analog feedback (current mirror) output pin (the FB pin) that provides a constant-current source ratioed to the active high side MOSFETs’ current. This can be used to provide “real time” monitoring of output current to facilitate closed-loop operation for motor speed/torque control, or for the detection of open load conditions. Two independent inputs, IN1 and IN2, provide control of the two totem-pole half-bridge outputs. Two independent disable inputs, D1 and EN/D2, provide the means to force the H-bridge outputs to a high-impedance state (all H-bridge switches OFF). The EN/D2 pin also controls an enable function that allows the IC to be placed in a power-conserving Sleep mode. The 33931 has output current limiting (via constant OFF- time PWM current regulation), output short-circuit detection with latch-OFF, and over-temperature detection with latch- OFF. Once the device is latched-OFF due to a fault condition, either of the Disable inputs (D1 or EN/D2), or VPWR must be “toggled” to clear the status flag. Current limiting (Load Current Regulation) is accomplished by a constant-OFF time PWM method using current limit threshold triggering. The current limiting scheme is unique in that it incorporates a junction temperature- dependent current limit threshold. This means that the current limit threshold is “reduced to around 4.2 A” as the junction temperature increases above 160°C. When the temperature is above 175°C, over-temperature shutdown (latch-OFF) will occur. This combination of features allows the device to continue operating for short periods of time (< 30 seconds) with unexpected loads, while still retaining adequate protection for both the device and the load. FUNCTIONAL PIN DESCRIPTION POWER GROUND AND ANALOG GROUND (PGND AND AGND) The power and analog ground pins should be connected together with a very low-impedance connection. POSITIVE POWER SUPPLY (VPWR) VPWR pins are the power supply inputs to the device. All VPWR pins must be connected together on the printed circuit board with as short as possible traces, offering as low an impedance as possible between pins. STATUS FLAG (SF) This pin is the device fault status output. This output is an active LOW open drain structure requiring a pull-up resistor to VDD. The maximum VDD is < 7.0 V. Refer to Table 5, Truth Table, page 15 for the SF Output status definition. INPUT 1,2 AND DISABLE INPUT 1 (IN1, IN2, AND D1) These pins are input control pins used to control the outputs. These pins are 3.0 V/ 5.0 V CMOS-compatible inputs with hysteresis. IN1 and IN2 independently control OUT1 and OUT2, respectively. D1 input is used to tri-state disable the H-bridge outputs. When D1 is SET (D1 = logic HIGH) in the disable state, outputs OUT1 and OUT2 are both tri-state disabled; however, the rest of the device circuitry is fully operational and the supply IPWR(STANDBY) current is reduced to a few mA. Refer to Table 3, Static Electrical Characteristics, page 6. H-BRIDGE OUTPUT (OUT1, OUT2) These pins are the outputs of the H-bridge with integrated free-wheeling diodes. The bridge output is controlled using the IN1, IN2, D1, and EN/ D2 inputs. The outputs have PWM current limiting above the ILIM threshold. The outputs also have thermal shutdown (tri-state latch-OFF) with hysteresis as well as short circuit latch-OFF protection. A disable timer (time t b) is incorporated to distinguish between load currents that are higher than the ILIM threshold and short circuit currents. This timer is activated at each output transition. CHARGE PUMP CAPACITOR (CCP) This pin is the charge pump output pin and connection for the external charge pump reservoir capacitor. The allowable value is from 30 nF to 100 nF. This capacitor must be connected from the CCP pin to the VPWR pin. The device cannot operate properly without the external reservoir capacitor. ENABLE INPUT/DISABLE INPUT 2 (EN/D2) The EN/D2 pin performs the same function as D1 pin, when it goes to a logic LOW the outputs are immediately tri- stated. It is also used to place the device in a Sleep mode so as to consume very low currents. When the EN/D2 pin voltage is a logic LOW state, the device is in the Sleep mode.

Analog Integrated Circuit Device Data

12 Freescale Semiconductor

FUNCTIONAL PIN DESCRIPTION The device is enabled and fully operational when the EN pin voltage is logic HIGH. An internal pull-down resistor maintains the device in Sleep mode in the event EN is driven through a high-impedance I/O or an unpowered microcontroller, or the EN/ D2 input becomes disconnected. FEEDBACK (FB) The 33931 has a feedback output (FB) for “real time” monitoring of H-bridge high side output currents to facilitate closed-loop operation for motor speed and torque control. The FB pin provides current sensing feedback of the H-bridge high side drivers. When running in the forward or reverse direction, a ground-referenced 0.24% of load current is output to this pin. Through the use of an external resistor to ground, the proportional feedback current can be converted to a proportional voltage equivalent and the controlling microcontroller can “read” the current proportional voltage with its analog-to-digital converter (ADC). This is intended to provide the user with only first-order motor current feedback for motor torque control. The resistance range for the linear operation of the FB pin is 100 Ω < RFB < 300 Ω. If PWM-ing is implemented using the disable pin input (only D1), a small filter capacitor (~1.0 µF) may be required in parallel with the RFB resistor to ground for spike suppression.

Figure 10. Functional Internal Block Diagram An on-chip voltage regulator supplies the internal logic. provides detection and protection for the output drivers. Output under-voltage protection shuts down the MOSFETS. output MOSFET for maximum accuracy and dependability.

14 Freescale Semiconductor

Figure 11. Operating States

Figure 12. 33931 Power Stage Operation Table 5. Truth Table H = HIGH, X = HIGH or LOW, and Z = High-impedance. All output power transistors are switched off.

  1. In the event of an under-voltage condition, the outputs tr i-state and status flag is SET logic LOW. Upon under-voltage
  2. When a short-circuit or over-temperat ure condition is detected, the power outputs are tri-state latched-OFF independent of

16 Freescale Semiconductor

gear-reduction train to be handled. permitted only for non-repetitive durations < 30 seconds. prolonged operation in the current-foldback region. the over-temperature threshold limit minus the hysteresis. will also reset the 33931 from the fault condition. would likely tri-state simultaneously due to the disable logic. Figure 13. Avalanche Protection

Figure 14. 33931 Typical Application Schematic

Analog Integrated Circuit Device Data

18 Freescale Semiconductor

For the most current package revision, visit www.freescale.com and perform a keyword search using the 98Axxxxxxxxx listed below. VW SUFFIX 44-PIN 98ARH98330A REVISION B

Analog Integrated Circuit Device Data Freescale Semiconductor 19 33931 PACKAGING PACKAGE DIMENSIONS VW SUFFIX 44-PIN 98ARH98330A REVISION B

Analog Integrated Circuit Device Data

20 Freescale Semiconductor

REVISION HISTORY

1.0 2/2008 • Initial Release 2.0 12/2008 • Updated Freescale for and style

  • Removed PC33931VW/R2 from the ordering information and added MC33931VW/R2
  • Changes Max R DS(ON) from 225 to 235 mOhm in the document
  • Changed Peak Package Reflow Temperature During Reflow(7),(8)
  • Changed Approximate Junction-to-Case Thermal Resistance(9)
  • I n SHORT-CIRCUIT PROTECTION, changed D2 to EN/D2

Rev.2.0 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”, must be validated for each customer application by customer’s technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc., 2008. All rights reserved. How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. Technical Information Center, EL516

2100 East Elliot Road

Tempe, Arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.com/support Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7

81829 Muenchen, Germany

+44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) www.freescale.com/support Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo 153-0064 Japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com Asia/Pacific: Freescale Semiconductor China Ltd. Exchange Building 23F No. 118 Jianguo Road Chaoyang District Beijing 100022 China +86 10 5879 8000 support.asia@freescale.com For Literature Requests Only: Freescale Semiconductor Literature Distribution Center P .O. Box 5405 Denver, Colorado 80217 1-800-441-2447 or 303-675-2140 Fax: 303-675-2150 LDCForFreescaleSemiconductor@hibbertgroup.com