33910

33910 FREESCALE | Alldatasheet

Document overview

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• PDF pages: 44

Technical content

Features

• Two 60mA high side switches
• One high voltage analog/logic input
• Full-duplex SPI at frequencies up to 4MHz
• LIN transceiver capable of up to 100kbps with wave shaping
• Configurable window watchdog
• 5.0V low drop regulator with fault detection and low voltage reset (LVR) circuitry
• Switched/protected 5.0V output (used for Hall sensors)
• Pb-free packaging designated by suffix code AC

Figure 1. 33910 Simplified Application Diagram

ORDERING INFORMATION

Range (TA) Package MC33910BAC/R2 - 40°C to 125°C 32-LQFP MC34910BAC/R2 - 40°C to 85°C AC SUFFIX (Pb-FREE) 98ASH70029A 32-PIN LQFP 33910 MCU LIN INTERFACE VS1 VS2 VSENSE HS1 HVDD HS2 WDCONFAGND LGND PGND LIN VDD PWMIN ADOUT0 MOSI MISO SCLK CS RXD TXD IRQ RST VBAT

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Figure 2. 33910 Simplified Internal Block Diagram

Figure 3. 33910 Pin Connections Table 1. 33910 Pin Definitions A functional description of each pin can be found in the Functional Pin Description section beginning on page 20.

1 RXD Receiver Output This pin is the receiver output of the LIN interface which reports the state of

the bus voltage to the MCU interface. 3 MISO SPI Output SPI data output. When CS is high, the pin is in the high-impedance state. 4 MOSI SPI Input SPI data input. 5 SCLK SPI Clock SPI clock Input. 6 CS SPI Chip Select SPI chip select input pin. CS is active low. 7 ADOUT0 Analog Output Pin 0 Analog multiplexer output. 8 PWMIN PWM Input High side pulse width modulation input.

9 RST Internal Reset I/O Bidirectional reset I/O pin - driven low when any internal reset source is

asserted. RST is active low.

10 IRQ Internal Interrupt

Normal and Normal Request Modes.

17 NC*

18 PGND

20 NC*

21 NC*

22 NC*

24 HS2

19 NC*

25 HS1

26 VS2

29 VSENSE

30 HVDD

32 AGND

31 VDD

27 VS1

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12 WDCONF Watchdog

13 LIN LIN Bus This pin represents the single-wire bus transmitter and receiver. analog via the analog multiplexer. 24, 25 HS2, HS1 High Side Outputs High side switch outputs.

30 HVDD Hall Sensor Supply

31 VDD Voltage Regulator

32 AGND Analog Ground Pin This pin is the device analog ground connection.

1. When used as digital input, a series 33k Ω resistor must be used to protect against automotive transients.
2. Reverse battery protection series diodes must be us ed externally to protect the internal circuitry.
3. This pin can be connected directly to the battery line for vo ltage measurements. The pin is self protected against reverse battery

connections. It is strongly recommended to connect a 10kΩ resistor in series with this pin for protection purposes.

1. External capacitor (1µF < C < 10µF; 0.1 Ω < ESR < 5Ω) required.
2. External capacitor (2µF < C < 100µF; 0.1 Ω < ESR < 10Ω) required.

A functional description of each pin can be found in the Functional Pin Description section beginning on page 20.

Analog Integrated Circuit Device Data Freescale Semiconductor 5 33910

ELECTRICAL CHARACTERISTICS

Table 2. Maximum Ratings permanent damage to the device.

1. Exceeding voltage limits on spec ified pins may cause a malfunction or permanent damage to the device.
2. Extended voltage range for programming purpose only.
3. Testing is performed in accordanc e with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω), the Machine Model (CZAP = 200 pF,

RZAP = 0Ω), and the Charge Device Model, Robotic (CZAP = 4.0pF).

1. Special configuration recommended / mandatory for marked NC pins. Please refer to the typical application shown on page 40.

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Operating Ambient Temperature(10) 33910 34910 TA -40 to 125 -40 to 85 Operating Junction Temperature(10) TJ -40 to 150 °C Storage Temperature TSTG -55 to 150 °C Thermal Resistance, Junction to Ambient Natural Convection, Single Layer board (1s)(11), (12) Natural Convection, Four Layer board (2s2p)(11), (13) RθJA °C/W Thermal Resistance, Junction to Case(14) RθJC 23 °C/W Peak Package Reflow Temperature During Reflow(15), (16) TPPRT Note 16 °C Notes 10. The limiting factor is junction temperat ure; taking into account the power dissipation, thermal resistance, and heat sinking. 11. Junction temperature is a function of on-chip power dissipat ion, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 12. Per JEDEC JESD51-2 with the singl e layer board (JESD51-3) horizontal. 13. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal. 14. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). 15. Pin soldering temperature limit is for 10 seconds maximum du ration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. 16. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics. Table 2. Maximum Ratings (continued) permanent damage to the device.

Analog Integrated Circuit Device Data Freescale Semiconductor 7 33910 STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics conditions, unless otherwise noted.

1. Device is fully functional . All features are operating.
2. Total current (I VS1 + IVS2) measured at GND pins excluding all loads, Cyclic Sense disabled.
3. Total I DD current (including loads) below 100µA.
4. Stop and Sleep Mode currents will increase if V SUP exceeds13.5V.
5. This parameter is guaranteed by proc ess monitoring but, not production tested.
6. The flag is set during power up sequence. To clear the flag, a SPI read must be performed.

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STATIC ELECTRICAL CHARACTERISTICS VOLTAGE REGULATOR(23) (VDD) Normal Mode Output Voltage 1.0mA < IVDD < 50mA; 5.5V < VSUP < 27V VDDRUN 4.75 5.00 5.25 V Normal Mode Output Current Limitation IVDDRUN 60 110 200 mA Dropout Voltage(24) IVDD = 50mA VDDDROP – 0.1 0.25 V Stop Mode Output Voltage IVDD < 5mA VDDSTOP 4.75 5.0 5.25 V Stop Mode Output Current Limitation IVDDSTOP 6.0 12 36 mA Line Regulation Normal Mode, 5.5V < VSUP < 18V; IVDD = 10mA Stop Mode, 5.5V < VSUP < 18V; IVDD = 1.0mA LRRUN LRSTOP 5.0 mV Load Regulation Normal Mode, 1.0mA < IVDD < 50mA Stop Mode, 0.1mA < IVDD < 5mA LDRUN LDSTOP mV Over-temperature Prewarning (Junction)(25) Interrupt generated, Bit VDDOT Set TPRE 110 125 140 Over-temperature Pre-Warning hysteresis(25) TPRE_HYS – 10 – °C Over-temperature Shutdown Temperature (Junction)(25) TSD 155 170 185 °C Over-temperature Shutdown hysteresis(25) TSD_HYS – 10 – °C HALL SENSOR SUPPLY OUTPUT(26) (HVDD) VDD Voltage matching HVDDACC = (HVDD-VDD) / VDD * 100% IHVDD = 15mA HVDDACC -2.0 – 2.0 Current Limitation IHVDD 20 30 50 mA Dropout Voltage IHVDD = 15mA; IVDD = 5mA HVDDDROP – 160 300 mV Line Regulation IHVDD = 5mA; IVDD = 5mA LRHVDD – 25 40 mV Load Regulation 1mA > IHVDD > 15mA; IVDD = 5mA LDHVDD – 10 20 mV Notes 23. Specification with external capacitor 2µF < C < 100µF and 100m Ω ≤ ESR ≤ 10Ω. 24. Measured when voltage has dropped 250mV below its nominal Value (5V). 25. This parameter is guaranteed by pr ocess monitoring but, not production tested. 26. Specification with external capacitor 1µF < C < 10µF and 100m Ω ≤ ESR ≤ 10Ω. Table 3. Static Electrical Characteristics (continued) conditions, unless otherwise noted.

Analog Integrated Circuit Device Data Freescale Semiconductor 9 33910 STATIC ELECTRICAL CHARACTERISTICS RST INPUT/OUTPUT PIN (RST) VDD Low Voltage Reset Threshold VRSTTH 4.3 4.5 4.7 V Low-State Output Voltage IOUT = 1.5mA; 3.5V ≤ VSUP ≤ 27V VOL 0.0 – 0.9 V High-State Output Current (0 < VOUT < 3.5V) IOH -150 -250 -350 µA Pull-down Current Limitation (internally limited) VOUT = VDD IPD_MAX 1.5 – 8.0 mA Low-State Input Voltage VIL -0.3 – 0.3 x VDD V High-State Input Voltage VIH 0.7 x VDD – VDD + 0.3 V MISO SPI OUTPUT PIN (MISO) Low-State Output Voltage IOUT = 1.5mA VOL 0.0 – 1.0 V High-State Output Voltage IOUT = -250µA VOH VDD - 0.9 – VDD V Tri-state Leakage Current

0 V ≤ VMISO ≤ VDD

-10 – 10 µA SPI INPUT PINS (MOSI, SCLK, CS) Low-state Input Voltage VIL -0.3 – 0.3 x VDD V High-state Input Voltage VIH 0.7 x VDD – VDD + 0.3 V MOSI, SCLK Input Current 0 ≤ VIN ≤ VDD IIN -10 – 10 µA CS Pull-up current 0 < VIN < 3.5V IPUCS 10 20 30 µA INTERRUPT OUTPUT PIN (IRQ) Low-state Output Voltage IOUT = 1.5 mA VOL 0.0 – 0.8 V High-state Output Voltage IOUT = -250µA VOH VDD - 0.8 – VDD V Leakage current VDD ≤ VOUT ≤ 10V VOH – – 2.0 mA PULSE WIDTH MODULATION INPUT PIN (PWMIN) Low-state Input Voltage VIL -0.3 – 0.3 x VDD V High-state Input Voltage VIH 0.7 x VDD – VDD + 0.3 V Pull-up current 0 < VIN < 3.5V IPUPWMIN 10 20 30 µA conditions, unless otherwise noted.

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STATIC ELECTRICAL CHARACTERISTICS HIGH SIDE OUTPUT HS1 AND HS2 PINS (HS1, HS2) Output Drain-to-Source On Resistance TJ = 25°C, ILOAD = 50mA; VSUP > 9.0V TJ = 150°C, ILOAD = 50mA; VSUP > 9.0V(27) TJ = 150°C, ILOAD = 30mA; 5.5V < VSUP < 9.0V(27) RDS(ON) 7.0 Ω Output Current Limitation(28) 0V < VOUT < VSUP - 2.0V ILIMHS1 60 120 250 mA Open Load Current Detection(29) IOLHSx – 5.0 7.5 mA Leakage Current (-0.2V < VHSx < VS2 + 0.2V) ILEAK – – 10 µA Short Circuit Detection Threshold(30) 5.5V < VSUP < 27V VTHSC VSUP - 2 – – V Over-temperature Shutdown(31), (32) THSSD 150 165 180 °C Over-temperature Shutdown Hysteresis(32) THSSD_HYS – 10 – °C L1 INPUT PIN (L1) Low Detection Threshold 5.5V < VSUP < 27V VTHL 2.0 2.5 3.0 V High Detection Threshold 5.5V < VSUP < 27V VTHH 3.0 3.5 4.0 V Hysteresis 5.5V < VSUP < 27V VHYS 0.5 1.0 1.5 V Input Current(33) -0.2V < VIN < VS1 IIN -10 – 10 µA Analog Input Impedance(34) RL1IN 800 1550 – kΩ Analog Input Divider Ratio (RATIOL1 = VL1 / VADOUT0) L1DS (L1 Divider Select) = 0 L1DS (L1 Divider Select) = 1 RATIOL1 0.95 3.42 1.0 3.6 1.05 3.78 Analog Output Offset Ratio L1DS (L1 Divider Select) = 0 L1DS (L1 Divider Select) = 1 VRATIOL1- OFFSET -80 -22 0.0 0.0 mV Analog Inputs Matching L1DS (L1 Divider Select) = 0 L1DS (L1 Divider Select) = 1 L1MATCHING 100 100 104 104 Notes 27. This parameter is production tested up to T A = 125°C and guaranteed by process monitoring up to TJ = 150°C. 28. When over-current occurs, the high side stays ON with li mited current capability and the HS1CL flag is set in the HSSR. 29. When open-load occurs, the flag (HS1OP) is set in the HSSR . 30. When short circuit occurs and if HVSE flag is enabled, HS1 automatic shutdown. 31. When over-temperature shutdown occurs, both High Sides are turned off. All flags in HSSR are set. 32. Guaranteed by characterization but, not production tested 33. Analog multiplexer input di sconnected from L1 input pin. 34. Analog multiplexer input connected to L1 input pin. conditions, unless otherwise noted.

Analog Integrated Circuit Device Data Freescale Semiconductor 11 33910 STATIC ELECTRICAL CHARACTERISTICS WINDOW WATCHDOG CONFIGURATION PIN (WDCONF) External Resistor Range REXT 20 – 200 kΩ Watchdog Period Accuracy with External Resistor (Excluding Resistor Accuracy)(35) WDACC -15 – 15 % ANALOG MULTIPLEXER Internal Chip Temperature Sense Gain STTOV – 10.5 – mV/K VSENSE Input Divider Ratio (RATIOVSENSE = VVSENSE / VADOUT0) 5.5V < VSUP < 27V RATIOVSENSE 5.0 5.25 5.5 VSENSE Output Related Offset -40°C < TA < -20°C OFFSETVSENS E -30 -45 mV ANALOG OUTPUT (ADOUT0) Maximum Output Voltage -5mA < IO < 5mA VOUT_MAX VDD - 0.35 – VDD V Minimum Output Voltage -5mA < IO < 5mA VOUT_MIN 0.0 – 0.35 V RXD OUTPUT PIN (LIN PHYSICAL LAYER) (RXD) Low-state Output Voltage IOUT = 1.5 mA VOL 0.0 – 0.8 V High-state Output Voltage IOUT = -250µA VOH VDD-0.8 – VDD V TXD INPUT PIN (LIN PHYSICAL LAYER) (TXD) Low-state Input Voltage VIL -0.3 – 0.3 x nVDD V High-state Input Voltage VIH 0.7 x VDD – VDD + 0.3 V Pin Pull-up Current, 0 < VIN < 3.5V IPUIN 10 20 30 µA Notes 35. Watchdog timing period ca lculation formula: tPWD [ms] = 0.466 * (REXT - 20) + 10 (REXT in kΩ) conditions, unless otherwise noted.

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STATIC ELECTRICAL CHARACTERISTICS LIN PHYSICAL LAYER, TRANSCEIVER (LIN)(36) Output Current Limitation Dominant State, VBUS = 18V IBUSLIM 40 120 200 mA Leakage Output Current to GND Dominant State; VBUS = 0V; VBAT = 12V Recessive State; 8V < VBAT < 18V; 8V < VBUS < 18V; VBUS ≥ VBAT GND Disconnected; GNDDEVICE = VSUP; VBAT = 12V; 0 < VBUS < 18V VBAT disconnected; VSUP_DEVICE = GND; 0 < VBUS < 18V IBUS_PAS_DOM IBUS_PAS_REC IBUS_NO_GND IBUS -1.0 -1.0 1.0 100 mA µA mA µA Receiver Input Voltages Receiver Dominant State Receiver Recessive State Receiver Threshold Center (V TH_DOM + VTH_REC)/2 Receiver Threshold Hysteresis (VTH_REC - VTH_DOM) VBUSDOM VBUSREC VBUS_CNT VHYS 0.6 0.475 0.5 0.4 0.525 0.175 VSUP LIN Transceiver Output Voltage Recessive State, TXD HIGH, IOUT = 1.0 µA Dominant State, TXD LOW, 500Ω External Pull-up Resistor, LDVS = Dominant State, TXD LOW, 500Ω External Pull-up Resistor, LDVS = VLIN_REC VLIN_DOM_0 VLIN_DOM_1 VSUP-1 1.1 1.7 1.4 V LIN Pull-up Resistor to VSUP RSLAVE 20 30 60 kΩ Over-temperature Shutdown(37) TLINSD 150 165 180 °C Over-temperature Shutdown Hysteresis TLINSD_HYS – 10 – °C Notes 36. Parameters guaranteed for 7.0V ≤ VSUP ≤ 18V. 37. When Over-temperature shutdown occurs, the LIN bus goes in recessive state and the flag LINOT in LINSR is set. conditions, unless otherwise noted.

Analog Integrated Circuit Device Data Freescale Semiconductor 13 33910 DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 4. Dynamic Electrical Characteristics conditions, unless otherwise noted.

1. This parameter is guaranteed by pr ocess monitoring but, not production tested.
2. Watchdog timing period ca lculation formula: tPWD [ms] = 0.466 * (REXT - 20) + 10 (REXT in kΩ)

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DYNAMIC ELECTRICAL CHARACTERISTICS L1 INPUT Wake-up Filter Time t WUF 8.0 20 38 µs STATE MACHINE TIMING Delay Between CS LOW-to-HIGH Transition (at End of SPI Stop Command) and Stop Mode Activation(40) t STOP – – 5.0 µs Normal Request Mode Timeout (see Figure 12, page 19) t NR TOUT 110 150 205 ms Delay Between SPI Command and HS Turn On(41) 9V < VSUP < 27V t S-ON – – 10 µs Delay Between SPI Command and HS Turn Off(41) 9V < VSUP < 27V t S-OFF – – 10 µs Delay Between Normal Request and Normal Mode After a Watchdog Trigger Command (Normal Request Mode)(40) t SNR2N – – 10 µs Delay Between CS Wake-up (CS LOW to HIGH) in Stop Mode and: Normal Request Mode, VDD ON and RST HIGH First Accepted SPI Command t WUCS t WUSPI 9.0 N/A µs Minimum Time Between Rising and Falling Edge on the CS t 2CS 4.0 — — µs LIN PHYSICAL LAYER: DRIVER CHARACTERISTICS FOR NORMAL SLEW RATE - 20.0KBIT/SEC(42), (43) Duty Cycle 1: D1 = tBUS_REC(MIN)/(2 x tBIT), tBIT = 50µs 7.0V ≤ VSUP ≤ 18V 0.396 — — Duty Cycle 2: D2 = tBUS_REC(MAX)/(2 x tBIT), tBIT = 50µs 7.6V ≤ VSUP ≤ 18V — — 0.581 LIN PHYSICAL LAYER: DRIVER CHARACTERISTICS FOR SLOW SLEW RATE - 10.4KBIT/SEC(42),(44) Duty Cycle 3: D3 = tBUS_REC(MIN)/(2 x tBIT), tBIT = 96µs 7.0V ≤ VSUP ≤ 18V 0.417 — — µs Duty Cycle 4: D4 = tBUS_REC(MAX)/(2 x tBIT), tBIT = 96µs 7.6V ≤ VSUP ≤ 18V — — 0.590 µs Notes 40. This parameter is guaranteed by pr ocess monitoring but, not production tested. 41. Delay between turn on or off command (rising edge on CS) and HS ON or OFF, excluding rise or fall time due to external load. defined at each parameter. See Figure 6, page 17. 43. See Figure 7, page 17. 44. See Figure 8, page 17. Table 4. Dynamic Electrical Characteristics (continued) conditions, unless otherwise noted.

Analog Integrated Circuit Device Data Freescale Semiconductor 15 33910 DYNAMIC ELECTRICAL CHARACTERISTICS LIN PHYSICAL LAYER: DRIVER CHARACTERISTICS FOR FAST SLEW RATE LIN Fast Slew Rate (Programming Mode) SRFAST —2 0— V / µs LIN PHYSICAL LAYER: CHARACTERISTICS AND WAKE-UP TIMINGS(45) Propagation Delay and Symmetry(46) Propagation Delay Receiver, tREC_PD=max (tREC_PDR, tREC_PDF) Symmetry of Receiver Propagation Delay tREC_PDF - tREC_PDR t REC_PD t REC_SYM - 2.0 3.0 6.0 2.0 µs Bus Wake-up Deglitcher (Sleep and Stop Modes)(47) t PROPWL 42 70 95 µs Bus Wake-up Event Reported From Sleep Mode(48) From Stop Mode(49) t WAKE t WAKE 9.0 1500 µs TXD Permanent Dominant State Delay t TXDDOM 0.65 1.0 1.35 s PULSE WIDTH MODULATION INPUT PIN (PWMIN) PWMIN pin(50) Max. frequency to drive HS output pins fPWMIN kHz Notes signal to LIN signal threshold defined at each parameter. See Figure 6, page 17. 46. See Figure 9, page 18 47. See Figure 10, page 18 for Sleep and Figure 11, page 19 for Stop Mode. 48. The measurement is done with 1µ F capacitor and 0mA current load on VDD. The value takes into account the delay to charge the capacitor. The delay is measured between the bus wake-up threshold (VBUSWU) rising edge of the LIN bus and when VDD reaches 3.0 V. See Figure 10, page 18. The delay depends of the load and capacitor on VDD. 49. In Stop Mode, the delay is measured between the bus wake-up threshold (V BUSWU) and the falling edge of the IRQ pin. See Figure 11, page 18. 50. This parameter is guaranteed by pr ocess monitoring but, not production tested. conditions, unless otherwise noted.

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Figure 4. Test Circuit for Transient Test Pulses (LIN) Figure 5. Test Circuit for Transient Test Pulses (L1) Figure 6. Test Circuit for LIN Timing Measurements NOTE: Waveform Per ISO 7637-2. Test Pulses 1, 2, 3a, 3b. NOTE: Waveform Per ISO 7637-2. Test Pulses 1, 2, 3a, 3b.

• 1.0KΩ and 1.0nF
• 660Ω and 6.8nF
• 500Ω and 10nF VSUP TXD RXD LIN C0C0

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Figure 9. LIN Receiver Timing Figure 10. LIN Wake-up Sleep Mode Timing

0.4 VSUP

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The 33910 is designed and developed as a highly integrated and cost-effective solution for automotive and industrial applications. For automotive body electronics, the 33910 is well suited to perform keypad applications via the LIN bus. Two power switches are provided on the device configured as high side outputs. Other ports are also provided, which include a wake-up capable pin amd a Hall Sensor port supply. An internal voltage regulator provides power to a MCU device. Also included in this device is a LIN physical layer, which communicates using a single wire. This enables this device to be compatible with 3-wire bus systems, where one wire is used for communication, one for battery, and one for ground. FUNCTIONAL PIN DESCRIPTION See Table 1, 33910 Simplified Application Diagram, page 1, for a graphic representation of the various pins referred to in the following paragraphs. Also, see the pin diagram on page 3 for a description of the pin locations in the package. RECEIVER OUTPUT (RXD) The RXD pin is a digital output. It is the receiver output of the LIN interface and reports the state of the bus voltage: RXD low when LIN bus is dominant, RXD high when LIN bus is recessive. TRANSMITTER INPUT (TXD) The TXD pin is a digital input. It is the transmitter input of the LIN interface and controls the state of the bus output (dominant when TXD is Low, recessive when TXD is High). This pin has an internal pull-up to force recessive state in case the input is left floating. LIN BUS (LIN) The LIN pin represents the single-wire bus transmitter and receiver. It is suited for automotive bus systems and is compliant to the LIN bus specification 2.0. The LIN interface is only active during Normal and Normal Request Modes. SERIAL DATA CLOCK (SCLK) The SCLK pin is the SPI clock input pin. MISO data changes on the negative transition of the SCLK. MOSI is sampled on the positive edge of the SCLK. MASTER OUT SLAVE IN (MOSI) The MOSI digital pin receives SPI data from the MCU. This data input is sampled on the positive edge of SCLK. MASTER IN SLAVE OUT (MISO) The MISO pin sends data to an SPI-enabled MCU. It is a digital tri-state output used to shift serial data to the microcontroller. Data on this output pin changes on the negative edge of the SCLK. When CS is High, this pin will remain in high-impedance state. CHIP SELECT (CS) CS is a active low digital input. It must remain low during a valid SPI communication and allow for several devices to be connected in the same SPI bus without contention. A rising edge on CS signals the end of the transmission and the moment the data shifted in is latched. A valid transmission must consist of 8 bits only. While in STOP Mode a low-to-high level transition on this pin will generate a wake-up condition for the 33910. ANALOG MULTIPLEXER (ADOUT0) The ADOUT0 pin can be configured via the SPI to allow the MCU A/D converter to read the several inputs of the Analog Multiplexer, including the L1 input voltage and the internal junction temperature. PWM INPUT CONTROL (PWMIN) This digital input can control the high sides in Normal Request and Normal Mode. To enable PWM control, the MCU must perform a write operation to the high side control register (HSCR). This pin has an internal 20uA current pull-up. RESET (RST) This bidirectional pin is used to reset the MCU in case the 33910 detects a reset condition or to inform the 33910 that the MCU has just been reset. After release of the RST pin Normal Request Mode is entered. The RST pin is an active low filtered input and output formed by a weak pull-up and a switchable pull-down structure which allows this pin to be shorted either to VDD or to GND during software development without the risk of destroying the driver.

Analog Integrated Circuit Device Data Freescale Semiconductor 21 33910 FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION INTERRUPT (IRQ) The IRQ pin is a digital output used to signal events or faults to the MCU while in Normal and Normal Request Mode or to signal a wake-up from Stop Mode. This active low output will transition to high, only after the interrupt is acknowledged by a SPI read of the respective status bits. WATCHDOG CONFIGURATION (WDCONF) The WDCONF pin is the configuration pin for the internal watchdog. A resistor can be connected to this pin to configure the window watchdog period. When connected directly to ground, the watchdog will be disabled. When this pin is left open, the watchdog period is fixed to its lower precision internal default value (150ms typical). GROUND CONNECTION (AGND, PGND, LGND) The AGND, PGND and LGND pins are the Analog and Power ground pins. The AGND pin is the ground reference of the voltage regulator. The PGND and LGND pins are used for high current load return as in the LIN interface pin. Note: PGND, AGND and LGND pins must be connected together. DIGITAL/ANALOG (L1) The L1 pin is a multi purpose input. It can be used as a digital input, which can be sampled by reading the SPI and used for wake-up when 33910 is in Low Power Mode or used as analog inputs for the analog multiplexer. When used to sense voltage outside the module, a 33kohm series resistor must be used on each input. When used as a wake-up input L1 can be configured to operate in Cyclic-Sense Mode. In this mode, one of the high side switches is configured to be periodically turned on and sample the wake-up input. If a state change is detected between two cycles a wake-up is initiated. The 33910 can also wake-up from Stop or Sleep by a simple state change on L1. When used as analog input, the voltage present on the L1 pins is scaled down by an selectable internal voltage divider and can be routed to the ADOUT0 output through the analog multiplexer. Note: If L1 input is selected in the analog multiplexer, it will be disabled as digital input and remains disabled in low Power Mode. No wake-up feature is available in that condition. When the L1 input is not selected in the analog multiplexer, the voltage divider is disconnected from that input. HIGH SIDE OUTPUTS (HS1 AND HS2) These high side switches are able to drive loads such as relays or lamps. Their structure is connected to the VS2 supply pin. The pins are short-circuit protected and also protected against overheating. HS1and HS2 are controlled by SPI and can respond to a signal applied to the PWMIN input pin. The HS1 and HS2 outputs can also be used during Low Power Mode for the cyclic-sense of the wake input. POWER SUPPLY (VS1 AND VS2) Those are the battery level voltage supply pins. In an application, VS1 and VS2 pins must be protected against reverse battery connection and negative transient voltages, with external components. These pins sustain standard automotive voltage conditions such as load dump at 40V. The high side switches (HS1 and HS2) are supplied by the VS2 pin, all other internal blocks are supplied by VS1 pin. VOLTAGE SENSE PIN (VSENSE) This input can be connected directly to the battery line. It is protected against battery reverse connection. The voltage present in this input is scaled down by an internal voltage divider, and can be routed to the ADOUT0 output pin and used by the MCU to read the battery voltage. The ESD structure on this pin allows for excursion up to +40V and down to -27V, allowing this pin to be connected directly to the battery line. It is strongly recommended to connect a 10kohm resistor in series with this pin for protection purposes. HALL SENSOR SWITCHABLE SUPPLY PIN (HVDD) This pin provides a switchable supply for external hall sensors. While in Normal Mode, this current limited output can be controlled through the SPI. The HVDD pin needs to be connected to an external capacitor to stabilize the regulated output voltage. +5V MAIN REGULATOR OUTPUT (VDD) An external capacitor has to be placed on the VDD pin to stabilize the regulated output voltage. The VDD pin is intended to supply a microcontroller. The pin is current limited against shorts to GND and over-temperature protected. During Stop Mode the voltage regulator does not operate with its full drive capabilities and the output current is limited. During Sleep Mode the regulator output is completely shut down.

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Figure 14. Functional Internal Block Diagram circuit will reset the connected MCU in case of an overflow. and the internal chip temperature (CTEMP). for periodic sense during low power modes.

Analog Integrated Circuit Device Data Freescale Semiconductor 23 33910 FUNCTIONAL DEVICE OPERATIONS OPERATIONAL MODES FUNCTIONAL DEVICE OPERATIONS OPERATIONAL MODES INTRODUCTION The 33910 offers three main operating modes: Normal (Run), Stop, and Sleep (Low Power). In Normal Mode the device is active and is operating under normal application conditions. The Stop and Sleep Modes are low power modes with wake-up capabilities. In Stop Mode the voltage regulator still supplies the MCU with VDD (limited current capability) and in Sleep Mode the voltage regulator is turned off (VDD = 0 V). Wake-up from Stop Mode is initiated by a wake-up interrupt. Wake-up from Sleep Mode is done by a reset and the voltage regulator is turned back on. The selection of the different modes is controlled by the MOD1:2 bits in the mode control register (MCR). Figure 15 describes how transitions are done between the different operating modes and Table 5, 25, gives an overview of the Operating Mode. RESET MODE The 33910 enters the Reset Mode after a power up. In this mode, the RST pin is low for 1ms (typical value). After this delay, the 33910 enters the Normal Request Mode and the RST pin is driven high. The Reset Mode is entered if a reset condition occurs (VDD low, watchdog trigger fail, after a wake-up from Sleep Mode, Normal Request Mode time-out occurs). NORMAL REQUEST MODE This is a temporary mode automatically accessed by the device after the Reset Mode or after a wake-up from Stop Mode. In Normal Request Mode, the VDD regulator is ON, the Reset pin is high and the LIN is operating in Rx Only Mode. As soon as the device enters the Normal Request Mode an internal timer is started for 150ms (typical value). During these 150ms, the MCU must configure the timing control register (TIMCR) and the MCR with MOD2 and MOD1 bits ste = 0 to enter in Normal Mode. If within the 150ms timeout the MCU does not command the 33910 to Normal Mode, it will enter in Reset Mode. If the WDCONF pin is grounded in order to disable the watchdog function, the 33910 goes directly in Normal Mode after the Reset Mode. If the WDCONF pin is open, the 33910 stays typically for 150ms in Normal Request before entering in Normal Mode. NORMAL MODE In Normal Mode, all 33910 functions are active and can be controlled by the SPI and the PWMIN pin. The VDD regulator is ON and delivers its full current capability. If an external resistor is connected between the WDCONF pin and the Ground, the window watchdog function will be enabled. The wake-up input (L1) can be read as a digital input or have its voltage routed through the analog-multiplexer. The LIN interface has slew rate and timing compatible with the LIN protocol specification 2.0. The LIN bus can transmit and receive information. The high side switches are active and have PWM capability according to the SPI configuration. The interrupts are generated to report failures 5 for VSUP over/under-voltage, thermal shutdown or thermal shutdown prewarning on the main regulator. SLEEP MODE The Sleep Mode is a low power mode. From Normal Mode, the device enters the Sleep Mode by sending one SPI command through the MCR. All blocks are in their lowest power consumption condition. Only some wake-up sources (wake-up input with or without cyclic sense, forced wake-up and LIN receiver) are active. The 5V regulator is OFF. The internal low-power oscillator may be active if the IC is configured for cyclic-sense. In this condition, one of the high side switches is turned on periodically and the wake-up inputs are sampled. Wake-up from Sleep Mode is similar to a power-up. The device goes in Reset Mode except that the SPI will report the wake-up source and the BATFAIL flag is not set. STOP MODE The Stop Mode is the second low power mode, but in this case the 5V regulator is ON with limited current drive capability. The application MCU is always supplied while the 33910 is operating in Stop Mode. The device can enter in Stop Mode only by sending the SPI command. When the application is in this mode, it can wake-up from the 33910 side (for example: cyclic sense, force wake-up, LIN bus, wake inputs) or the MCU side (CS RST pins). Wake-up from Stop Mode will transition the 33910 to Normal Request Mode and generates an interrupt except if the wake-up event is a low to high transition on the CS pin or comes from the RST pin.

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Figure 15. Operating Modes and Transitions CS rising edge wake-up or RST wake-up. Wake-up from Sleep Mode: L1 state change, LIN bus wake-up, Periodic wake-up.

Request Mode the wake-up source can be read by SPI. writing to the SPI-interrupt mask register (IMR). above the VSOV threshold (VSOV). must be acknowledged by reading the SPI. Signals a shutdown of the high side outputs. time the reset condition lasts. value before driving it high. Table 5. Operating Modes Overview

1. Operation can be enabled/controlled by the SPI.
2. Operation can be controlled by the PWMIN input.
3. HSx switches can be configured for cyclic sense operation in Stop Mode.
4. HSx switches can be configured fo r cyclic sense operation in Sleep Mode.
5. Windowing operation when enabled by an external resistor.

Analog Integrated Circuit Device Data

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FUNCTIONAL DEVICE OPERATIONS OPERATIONAL MODES temperature, the voltage regulator will be disabled and the voltage monitoring will issue a VDDOT Flag independently of the V DD voltage. Window Watchdog Overflow If the watchdog counter is not properly serviced while its window is open, the 33910 will detect a MCU software runaway and will reset the microcontroller. Wake-up From Sleep Mode During Sleep Mode, the 5V regulator is not active, hence all wake-up requests from Sleep Mode require a power-up/ reset sequence. External Reset The 33910 has a bidirectional reset pin which drives the device to a safe state (same as Reset Mode) for as long as this pin is held low. The R ST pin must be held low long enough to pass the internal glitch filter and get recognized by the internal reset circuit. This functionality is also active in Stop Mode. After the RST pin is released, there is no extra t RST to be considered. WAKE-UP CAPABILITIES Once entered in to one of the low-power modes (Sleep or Stop) only wake-up sources can bring the device into Normal Mode operation. In Stop Mode, a wake-up is signaled to the MCU as an interrupt, while in Sleep Mode the wake-up is performed by activating the 5V regulator and resetting the MCU. In both cases the MCU can detect the wake-up source by accessing the SPI registers. There is no specific SPI register bit to signal a CS wake-up or external reset. If necessary this condition is detected by excluding all other possible wake-up sources. Wake-up From Wake-up Input (L1) With Cyclic Sense Disabled The wake-up line is dedicated to sense state changes of external switches and wake-up the MCU (in Sleep or Stop Mode). In order to select and activate direct wake-up from the L1 input, the wake-up control register (WUCR) must be configured with L1WE input enabled. The wake-up input state is read through the wake-up status register (WUSR). L1 input is also used to perform cyclic-sense wake-up. Note: Selecting the L1 input in the analog multiplexer before entering Low Power Mode will disable the wake-up capability of the L1 input. Wake-up From Wake-up Input (L1) With Cyclic Sense Timer Enabled The SBCLIN can wake-up at the end of a cyclic sense period if on the wake-up input lines (L1) a state change occurs. The HSx switch is activated in Sleep or Stop Modes from an internal timer. Cyclic sense and force wake-up are exclusive. If cyclic sense is enabled, the force wake-up can not be enabled. In order to select and activate the cyclic sense wake-up from the L1 input, before entering in low power modes (Stop or Sleep Modes), the following SPI set-up has to be performed:

• In WUCR: select the L1 input to WU-enable.
• In HSCR: enable HSx.
• In TIMCR: select the CS/ WD bit and determine the cyclic sense period with CYSTx bits.
• Perform Goto Sleep/Stop command. Forced Wake-up The 33910 can wake-up automatically after a predetermined time spent in Sleep or Stop Mode. Cyclic sense and forced wake-up are exclusive. If forced wake-up is enabled, the cyclic sense can not be enabled. To determine the wake-up period, the following SPI set-up has to be sent before entering in Low Power Modes:
• In TIMCR: select the CS/ WD bit and determine the Low Power Mode period with CYSTx bits.
• In HSCR: the HSx bit must be disabled. CS Wake-up While in Stop Mode, a rising edge on the CS will cause a wake-up. The CS wake-up does not generate an interrupt and is not reported on SPI. LIN Wake-up While in the low power modes the 33910 monitors the activity on the LIN bus. A dominant pulse larger than t PROPWL followed by a dominant to recessive transition will cause a LIN wake-up. This behavior protects the system from a short- to-ground bus condition. RST Wake-up While in Stop Mode, the 33910 can wake-up when the RST pin is held low long enough to pass the internal glitch filter. Then, the 33910 will change to Normal Request or Normal modes depending on the WDCONF pin configuration. The RST wake-up does not generate an interrupt and is not reported via SPI. From Stop Mode, the following wake-up events can be configured:
• Wake-up from L1 input without cyclic sense
• Cyclic sense wake-up inputs
• Force wake-up
• CS wake-up
• LIN wake-up
• RST wake-up From Sleep Mode, the following wake-up events can be configured:
• Wake-up from L1 input without cyclic sense

• Cyclic sense wake-up inputs
• Force wake-up
• LIN wake-up WINDOW WATCHDOG The 33910 includes a configurable window watchdog which is active in Normal Mode. The watchdog can be configured by an external resistor connected to the WDCONF pin. The resistor is used to achieve higher precision in the timebase used for the watchdog. SPI clears are performed by writing through the SPI in the MOD bits of the MCR. During the first half of the SPI timeout watchdog clears are not allowed; but after the first half of the PSPI-timeout window the clear operation opens. If a clear operation is performed outside the window, the 33910 will reset the MCU, in the same way as when the watchdog overflows.

Figure 16. Window Watchdog Operation again into Normal Request Mode.

• PWM capability (software maskable)
• Open load detection
• Current limitation
• Over-temperature shutdown (with maskable interrupt)
• High-voltage shutdown (software maskable)
• Cyclic sense The high side switches are controlled by the bits HS1:2 in the High Side Control Register (HSCR). PWM Capability (direct access) Each high side driver offers additional (to the SPI control) direct control via the PWMIN pin. If both the bits HS1 and PWMHS1 are set in the High Side Control Register (HSCR), then the HS1 driver is turned on if the PWMIN pin is high and turned of if the PWMIN pin is low. This applies to HS2 configuring HS2 and PWMHS2 bits. WD PERIOD (tPWD) WINDOW CLOSED NO WATCHDOG CLEAR ALLOWED WINDOW OPEN FOR WATCHDOG CLEAR WD TIMING X 50% WD TIMING X 50% WD TIMING SELECTED BY REGISTER ON WDCONF PIN

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Figure 17. High Side Drivers HS1 and HS2 and HS2OP in the High Side Status Register (HSSR). indicated with the bits HS1CL and HS2CL in the HSSR. excessive power might be dissipated. Interrupt in the Interrupt Source Register (ISR). setting all HSxOP and HSxCL bits simultaneously. then an interrupt (IRQ) is generated. (MCR) is set) both high side drivers are shut down.

• LIN physical la yer 2.0 compliant
• Slew rate selection
• Over-current shutdown
• Over-temperature shutdown
• LIN pull-up disable in Stop and Sleep Modes
• Advanced diagnostics
• LIN dominant voltage level selection The LIN driver is a low side MOSFET with over-current and thermal shutdown. An internal pull-up resistor with a serial diode structure is integrated, so no external pull-up components are required for the application in a Slave Mode. The fall time from dominant to recessive and the rise time from recessive to dominant is controlled. The symmetry between both slopes is guaranteed. LIN Pin The LIN pin offers a high susceptibility immunity level from external disturbance, guaranteeing communication.

Figure 18. LIN Interface rate is optimized for 20kBit/s. the current consumption in Stop and Sleep modes.

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FUNCTIONAL DEVICE OPERATIONS OPERATIONAL MODES short to VBAT), the transmitter will not be shut down. The bit LINOC in the LIN status register (LINSR) is set. If the bit LINM is set in the interrupt mask register (IMR) an Interrupt IRQ will be generated. Over-Temperature Shutdown (LIN Interrupt) The output low side FET is protected against over- temperature conditions. In case of an over-temperature condition, the transmitter will be shut down and the bit LINOT in the LIN status register (LINSR) is set. If the bit LINM is set in the interrupt mask register (IMR) an Interrupt IRQ will be generated. The transmitter is automatically re-enabled once the condition is gone and TXD is high. A read of the LIN status register (LINSR) with the TXD pin will re-enable the transmitter. RXD Short Circuit Detection (LIN Interrupt) The LIN transceiver has a short-circuit detection for the RXD output pin. In case of an short-circuit condition, either 5V or ground, the bit RXSHORT in the LIN status register (LINSR) is set and the transmitter is shutdown. If the bit LINM is set in the interrupt mask register (IMR) an interrupt IRQ will be generated. The transmitter is automatically re-enabled once the condition is gone (transition on RXD) and TXD is high. A read of the LIN status register (LINSR) without the RXD pin short circuit condition will clear the bit RXSHORT. TXD Dominant Detection (LIN Interrupt) The LIN transceiver monitors the TXD input pin to detect stuck in dominant (0V) condition. In case of a stuck condition (TXD pin 0V for more than 1 second (typ.)) the transmitter is shut down and the bit TXDOM in the LIN status register (LINSR) is set. If the bit LINM is set in the interrupt mask register (IMR) an interrupt IRQ will be generated. The transmitter is automatically re-enabled once TXD is high. A read of the LIN status register (LINSR) with the TXD pin is high will clear the bit TXDOM. LIN Dominant Voltage Level Selection The LIN dominant voltage level can be selected by the bit LDVS in the LIN control register (LINCR). LIN Receiver Operation Only While in Normal Mode the activation of the RXONLY bit disables the LIN TX driver. In the case of a LIN error condition this bit is automatically set. In case a Low Power Mode is selected with this bit set, the LIN wake-up functionality is disabled, then, in Stop Mode, the RXD pin will reflect the state of the LIN bus. STOP Mode And Wake-up Feature During Stop Mode operation the transmitter of the physical layer is disabled. In case the bit LIN-PU was set in the Stop Mode sequence the internal pull-up resistor is disconnected from VSUP and a small current source keeps the LIN pin in the recessive state. The receiver is still active and able to detect wake-up events on the LIN bus line. A dominant level longer than tPROPWL followed by a rising edge will generate a wake-up interrupt and will be reported in the ISR. Also see Figure 11, page 19. SLEEP Mode And Wake-up Feature During Sleep Mode operation the transmitter of the physical layer is disabled. In case the bit LIN-PU was set in the Sleep Mode sequence the internal pull-up resistor is disconnected from VSUP and a small current source keeps the LIN pin in recessive state. The receiver is still active to be able to detect wake-up events on the LIN bus line. A dominant level longer than tPROPWL followed by a rising edge will generate a system wake-up (Reset) and will be reported in the ISR. Also see Figure 10, page 18.

microcontroller (master) and the 33910.

• CS — Chip Select
• M O S I — Master-Out Slave-In
• M I S O — Master-In Slave-Out
• S C L K — Serial Clock A complete data transfer via the SPI consists of 1 byte. The master sends 4 bits of address (A3:A0) + 4 bits of control information (C3:C0) and the slave replies with 3 system status bits and one not defined bit (VMS,LINS,HSS,n.d.) + 4 bits of status information (S3:S0).

Figure 19. SPI Protocol latches the analog status data (Register read data). clock (SCLK) the data is sampled by the receiver. edges are present during the active (low) phase of CS.

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Table 7 summarizes the SPI Register content for Control Information (C3:C0)=W and status information (S3:S0) = R. Note: Address $8 and $9 are reserved and must not be used. Table 6. System Status Register Table 7. SPI Register Overview

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Table 10. Mode Control Bits register is also returned when writing to the MCR. 1 = Under-voltage condition. BATFAIL - Battery Fail Flag. the 33910 had a power on reset (POR). will clear the BATFAIL flag. This register is used to control the digital wake-up input. wake-up status register (WUSR). Table 12. Wake-up Control Register - $2 L1 input is not enabled then the wake-up status will return 0. the wake-up status register (WUSR). 0 = L1 Wake-up disabled or selected as analog input. Table 11. Voltage Status Register - $0/$1 Table 13. Wake-up Status Register - $2/$3

This register controls the LIN physical interface block. resets automatically when the failure is gone. Table 15. LIN Slew-Rate Control driver is automatically re-enabled once the condition is gone. 1 = RXD short circuit condition. To clear this bit, it must be read after TXD has gone high. 1 = TXD stuck at dominant fault detected. after SPI read once the condition is gone. Table 14. LIN Control Register - $4 Table 16. LIN Status Register - $4/$5

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This register controls the operation of the high side drivers. 1 = PWMIN input controls HS1 output. 0 = HSx is controlled only by SPI. HSx - High Side Switch Control. This write-only bit enables/disables the high side switch. is also returned when writing to the HSCR. setting the HSxOP and HSxCL bits simultaneously. possible load disconnection. operating in current Limitation Mode. to the TIMCR will also return the WDSR.

• Cyclic Sense or Watchdog Prescaler Select.

to, the cyclic sense prescaler or the watchdog prescaler. windowing watchdog is active. Table 20. Watchdog Prescaler Table 17. High Side Control Register - $6 Table 18. High Side Status Register - $6/$7 Table 19. Timing Control Register - $A

wake-up is performed after the period shown in Table 21. Table 21. Cyclic Sense Interval is also returned when writing to the TIMCR. watchdog within the window closed. software debugging and for programming the Flash memory. be ignored in case WDERR is High. the divider ration for the L1 input divider. analog input. Voltage is internally clamped to VDD.

1. bit CYSX8 is located in configuration register (CFR)

Table 22. Watchdog Status Register - $A/$B Table 23. Analog Multiplexer Control Register -$C

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multiplexed to the ADOUT0 pin according to Table 24. to achieve lower current consumption. Table 24. Analog Multiplexer Channel Select This register controls the cyclic sense timing multiplier. Table 25. Configuration Register - $D

Table 28. If no interrupt is pending than all bits are 0. interrupt sources are handled sequentially multiplex. Table 28. Interrupt Sources Table 26. Interrupt Mask Register - $E

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LOGIC COMMANDS AND REGISTERS TYPICAL APPLICATIONS The 33910 can be configured in several applications. The figure below shows the 33910 in the typical Slave Node Application. Voltage Regulator SPI CONTROL Reset Control Module LVR, HVR, HTR, WD, Window Watchdog Module LIN Physical Layer VS2 5V Output Module HS1 HVDD VSENSE Analog Input Module Digital Input Module LIN RXD ADOUT0 SCLK MOSI MISO TXD CS Wake Up Module Interrupt Control Module LVI, HVI, HTI, OCI VBAT Sense Module Analog Multiplexer L1 HS2 WDCONF Chip Temp Sense Module PWMIN High Side Control Module LGND Internal Bus MCU RST IRQ AGND PGND VS1 AGND VDD A/D A/D SCI SPI TIMER RST VDD IRQ C4 C3 C2 C1 V LIN Hall Sensor Supply BAT Typical Component Values: C1 = 47µF; C2 = C4 = 100nF; C3 = 10µF; C5 = 220pF R1 = 10kΩ; R2 = 20kΩ-200kΩ Recommended Configuration of the not Connected Pins (NC): Pin 15, 16, 17, 19, 20, 21, 22 = GND Pin 11 = open (floating) Pin 28 = this pin is not internally connected and may be used for PCB routing optimization.

Analog Integrated Circuit Device Data Freescale Semiconductor 41 33910 PACKAGING PACKAGE DIMENSIONS PACKAGING PACKAGE DIMENSIONS Important For the most current revision of the package, visit www.Freescale.com and select Documentation, then under Available Documentation column select Packaging Information. AC SUFFIX (PB-FREE) 32-PIN LQFP 98ASH70029A REVISION D

Analog Integrated Circuit Device Data

42 Freescale Semiconductor

IMPORTANT FOR THE MOST CURRENT REVISION OF THE PACK- AGE, VISIT WWW.FREESCALE.COM AND SELECT DOCUMENTA- PACKAGE DIMENSIONS (Continued) AC SUFFIX (PB-FREE) 32-PIN LQFP 98ASH70029A REVISION D

Analog Integrated Circuit Device Data Freescale Semiconductor 43 33910

REVISION HISTORY

Revision Date Description of Changes 3.0 9/2007 • Initial Release 4.0 2/2008 • Changed Functional Block Diagram on page 22.

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