33908

MC33907-MC33908D2 NXP | Alldatasheet

Document overview

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Technical content

Features

• Battery voltage sensing & MUX output pin
• Highly flexible SMPS pre-regulator, allowing two topologies: non-inverting buck-boost and standard buck
• Switching mode power supply (SMPS) dedicated to MCU core supply, from 1.2 V to 3.3 V delivering up to 1.5 A
• Multiple wake-up sources in low-power mode: CAN, LIN, and/or IOs
• Six configurable I/Os
• Linear voltage regulator dedicated to aux iliary functions, or to a sensor supply (VCCA tracker or independent), 5.0 V or 3.3 V
• Linear voltage regulator dedicated to MCU A/D reference voltage or I/Os supply (VCCA), 5.0 V or 3.3 V

Figure 1. 33907/33908 simplified application diagram - buck boost configuration

Applications

• Electrical power steering
• Engine management
• Battery management
• Active suspension
• Gear box
• Transmission
• Electrical vehicle (EV), hybrid electrical vehicle (HEV), and inverter
• Advanced driver assistance systems VAUX_E VAUX_B VAUX CAN-5V MOSI MISO SCLK NCS RXDTXD CANH CANL SELECT INTB RSTB FS0B DEBUG IO_0 IO_1 IO_2 IO_3 IO_4 IO_5 GND_COM VDDIO CAN BUS VDDIO VPRE DEBUG mode GNDA DGND VCORE or VCCA VSUP1 SW_PRE2 VPRE SW_CORE FB_CORE VCCA_E VCCA_B VCCA VSENSE COMP_CORE VSUP2 BOOTS_PRE BOOTS_CORE GATE_LS SW_PRE1 VCORE_SNS VSUP3 +Battery (KL30) VDDIO MUX_OUT VAUX VCCA MCU SPI VDD ADC Input AD ref. voltage NMI Reset FCCUCAN Ignition Key (KL15) VDD VSUP3 LIN BUS LIN RXDL TXDL LIN

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Figure 2. Simplified application diagram - buck configuration, VAUX not used, VCCA = 100 mA

1 Orderable parts

Table 1. Orderable part variations

1. To order parts in Tape & Reel, add the R2 suffix to the part number.

2 Internal Block Diagram

Figure 3. 33907L/33908L with CAN and LIN simplified internal block diagram

Figure 4. 33907N/33908N with CAN only simplified internal block diagram

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3 Pin connections

3.1 Pinout diagram for 33907/33908

Figure 5. 33907L/33908L pinout with CAN and LIN Figure 6. 33907N/33908N pinout with CAN only

3.2 Pin definitions

A functional description of each pin can be found in the functional pin description section beginning on page 26. Table 2. 33907/33908 pin definition VSUP1. VSUP1 and VSUP2 must be connected together externally.

44 V S U P 3 A _ I N

11 IO_4:5 D_IN

from another IC for safety purposes. Output gate driver: Can drive a logic level low-side NMOS transistor. Controlled by the SPI.

13 IO_0:1 A_IN

resistor bridge connected on Vcore (in parallel to the one used to set the Vcore voltage). condition is detected. Open drain structure. is available at MUX-OUT through the SPI.

19 IO_2:3 D_IN

from MCU for safety purposes. to VDDIO. Internal pull-up to VDDIO.

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fault condition. Open drain structure. configurable. Internal pull-up to VDDIO. 30 30 VDDIO A_IN Input voltage for MISO output buffer. Allows voltage compatibility with MCU I/Os. 32 32 FB_CORE A_IN VCORE voltage feedback. Input of the error amplifier. 33 33 COMP_CORE A_IN Compensation network. Output of the error amplifier. Table 2. 33907/33908 pin definition (continued)

4 General product characteristics

4.1 Maximum ratings

Table 3. Maximum ratings

1. All Vsups (V SUP1/2/3) shall be connected to the same supply (Figure 58)

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• A l l p i n s
• VSUP1,VSUP2, VSUP3, VSENSE, VAUX, IO_0:1, IO_4:5,FS0B, DEBUG
• CANH, CANL
• L I N Charge Device Model (JESD22/C101):
• A l l P i n s
• Corner Pins System level ESD (Gun Test)
• VSUP1, VSUP2, VSUP3, VSENSE, VAUX, IO_0:1, IO_4:5, FS0B 330 Ω / 150 pF Unpowered According to IEC61000-4-2: 330 Ω / 150 pF Unpowered According to OEM LIN, CAN, FLexray Conformance 2.0 kΩ / 150 pF Unpowered According to ISO10605.2008 2.0 kΩ / 330 pF Powered According to ISO10605.2008
• CANH, CANL 330 Ω / 150 pF Unpowered According to IEC61000-4-2: 330 Ω / 150 pF Unpowered According to OEM LIN, CAN, FLexray Conformance 2.0 kΩ / 150 pF Unpowered According to ISO10605.2008 2.0 kΩ / 330 pF Powered According to ISO10605.2008
• L I N 330 Ω / 150 pF Unpowered According to IEC61000-4-2: 330 Ω / 150 pF Unpowered According to OEM LIN, CAN, FLexray Conformance 2.0 kΩ / 150 pF Unpowered According to ISO10605.2008 2.0 kΩ / 330 pF Powered According to ISO10605.2008 ±2.0 ±4.0 ±6.0 ±8.0 ±500 ±750 ±8.0 ±8.0 ±8.0 ±8.0 ±15.0 ±12.0 ±15.0 ±15.0 ±15.0 ±15.0 ±12.0 ±15.0 kV kV kV kV V V kV kV kV kV kV kV kV kV kV kV kV kV (3) Thermal ratings TA Ambient Temperature -40 to 125 °C TJ Junction Temperature -40 to 150 °C TSTG Storage Temperature -55 to 150 °C Thermal resistance RθJA Thermal Resistance Junction to Ambient 30 °C/W (4) RθJCTOP Thermal Resistance Junction to Case Top 24.2 °C/W (5) RθJCBOTTOM Thermal Resistance Junction to Case Bottom 0.9 °C/W (6) Notes 3. Compared to AGND. 4. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal. 5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC - 883 Method 1012.1). 6. Thermal resistance between the die and the solder par on the bo ttom of the packaged based on simulation without any interface resistance.

Table 3. Maximum ratings (continued)

4.2 Static electrical characteristics

Table 4. Operating range ground. When 28 V < VSUP < 40 V, thermal dissipation must be considered (Figure 25).

• Buck mode (VSUP > VSUP_UV_7)
• Buck mode (VSUP_UV_7 ≥ VSUP ≥ 4.6 V)
• Boost mode (VSUP ≥ 2.7 V) 6.25 VPRE_UV_4 6.0 VSUP - RDSON_PR E * IPRE 6.75 7.0 V IPRE VPRE Maximum Output Current Capability
• Buck or Boost with VSUP > VSUP_UV_7
• Buck with VSUP_UV_7 ≥ VSUP ≥ 4.6 V
• Boost with VSUP_UV_7 ≥ VSUP ≥ 6.0 V
• Boost with 6.0 V ≥ VSUP ≥ 4.0 V
• Boost with 4.0 V ≥ VSUP ≥ 2.7 V 2.0 0.5 2.0 1.0 0.3 2.0 A (8) IPRE_LPOFF VPRE Maximum Output Current Capability in LPOFF at low VSUP voltage
• Buck with VSUP_UV_7 ≥ VSUP ≥ 4.6 V
• Boost with VSUP_UV_7 ≥ VSUP ≥ 6.0 V
• Boost with 6.0 V ≥ VSUP ≥ 4.0 V
• Boost with 4.0 V ≥ VSUP ≥ 2.7 V 0.05 2.0 1.0 0.3 A (8) IPRE_LIM VPRE Output Current Limitation with VSUP ≤ 28 V 3.5 – – A IPRE_OC VPRE Overcurrent Detection Threshold (in buck mode only) with VSUP ≤ 28 V 5.0 – – A VPRE_UV VPRE Undervoltage Detection Threshold (Falling) 5.5 – 6.0 V Notes 7. V SUP_UV_L_B = VPRE_UV_4P3 + RDSON_PRE * IPRE 8. Guaranteed by design

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• I PRE from 50 mA to 2.0 A - Buck mode – 100 – mV (9) LORVPRE_BOOST VPRE Load Regulation for COUT = 57 µF
• I PRE from 50 mA to 2.0 A - Boost mode – 500 – mV (9) VPRE_LL_H VPRE_LL_L VPRE Pulse Skipping Thresholds – 200 180 – mV TWARN_PRE VPRE Thermal Warning Threshold – 125 – °C TSD_PRE VPRE Thermal Shutdown Threshold 160 – – °C TSD_PRE_HYST VPRE Thermal Shutdown Hysteresis – 10 – °C (9) VSUP_IPFF IPFF Input Voltage Detection 18 – 24 V VSUP_IPFF_HYST IPFF Input Voltage Hysteresis 0.2 – – V IPRE_IPFF_PK IPFF High-side Peak Current Detection with VSUP ≤ 28 V 1.7 – – A VG_LS_OH LS Gate Driver High Output Voltage (IOUT = 50 mA) V PRE-1 – V PRE V VG_LS_OL LS Gate driver Low Level (IOUT = 50 mA) – – 0.5 V Vcore voltage regulator VCORE_FB VCORE Feedback Input Voltage 0.784 0.8 0.816 V ICORE VCORE Output Current Capability in Normal Mode
• 33907N
• 33908N
• 33907L
• 33908L 0.8 1.5 0.8 1.5 A I CORE_LIM VCORE Output Current Limitation
• 33907N
• 33908N
• 33907L
• 33908L 1.8 1.8 3.5 3.5 A R DSON_CORE VCORE Pass Transistor On Resistance – – 200 m Ω Notes 9. Guaranteed by design

Table 4. Operating range (continued) ground. When 28 V < VSUP < 40 V, thermal dissipation must be considered (Figure 25).

• 5 . 0 V config. with Internal ballast at 100 mA
• 5 . 0 V config with external ballast at 200 mA
• 5 . 0 V config with external ballast at 300 mA
• 3 . 3 V config with Internal ballast at 100 mA
• 3 . 3 V config with external ballast at 200 mA
• 3 . 3 V config with external ballast at 300 mA 4.95 4.9 4.85 3.2505 3.234 3.201 5.0 5.0 5.0 3.3 3.3 3.3 5.05 5.1 5.15 3.3495 3.366 3.399 V (12) ICCA_IN VCCA Output Current (int. MOSFET) – – 100 mA ICCA_OUT VCCA Output Current (external PNP) – – 300 mA ICCA_LIM_INT VCCA Output Current Limitation (int. MOSFET) 100 – 675 mA ICCA_LIM_OUT VCCA Output Current Limitation (external PNP) 300 – 675 mA ICCA_LIM_FB VCCA Output Current Limitation Foldback 80 – 200 mA VCCA_LIM_FB VCCA Output Voltage Foldback Threshold 0.5 – 1.1 V VCCA_LIM_HYST VCCA Output Voltage Foldback Hysteresis 0.03 – 0.3 V ICCA_BASE_SC ICCA_BASE_SK VCCA Base Current Capability – – mA TWARN_CCA VCCA Thermal Warning Threshold (int. MOSFET only) – 125 – °C TSDCCA VCCA Thermal Shutdown Threshold (int. MOSFET only) 160 – – °C TSDCCA_HYST VCCA Thermal Shutdown Hysteresis – 10 – °C (13) LORTVCCA VCCA Transient Load Regulation
• I CCA = 10 mA to 100 mA (internal MOSFET)
• I CCA = 10 mA to 300 mA (external ballast) –– 1 . 0 % (13) Notes 10. Guaranteed by design. 11. C OUT = 40 µF, ICORE = 10 mA to 1.5 A, dICORE/dt ≤ 2.0 A/µs 12. External PNP gain within 150 to 450 13. Guaranteed by design.

ground. When 28 V < VSUP < 40 V, thermal dissipation must be considered (Figure 25).

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• I AUX_OUT = 10 mA to 300 mA –– 1 . 0 % (14) CAN_5V voltage regulator VCAN VCAN Output Voltage VSUP > 6.0 V in Buck mode VSUP > VSUP_UV_L in Boost mode 4.8 5.0 5.2 V ICAN_OUT VCAN Output Current – – 100 mA ICAN_LIM VCAN Output Current Limitation 100 – 250 mA TSDCAN VCAN Thermal Shutdown Threshold 160 – – °C TSDCAN_HYST VCAN Thermal Shutdown Hysteresis – 10 – °C (14) VCAN_UV VCAN Undervoltage Detection Threshold 4.25 – 4.8 V VCAN_UV_HYST VCAN Undervoltage Hysteresis 0.07 – 0.22 V VCAN_OV VCAN Overvoltage Detection Threshold 5.2 – 5.55 V VCAN_OV_HYST VCAN Overvoltage Hysteresis 0.07 – 0.22 V LORVCAN VCAN Load Regulation (from 0 to 50 mA) – 100 – mV (14) Notes 14. Guaranteed by design.

ground. When 28 V < VSUP < 40 V, thermal dissipation must be considered (Figure 25).

ground. When 28 V < VSUP < 40 V, thermal dissipation must be considered (Figure 25).

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• Min Limit = 2.7 V at VSUP = 40 V 2.6 – – V VIO23_IH Digital High Input voltage level (IO_2, IO_3) 2.0 – – V VIO_IL Digital Low Input voltage Level (IO_0:1; IO_4:5) – – 2.1 V VIO_HYST Input Voltage Hysteresis (IO_0:1, IO_4:5) 50 120 500 mV (17) VIO23_IL Digital Low Input voltage Level (IO_2, IO_3) – – 0.9 V VIO23_HYST Input Voltage Hysteresis (IO_2, IO_3) 200 450 700 mV (17) IIO_IN_0:1 Input Current for IO_0:1 -5.0 – 100 µA IIO_IN_1 Input Current for IO_1 when used for FB_Core monitoring -1.0 – 1.0 µA IIO_IN_2:5 Input Current for IO_2:5 -5.0 – 5.0 µA IIO_IN_LPOFF Input Current for IO_0:5 in LPOFF -1.0 – 1.0 µA Output gate driver VIO_OH High Output Level at IIO_OUT = -2.5 mA V PRE - 1.5 – V PRE V VIO_OL Low Output Level at IIO_OUT = +2.5 mA 0.0 – 1.0 V VIO_OUT_SK VIO_OUT_SC Output Current Capability 2.5 -2.5 mA Notes 16. For V SUP < 2.0 V, all supplies are already off and external pull-up on RSTB (e.g VCORE or VCCA) pulls the line down. 17. Guaranteed by design.

ground. When 28 V < VSUP < 40 V, thermal dissipation must be considered (Figure 25).

1. If a higher resistor value than recommended is used, the accuracy degrades.

ground. When 28 V < VSUP < 40 V, thermal dissipation must be considered (Figure 25).

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• TX dominant state
• TX recessive state 2.75 2.0 2.5 4.5 3.0 V VCANL CANL Output Voltage (45 Ω < RBUS < 65 Ω)
• TX dominant state
• TX recessive state 0.5 2.0 2.5 2.25 3.0 V VCAN_SYM CAN dominant voltage symmetry (VCANL + VCANH) 4.5 5 5.5 V VOH-VOL Differential Output Voltage
• TX dominant state (45 Ω < RBUS < 65 Ω)
• TX recessive state 1.5 -50 2.0 0.0 3.0 V mV ICANL-SK CANL Sink Current Under Short-circuit Condition (VCANL ≤ 12 V, CANL driver ON, TXD low) 40 – 100 mA ICANH-SC CANH Source Current Under Short-circuit Condition (VCANH = -2.0 V, CANH driver ON, TXD low) -100 – -40 mA RINSLEEP CANH, CANL Input Resistance Device Supplied and in CAN Sleep Mode 5.0 – 50 k Ω ICAN CANH, CANL Input Current, Device Unsupplied, (VCANH, VCANL =5.0V)
• V SUP and VCAN connected to GND
• V SUP and VCAN connected to GND via 47k resistor -10 -10 µA µA (20) TOT Overtemperature Detection 160 – – °C THYST Overtemperature Hysteresis – – 20 °C Digital interface MISOH High Output Level on MISO (IMISO = 1.5 mA) V DDIO - 0.4 – – V MISOL Low Output Level on MISO (IMISO = 2.0 mA) – – 0.4 V IMISO Tri-state Leakage Current (VDDIO = 5.0 V) -5.0 – 5.0 µA VDDIO Supply Voltage for MISO Output Buffer 3.0 – 5.5 V IVDDIO Current consumption on VDDIO – 1.0 3.0 mA SPILK SCLK, NCS, MOSI Input Current -1.0 – 1.0 µA VSPI_IH SCLK, NCS, MOSI High Input Threshold 2.0 – – V RSPI NCS, MOSI Internal Pull-up (pull-up to VDDIO) 200 400 800 K Ω VSPI_IL SCLK, NCS, MOSI Low Input Threshold – – 0.8 V

ground. When 28 V < VSUP < 40 V, thermal dissipation must be considered (Figure 25).

1. Guaranteed by design and characterization.
2. V BAT is the voltage at the input of the control unit.
3. Current flowing inside the pin. A transc eiver must be capable to sink at least 40 mA.
4. V BAT: voltage across the battery connectors of the vehicle. VGND_ECU: voltage on the local ECU ground connector with respect to battery ground

of the vehicle (VGND_BATTERY). ground. When 28 V < VSUP < 40 V, thermal dissipation must be considered (Figure 25).

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Ground Disconnection. GND = VSUP, 0 V < VBUS < 18 V, VBAT = 12 V.

1. This constraint refers to duty cycle D1 and D2 only.
2. V TH_DOM: receiver threshold of the recessive to dominant LIN bus edge. VTH_REC receiver threshold of the dominant to recessive LIN bus edge.
3. V SUP is the voltage at the input of the device (different from Vbat when a reverse current protection diode is implemented.

ground. When 28 V < VSUP < 40 V, thermal dissipation must be considered (Figure 25).

4.3 Dynamic electrical characteristics

Table 5. Dynamic electrical characteristics ground. When 28 V < VSUP < 40 V, thermal dissipation must be considered (Figure 25).

• V DDIO = 5.0 V, CLOAD = 50 pF
• V DDIO = 5.0 V, CLOAD = 150 pF 5.0 5.0 ns tCLH Minimum Time SCLK = HIGH 62 – – ns tCLL Minimum Time SCLK = LOW 62 – – ns tPCLD Propagation Delay (SCLK to data at 10% of MISO rising edge) – – 30 ns tCSDV NCS = LOW to Data at MISO Active – – 75 ns tSCLCH SCLK Low Before NCS Low (setup time SCLK to NCS change H/L) 75 – – ns tHCLCL SCLK Change L/H after NCS = low 75 – – ns tSCLD SDI Input Setup Time (SCLK change H/L after MOSI data valid) 40 – – ns tHCLD SDI Input Hold Time (MOSI data hold after SCLK change H/L) 40 – – ns tSCLCL SCLK Low Before NCS High 100 – – ns tHCLCH SCLK High After NCS High 100 – – ns tPCHD NCS L/H to MISO at High-impedance – – 75 ns tONNCS NCS Min. High Time 500 – – ns tNCS_MIN NCS Filter Time 10 – 40 ns

Figure 7. SPI timing diagram Figure 8. Register access restriction

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• R LOAD = 120 Ω, C between CANH and CANL = 100 pF, C at RxD < 15 pF – – 255 ns t1PWU Single Pulse Wake-up Time 0.5 – 5.0 µs t3PWU Multiple Pulse Wake-up Time 0.5 – 1.0 µs t3PTO1 Multiple Pulse Wake-up Timeout (120 µs bit selection) 110 120 – µs t3PTO2 Multiple Pulse Wake-up Timeout (360 µs bit selection) 350 360 – µs tCAN_READY Delay to Enable CAN by SPI Command (NCS rising edge) to CAN to Transmit (device in normal mode and CAN interface in TX/RX mode) – – 100 µs (28) Fail-safe state machine OSCFSSM Oscillator 405 – 495 kHz CLKFS_MIN Fail-safe Oscillator Monitoring 150 – – kHz tIC_ERR IO_0:5 Filter Time 4.0 – 20 µs tACK_FS Acknowledgement Counter (used for IC error handling IO_1 and IO_5) 7.0 – 9.7 ms t_DFS_RECOVERY IO_0 Filter Time to Recover from Deep Reset and Fail State 0.8 – 1.3 ms tIO1_DRIFT_MON IO_1 filter time 1.0 – 2.0 ms Fail-safe output tRSTB_FB RSTB Feedback Filter Time 8.0 – 15 µs tFSOB_FB FS0B Feedback Filter Time 8.0 – 15 µs tRSTB_BLK RSTB Feedback Blanking Time 180 – 320 µs tFSOB_BLK FS0B Feedback Blanking Time 180 – 320 µs tRSTB_POR Reset Delay Time (after a Power On Reset or from LPOFF) 12 15.9 23.6 ms (29) tRSTB_LG Reset Duration (long pulse) 8.0 – 10 ms tRSTB_ST Reset duration (short pulse) 1.0 – 1.3 ms tRSTB_IN External Reset Delay time 8.0 – 15 µs tDIAG_SC Fail-safe Output Diagnostic Counter (FS0B) 550 – 800 µs VSUP voltage supply CSUP Minimum capacitor on Vsup 44 – – µF Notes 28. For proper CAN operation, TXD must be set to high leve l before CAN enable by SPI, and must remain high for at least TCAN_READY. 29. This timing is not guaranteed in case of fault during startup phase (after Power On Reset of from LPOFF)

Table 5. Dynamic electrical characteristics (continued) ground. When 28 V < VSUP < 40 V, thermal dissipation must be considered (Figure 25).

1. Guaranteed by characterization.

ground. When 28 V < VSUP < 40 V, thermal dissipation must be considered (Figure 25).

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• V DDIO = 5.0 V, CMUX_OUT = 1.0 nF –– 1 0 µs Interrupt tINTB_LG INTB Pulse Duration (long) 90 100 – µs tINTB_ST INTB Pulse Duration (short) 20 25 – µs Functional sate machine tWU_GEN General Wake-up Signal Deglitch Time (for any wu signal on IOs) 60 70 80 µs Notes 31. Guaranteed by characterization.

ground. When 28 V < VSUP < 40 V, thermal dissipation must be considered (Figure 25).

1. LIN Driver, Bus load conditions (CBUS,RBUS): 1.0 nF;1.0 kΩ / 6.8 nF;660 Ω / 10 nF;500 Ω

ground. When 28 V < VSUP < 40 V, thermal dissipation must be considered (Figure 25).

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5 Functional pin description

5.1 Introduction

The 33907/33908 is the third generation of the System Basis Chip, combining:

• High efficiency switching voltage regulator for MCU, and linear voltage regulators for integrated CAN interface, external ICs such as sensors, and accurate reference voltage for A to D converters.
• Built-in enhanced high-speed CAN interface (ISO11898-2 and -5), and LIN interface (LIN up to Rev. 2.2/ SAEJ2602-2), with local and bus failure diagnostic, protection, and Fail-safe operation mode.
• Low-power mode, with ultra low-current consumption.
• Various wake-up capabilities.
• Enhanced safety features with multiple fail-safe outputs and scheme to support ASIL D applications.

5.2 Power supplies (VSUP1, VSUP2, VSUP3)

VSUP1 and VSUP2 are the inputs pins for internal supply dedicated to SMPS regulators. VSUP3 is the input pin for internal voltage reference. VSUP1, 2, and 3 are robust against ISO7637 pulses. VSUP1,2, and 3 shall be connected to the same supply (Figure 58).

5.3 Vsense input (VSENSE)

This pin must be connected to the battery line (before the reverse battery protection diode), via a serial resistor. It incorporates a threshold detector to sense the battery voltage, and provide a battery early warning. It also includes a resistor divider to measure the VSENSE voltage via the MUX-OUT pin. VSENSE pin is robust against ISO7637 pulses.

5.4 Pre-regulator (VPRE)

A highly flexible SMPS pre-regulator is implemented in the 33907/33908. It can be configured as a “non-inverting buck-boost converter” (Figure 27) or “standard buck converter” (Figure 26), depending on the external configuration (connection of pin GATE_LS). The configuration is detected automatically during start-up sequence. The SMPS pre-regulator is working in current mode control and the compensation network is fully integrated in the device. The high-side switching MOSFET is also integrated to make the current control easier. The pre-regulator delivers a typical output voltage of 6.5 V, which is used internally. Current limitation, overcurrent, overvoltage, and undervoltage detectors are provided. VPRE is enabled by default. 5.5 VCORE Output (from 1.2 V to 3.3 V range) The VCORE block is an SMPS regulator. The voltage regulator is a step down DC-DC converter operating in voltage control mode. The output voltage is configurable from 1.2 V to 3.3 V range thanks to an external resistor divider connected between VCORE and the feedback pin (FB_CORE) (as example in Figure 1, Figure 2, and Figure 58). The stability of the converter is done externally, by using the COMP_CORE pin. Current limitation, overvoltage, and undervoltage detectors are provided. VCORE can be turned ON or OFF via a SPI command, however it is not recommended to turn OFF VCORE by SPI when VCORE is configured safety critical (both overvoltage and undervoltage have an impact on RSTB and FS0B). VCORE overvoltage information disables VCORE. Diagnostics are reported in the dedicated register and generate an Interrupt. VCORE is enabled by default.

impact on RSTB and FS0B). VCCA overcurrent (with the use of external PNP only) and overvoltage information disables VCCA. Diagnostics are reported in the dedicated register and generate an Interrupt. VCCA is enabled by default. generates an Interrupt. VAUX is enabled by default.

5.8 SELECT Input (VCCA, VAUX voltage configuration)

Table 6. VCCA/VAUX Voltage Selection (Figure 59) Table 7. VCCA Voltage Selection (VAUX not used, Figure 60, Figure 61)

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5.9 CAN_5V voltage regulator

The CAN_5V voltage regulator is a linear regulator dedicated to the internal HSCAN interface. An external capacitor is required. Current limitation, overvoltage, and undervoltage detectors are provided. If the internal CAN transceiver is not used, the CAN_5V regulator can supply an external load (CAN_5V voltage regulator). CAN_5V is enabled by default.

5.10 INTERRUPT (INTB)

The INTB output pin generates a low pulse when an Interrupt condition occurs. The INTB behavior as well as the pulse duration are set through the SPI during INIT phase. INTB has an internal pull-up resistor connected to VDDIO.

5.11 CANH, CANL, TXD, RXD

These are the pins of the high speed CAN physical interface. The CAN transceivers provides the physical interface between the CAN protocol controller of an MCU and the physical dual wires CAN bus. The CAN interface is connected to the MCU via the RXD and TXD pins.

5.11.1 TXD

TXD is the device input pin to control the CAN bus level. TXD is a digital input with an internal pull-up resistor connected to VDDIO. In the application, this pin is connected to the microcontroller transmit pin. In Normal mode, when TXD is high or floating, the CANH and CANL drivers are OFF, setting the bus in a recessive state. When TXD is low, the CANH and CANL drivers are activated and the bus is set to a dominant state. TXD has a built-in timing protection that disables the bus when TXD is dominant for more than TDOUT. In LPOFF mode, VDDIO is OFF, pulling down this pin to GND.

5.11.2 RXD

RXD is the bus output level report pin. In the application, this pin is connected to the microcontroller receive pin. In Normal mode, RXD is a push-pull structure. When the bus is in a recessive state, RXD is high. When the bus is dominant, RXD is low. In LPOFF mode, this pin is in high-impedance state.

5.11.3 CANH and CANL

These are the CAN bus pins. CANL is a low side driver to GND, and CANH is a high side driver to CAN_5V. In Normal mode and TXD high, the CANH and CANL drivers are OFF, and the voltage at CANH and CANL is approximately 2.5 V, provided by the internal bus biasing circuitry. When TXD is low, CANL is pulled to GND and CANH to CAN_5V, creating a differential voltage on the CAN bus. In LPOFF mode, the CANH and CANL drivers are OFF, and these pins are pulled down to GND via the device RIN_CHCL resistors. CANH and CANL have integrated ESD protection and extremely high robustness versus external disturbance, such as EMC and electrical transients. These pins have current limitation and thermal protection.

5.12 LIN, TXDL, RXDL

These pins apply to 33907L and 33908L versions. These are the pins of the LIN physical interface. The LIN transceivers provides the physical interface between the MCU and the physical single wire LIN bus. The LIN interface is connected to the MCU via the RXDL and TXDL pins.

5.12.1 TXDL

The TXDL input pin is the MCU interface to control the state of the LIN output. TXDL is a digital input with an internal pull-up resistor connected to VDDIO. In the application, this pin is connected to the microcontroller transmit pin. In Normal mode, when TXDL is high or floating, the LIN output transistor is OFF, setting the bus in recessive state. When TXDL is low, the LIN output transistor is ON and the bus is set to a dominant state. TXDL has a built-in timing protection that disables the bus when TXDL is dominant for more than TXD_DOM. In LPOFF mode, VDDIO is OFF, pulling down this pin to GND.

5.12.2 RXDL

RXDL is the bus output level report pin. In the application, this pin is connected to the microcontroller receive pin. In Normal mode, RXD is a push-pull structure. When the bus is in a recessive state, RXD is high. When the bus is dominant, RXD is low. In LPOFF mode, this pin is in high-impedance state.

5.12.3 LIN

This is the LIN bus pin. The LIN driver is a low-side MOSFET with internal overcurrent thermal shutdown. An internal pull-up resistor with a serial diode structure is integrated so no external pull-up components are required for the application in a slave node. An additional pull- up resistor of 1.0 kΩ must be added when the device is used in the master node. In Normal mode and TXDL high, the LIN transistor is OFF, and the voltage at LIN is approximately VSUP3, provided by the pull up resistor with a serial diode structure. When TXD is low, LIN is pulled to GND The device has two selectable baud rates: 20 kBits/s for Normal Baud rate and 10 kBits/s for slow baud rate. An additional fast baud rate (100 kBits/s) is implemented. It can be used to flash the MCU or in the garage for diagnostic. The LIN Consortium specification does not specify electrical parameters for this baud rate. The communication only must be guaranteed. In LPOFF mode, the LIN transistor is OFF, and this pin is pulled up to VSUP3. LIN has integrated ESD protection and extremely high robustness versus external disturbance, such as EMC and electrical transients.

5.13 Multiplexer output MUX_OUT

The MUX_OUT pin (Figure 9) delivers analog voltage to the MCU ADC input. The voltage to be delivered to MUX_OUT is selected via the SPI, from one of the following parameters:

• VSENSE
• VIO_0
• VIO_1
• Internal 2.5 V reference
• Die temperature sensor T(°C) = (V AMUX - VAMUX_TP) / VAMUX_TP_CO + 165 Voltage range at MUX_OUT is from GND to VDDIO (3.3 V or 5.0 V)

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Figure 9. Simplified analog multiplexer block diagram

5.14 I/O pins (I/O_0:I/O_5)

• IO_0:1 are selectable as follows: Analog input (load dump proof) sent to the MCU through the MUX_OUT pin. Wake-up input on the rising or falling edge or based on the previous state. Digital input (logic level) sent to the MCU through the SPI. Safety purpose: Digital input (logic level) to perform an IC error monitoring (both IO_0 AND IO_1 are used if configured as safety inputs, see Figure 11).
• IO_1 is also selectable as follow: Safety purpose: FB_Core using a second resistor bridge (R3/R4 duplicated) connected to IO_1, to detect external resistor drift and trigger when FB_Core - IO_1 > ±150 mV max.
• IO_2:3 are selectable as follows: Digital input (logic level) sent to the MCU through the SPI. Wake-up input (logic level) on the rising or falling edge or based on the previous state. Safety purpose: Digital input (logic level) to monitor MCU error signals (both IO_2 AND IO_3 are used if configured as safety inputs). Only bi-stable protocol is available.

Table 8. I/Os configuration

Figure 10. IO_2:3 MCU error monitoring: bi-stable protocol

• IO_4:5 are selectable as follows: Digital input (logic level) sent to the MCU through the SPI. Wake-up input (load dump proof) on rising or falling edge or based on previous state. Output gate driver (from VPRE) for low-side logic level MOSFET. Safety purpose: Digital input (logic level) to perform an IC error monitoring (both IO_4 AND IO_5 are used if configured as safety inputs, see Figure 11).

Figure 11. External error signal handling

5.15 SAFE output pi ns (FS0B, RSTB)

an electrical safe circuitry independent from MCU to deactivate the whole system and set the ECU in a protected and known state. FS0B pin, when the application is ready to start. An external pull-up circuitry is mandatory connected to VDDIO or VSUP3.

• If the pull-up is connected to V DDIO, the value recommended is 5.0kΩ, there will be no current in LPOFF since VDDIO is OFF in LPOFF mode.
• If the pull-up is connected to VSUP3, the value must be above 10 kΩ, there will be a current in the pull-up resistor to consider at application level in LPOFF mode. FCCU_eout[0] FCCU_eout[1] Reset Phase Normal Phase Error Phase Config Phase 33907_8 Internal IO_4 signal latched Error signal (IO_4 input) Acknowledgment counter Acknowledgement signal from MCU (IO_5 input) Filter time Reset counter Restart Acknowledgment counter FS0B RSTB The error is acknowledged by the MCU then, internal IO_4 signal is released The error is NOT acknowledged by the MCU So, FS0B is activated at the end of the counter

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The RSTB pin must be connected to MCU and is active low. An external pull-up resistor must be connected to VDDIO. In default configuration, the RST delay time has three possible values depending on the mode and product configuration:

• The longest one is used automatically fo llowing a Power On Reset or when resulting from LPOFF mode (Low Power Off).
• The two reset durations are then available in the INIT_FSSM1 register, which are 1.0 ms and 10 ms. The configured duration is finally used in the normal operation when a fault occurs leading to a reset activation. The INIT_FSSM1 register is available (writing) in the INIT FS phase.

5.16 DEBUG input (entering in debug mode)

The DEBUG pin allows the product to enter Debug mode. To activate the Debug mode, voltage applied to the DEBUG pin must be within the VDEBUG_IL and VDEBUG_IH range at start-up. If the voltage applied to DEBUG pin is out of these limits, before VCORE ramp-up, the device settles into Normal mode. When the Debug mode is activated, the FS0B output is asserted low at start-up. As soon as the FS0B is released to “high” via SPI (Good WD answer and FS_OUT writing) this pin is never activated whatever the fault is reported. In Debug mode, any errors from watchdog are ignored (No reset and No fail-safe), even if the whole functionality of the watchdog is kept ON (Seed, LFSR, Wd_refresh counter, WD error counter). This allows an easy debug of the hardware and software routines (i.e. SPI commands). When the Debug mode is activated, the CAN transceiver is set to Normal operation mode. This allows communication with the MCU, in case SPI communication is not available (case of MCU not programmed). To exit Debug mode, the pin must be tied to Ground through an external pull-down resistor or to VPRE through an external pull-up resistor and a Power On Reset occurs.

6 Functional device operation

6.1 Mode and state description of main state machine

The device has several operation modes. The transition and conditions to enter or leave each mode are illustrated in the functional state diagram (Figure 13). Two state machines are working in parallel. The Main state machine is in charge of the power management (VPRE,

6.1.1 Buck or buck boost configuration

An external low side logic level MOSFET (N-type) is required to operate in non-inverting buck-boost converter. The connection of the external MOSFET is detected automatically during the start-up phase (after a Power On Reset or From LPOFF).

• If the external low-side MOSFET is NOT connected (GATE_LS pi n connected to PGND), the product is configured as a standard buck converter.
• If the external low-side MOSFET is connected (GATE_LS pin connec ted to external MOSFET gate), the product is configured as a non-inverting buck-boost converter. The automatic detection is done by pushing 300 μA current on Gate_LS pin and monitoring the corresponding voltage generated. If a voltage >120 mV is detected before the 120 μs timeout, the non-inverting buck-boost configuration is locked. Otherwise, the standard buck configuration is locked. The boost driver has a current capability of ±300 mA.

6.1.2 VPRE on

Pre-regulator is an SMPS regulator. In this phase, the pre-regulator is switched ON and a softstart with a specified duration tPRE_SOFT is started to control the VPRE output capacitor charge.

6.1.3 Select pin configuration

This phase is detecting the required voltage level on VAUX and VCCA, according to resistor value connected between the SELECT pin and ground. If the SELECT pin is connected to VPRE via the resistor, it disables the VAUX regulator at start-up.

6.1.4 VCORE/VAUX/VCCA on

In this stage, the three regulators VCORE, VAUX, VCCA are switched ON at the same time with a specified soft start duration. The CAN_5V is also started at that time.

6.1.5 INIT main

This mode is automatically entered after the device is “Powered ON”. When RSTB is released, initialization phase starts where the device can be configured via the SPI. During INIT phase, some registers can only be configured in this mode (refer to Table 15 and Table 16). Other registers can be written in this mode, and also in Normal mode. Once the INIT registers configurations are complete, a last register called “INIT INT” must be configured to switch to Normal mode. Writing data in this register (even same default values), automatically locks the INIT registers, and the product switches automatically to Normal mode in the Main state machine.

6.1.6 Normal

In this mode, all device functions are available. This mode is entered by a SPI command from the INIT phase by writing in the INIT INT register. While in Normal mode, the device can be set to Low Power mode (LPOFF) using secured SPI command.

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6.1.7 Low power mode off

The Main State Machine has 3 LPOFF modes with different conditions to enter and exit each LPOFF mode as described here after. After wake up from LPOFF, all the regulators are enabled by default. In LPOFF, all the regulators are switched OFF. The register configuration, the Vpre behavior and the ISO pulse requirement are valid for the 3 LPOFF modes.

6.1.7.1 LPOFF - sleep

Entering in Low Power mode LPOFF - SLEEP is only available if the product is in Normal mode by sending a secured SPI command. In this mode, all the regulators are turned OFF and the MCU connected to the VCORE regulator is unsupplied. Before entering in LPOFF Power mode OFF-sleep, the Reset Error Counter must go back to value “0” (“N” consecutive good watchdog refresh decreases the reset error counter to 0). “N” = RSTb_err_2:0 x (WD_refresh_2:0 + 1). Once the 33907/33908 is in LPOFF - SLEEP, the device monitors external events to wake-up and leave the Low Power mode. The wake-up events can occur and depending of the device configuration from:

• C A N
• L I N
• I/O inputs When a wake-up event is detected, the device starts the main state machine again by detecting the VPRE configuration (BUCK or BUCK- BOOST), the wake-up source is reported to the dedicated SPI register, and the Fail-safe state machine is also restarted.

6.1.7.2 LPOFF - V PRE_UV

LPOFF- VPRE_UV is entered when the device is in the INIT or Normal mode, and if the VPRE voltage level is passing the VPRE_UV_L_4P3 threshold (typ 4.3 V). After 1.0 ms the device attempts to recover by switching ON the VPRE again.

6.1.7.3 LPOFF - deep FS

LPOFF - DEEP FS is entered when the device is in Deep Fail-safe and if the Key is OFF (IO_0 is low). To exit this mode, a transition to high level on IO_0 is required. IO_0 is usually connected to key ON key OFF signal.

6.1.7.4 Register configuration in LPOFF

In LPOFF, the register settings of the Main State Machine are kept because the internal 2.5 V main digital regulator is available for wake- up operation. However, the register settings of the Fail-safe state machine are erased because the 2.5 V fail safe digital regulator is not available in LPOFF. As a consequence, after a wake-up event, the configuration of the Fail-safe registers must be done again during initialization phase (256 ms open window).

6.1.7.5 V PRE behavior in LPOFF

When device is in LPOFF Sleep mode, and if the VSUP < VSUP_UV_7, VPRE is switched on to maintain internal biasing and wake-up capabilities on IOs, CAN or LIN.

• I f VPRE is configured as a non-inverting buck-boost converter, VPRE is switched ON in SMPS mode with boost functionality.
• I f VPRE is configured as a standard buck converter, VPRE is switched ON in Linear mode following VSUP.

6.1.7.6 ISO pulse in LPOFF

If the application has to sustain ISO pulses on VBAT in LPOFF mode, the connection of a an external zener diode and a serial resistor to the ground is mandatory (see Figure 12). During repetitive ISO pulses on Vbat, the capacitors connected on VSUP line are more and more charged and cannot be discharged thanks to the extremely low-current needed to maintain wake-up capabilities on IOs, CAN, and LIN. As a consequence, if a leakage path is not created artificially with those discrete components the voltage on VSUP line can exceed the absolute maximum rating supported by this pin.

Figure 12. Components involved under ISO pulse in LPOFF

6.2 Mode and state description of fail-safe state machine

6.2.1 LBIST

is run at start-up and after each wake-up event when the device is in LPOFF mode.

6.2.2 Select pin configuration

VAUX for the voltage supervision.

6.2.3 ABIST

like the overvoltage and undervoltage detections of the voltage supervisor and the RTSTB and FS0B fail-safe outputs feedback (Table 9). The ABIST is run at start-up and after each wake-up event when device is in LPOFF mode.

6.2.4 Release RSTB

In this state, the device releases the RSTB pin. Table 9. Regulators and fail-safe pins checked during ABIST

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6.2.5 INIT FS

This mode is automatically entered after the device is “powered on” and only if Built-in Self Tests (Logic and Analog) have been passed successfully. This INIT FS mode starts as soon as RSTB is released (means no “Activate RST” faults are present and no external reset is requested). Faults leading to an “Activate RST” are described in Reset error counter. In this mode, the device can be configured via the SPI within a maximum time of 256 ms, including first watchdog refresh. Some registers can only be configured in this mode and is locked when leaving INIT FS mode (refer to Table 15 and Table 16). It is recommended, to configure first the device before sending the first WD refresh. As soon as the first good watchdog refresh is sent by the MCU, the device leaves this mode and goes into Normal WD mode.

6.2.6 Normal WD is running

In this mode, the device waits for a periodic watchdog refresh coming from the MCU, within a specific configured window timing. Configuration of the watchdog window period can be set during INIT FS phase or in this mode. This mode is exited if there are consecutive bad watchdog refreshes if there is an external reset request, or if a fault occurs leading to a RSTB activation.

6.2.7 RST delay

When the reset pin is asserted low by the device, a delay runs, to release the RSTB, if there are no faults present. The reset low duration time is configurable via the SPI in the INIT_ FSSM1 register, which is accessible for writing only in the INIT FS phase.

6.3 Deep fail safe state

The Fail-safe state machine monitors the RSTB pin of the device and count the number of reset(s) happening in case of fault detection (see Reset error counter). As soon as either the Reset Error Counter reach its final value or the RESET pin remains asserted low for more than 8.0 s, the device moves to Deep Fail-safe state, identified by the “Wait Deep Fail-safe” state in the functional state diagram (Figure 13). When the device is in Deep Fail-safe state, all the regulators are OFF. To exit this state, a Key OFF / Key ON action is needed. IO_0 is usually connected to key signal. Key OFF (IO_0 low) will move the device to LPOFF-Deep FS, and Key ON (IO_0 high) will wake-up the device. The final value of the Reset Error Counter can be configured to 2 or 6 in the register INIT FSSM 2. During power up phase, the 8.0 s timer starts when the Fail-safe state machine enters in the “Select pin config detection” state and stop when the RSTB pin is released. During “INIT FS” state, the 8.0 s timer can be disabled in the register INIT SUPERVISOR 2. During “Normal WD running” state, the 8.0 s timer is activated at each RSTB pin assertion.

6.4 Functional state diagram

Figure 13. Simplified state diagram

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6.5 Fail-safe machine

independent from the rest of the circuitry, to avoid common cause failure. bonding wire per pin is used). Additionally, the ground connection is redundant as well to avoid any loss of ground. handling and controls the fail-safe outputs. handle the different kinds of failures, and to give a chance for the system to come back to a normal state.

6.5.1 Fail-safe machine state diagram

Figure 14. Detailed fail-safe state diagram

6.5.2 Watchdog operation

voltage on the DEBUG pin at start-up. The watchdog can also be inhibited through the SPI register to allow “reprogramming” (ie.at vehicle level through CAN). window is considered a wrong WD refresh.

6.5.2.1 Normal operation (first watchdog refresh)

a simple calculation based on this formula. As an example, the result of this calculation based on LFSR default value (0xB2) is 0x4D. Figure 15. Watchdog answer calculation Table 74. If the watchdog refresh is wrong or if the watchdog is not refreshed during this 256 ms open window (INIT FS phase), the device asserts the reset low and the RSTB error counter is incremented by “1”.

6.5.2.2 Normal wa tchdog refresh

restarts the window. This ensures the synchronization between MCU and 33907/33908.

• The new WD window duration (except after disable) will be taken in to account when a write in the WD_answer register occurs (good or bad WD answer) or when the previous WD window is finished without any writing (WD timeout)
• The new WD window duration after disable will be taken into account when SPI command is validated The duty cycle of the window is set to 50% and is not modifiable.

Figure 16. Windowed watchdog

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6.5.2.3 Watchdog in debug mode

counter, and reset counter. This allows the user to debug their software and ensure a good watchdog strategy in the application.

6.5.2.4 Wrong watchdo g refresh handling

On Reset or a transition on IO_O helps the system to recover.

6.5.2.5 Watchdog error counter

value of this counter is configurable in the INIT_WD register, but only when device is in INIT FS mode. Figure 17. Watchdog error counter configuration (INIT_WD register, Bits WD_CNT_error_1:0)

6.5.2.6 Watchdog refresh counter

error counter is decremented by “1” (case with WD_CNT_refresh_1:0 configured at 6). register, but only when device is in INIT FS mode. Figure 18. Watchdog refresh counter configuration (INIT_WD register, WD_CNT_refresh_1:0) meaning no WD refresh during closed or open windows, is considered as a wrong WD refresh. Table 10. Watchdog error table

1 WD Refresh NOK /

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6.5.3 Reset error counter

The reset error counter manages the reset events and counts the number of resets occurring in the application. This counter is incremented not only for the reset linked to consecutive wrong refresh watchdogs, but also for other sources of reset (undervoltage, overvoltage, external reset). The RST error counter is incremented by 1, each time a reset is generated. The reset error counter has two output values (intermediate and final). The intermediate output value is used to handle the transition from reset (RSTB is asserted low) to reset and fail where RSTB and FS0B are activated. The final value is used to handle the transition from reset and fail to deep reset and fail (Deep Fail-safe mode), where regulators are off, RSTB and FS0B are activated, and a power on reset or a transition on IO_0 is needed to recover. The intermediate value of the reset error counter is configurable to “1” or “3” using the RSTB_err_FS bit in the INIT FSSM2 register (Table 71). If RSTB_err_FS is set to “0”, it means the device activates FS0B when the reset error counter reaches level “3”. If RSTB_err_FS is set to “1”, it means the device activates FS0B when the reset error counter reaches level “1”. This configuration must be done during INIT FS phase. The final value of the reset error counter is based on the intermediate configuration.

• RSTB_err_FS = 0 / Intermediate = 3; Final = 6 (Figure 19). When reset error counter reaches 6, the device goes into deep reset and fails.
• RSTB_err_FS = 1 / Intermediate = 1; Final = 2 (Figure 20). When reset error counter reaches 2, the device goes into deep reset and fails. In any condition, if the RSTB is asserted LOW for a duration longer than eight seconds, the device goes into deep reset and fails. Conditions that leads to an increment of the RSTB error counter, and according to the product configuration are:
• Watchdog error counter = 6
• Watchdog refresh NOK during INIT phase or Watchdog timeout
• IO_23 error detection (FCCU)
• Undervoltage
• O v e r v o l t a g e
• IO_1 FB_Core Delta
• FS0B shorted to VDD
• SPI DED
• Reset request by the SPI
• External reset Conditions leading to a transition go to FS, according to the product configuration are:
• IO_01/IO_23/IO_45 error detection
• Undervoltage
• O v e r v o l t a g e
• IO_1 FB_Core Delta
• Analog BIST fail
• SPI DED
• RSTB shorted to high

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6.5.3.1 RST error counter at star t-up or resuming from LPOFF mode

down to 0) and a right command is sent to FS_OUT register (Figure 23). Figure 21. Example of WD operation generating a reset (WD_error_cnt = 6) Figure 22. Example of WD operation leading a decrement of the reset error counter (WD_resfresh_cnt = 6)

Figure 23. Reset error counter and FS0B deactivation sequence (RSTB_err_FS = 0 & WD_CNT_error1:0 = 6)

6.5.4 Fail-safe output (FS0B) deactivation

• Fault is removed
• Reset error counter must be at “0”
• FS_OUT register must be filled with the right value.

6.5.4.1 Faults triggering FS0B activation

• IO_01/IO_23/IO_45 error detection
• Undervoltage
• Overvoltage
• IO_1 FB_Core Delta
• Analog BIST fail (not configurable)
• SPI DED (not configurable)
• RSTB shorted to high (not configurable)
• RSTB error counter level

6.5.5 SPI DED

Event Upset). Only fail-safe registers are concerned. During INIT FS mode, access to fail-safe registers for product configuration is open. Then once the INIT FS phase is over, the Hamming circuitry is activated to protect registers content. code but detected errors cannot be corrected. Flag is sent, RSTB and FS0B are activated.

6.5.6 FS_OUT register

dependant on the current WD_LFSR. LSB and MSB must be swapped and negative operation per bit must be applied. Figure 24. FS_OUT register based on LFSR value

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6.6 Input voltage range

can still be covered using only the Buck configuration. Figure 25. Input voltage range

• V SUP > 28 V: Potential VPRE thermal limitation RDS(on), Current limitation and Overcurrent detection are specified for VSUP < 28 V.
• V SUP < 19 V: Mux_out limitation IO_0 and IO_1 maximum analog input voltage range is 19 V. Internal 2.5 V reference voltage accuracy degraded.
• Buck only, V SUP < VSUP_UV_7: CAN communication is guaranteed for VSUP > 6.0 V. LIN communication according to SAEJ2602-2 specification is stopped (VSUP < 7.0 V). For VCCA and VAUX 5.0 V configuration, undervoltage triggers at low VSUP (refer to VCCA_UV_5 and VAUX_UV_5).

6.7 Power management operation

when the junction temperature of the pass transistor decrease below the TSD threshold.

6.7.1 VPRE voltage pre-regulator

regulated between 6.0 V and 7.0 V. fulfill application needs while the current load remains below the maximum current capability in all conditions. Figure 26. Pre-regulator: buck configuration Figure 27. Pre-regulator: buck boost configuration by the device at VSUP_UV_7 threshold. Transition between buck mode and boost mode is based on hysteresis (Figure 28).

• When VSUP > V SUP_UV_7, the converter works in buck mode and VPRE output is regulated at 6.5 V typic.
• When VSUP < V SUP_UV_7, the converter works in boost mode and VPRE output is regulated at 6.3 V typic. SW_pre2 VPRE Boots_pre Gate_LS SW_pre1 L_VPRE Cboot_pre Csnub_Vpre Rsunb_Vpre PGND PGND PGND D_Vpre PGND PGND PGND ESR cap. <100 mΩ ESR cap. <10 mΩ PGND Cout_Vpre1 Cout_Vpre2 Cout_Vpre3 Cout_Vpre4 SW_pre2 VPRE Boots_pre Gate_LS SW_pre1 L_Vpre Cboot_pre Csnub_Vpre Rsunb_Vpre PGND PGND PGND Optional D_Vpre LS_BB D_BB PGND PGND PGND ESR cap. <100 mΩ ESR cap. <10 mΩ PGND Cout_Vpre1 Cout_Vpre2 Cout_Vpre3 Cout_Vpre4

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Figure 28. Transition between buck and boost

6.7.1.1 Power up and power down sequence

Figure 29. Buck configuration power-up and power-down

Figure 30. Buck boost configuration power-up and power-down

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6.7.1.2 Cranking management

current guaranteed on VPRE.. Figure 31. Behavior during cranking (buck configuration) during cold cranking conditions.

Figure 32. Behavior during cranking (buck boost configuration)

6.7.1.3 Light load condition

Skipping mode during light load condition. Figure 33. Description of light load condition

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6.7.1.4 Input power feed forward condition

is transparent for the application. Figure 34. Input power feed forward principle

6.7.1.5 Overcurrent detection and current limitation

6.7.1.5.1 Overcurrent protection:

blanked when the pass transistor is switched ON during TPRE_OC to avoid parasitic switch OFF of the high-side gate driver.

6.7.1.5.2 Current limitation:

the next rising edge of the switching clock. limitation does not switch OFF the regulator. The current limitation protects the regulator when VPRE pin is shorted to GND.

Figure 35. Overcurrent and current limitation scheme

6.7.1.6 VPRE voltage monitoring

reporting an undervoltage. Diagnostic is reported in the dedicated register and generate an Interrupt. configuration (registers INIT SUPERVISOR 1,2,3).

6.7.1.7 VPRE efficiency

and has to be verified by measurement at application level.

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Figure 36. VPRE efficiency

6.7.2 VCORE voltage regulator

to use 1% accuracy resistors and set R4 = 8.06 kΩ and adjust R3 to obtain the final VCORE voltage needed for the MCU core supply. Figure 37. VCORE buck regulator

6.7.2.1 Light load condition

6.7.2.2 Current limitation

again before the next rising edge of the switching clock. undervoltage condition and bring the device in Fail-safe state. The current limitation does not switch OFF the regulator.

6.7.2.3 Voltage monitoring

(registers INIT SUPERVISOR 1,2, 3).

6.7.2.4 VCORE efficiency

the recirculation phase. Lower the diode Forward Voltage (VF) is, the better the efficiency. Figure 38. VCORE efficiency

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6.7.3 Charge pump and bootstrap

Both switching MOSFETs of VPRE and VCORE SMPS are driven by external bootstrap capacitors. Additionally, a charge pump is implemented to ensure 100% duty cycle for both converters. Each converter uses a 100 nF external capacitor minimum to operate properly.

6.7.4 VCCA voltage regulator

VCCA is a linear voltage regulator mainly dedicated to supply the MCU I/Os, especially the ADC. The output voltage is selectable at 5.0 V or 3.3 V. Since this output voltage can be used to supply MCU I/Os, the output voltage selection is done using an external resistor connected to the SELECT pin and ground if VAUX is used. When VAUX is not used, the resistor is connected between the SELECT pin and VPRE. When VCCA is used with the internal MOS transistor, VCCA_E pin must be connected to VPRE. The voltage accuracy is ±1.0% for 5.0 V configuration and ±1.5% for 3.3 V configuration with an output current capability at 100 mA. When VCCA is used with an external PNP transistor to boost the current capability up to 300 mA, the connection is detected automatically during the start-up sequence of the 33907/33908. In such condition, the internal pass transistor is switched OFF and all the current is driven through the external PNP to reduce the internal power dissipation. The output voltage accuracy with an external PNP is reduced to ±3.0% at 300 mA current load. The VCCA output voltage is used as a reference for the Auxiliary voltage supply (VAUX) when VAUX is configured as a tracking regulator.

6.7.4.1 Current limitation

A current limitation is implemented to avoid uncontrolled power dissipation of the internal MOSFET or external PNP transistor. By default, the current limitation threshold is selected based on the auto detection of the external PNP during start up phase.

• When the internal MOSFET transistor is used, the current is limited to I CCA_LIM_INT and the regulator is kept ON
• When the external PNP transistor is used, the current is limited to ICCA_LIM_OUT and the regulator is switch OFF after a dedicated duration TCCA_LIM_OFF under current limitation. A SPI command is needed to restart the regulator. In case of external PNP configuration only, the lowest current limitation threshold can be selected by SPI in the register INIT VREG 2 instead of the highest one. In order to limit the power dissipation in the external PNP transistor in case of short circuit to GND of VCCA pin, a current limitation foldback scheme is implemented to reduce the current limitation to ICCA_LIM_FB when VCCA is below VCCA_LIM_FB.

6.7.4.2 Voltage monitoring

The overvoltage detection switches OFF the regulator. The regulator remains ON in case of undervoltage detection. Diagnostic is reported in the dedicated register, generate an Interrupt and may bring the application in Fail-safe state depending on the supervisor configuration (registers INIT SUPERVISOR 1, 2, 3).

6.7.5 VAUX voltage regulator

VAUX is a highly flexible linear voltage regulator that can be used either as an auxiliary supply dedicated to additional device in the ECU or as a sensor supply (i.e. outside the ECU). An external PNP transistor must be used (no internal current capability). If VAUX is not used in the application, VAUX_E and SELECT pins must be connected to VPRE in order to not populate the external PNP as described in Figure 60. If VAUX is used as an auxiliary supply, the output voltage is selectable between 5.0 V, 3.3 V. Since this voltage rail can be used to supply MCU IOs, the selection is done with an external resistor connected between the SELECT pin and ground. In such case, the voltage accuracy is ±3.0% with a maximum output current capability at 300 mA. If VAUX is used as a sensor supply rail, the output voltage is selectable between 5.0 V and 3.3 V. VCCA can be used as reference for the sensor supply used as tracker. The selection is done during the INIT phase and secured (bit VAUX_TRK_EN in the register INIT VREG2). The tracking accuracy is ±15 mV.

Figure 39. Example of VAUX used in tracker mode

6.7.5.1 Current limitation

limitation foldback scheme is implemented to reduce the current limitation to IAUX_LIM_FB when VAUX is below VAUX_LIM_FB. Figure 40. VAUX current limitation scheme with foldback mechanism

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6.7.5.2 Voltage monitoring

The overvoltage detection switches OFF the regulator. The regulator remains ON in case of undervoltage detection. Diagnostic is reported in the dedicated register, generate an Interrupt and may bring the application in Fail-safe state depending on the supervisor configuration (registers INIT SUPERVISOR 1, 2, 3).

6.7.6 CAN_5V voltage regulator

The CAN_5V voltage regulator is a linear regulator fully dedicated to the internal HSCAN interface. By default, the CAN_5V regulator and the undervoltage detector are enabled, the overvoltage detector is disabled. The overvoltage detector can be enabled by SPI during INIT_MAIN sate. If the overvoltage detector is enabled, the CAN_5V regulator switches OFF when an overvoltage is detected. The undervoltage detector is disabled when the regulator is switched OFF reporting an undervoltage. Diagnostic is reported in the dedicated register and generate an Interrupt. The CAN_5V regulator is not safety regulator. Consequently, the CAN_5V voltage monitoring (overvoltage, undervoltage) will never assert RSTB or FS0B Fail-safe pins. If the 33907/33908 internal CAN transceiver is not used in the application, the CAN_5V regulator can be used to supply an external standalone CAN or FLEX-RAY transceiver, providing that the current load remains below the maximum current capability in all conditions. In that case, the internal CAN transceiver must be put in Sleep mode without wake-up capability.

6.7.7 Power dissipation

The 33907/33908 provides high performance SMPS and Linear regulators to supply high end MCU in automotive applications. Each regulator can deliver:

• V PRE (6. 5V) up to 2.0 A
• V CORE (from 1.2 V to 3.3 V range) up to 0.8 A (33907) or up to 1.5 A (33908)
• V CCA (3.3 V or 5.0 V) up to 100 mA (with internal MOS) or up to 300 mA (with external PNP)
• V AUX (3.3 V or 5.0 V) up to 300 mA (with external PNP)
• V CAN (5.0 V) up to 100 mA A thermal dissipation analysis has to be performed based on application use case to ensure the maximum silicon junction temperature does not exceed 150 °C. Two use cases covering the two main VCORE voltage configurations are provided in Figure 41.
• use case 1: V CORE = 3.3 V, ICORE = 0.7 A, VCCA with int. MOS
• use case 2: V CORE = 1.2 V, ICORE = 1.4 A, VCCA with ext. PNP Both use cases have a total internal power dissipation below 0.9 W. A junction to ambient thermal resistivity of 30 °C/W allows the application to work up to 125 °C ambient temperature. A good soldering of the package expose pad is highly recommended to achieve such thermal performance.

Figure 41. Power dissipation use case 1) CAN transceiver dissipation includes CAN_5V regulator dissipation. 2) 25% CAN traffic means the CAN bus is dominant for 25% of time and recessive for the remaining 75%.

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Figure 42. Power dissipation versus ICORE, ICCA, or IPRE

6.7.8 Start-up sequence

out is only applicable when the device is under a Power-On-Reset condition, which means the initial condition is VSUP < VSUP_UV_L (i.e. other different voltage rails automatically start, as described in Figure 43. Figure 43. Start-up scheme monitoring the RSTB pin low, will finally send the device in Deep Fail-safe mode after 8.0 s.

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6.8 CAN transceiver

Figure 44. CAN simplified block diagram

6.8.1 Operating modes

6.8.1.1 Normal mode

internal pull up resistor TXDPULL-UP connected to VDDIO.

Figure 45. CAN timing diagram

6.8.1.2 Sleep mode

and RXD pins are pulled down to GND, both driver and receiver are OFF. device enters is LPOFF. After LPOFF, the initial CAN mode prior to enter LPOFF is restored (Figure 46). Figure 46. CAN transition when device goes to LPOFF

6.8.2 Fault detection

6.8.2.1 TXD permanent dominant (timeout)

If TXD is set low for a time longer than TDOUT parameter, the CAN drivers are disabled, and the CAN bus will return to recessive state. operating when the CAN transceiver is in Normal mode and Listen only mode.

0 Sleep, no wake-up capab ility 0 Sl eep, no wake-up capability 0 Sleep, no wake-up capability

1 Listen Only 1 Listen Only

10 Sleep, wake-up capability 10 Sleep, wake-up capab ility

11 Normal 11 Normal

10 Sleep, wake-up capability

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Figure 47. TXD Dominant Timeout Detection

6.8.2.2 RXD permanent recessive

level, and seen from a CAN controller as a bus idle state.

6.8.2.3 CAN bus short-circuits

receiver are not be disabled. The CANH and CANL failure detection is operating when the CAN transceiver is in Normal mode. is operating when the CAN transceiver is in Normal mode and Listen Only mode.

6.8.2.4 CAN current limitation

6.8.2.5 CAN overtemperature

receiver continues to operate. The CAN_mode MSB bit is set to 0 and the flag CAN_OT is reported in the Diag CAN_LIN register. error detection after setting the CAN_mode to Normal Operation and when a high level is detected on TXD.

Figure 48. Overtemperature behavior

6.8.2.6 Distinguish CAN diagnostics and CAN errors

generated by the CAN errors can be inhibited setting INT_inh_CAN bit at “1” in the “INIT INT” register. The list of CAN Diagnostic and CAN Error bits is provided in Table 11.

6.8.3 Wake-up mechanism

T3PTOX timeout. T3PTOX = T3PTO1 or T3PTO2 depending on the SPI selection. Table 11. CAN diagnostic and CAN error bits Event 1: over temperature detection. CAN driver disable. Event 2: temperature falls below “overtemp. threshold minus hysteresis” => CAN driver remains disable. Event 3: temperature below “overtemp. threshold minus hysteresis” and TxD high to low transition => CAN driver enable. Event 4: temperature above “overtemp. threshold minus hysteresis” and TxD high to low transition => CAN driver remains disable.

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6.8.3.1 Single pulse detection

Figure 49. Single pulse wake-up pattern illustration

6.8.3.2 Multiple pulse detection

• event 3: a dominant level (event 3) longer than t3PWU.

which would prevent system to enter in low-power mode. Figure 50. Multiple pulse wake-up pattern illustration

6.9 LIN transceiver

This chapter applies to 33907L and 33908L versions.

6.9.1 Simplified block diagram

Figure 51. LIN simplified block diagram

6.9.2 Operating modes

6.9.2.1 Normal mode

TXDLPULL-UP connected to VDDIO.

6.9.2.2 Sleep mode

RXDL pins are pulled down to GND.

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6.9.3 Baud rate selection

of the main logic. Depending of the baud rate setting, the corresponding LIN slope control is automatically selected. Figure 52. LIN timings for normal baud rate (20 kB/s) Figure 53. LIN timings for slow baud rate (10 kB/s)

Figure 54. LIN receiver timings

6.9.4 Fault detection

6.9.4.1 VSUP undervoltage

(VSUP<VLIN_UV), the LIN bus goes in recessive state to avoid wrong communication.

6.9.4.2 TXDL permanent dominant (timeout)

prevents the bus to be set in dominant state permanently, in case a failure sets the TXDL input permanently to a low level. on TXDL. The TXDL failure detection is operating when the LIN transceiver is in Normal mode and Listen Only mode.

6.9.4.3 RXDL permanent recessive

failure detection is operating when the LIN transceiver is in Normal mode and Listen Only mode.

6.9.4.4 LIN bus short-circuit

6.9.4.5 LIN current limitation

failure when the current falls below the current limitation value.

6.9.4.6 LIN overtemperature

receiver continues to operate. The LIN_mode MSB bit is set to 0 and the flag LIN_OT is reported in the Diag CAN_LIN register.

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high level is detected on TXDL.

6.9.4.7 LIN errors

bits is provided in Table 12.

6.9.5 Wake-up mechanism

for t > tBUS_WU, then a dominant to recessive transition. Figure 55. LIN wake-up pattern illustration Table 12. LIN error bits

7 Serial peripheral interface

7.1 High level overview

7.1.1 SPI

• Bit 15 read/write
• Bit 14 Main or fail -safe register target
• bit 13 to 9 (A4 to A0) to select the register address. Bit 8 is a parity bit in write mode, Next bit (=0) in read mode.
• bit7 to 0 (D7 to D0): control bits MISO, Master IN Slave Out bits:
• bits 15 to 8 (S15 to S8) are device status bits
• bits 7 to 0(Do7 to Do0) are either extended device status bi ts, device internal control register content or device flags. Figure 56 is an overview of the SPI implementation.

7.1.2 Parity bit 8 calculation

15-9, 7-0 sequence (this is the whole 16-bits of the write command except bit 8). Bit 8 must be set to 0 if the number of 1 is odd. Bit 8 must be set to 1 if the number of 1 is even.

7.1.3 Device status on MISO

to allow bi-directional communication between the 33907/33908 and the MCU. The SPI is used for configuration and diagnostic purposes. Figure 56. SPI overview and sampled at falling edge. Msb first. for write commands, MOSI bits [15] = [1].

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read back in order to ensure that its content (default setting or value previously written) is correct.

7.1.4 Register description

accesses is 3.5 µs, some SPI accesses to the main registers can be done in between (Figure 57).

7.2 Detail operation

Figure 57. MOSI / MISO SPI command organization Table 13. MOSI bits description

0 READ

0 Number of “1” (bit15:9 and bit 7:0) is odd

1 Number of “1” (bit15:9) and bit 7:0) is even

Table 14. MISO bits description

0 No WU event

1 WU event

0 No event

1 CAN event

1 LIN event

0 No IO transition

1 IO transition

1 Event occurred

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7.2.1 Register address table

Table 15 is a list of device registers and addresses coded in bits 13 to 9 in MOSI for main logic. Table 15. Register mapping of main logic Table 16. Register mapping of fail-safe logic

7.2.2 Secured SPI command

• Secure 3 = NOT(Bit5)
• Secure 2 = NOT(Bit4)
• Secure 1 = Bit7
• Secure 0 = Bit6 W D _ L F S R 1 00111 #39(27h) Write (No restriction) and Read Table 74 WD_answer 1 01000 #40(28h) Write (No restriction) and Read Table 76 F S _ O U T 1 01001 #41(29h) Write (No restriction) Table 78 RSTb request 1 01010 #42(2Ah) Write (No restriction) Table 80 I N I T W D 1 01011 #43(2Bh) Write during INIT phase then Read only Table 82 D i a g F S 1 1 01100 #44(2Ch) Read only Table 84 WD_Counter 1 01101 #45(2Dh) Read only Table 86 Diag_FS2 1 01110 #46(2Eh) Read only Table 88

Table 17. Secured SPI Table 16. Register mapping of fail-safe logic (continued)

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7.3 Detail of register mapping

7.3.1 Init VREG 1

7.3.2 Init Vreg 2

Table 18. INIT VREG1 register configuration Table 19. Description and configuration of the bits (Default value in bold)

0 ENABLED

1 DISABLED

0 No Monitoring (IO_1 is used as analog & digital input)

1 Monitoring enabled (IO_1 can NOT be used for analog /digital input neither for WU from LPOFF)

Table 20. INIT VREG2 register configuration

7.3.3 Init CAN_LIN

Table 21. INIT VREG2. description and configuration of the bits (default value in bold)

1 Tracking enabled

Table 22. INIT CAN_LIN register description Table 20. INIT VREG2 register configuration (continued)

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7.3.4 INIT IO_WU1

Table 23. INIT CAN_LIN. description and configuration of the bits (default value in bold)

1 Single dominant pulse

Table 24. INIT IO_WU1 register description Table 22. INIT CAN_LIN register description (continued)

7.3.5 INIT IO_WU2

Table 25. INIT IO_WU1. description and configuration of the bits (default value in bold)

00 NO wake-up capability

01 Wake-up on rising edge only

10 Wake-up on falling edge only

11 Wake-up on any edge

0 INT NOT masked

Table 26. INIT IO_WU2 register description

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Table 27. INIT IO_WU2. description and configuration of the bits (default value in bold)

1 INT masked

Table 26. INIT IO_WU2 register description (continued)

7.3.6 INIT INT

Table 28. INIT INT register description Table 29. INIT INT. description and configuration of the bits (default value in bold)

0 All INT sources

1 LIN error bits changed INHIBITED

1 All INT INHIBITED

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7.3.7 HW config

1 CAN error bits changed INHIBITED

Table 30. HW config register description Table 31. HW config. description and configuration of the bits (default value in bold)

0 Buck-Boost

1 Buck only

0 External PNP connected

1 Internal MOSFET

Table 29. INIT INT. description and configuration of the bits (default value in bold) (continued)

7.3.8 WU source

0 Normal operation

1 DEBUG mode selected

Table 32. WU source register description Table 33. WU source. description and configuration of the bits (default value in bold)

0 No Wake-up

1 WU event detected

Table 31. HW config. description and configuration of the bits (default value in bold) (continued)

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7.3.9 IO input

Table 34. IO input register description Table 35. IO input. description and configuration of the bits

0 Low

Table 33. WU source. description and configuration of the bits (default value in bold)(continued)

7.3.10 Status Vreg1

7.3.11 Status VREG2

Table 36. STATUS VREG1 register description Table 37. Status Vreg1. description and configuration of the bits (default value in bold)

1 Ipff mode activated

0 No current limitation (I PRE_PK < IPRE_LIM)

1 Current limitation (I PRE_PK > IPRE_LIM)

0 No thermal warning (T J < TWARN_PRE)

1 Thermal warning (T J > TWARN_PRE)

Table 38. STATUS VREG2 register description Table 35. IO input. description and configuration of the bits(continued)

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7.3.12 Diag Vreg1

Table 39. Status Vreg2. description and configuration of the bits (default value in bold)

0 No current limitation (I CORE_PK < ICORE_LIM)

1 Current limitation (I CORE_PK > ICORE_LIM)

0 No thermal warning (T J < TWARN_CORE)

1 Thermal warning (T J > TWARN_CORE)

0 SMPS OFF

1 SMPS ON

0 No thermal warning (T J < TWARN_CCA)

1 Thermal warning (T J > TWARN_CCA)

0 No current limitation (I CCA < ICCA_LIM)

1 Current limitation (I CCA > ICCA_LIM)

0 No current limitation (I AUX < IAUX_LIM)

1 Current limitation (I AUX > IAUX_LIM)

0 No current limitation (I CAN < ICAN_LIM)

1 Current limitation (I CAN > ICAN _LIM)

Table 40. DIAG VREG1 register description

7.3.13 Diag Vreg2

Table 41. Diag Vreg1. description and configuration of the bits (default value in bold)

1 TSD occurred (T J > TSD_PRE)

0 No overvoltage (V PRE < VPRE_OV)

1 Overvoltage detected (V PRE > VPRE_OV)

0 No undervoltage (VPRE > VPRE_UV)

1 Undervoltage detected (V PRE < VPRE_UV)

1 TSD occurred (T J > TSD_CORE)

0 No overvoltage (V CORE_FB < VCORE_FB_OV)

1 Overvoltage detected (V CORE_FB > VCORE_FB_OV)

0 No undervoltage (V CORE_FB > VCORE_FB_UV)

1 Undervoltage (V CORE_FB < VCORE_FB_UV)

Table 42. DIAG VREG2 register description

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7.3.14 Diag Vreg3

Table 43. Diag Vreg2. description and configuration of the bits (default value in bold)

1 TSD occurred (T J > TSD_CAN)

0 No Overvoltage (V CAN < VCAN_OV)

1 Overvoltage detected (V CAN > VCAN_OV)

0 No undervoltage (V CAN > VCAN_UV)

1 Undervoltage detected (V CAN < VCAN_UV)

0 No TSD (T J < TSD_AUX)

1 TSD occurred (T J > TSD_AUX)

0 No overvoltage (V AUX < VAUX_OV)

1 Overvoltage detected (V AUX > VAUX_OV)

0 No undervoltage (V AUX > VAUX_UV)

1 Undervoltage detected (V AUX < VAUX_UV)

Table 44. DIAG VREG3 register description

Table 45. Diag Vreg3. description and configuration of the bits (default value in bold)

1 TSD occurred (T J > TSD_CCA)

0 No overvoltage (V CCA < VCCA_OV)

1 Overvoltage detected (V CCA > VCCA_OV)

0 No undervoltage (V CCA > VCCA_UV)

1 Undervoltage detected (V CCA < VCCA_UV)

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7.3.15 Diag CAN1

Table 46. DIAG CAN1 register description Table 47. Diag CAN1. description and configuration of the bits (default value in bold)

0 No failure

1 Failure detected

7.3.16 Diag CAN_LIN

Table 48. DIAG CAN_LIN register description Table 49. Diag CAN_LIN. description and configuration of the bits (default value in bold)

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7.3.17 Diag SPI

Table 50. DIAG SPI register description Table 51. Diag SPI. description and configuration of the bits (default value in bold)

1 Error detected in the secured bits

1 Wrong number of clock cycles (<16 or > 16)

1 SPI violation

0 Parity bit OK

1 Parity bit error

7.3.18 Mode

7.3.19 Vreg mode

Table 52. Mode register description Table 53. Mode. description and configuration of the bits (default value in bold)

0 No action

1 LPOFF mode

0 Not in INIT mode

1 INIT MODE

0 Not in Normal mode

1 Normal mode

0 No Request

1 Request for an INT pulse

Table 54. VREG mode register description

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7.3.20 IO_OUT-AMUX

Table 55. VREG mode. description and configuration of the bits (default value in bold)

0 DISABLED

1 ENABLED

Table 56. IO_OUT-AMUX register description

7.3.21 CAN_LIN mode

Table 57. IO_OUT-AMUX. description and configuration of the bits (default value in bold)

0 High-impedance (IO_4 configured as input)

1 ENABLED (IO_4 configured as output gate driver)

0 High-impedance (IO_5 configured as input)

1 ENABLED (IO_5 configured as output gate driver)

000 Vref

001 Vsns wide range

010 IO_0 wide range

011 IO_1 wide range

100 Vsns tight range

101 IO_0 tight range

110 IO_1 tight range

111 Die Temperature Sensor

Table 58. CAN_LIN mode register description

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Table 59. CAN_LIN mode. description and configuration of the bits (default value in bold)

00 Sleep / NO wake-up capability

01 LISTEN ONLY

10 Sleep / Wake-up capability

11 Normal operation mode

0 NO auto disable

1 Reset CAN_mode from “11” to “01” on CAN over temp or TXD dominant or RXD recessive event

1 Reset LIN_mode from “11” to “01” on LIN over temp or TXDL dominant or RXDL recessive event

1 Wake-up detected

1. CAN mode is automatically configured to “sleep + wake-up capability[10]” if CAN mode was different than “sleep + no wake-up capability [00]”

before the device enters in LPOFF. After LPOFF, the initial CAN mode prior to enter LPOFF is restored.

7.3.22 Can_Mode_2

7.3.23 INIT SUPERVISOR1

Table 60. CAN_MODE_2 register description Table 61. CAN_MODE_2. description and configuration of the bits (default value in bold) 1O N . V CAN OV flag is under monitoring. In case of OV the VCAN regulator is switched OFF. Table 62. INIT SUPERVISOR1 register description

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Table 63. INIT SUPERVISOR1. description and configuration of the bits (default value in bold) Description V CORE safety input.

00 No effect of V CORE_FB_OV and VCORE_FB_UV on RSTb and FSxx

11 Both V CORE_FB_OV and VCORE_FB_UV DO HAVE an impact on RSTb and FSxx

Description V CCA safety input.

00 No effect of V CCA_OV and VCCA_UV on RSTb and FSxx

11 Both V CCA_OV and VCCA_UV DO HAVE an impact on RSTb and FSxx

1 Wrong number of clock cycles (<16 or >16)

7.3.24 INIT SUPERVISOR2

Table 64. INIT SUPERVISOR2 register description Table 65. INIT SUPERVISOR2. description and configuration of the bits (default value in bold) Description V AUX safety input.

00 No effect of V AUX_OV and VAUX_UV on RSTb and FSxx

11 Both V AUX_OV and VAUX_UV DO HAVE an impact on RSTb and FSxx

Description Secured SPI communication chec k, concerns fail-safe logic only.

0 No error

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Table 65. INIT SUPERVISOR2. description and configuration of the bits (default value in bold) (continued)

7.3.25 INIT SUPERVISOR3

Table 66. INIT SUPERVISOR3 register description Table 67. INIT SUPERVISOR3. description and configuration of the bits (default value in bold)

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7.3.26 Init FSSM1

Table 68. INIT FSSM1 register description Table 69. INIT FSSM1. description and configuration of the bits (default value in bold)

1 SAFETY CRITICAL

1 SAFETY CRITICAL (External resi stor bridge monitoring active)

Table 67. INIT SUPERVISOR3. description and configuration of the bits (default value in bold) (continued)

7.3.27 Init FSSM2

Table 70. INIT FSSM2 register description Table 69. INIT FSSM1. description and configuration of the bits (default value in bold) (continued)

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Table 71. INIT FSSM2. description and configuration of the bits (default value in bold)

0 NOT SAFETY

0 Fccu_eaout_1:0 active HIGH

1 Fccu_eaout_1:0 active LOW

Table 70. INIT FSSM2 register description (continued)

7.3.28 WD window

Table 72. WD window register description Table 73. WD window. description and configuration of the bits (default value in bold)

0000 DISABLE

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7.3.29 WD_LFSR

main and fail-safe logics. Other errors flagged by the SPI_CLK bit. Table 74. WD LFSR register description Table 75. WD LFSR. description and configuration of the bits

1. Value Bit7:Bit0: 1111 1111 is prohibited.
2. During a write command, MISO reports the previous register content.

Table 73. WD window. description and configuration of the bits (default value in bold) (continued)

7.3.30 WD answer

Table 76. WD answer register description Table 77. WD answer. description and configuration of the bits (default value in bold)

0 No Reset

1 Reset occurred

0 No fail-safe

1 Fail safe event occurred / Also default state at power-up after LPOFF as FS0b is asserted low

0 WD refresh OK

1 WRONG WD refresh

1 Error detected

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report the latest information.

7.3.31 Fail-safe out (FS_out)

1 ECC done

Table 78. Fail-safe out register description Table 79. Fail-safe out. description and configuration of the bits Table 77. WD answer. description and configuration of the bits (default value in bold) (continued)

7.3.32 RSTB request

7.3.33 INIT_WD

Table 80. RSTB request register description Table 81. RSTB request. description and configuration of the bits (default value in bold)

1 Request a RSTb low pulse

Table 82. INIT WD register description

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Table 83. INIT WD. description and configuration of the bits (default value in bold) main and fail-safe logics. Other errors flagged by the SPI_CLK bit.

7.3.34 Diag FS1

7.3.35 WD counter

Table 84. DIAG FS1 register description Table 85. Diag FS1. description and configuration of the bits (default value in bold)

1 Short-circuit HIGH

0 No external RSTb

1 External RSTb

00 No Failure

01 Short-circuit LOW / open load

Table 86. WD counter register description

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7.3.36 Diag FS2

Table 87. WD counter. description and configuration of the bits (default value in bold) Table 88. DIAG FS2 register description Table 89. Diag FS2. description and configuration of the bits (default value in bold)

8 List of interruptions and description

through the SPI during INIT phase. It is possible to mask some Interruption source (see Detail of register mapping). Table 90. Interruptions list ILIM_CCA_OFF Current limitation maximum duration expiration. Only used when external PNP connected. ILIM_AUX_OFF Current limitation maximum duration expiration. Only used when external PNP connected. TSDCAN Temperature shutdown on the pass transistor. Auto restart when TJ < (TSDCAN - TSDCAN_HYST).

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Table 90. Interruptions list (continued)

9 Typical applications

Figure 58. 33907/33908 simplified application schematic with non-inverting buck-boost configuration Figure 59. VAUX/VCCA connection

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Figure 60. VCCA connection, VAUX not used Figure 61. VAUX not used, VCCA configuration up to 100 mA

10 Packaging

10.1 Package mechanical dimensions

perform a keyword search for the drawing’s document number. Table 91. Package mechanical dimensions

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11 References

The following are URLs where you can obtain information on related NXP products and application solutions NXP.com support pages Description URL AN4766 MC33907_08 System Basis Chip: Recommendations for PCB layout and external components https://www.nxp.com/webapp/Download?colCode=AN4766 AN4661 Designing the VCORE Compensation Network For The MC33907/MC33908 System Basis Chips http://www.nxp.com/files/analog/doc/app_note/AN4661.pdf AN4442 Integrating the MPC5643L and MC33907/08 for Safety Applications http://www.nxp.com/files/analog/doc/app_note/AN4442.pdf AN4388 Quad Flat Package (QFP) http://www.nxp .com/files/analog/doc/app_note/AN4388.pdf Power Dissipation Tool (Excel file) http://www.nxp.com/webapp/sps/site/ prod_summary.jsp?code=MC33908&fpsp=1&tab=Design_Tools_Tab MC33907_8SMUG MC33907_8 Safety Manual - User Guide https ://www.nxp.com/webapp/Download?colCode=MC33907_8SMUG FMEDA MC33907_8 FMEDA Upon demand KIT33907LAEEVB Evaluation Board http://www.nxp.com/webapp/sps/site/ prod_summary.jsp?code=KIT33907LAEEVB KIT33908LAEEVB Evaluation Board http://www.nxp.com/webapp/sps/site/ prod_summary.jsp?code=KIT33908LAEEVB KITMPC5643DBEVM Evaluation Daught er Board (Qorivva MPC5643L) http://www.nxp.com/webapp/sps/site/ prod_summary.jsp?code=KITMPC5643DBEVM MC33907 Product Summary Page http://www.nxp.com /webapp/sps/site/prod_summary.jsp?code=MC33907 MC33908 Product Summary Page http://www.nxp.com /webapp/sps/site/prod_summary.jsp?code=MC33908 Analog Home Page http://www.nxp.com/analog

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Revision Date Description of changes 1.0 11/2014 • Product Preview release 12/2014 • Initial release. No change to content. 2.0 1/2015

• Corrected WD_LFSR register access in read mode
• Added (35)
• Added clarifications after Table 77
• Correct minor typographic errors
• Changed document status to Advance Information
• Changed the document order number to MC33907-MC33908D2 3.0 1/2015 • Corrected Revision History
• Corrected typo for ICORE_LIM 4.0
• Updated V SUP_UV_7 max. value from 8.2 to 8.0 V in Table 4
• Updated Thermal Resistance values in Table 3
• Changed Thermal Resistance Junction to Case Top value from 14.4 to 24.2 in Table 3 on page 10
• Corrected a typo on page 46 (changed “For V SUP and VAUX 5.0 V” to “For VCCA and VAUX 5.0 V”)
• Corrected typo for V BUS_CNT in Table 4 on page 20
• Corrected typo for D2 and D3 in Table 5 on page 25 8/2016 • Updated to NXP document form and style 5.0 10/2016 • Corrected format (default values in bold) of the defaul t SPI register values to match Data sheet Rev. 4.0, 2/2015

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