33904

33904 FREESCALE | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 91

Technical content

Features

• Protected 5.0V or 3.3V regulators for MCU (part number selectable) and additional ICs (SPI configurable) with optional external PNP usage to increase current capability for MCU.
• Fully-protected embedded 5.0 V regulator for the CAN driver
• Extremely low quiescent current in low power modes
• Multiple under-voltage detections to address various MCU specifications and system operation modes (i.e. cranking)
• Multiple wake-up sources in low power modes: CAN or LIN bus, I/O transition, automatic timer, SPI message, and VDD over-current detection.
• Voltage, current and temperature protection with enhanced diagnostics that can be monitored by system via MUX output
• ISO11898-5 high speed CAN interfac e compatibility for baud rates of 40 kb/s to 1.0 Mb/s. LIN 2.1 and J2602 LIN interface compatibility
• Pb-free packaging designated by suffix code EK

Figure 1. 33905D Simplified Application Diagram

ORDERING INFORMATION

Range (TA) Package PCZ33905D3EK/R2 -40°C to 125°C

54 SOIC EP

32 SOIC EP

Q1* VBAUX SAFE RXD-L1 TXD-L1LIN-TERM 1 LIN-1 VE (5.0 V/3.3 V) VDD VSUP2 VAUXVCAUX LIN-TERM 2 LIN-2 RXD-L2 TXD-L2 MUX-OUT 33905D MCUSPI A/D CAN Bus LIN Bus LIN Bus VSENSE * = Optional

2 Freescale Semiconductor

Figure 2. 33905S Simplified Application Diagram Figure 3. 33904A Simplified Application Diagram

Table 1. Device Variations

Analog Integrated Circuit Device Data

4 Freescale Semiconductor

Figure 4. 33905D Internal Block Diagram

5 V Auxiliary

6 Freescale Semiconductor

Figure 5. 33905S Internal Block Diagram

Figure 6. 33904A Internal Block Diagram

8 Freescale Semiconductor

Figure 7. 33904/5 Pin Connections Table 2. 33904/5 Pin Definitions A functional description of each pin can be found in the Functional Pin Description section beginning on page 28. circuitry and the VDD regulator. Note 1: Exposed pad should be connected to electrical ground.

voltage detection, is available. voltage detection, is available. must be connected to this pin. 10 7 7 CANH Output CAN High CAN high output. 11 8 8 CANL Output CAN Low CAN low output. 16 13 13 VAUX Output VOUT Auxiliary Output pin for the auxiliary voltage. 17 14 14 MUX-OUT Output Multiplex Output Multiplexed output to be connected to an MCU A/D input. DD current sense measurements. Table 2. 33904/5 Pin Definitions (continued) A functional description of each pin can be found in the Functional Pin Description section beginning on page 28.

10 Freescale Semiconductor

low side can be activated for a cyclic sense function. selection of Safe Mode functionality.

23 N/A N/A TXD-L2 Input LIN Transmit

24,31 N/A N/A GND Ground Ground Ground of the IC.

25 N/A N/A RXD-L2 Output LIN Receive

LIN bus receive data output. 26 N/A N/A LIN2 Input/Output LIN bus LIN bus input output connected to the LIN bus. Input/Output LIN bus LIN bus input output connected to the LIN bus. LIN bus receive data output. to limit the input current during high voltage transients. condition occurs. The output is a push-pull structure. A functional description of each pin can be found in the Functional Pin Description section beginning on page 28.

A functional description of each pin can be found in the Functional Pin Description section beginning on page 28.

Analog Integrated Circuit Device Data

12 Freescale Semiconductor

ELECTRICAL CHARACTERISTICS

Table 3. Maximum Ratings permanent damage to the device.

Analog Integrated Circuit Device Data Freescale Semiconductor 13

• AECQ100(1) Human Body Model - JESD22/A114 (CZAP = 100 pF, RZAP = 1500 Ω) CANH and CANL. LIN1 and LIN2, Pins versus all GND pins all other Pins including CANH and CANL Charge Device Model - JESD22/C101 (CZAP = 4.0 pF) Corner Pins (Pins 1, 16, 17, and 32) All other Pins (Pins 2-15, 18-31) * According to IEC 61000-4-2 (CZAP = 150 pF, RZAP = 330 Ω) device unpowered, CANH and CANL pin without capacitor, versus GND device unpowered, LIN pin, versus GND device unpowered, VS1/VS2 (100 nF to GND), versus GND * According to “OEM_HW_Requirements_For_CAN_LIN_FR-Interfaces_V1 0_20081210.pdf” CANH, CANL without bus filter LIN with and without bus filter I/O with external components (22k - 10nF) VESD1-1 VESD1-2 VESD2-1 VESD2-2 VESD3-1 VESD3-2 VESD3-3 VESD4-1 VESD4-2 VESD4-3 ±8000 ±2000 ±750 ±500 ±15000 ±15000 ±15000 ±9000 ±12000 ±7000 V THERMAL RATINGS Junction temperature TJ 150 °C Ambient temperature TA -40 to 125 °C Storage temperature TST -55 to 165 °C THERMAL RESISTANCE Thermal resistance junction to ambient RθJA 50(4) °C/W Peak Package Reflow Temperature During Reflow(2), (3) TPPRT Note 3 °C Notes 1. ESD testing is performed in accordance with the Human Body Model (HBM) (C ZAP = 100 pF, RZAP = 1500 Ω) and the Charge Device Model (CDM), Robotic (CZAP = 4.0 pF). 2. The voltage on non-Vsup pins should never ex ceed the Vsup voltage at any time or permanent damage to the device may occur.Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. 3. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics. 4. This parameter was measured according to Figure 8 below:

Figure 8. PCB with Top and Bottom Layer Dissipation Area (Dual Layer) Table 3. Maximum Ratings (continued) permanent damage to the device.

Analog Integrated Circuit Device Data

14 Freescale Semiconductor

STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 4. Static Electrical Characteristics reflect the approximate parameter means at TA = 25°C under nominal conditions, unless otherwise noted.

Analog Integrated Circuit Device Data Freescale Semiconductor 15 STATIC ELECTRICAL CHARACTERISTICS Notes 5. All parameters in spec (ex: V DD regulator tolerance). 6. Device functional, some parameters could be out of spec. V DD is active, device is not in Reset Mode if the lowest VDD under-voltage reset threshold is selected (approx. 3.4 V). CAN and I/Os are not operational. 7. In Run Mode, CAN interface in Sleep Mode, 5 V-CAN and VAUX turned off. IOUT at VDD < 50 mA. Ballast: turned off or not connected. VDD VOLTAGE REGULATOR, PIN VDD Output Voltage VSUP 5.5 to 27 V, IOUT 0 to 100 mA VSUP 5.5 to 27 V, IOUT 100 to 150 mA VSUP 5.5 to 27 V, IOUT 0 to 150 mA VOUT-5 4.9 4.9 5.0 5.0 5.0 5.1 5.1 V Drop voltage without external PNP pass transistor IOUT = 100 mA IOUT = 150 mA VDROP 330 450 500 mV Drop voltage with external transistor IOUT = 200 mA (I_BALLAST + I_INTERNAL) VDROP-B - 350 500 mV External ballast versus internal current ratio (I_BALLAST = K x Internal current) K 1.5 2.0 2.5 Output Current limitation, without external transistor ILIM 150 350 550 mA Temperature prewarning (guaranteed by design) TPW - 140 - °C Thermal shutdown (guaranteed by design) TSD 160 - - °C Range of decoupling capacitor (guaranteed by design) CEXT 4.7 - 100 μF Low Power Mode VDD ON, output voltage -5.0 V, IOUT ≤ 50 mA (time limited)

5.6 V ≤ VSUP ≤ 27 V

4.75 5.0 5.25 V Low Power Mode VDD ON, dynamic output current capability (Limited duration. Ref to device description). LP-IOUTDC - - 50 mA Low Power VDD ON Mode: - Over-current wake-up threshold. - Hysteresis LP-ITH 1.0 0.1 3.0 1.0 mA Low Power Mode VDD ON, drop voltage, at IOUT =30 mA (Limited duration. Ref to device description). LP-VDROP - 200 400 mV Low Power Mode VDD ON, min VSUP operation (Below this value, a VDD, under-voltage reset may occur) LP-MINVS 5.5 - - V VDD when Vsup < Vsup-th1, at I_VDD <= 10uA (guaranteed by design) VDD_off 0.3 V VDD when Vsup >= Vsup-th1, at I_VDD <= 40mA (guaranteed with parameter Vsup-th1 VDD_start up 3.0 V Table 4. Static Electrical Characteristics (continued) reflect the approximate parameter means at TA = 25°C under nominal conditions, unless otherwise noted.

Analog Integrated Circuit Device Data

16 Freescale Semiconductor

STATIC ELECTRICAL CHARACTERISTICS VOLTAGE REGULATOR FOR CAN INTERFACE SUPPLY, PIN 5 V-CAN(8) Output voltage, VSUP2 = 5.5 to 40 V IOUT 0 to 80 mA IOUT 80 to 200 mA 5V-C OUT 4.75 4.75 5.0 5.0 5.25 5.25 V Output Current limitation (10) 5V-C ILIM 160 280 - mA Under-voltage threshold 5V-C UV 4.1 4.5 4.7 V Thermal shutdown (guaranteed by design) 5V-C TS 160 - - °C External capacitance (guaranteed by design) CEXT-CAN 1.0 - 100 μF V AUXILIARY OUTPUT, 5 V AND 3.3 V SELECTABLE PIN VB-AUX, VC-AUX, VAUX(9) VAUX output voltage, VSUP = VSUP2 5.5 to 40 V, IOUT 0 to 150 mA VAUX5 4.75 5.0 5.25 V VAUX output voltage, VSUP = VSUP2 5.5 to 40 V, IOUT 0 to 150 mA VAUX3 3.2 3.3 3.4 V VAUX under-voltage detector (5.0 V) - Low Threshold - Hysteresis VAUX-UVTH5 4.2 0.06 4.5 4.70 0.12 V VAUX under-voltage detector (5 and 3.3V versions) VAUX-UVTH3 2.75 3.0 3.2 V VAUX over-current threshold detector Vaux set to 3.3V Vaux set t 5.0V VAUX-ILIM 250 230 360 330 450 430 mA External capacitance (guaranteed by design) Vaux cap 2.2 - 100 μF UNDERVOLTAGE RESET AND RESET FUNCTION, RST PIN VDD under-voltage threshold down - 90% VDD (VDD 5.0 V)(11), (13) VDD under-voltage threshold up - 90% VDD (VDD 5.0 V) RST-TH1-5 4.5 4.65 4.85 4.90 V VDD under-voltage reset threshold down - 70% VDD (VDD 5.0 V)(12), (13) RST-TH2-5 2.95 3.2 3.45 V Hysteresis for threshold 90% VDD, 5.0 V device for threshold 70% VDD, 5.0 V device RST-HYST 150 150 mV VDD under-voltage reset threshold down - Low Power VDD ON Mode (note: device change to Normal Request Mode). RST-LP 4.0 4.5 4.85 V Reset VOL @ 1.5 mA, VSUP 2.5 to 40 V VOL - 300 500 mV Current limitation, Reset activated, VRESET = 0.9 x VDD IRESET LOW 2.5 7.0 10 mA Pull-up resistor (to VDD pin) IPULL-UP 8.0 11 15 kΩ VSUP to guaranteed reset low level(14) VSUP-RSTL 2.5 - - V Notes 8. The regulator is stable without external capacitor. Usage of external capacitor recommended for AC performance. 9. No external capacitor required for stability. External capacitor might be used to improve AC transient response. 10. Current limitation will report into a flag. 11. Generate a reset or an INT. SPI programmable 12. Generate a reset 13. In Run Mode 14. Reset must be maintained low reflect the approximate parameter means at TA = 25°C under nominal conditions, unless otherwise noted.

Analog Integrated Circuit Device Data Freescale Semiconductor 17 STATIC ELECTRICAL CHARACTERISTICS UNDERVOLTAGE RESET AND RESET FUNCTION, RST PIN (CONTINUED) Reset input threshold Low threshold High threshold RST-VTH 1.5 2.5 1.9 3.0 2.2 3.5 V Reset input hysteresis HYST 0.5 1.0 1.5 V I/O PINS WHEN FUNCTION SELECTED IS OUTPUT I/O-0 high side switch drop @ I = -12 mA, VSUP = 10.5 V I/O-0 HSDRP - 0.5 1.4 V I/O-2 and I/O-3 high side switch drop @ I = -20 mA, VSUP = 10.5 V I/O-2-3 HSDRP - 0.5 1.4 V I/O-1, high side switch drop @ I = -400 μA, VSUP = 10.5 V I/O-1 HSDRP - 0.4 1.4 V I/O-0, I/O-1 low side switch drop @ I = 400 μA, VSUP = 10.5 V I/O-0-1 LSDRP - 0.4 1.4 V Leakage current I/O-LEAK - 0.1 3.0 μA I/O PINS WHEN FUNCTION SELECTED IS INPUT Negative threshold I/O-NTH 1.4 2.0 2.9 V Positive threshold I/O-PTH 2.1 3.0 3.8 V Hysteresis I/O-HYST 0.2 1.0 1.4 V Input current I/O-IN -5.0 1.0 5.0 μA I/O-0 and I/O-1 input resistor. /O_0 (or I/O-1) selected in MUX register, 2.0 V < Vi/o_x <16 V (guaranteed by design). RI/O-X - 100 - kΩ VSENSE INPUT VSENSE under-voltage threshold (Not active in Low Power Modes) - Low Threshold - High threshold - Hysteresis VSENSE_TH 8.1 0.1 8.6 0.25 9.0 9.1 0.5 V Input resistor to GND. In all modes except in Low Power modes. (guaranteed by design). VSENSE_R - 125 - kΩ ANALOG MUX OUTPUT Output Voltage Range, with external resistor to GND >2.0 kΩ VOUT_MAX 0.0 - VDD - 0.5 V Internal pull-down resistor for regulator output current sense RMI 0.8 1.9 2.8 kΩ External capacitor at MUX OUTPUT(15) (guaranteed by design) CMUX - - 1.0 nF Chip temperature sensor coeff (guaranteed by design and device characterization) TEMP-COEFF 20 21 22 mv/°C Chip temperature: MUX-OUT voltage at TA = 25°C, guaranteed by design and characterization. VTEMP 1.5 1.65 1.8 V Chip temperature: MUX-OUT voltage at TA = 125°C VTEMP 3.6 3.75 3.9 V Gain for VSENSE, with external 1.0 k 1% resistor VSENSE GAIN 5.13 5.48 5.67 Offset for VSENSE, with external 1.0 k 1% resistor VSENSE OFFSET -20 - 20 mV Divider ratio for VSUP1 VSUP1 RATIO 5.335 5.5 5.665 Divider ratio for I/O-0 and I/O-1 actual voltage - with attenuation selected (MUX-OUT register bit 3 set to 1); VSUP= 16V VSUP= 27V - with gain selected (MUX-OUT register bit 3 set to 0) VI/O RATIO 3.8 3.75 4.0 3.95 2.0 4.2 4.15 Notes 15. When C is higher than CMUX, a serial resistor must be inserted reflect the approximate parameter means at TA = 25°C under nominal conditions, unless otherwise noted.

Analog Integrated Circuit Device Data

18 Freescale Semiconductor

STATIC ELECTRICAL CHARACTERISTICS ANALOG MUX OUTPUT (CONTINUED) Internal reference voltage VREF 2.425 2.5 2.575 V Current ratio between VDD output & IOUT at MUX-OUT (IOUT at MUX-OUT = IDD out / IDD_RATIO) - At IOUT = 50 mA - I_OUT from 25 mA to 150 mA IDD_RATIO 62.5 115 117 SAFE OUTPUT SAFE low level, at I = 500 μA VOL 0.0 0.2 1.0 V Safe leakage current (VDD low, or device unpowered). VSAFE 0 to 27 V. VSAFE-IN - 0.0 1.0 μA INTERRUPT Output low voltage, IOUT = 1.5 mA VOL - 0.2 1.0 V Pull-up resistor RPU 6.5 10 14 kΩ Output high level in Low Power VDD ON Mode (guaranteed by design) VOH-LPVddon 3.9 4.3 V Leakage current INT voltage = 10 V (to allow high-voltage on MCU INT pin) VMAX - 35 100 μA Sink current, VINT > 5.0 V, INT low state I SINK 2.5 6.0 10 mA MISO, MOSI, SCLK, CS PINS Output low-voltage, IOUT = 1.5 mA (MISO) VOL - - 1.0 V Output high-voltage, IOUT = -0.25 mA (MISO) VOH VDD -0.9 - V Input low voltage (MOSI, SCLK,CS) VIL - - 0.3 x VDD V Input high-voltage (MOSI, SCLK,CS) VIH 0.7 x VDD - - V Tri-state leakage current (MISO) IHZ -2.0 - 2.0 μA Pull-up current (CS) IPU 200 370 500 μA CAN LOGIC INPUT PINS (TXD) High Level Input Voltage VIH 0.7 x VDD - VDD + 0.3 V Low Level Input Voltage VIL -0.3 - 0.3 x VDD V Pull-up Current, TXD, VIN = 0 V IPDWN -850 -650 -200 µA CAN DATA OUTPUT PINS (RXD) Low Level Output Voltage IRXD = 5.0 mA VOUTLOW 0.0 - 0.3 x VDD V High Level Output Voltage IRXD = -3.0 mA VOUTHIGH 0.7 x VDD - VDD V High Level Output Current VRXD = VDD - 0.4 V IOUTHIGH 2.5 5.0 9.0 mA Low Level Input Current VRXD = 0.4 V IOUTLOW 2.5 5.0 9.0 mA reflect the approximate parameter means at TA = 25°C under nominal conditions, unless otherwise noted.

Analog Integrated Circuit Device Data Freescale Semiconductor 19 STATIC ELECTRICAL CHARACTERISTICS CAN OUTPUT PINS (CANH, CANL) Bus pins common mode voltage for full functionality VCOM -12 - 12 V Differential input voltage threshold VCANH-VCANL 500 - 900 mV Differential input hysteresis VDIFF-HYST 50 - - mV Input resistance RIN 5.0 - 50 kΩ Differential input resistance RIN-DIFF 10 - 100 kΩ Input resistance matching RIN-MATCH -3.0 0.0 3.0 % CANH output voltage (45 Ω < RBUS < 65 Ω) TX dominant state TX recessive state VCANH 2.75 2.0 3.5 2.5 4.5 3.0 V CANL output voltage (45 Ω < RBUS < 65 Ω) TX dominant state TX recessive state VCANL 0.5 2.0 1.5 2.5 2.25 3.0 V Differential output voltage (45Ω < RBUS < 65 Ω) TX dominant state TX recessive state VOH-VOL 1.5 -0.5 2.0 0.0 3.0 0.05 V CAN H output current capability - Dominant state ICANH - - -30 mA CAN L output current capability - Dominant state ICANL 30 - - mA CANL over-current detection - Error reported in register ICANL-OC 75 120 195 mA CANH over-current detection - Error reported in register ICANH-OC -195 -120 -75 mA CANH, CANL input resistance to gnd, device supplied, CAN in Sleep Mode, V_CANH, V_CANL from 0 to 5.0 V RINSLEEP 5.0 - 50 kΩ CANL, CANH output voltage in Low Power VDD OFF and Low Power VDD ON Modes VCANLP -0.1 0.0 0.1 V CANH, CANL input current, VCANH, VCANL = 0 to 5V, device not supplied (Vsup, Vdd, 5V-CAN: open, direct connection to gnd, connect to gnd via 47k resistor). ICAN-UN_SUP1 - 3.0 10 µA CANH, CANL input current, VCANH, VCANL = -2 to 7V, device not supplied (Vsup, Vdd, 5V-CAN: open, direct connection to gnd, connect to gnd via 47k resistor). ICAN-UN_SUP2 - - 250 µA Differential voltage for recessive bit detection in LP mode(16) VDIFF-R-LP - - 0.4 V Differential voltage for dominant bit detection in LP mode(16) VDIFF-D-LP 1.15 - - V CANH AND CANL DIAGNOSTIC INFORMATION CANL to GND detection threshold VLG 1.6 1.75 2.0 V CANH to GND detection threshold VHG 1.6 1.75 2.0 V CANL to VBAT detection threshold, VSUP1 and VSUP2 > 8.0 V VLVB - VSUP -2.0 - V CANH to VBAT detection threshold, VSUP1 and VSUP2 > 8.0 V VHVB - VSUP -2.0 - V CANL to VDD detection threshold VL5 4.0 VDD -0.43 - V CANH to VDD detection threshold VH5 4.0 VDD -0.43 - V Notes 16. Guaranteed by design and device characterization. reflect the approximate parameter means at TA = 25°C under nominal conditions, unless otherwise noted.

Analog Integrated Circuit Device Data

20 Freescale Semiconductor

STATIC ELECTRICAL CHARACTERISTICS SPLIT Output voltage Loaded condition ISPLIT = ± 500 µA Unloaded condition Rmeasure > 1.0 MΩ VSPLIT 0.3 x VDD 0.45 x VDD 0.5 x VDD 0.5 x VDD 0.7 x VDD 0.55 x VDD V Leakage current -12 V < VSPLIT < +12 V -22 to -12 V < VSPLIT < +12 to +35 V ILSPLIT 0.0 5.0 200 µA LIN TERM1, LIN TERM2 LIN-T1, LIN-T2, high side switch drop @ I = -20 mA, VSUP > 10.5 V LT_HSDRP - 1.0 1.4 V LIN1 AND LIN 2 MC33905D PIN - LIN1 MC33905S PIN (Parameters guaranteed for VSUP1, VSUP2 7 V ≤ VSUP ≤ 18 V) Operating Voltage Range VBAT 8.0 - 18 V Supply Voltage Range VSUP 7.0 - 18 V Current Limitation for Driver Dominant State Driver ON, VBUS = 18 V IBUS_LIM 40 90 200 mA Input Leakage Current at the receiver Driver off; VBUS = 0V; VBAT = 12 V IBUS_PAS_DOM -1.0 - - mA Leakage Output Current to GND Driver Off; 8.0 V < VBAT < 18 V; 8.0 V < VBUS < 18 V; VBUS ≥ VBAT IBUS_PAS_REC - - 20 µA Control unit disconnected from ground (Loss of local ground must not affect communication in the residual network) GNDDEVICE = VSUP; VBAT = 12 V; 0 < VBUS < 18 V (guaranteed by design) IBUS_NO_GND -1.0 - 1.0 mA VBAT Disconnected; VSUP_DEVICE = GND; 0 < VBUS < 18 V (Node has to sustain the current that can flow under this condition. Bus must remain operational under this condition) IBUSNO_BAT - - 100 µA Receiver Dominant State VBUSDOM - - 0.4 VSUP Receiver Recessive State VBUSREC 0.6 - - VSUP Receiver Threshold Center (VTH_DOM + VTH_REC)/2 VBUS_CNT 0.475 0.5 0.525 VSUP Receiver Threshold Hysteresis (VTH_REC - VTH_DOM) VHYS - - 0.175 VSUP LIN Wake-up threshold from Low Power VDD ON or Low Power VDD OFF Mode VBUSWU - 5.3 5.8 V LIN Pull-up Resistor to VSUP RSLAVE 20 30 60 kΩ Over-temperature Shutdown (guaranteed by design) TLINSD 140 160 180 °C Over-temperature Shutdown Hysteresis (guaranteed by design) TLINSD_HYS - 10 - °C reflect the approximate parameter means at TA = 25°C under nominal conditions, unless otherwise noted.

Analog Integrated Circuit Device Data Freescale Semiconductor 21 DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 5. Dynamic Electrical Characteristics values noted reflect the approximate parameter means at TA = 25°C under nominal conditions, unless otherwise noted.

Analog Integrated Circuit Device Data

22 Freescale Semiconductor

DYNAMIC ELECTRICAL CHARACTERISTICS STATE DIGRAM TIMINGS Delay for SPI Timer A, Timer B or Timer C write command after entering Normal Mode (No command should occur within Td_nm. TD_NM delay definition: from CS rising edge of “Go to Normal Mode” command to CS falling edge of “Timer write” command) tD_NM 60 - - μs Tolerance for: W/D period in all modes, FWU delay, Cyclic sense period and active time, Cyclic Interrupt period, LP mode over current (unless otherwise noted)(20) tTIMING-ACC -10 - 10 % CAN DYNAMIC CHARACTERISTICS TXD Dominant State Timeout tDOUT 300 600 1000 µs Bus dominant clamping detection tDOM 300 600 1000 µs Propagation loop delay TXD to RXD, recessive to dominant (Fast slew rate) tLRD 60 120 210 ns Propagation delay TXD to CAN, recessive to dominant tTRD - 70 110 ns Propagation delay CAN to RXD, recessive to dominant tRRD - 45 140 ns Propagation loop delay TXD to RXD, dominant to recessive (Fast slew rate) tLDR 100 120 200 ns Propagation delay TXD to CAN, dominant to recessive tTDR - 75 150 ns Propagation delay CAN to RXD, dominant to recessive tRDR - 50 140 ns Loop time TXD to RXD, Medium Slew rate (Selected by SPI) Rec to Dom Dom to Rec tLOOP-MSL 200 200 ns Loop time TXD to RXD, Slow Slew rate (Selected by SPI) Rec to Dom Dom to Rec tLOOP-SSL 300 300 ns CAN wake up filter time, single dominant pulse detection(17) (See Figure 29) tCAN-WU1 0.5 2.0 5.0 μs CAN wake up filter time, 3 dominant pulses detection(18) tCAN-WU3-F 300 - - ns CAN wake up filter time, 3 dominant pulses detection time out(19) (See Figure 30) tCAN-WU3-TO - - 120 μs Notes 17. No wake up for single pulse shorter than t CAN-WU1 min. Wake up for single pulse longer than tCAN-WU1 max. 18. Each pulse should be greater than t CAN-WU3-F min. Guaranteed by design, and device characterization. 19. The 3 pulses should occur within t CAN-WU3-TO. Guaranteed by design, and device characterization. 20. Guaranteed by design. values noted reflect the approximate parameter means at TA = 25°C under nominal conditions, unless otherwise noted.

Analog Integrated Circuit Device Data Freescale Semiconductor 23 DYNAMIC ELECTRICAL CHARACTERISTICS LIN 1 AND LIN 2 PHYSICAL LAYER: DRIVER CHARACTERISTICS FOR NORMAL SLEW RATE - 20.0 KBIT/SEC ACCORDING TO LIN PHYSICAL LAYER SPECIFICATION Duty Cycle 1: THREC(max) = 0.744 * VSUP THDOM(max) = 0.581 * VSUP D1 = tBUS_REC(MIN)/(2 x tBIT), tBIT = 50 µs, 7.0 V ≤ VSUP ≤ 18 V 0.396 - - Duty Cycle 2: THREC(MIN) = 0.422 * VSUP THDOM(MIN) = 0.284 * VSUP D2 = tBUS_REC(MAX)/(2 x tBIT), tBIT = 50 µs, 7.6 V ≤ VSUP ≤ 18 V - - 0.581 LIN PHYSICAL LAYER: DRIVER CHARACTERISTICS FOR SLOW SLEW RATE - 10.4 KBIT/SEC ACCORDING TO LIN PHYSICAL LAYER SPECIFICATION Duty Cycle 3: THREC(MAX) = 0.778 * VSUP THDOM(MAX) = 0.616 * VSUP D3 = tBUS_REC(MIN)/(2 x tBIT), tBIT = 96 µs, 7.0 V ≤ VSUP ≤ 18 V 0.417 - - Duty Cycle 4: THREC(MIN) = 0.389 * VSUP THDOM(MIN) = 0.251 * VSUP D4 = tBUS_REC(MAX)/(2 x tBIT), tBIT = 96 µs, 7.6 V ≤ VSUP ≤ 18 V - - 0.590 LIN PHYSICAL LAYER: DRIVER CHARACTERISTICS FOR FAST SLEW RATE LIN Fast Slew Rate (Programming Mode) SRFAST - 20 - V / μs LIN PHYSICAL LAYER: CHARACTERISTICS AND WAKE-UP TIMINGS Propagation Delay and Symmetry (See Figure 13, page 25 and Figure 14, page 26) Propagation Delay of Receiver, tREC_PD=MAX (tREC_PDR, tREC_PDF) Symmetry of Receiver Propagation Delay, tREC_PDF - tREC_PDR t REC_PD t REC_SYM - 2.0 4.2 6.0 2.0 μs Bus Wake-Up Deglitcher (Low Power VDD OFF and Low Power VDD ON Modes) (See Figure 15, page 25 for Low Power VDD OFF Mode and Figure 16, page 26 for Low Power Mode) t PROPWL 42 70 95 μs Bus Wake-up Event Reported From Low Power VDD OFF Mode From Low Power VDD ON Mode t WAKE_LPVDD OFF t WAKE_LPVDD ON 1.0 1500 μs TXD Permanent Dominant State Delay (guaranteed by design) t TXDDOM 0.65 1.0 1.35 s values noted reflect the approximate parameter means at TA = 25°C under nominal conditions, unless otherwise noted.

Analog Integrated Circuit Device Data

24 Freescale Semiconductor

Figure 9. SPI Timings Figure 10. CAN Signal Propagation Loop Delay TXD to RXD Figure 11. CAN Signal Propagation Delays TXD to CAN and CAN to RXD

Analog Integrated Circuit Device Data

26 Freescale Semiconductor

Figure 14. LIN Timing Measurements for Slow Slew Rate Figure 15. LIN Wake-up Low Power VDD OFF Mode Timing

Analog Integrated Circuit Device Data Freescale Semiconductor 27 Figure 16. LIN Wake-up Low Power VDD ON Mode Timing

Analog Integrated Circuit Device Data

28 Freescale Semiconductor

The MC33904_5 is the second generation of System Basis Chip, combining: - Advanced power management unit for the MCU, the integrated CAN interface and for additional ICs such as sensors, CAN transceiver. - Built in enhanced high speed CAN interface (ISO11898- 2 and -5), with local and bus failure diagnostic, protection and fail safe operation mode. - Built in LIN interface, compliant to LIN 2.1 and J2602-2 specification, with local and bus failure diagnostic and protection. - Innovative and hardware configurable fail safe state machine solution. - Multiple low power modes, with low current consumption. - Family concept; with and without LIN interface devices with pin compatibility. FUNCTIONAL PIN DESCRIPTION POWER SUPPLY (VSUP1 AND VSUP2) VSUP1 pin is the input pin for the device internal supply and the VDD regulator. VSUP2 is the input pin for the 5V- CAN regulator, LINs interfaces and I/O functions. The VSUP block includes over and under-voltage detections which can generate interrupt. The device includes a loss of battery detector connected to VSUP1. Loss of battery is reported through a bit (called BATFAIL). This generates a POR (Power On Reset). VDD VOLTAGE REGULATOR (VDD) The regulator has two main modes of operation (Normal Mode and Low Power Mode). It can operate with or without an external PNP transistor. In Normal Mode, without external PNP, the max DC capability is 150mA. Current limitation, temperature pre warning flag and over temperature shutdown features are included. When VDD is turned ON, rise time from 0 to 5.0V is controlled. Output voltage is 5.0V. A 3.3V option is available via dedicated part number. If current higher than 150mA is required, an external PNP transistor must be connected to VEM (PNP emitter) and VB (PNP base) terminals, in order to increase total current capability and share the power dissipation between internal VDD transistor and the external transistor. See External Transistor Q1 (VE and VB). The PNP can be used even if current is less than 150mA, depending upon ambient temperature, maximum supply and thermal resistance. Typically, above 100-200mA, an external ballast transistor is recommended. VDD REGULATOR IN LOW POWER MODE When the device is set in Low Power VDD ON Mode, the VDD regulator is able to supply the MCU with a DC current below typ 1.5mA (LP-ITH). Transient current can also be supplied up to tenth of mA. Current in excess of 1.5mA is detected, and this event is managed by the device logic (wake-up detection, timer start for over current duration monitoring or watchdog refresh). EXTERNAL TRANSISTOR Q1 (VE AND VB) The device has a dedicated circuit to allow usage of an external P type transistor, with the objective to share the power dissipation between the internal transistor of the VDD regulator and the external transistor. The bipolar PNP recommended transistor are MJD42C or BCP52-16. When the external PNP is connected, the current is shared between the internal path transistor and the external PNP, with the following typical ratio: 1/3 in the internal transistor and 2/3 in the external PNP. The PNP activation and control is done by SPI. The device is able to operate without an external transistor. In this case the VEM and VB pins must remain open. VOLTAGE REGULATOR FOR CAN INTERFACE SUPPLY (5V-CAN) This regulator is supplied from the VSUP2 pin. A capacitor is required at 5V-CAN terminal. Analog MUX and part of the LIN interfaces are supplied from 5V-CAN. 5V-CAN regulator is OFF by default and must be turn ON by SPI. In Debug mode 5V-CAN is ON be default. V AUXILIARY OUTPUT, 5V AND 3.3V SELECTABLE (VB-AUX, VC-AUX, AND VCAUX) - Q2 The VAUX block is used to provide an auxiliary voltage output, 5 or 3.3V, selectable by the SPI. It uses an external PNP pass transistor for flexibility and power dissipation constraints. The external recommended bipolar transistors are MJD42C or BCP52-16. An over-current and under voltage detectors are provided. VAUX is controlled via the SPI, and can be turned ON or OFF. VAUX low threshold detection and over-current information will disable Vaux, and flags are reported in the SPI and can generate INT. Vaux is OFF by default and must be turned ON by SPI.

Analog Integrated Circuit Device Data Freescale Semiconductor 29 FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION UNDER-VOLTAGE RESET AND RESET FUNCTION (RST) The RESET pin is an open drain structure with an internal pull-up current source. The low side driver has limited current capability when asserted low, in order to tolerate a short to 5.0V.The Reset terminal voltage is monitored in order to detect failure (e.g. RESET pin shorted to 5.0V or GND). The RESET pin reports to the MCU under -voltage condition at the VDD pin, as well as failure in watchdog refresh operation. VDD under-voltage reset operate also in Low Power VDD ON Mode. Two VDD under-voltage threshold are included. The upper on (typ 4.65V, RST-TH1-5) can lead to a Reset or an Interrupt. This is selected by the SPI. When “RST-TH2-5“is selected, in Normal Mode, an INT is asserted when VDD falls below “RST- TH1-5“. This will allow the MCU to operate in a degraded mode, for example, with 4.0V VDD. I/O PINS (I/O-1: I/O-3) I/O s are configurable input output pins. They can be used for small load or to drive external transistors. When used as output drivers, the I/Os are high side or low side type. They can also be set to high-impedance. I/Os are controlled by SPIn and at power on, the I/Os are set as inputs. They include over load protection by temperature or excess of drop voltage. In Low Power Mode, state of the I/O can be turned on or off, with extremely low extra consumption (except load). Protection is disabled in low power mode. When cyclic sense is used, I/O-0 is the high side/low side switch, I/O-1, 2 and 3 and the wake inputs. I/O-2 and I/O-3 terminals share also the LIN Master terminal function. VSENSE INPUT (VSENSE) This pin can be connected to the battery line (before the reverse battery protection diode), via a serial resistor and a capacitor to gnd. It incorporates a threshold detector to sense the battery voltage and provide a battery early warning. It also includes a resistor divider to measure the VSENSE voltage via the MUX OUT pin. MUX OUTPUT (MUXOUT) The MUX-OUT terminal (Figures 17) delivers an analog voltage to the MCU A/D input. The voltage to be delivered to MUX-OUT is selected via the SPI, from one of the following functions: Vsup1, Vsense, I/O-0, I/O-1, Internal 2.5V reference, die temperature sensor, VDD current copy. Voltage divider or amplifier are inserted in the chain, as shown in Figures 17. For the VDD current copy, a resistor must be added to the MUX OUT pin, to convert current into voltage. Device includes an internal 2k resistor selectable by SPI. Voltage range at MUX_OUT is from gnd to VDD. It is automatically limited to VDD (max 3.3V for 3.3V part numbers). The MUX-OUT buffer is supplied from 5V-CAN regulator, so the 5V-CAN regulator must be ON in order to have: 1) MUX-OUT functionality and 2) SPI selection of the analog function. If 5V-CAN is OFF, MUX-OUT voltage is near gnd and the SPI command that selects one of the analog input is ignored. Delay must be respected between SPI commands for 5V- CAN turn ON and SPI to select MUX-OUT function. The delay depends mainly upon the 5V-CAN capacitor and load on 5V-CAN. The delay can be estimated using the following formula: delay = C(5V-CAN) x U (5V) / I_lim 5V-CAN. C = cap at 5V-CAN regulator, U = 5V, I_lim 5V-CAN = min current limit of 5V-CAN regulator (parameter 5V-C ILIM).

30 Freescale Semiconductor

Figure 17. Analog Multiplexer Block Diagram within the 8-10V range, and activate the debug mode. hardware and software routines (i.e SPI commands). higher priority than providing 8-10V at debug pin. operation via a resistor at the DBG pin or via SPI command. selection via Debug resistor. not be configured via the resistor connected at DBG pin. SBC, once a failure has been detected. as well as pulse duration are selected by SPI. S_g3.3 and S_g5 for 5.0V or 3.3V MCU. S_in1 for Low Power Mode resistor bridge disconnection. S_ir to switch on/off of the internal RMI resistor.

Analog Integrated Circuit Device Data Freescale Semiconductor 31 FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION INT has internal pull up structure to VDD. In Low Power VDD ON Mode, a diode is inserted in series with the pull up, so the high level is slightly lower than in other modes. CANH, CANL, SPLIT, RXD, TXD These are the terminals of the high speed CAN physical interface, between the CAN bus and the micro controller. A detail description is provided in the document. LIN, TXDL, RXDL AND LINTERM These are the terminals of the Local Interconnect Network physical interface. Device contains zero, one or two LIN interfaces. MC33904 has no LIN interface. MC33905S (S as Single) and MC33905D (D as Dual) contain respectively 1 and 2 LIN interfaces. LIN 1 and LIN 2 terminals are the connection to the LIN sub buses. LIN interfaces are connected to the MCU via the TxDL1 (TxDL2) and RxDL1 (RxDL2) terminals. The device also include one or two high side switches to Vsup2 terminal which can be used as a LIN master termination switch. Pins LINT-1 and LINT-2 are the same as I/O-2 and I/O-3. A detail description is provided in the document

Analog Integrated Circuit Device Data

32 Freescale Semiconductor

FUNCTIONAL DEVICE OPERATION MODE AND STATE DESCRIPTION FUNCTIONAL DEVICE OPERATION MODE AND STATE DESCRIPTION The device has several operation modes. The transitions and conditions to enter or leave each modes are illustrated in the state diagram. INIT RESET This mode is automatically entered after device “power on”. In this mode, the RSTb pin is asserted low, for a duration of typ 1ms. Control bits and flags are “set” to their default reset condition. The BATFAIL is set to indicated that the device is coming from an unpowered condition, and that all previous device configuration are lost and “reset” the default value. The duration of the INIT reset is typ 1ms. INIT reset mode is also entered from INIT mode in case the expected SPI command does not occur in due time (ref. INIT mode), and if device is not in debug mode. INIT This mode is automatically entered from “INIT reset” mode. In this mode, the device must be configured via SPI within a time of 256ms max. Four registers called INIT Wdog, INIT REG, INIT LIN I/O and INIT MISC must be and can only be configured during INIT mode. Other registers can be written in this mode, however they can be also written in other modes. Once the INIT registers configuration is done, a SPI Watchdog Refresh command must be send in order to set the device into Normal mode. If the SPI W/D refresh does not occur within the 256ms period, the device will return into INIT reset mode for typ 1ms, and then re enter into INIT mode. Register read operation is allowed in INIT mode to collect device status or to read back the INIT register configuration When INIT mode is left by a SPI W/D refresh command, it is only possible to re enter the INIT mode using a secured SPI command. RESET In this mode, the RSTb pin is asserted low. Reset mode is entered from Normal mode, Normal Request mode, LP VDD on mode and from Flash mode, when the W/D is not triggered, or if a VDD low condition is detected. The duration of reset is typ 1ms by default. The user can defined a longer Reset pulse activation only for the case the reset mode is entered following a VDD low condition. Reset pulse is always 1ms, in case Reset mode in entered due to wrong W/D refresh command. Reset mode can be entered via secured SPI command. NORMAL REQUEST This mode is automatically entered after RESET mode, or after a wake up from Low Power VDD ON Mode. A W/D refresh SPI command is necessary to transition to NORMAL mode. The duration of the Normal request mode is 256ms when Normal Request mode is entered after RESET mode. Different duration can be selected by SPI for the case when normal request is entered from LP VDD ON mode. If the W/D refresh SPI command does not occur within the 256ms (or the shorter user defined time out), then the device will enter into RESET mode, for a duration of typ 1ms. note: in init reset, init, reset and normal request modes as well as in low power modes, the VDD external PNP is disabled. NORMAL In this mode, all device functions are available. This mode is entered by a SPI W/D refresh command from Normal Request mode, or from INIT mode. During Normal mode, the device Watchdog function is operating, and a periodic W/D refresh must occurs. In case of incorrect or missing W/D refresh command device will enter into Reset mode. From Normal mode, the device can be set by SPI command into Low Power modes (Low Power VDD ON or Low Power VDD OFF Modes). Dedicated secured SPI commands must be used to enter from Normal mode in RESET mode, INIT mode or FLASH mode. FLASH In this mode, the software watchdog period is extended up to typ 32 seconds. This allow programming of the MCU flash memory while minimizing the software over head to refresh the W/D. The flash mode is entered by Secured SPI command and is left by SPI command. Device will enter into RESET mode. In case of incorrect or missing W/D refresh command device will enter into Reset mode. An INT can be generated at 50% of the W/D period. CAN interface operates in Flash mode to allow flash via CAN bus, inside the vehicle. DEBUG Debug is a special operation mode of the device which allows system easy software and hardware debugging. The debug operation is detected after power up if the DBG pin is set in the 8.0-10V range. When debug is detected, all the software watchdog operations are disabled: 256ms of INIT mode, W/D refresh of Normal mode and Flash mode, Normal Request time out (256ms or user defined value) are not operating and will not lead to transition into INIT reset or Reset mode. When device is in Debug, SPI command can be send without any time constraints with respect to W/D operation, MCU program can be “halted” or “paused” to verify proper operation. Debug can be left by removing 8-10V from debug pin, or by SPI command (ref to MODE register). 5V-CAN regulator is ON by default in debug mode.

Analog Integrated Circuit Device Data Freescale Semiconductor 33 FUNCTIONAL DEVICE OPERATION LOW POWER MODES LOW POWER MODES The device has two main Low Power Modes: Low Power Mode with VDD off, and Low Power Mode with VDD on. note: Prior to enter in Low Power mode, I/O and CAN wake up flags must be cleared (ref to Mode register). LOW POWER - VDD OFF In this mode, VDD is turned off and the MCU connected to VDD is unsupplied. This mode is entered by the SPI. It can also be entered by automatic transition due to fail safe management. 5V-CAN and Vaux regulators are also turned OFF. When the device is in Low Power VDD OFF Mode, it monitors external events to wake up and leave the LP mode. The wake up events can occurs from:

• C A N
• LIN interface, depending upon device part number
• Expiration of an internal timer
• I/O-0, and I/O-inputs, a nd depending upon device part number and configuration, I/O-2 and/or 3 input
• Cyclic sense of I/O-1 input, associated by I/O-0 activation, and depending upon device part number and configuration, cyclic sense of I/O-2 and 3 input, associated by I/O-0 activation When a wake up event is detected, the device enters into reset mode and then into Normal Request mode. The wake up source are reported into the device SPI registers. In summary, a wake up event from LP Vdd off, lead to Vdd regulator turn ON, and MCU operation restart. LOW POWER - VDD ON In this mode, the voltage at the VDD terminal remains at 5.0V (or 3.3V, depending upon device part number). The objective is to maintain the MCU powered, with reduced consumption. In such mode, the DC output current is expected to be limited to few 100uA or few mA, as the ECU is in reduced power operation mode. During this mode, the 5V-CAN and VAUX regulators are OFF. The same wake-up events as in LP Vdd off mode (CAN, LIN, I/O, timer, cyclic sense) are available in LP Vdd on mode. In addition, two additional wake up conditions are available.
• Dedicated SPI command. When device is in LP Vdd ON mode, the wake up by SPI command uses a write to “Normal Request Mode”, 0x5C10.
• Output current from Vdd exceeding typ 1.5mA threshold. In Low Power VDD ON Mode, the device is able to source several tenth of mA DC. The current source capability can be time limited, by a selectable internal timer. Timer duration is up to 32ms, and is triggered when the output current exceed the output current threshold typ 1.5mA. This allow for instance a periodic activation of the MCU, while the device remains in LP VDD on mode. If the duration exceed the selected time (ex 32ms), the device will detect a wake up. Wake up event are reported to the MCU via a low level pulse at INT pulse. The MCU will detect the INT pulse and resume operation. Watchdog function in LP VDD ON mode It is possible to enable the W/D function in Low Power VDD ON Mode. In this case, the principle is time out. Refresh of the W/D is done either by:
• a dedicated SPI command (different from any other SPI command or simple CSb activation which would wake up - ref to above paragraph)
• or by a temporary (less than 32ms max) Vdd over current wake-up (Idd > 1.5mA typ). As long as the W/D refresh occurs, the device remains in LP Vdd on mode. MODE transition mode transition are either done automatically (i.e after time out expired or voltage conditions), or via SPI command, or by external event such as wake up. Some mode change are performed via “secured” SPI commands.

34 Freescale Semiconductor

Figure 18. State Diagram (4) Vdd external PNP is disable in all mode except Normal and Flash modes.

Analog Integrated Circuit Device Data Freescale Semiconductor 35 FUNCTIONAL DEVICE OPERATION MODE CHANGE MODE CHANGE “SECURED SPI” DESCRIPTION: A request is done by a SPI command, the device provide on MISO an unpredictable “random code”. Software must perform a logical change on the code and return it to the device with the new SPI command to perform the desired action. The “random code” is different at every exercise of the secured procedure and can be read back at any time. The secured SPI uses the Special MODE register for the following transitions: - from Normal mode to INT mode - from Normal mode to FLASH mode - from Normal mode to RESET mode (reset request). “Random code” is also used when the “advance watchdog” is selected. CHANGING OF DEVICE CRITICAL PARAMETERS Some critical parameters are configured one time at device power on only, while the batfail flag is set in the INIT Mode. If a change is required while device is no longer in INIT mode, device must be set back in INIT mode using the “SPI secure” procedure. WATCHDOG OPERATION IN NORMAL REQUEST MODE In Normal Request Mode, the device expects to receive a watchdog configuration before the end of the normal request time out period. This period is reset to a long (256ms) after power on and when BATFAIL is set. The device can be configured to a different (shorter) time out period which can be used after wake-up from LP Vdd on mode. After a software watchdog reset, the value is restored to 256ms, in order to allow for a complete software initialization, similar to a device power up. In Normal Request Mode the watchdog operation is ”timeout” only and can be triggered/served any time within the period. WATCHDOG TYPE SELECTION Two different watchdog modes are implemented: Window or Advance. The selection of “Window” or “Advance” is done in INIT Mode, after device power up when the Batfail flag is set. Configuration is done via the SPI. Then the watchdog mode selection content is locked and can be changed only via a secured SPI procedure. Window Watchdog Operation The window watchdog is available in Normal Mode only. The watchdog period selection can be kept (SPI is selectable in INIT Mode), while the device enters into Low Power VDD ON Mode. The watchdog period is reset to the default long period after BATFAIL. The period and the refresh of watchdog is done by the SPI. A refresh must be done in the open window of the period, which starts at 50% of the selected period and ends at the end of the period. If the watchdog is triggered before 50%, or not triggered before end of period, a reset has occurred. The device enters into Reset Mode. Watchdog in Debug Mode When the device is in Debug Mode (entered via the DBG pin), the watchdog continues to operate but does not affect the device operation by asserting a reset. For the user, operation appears without the watchdog. When debug is left by software (SPI mode reg) the watchdog period starts at the end of the SPI command. When debug mode is left by hardware (DBG pin below 8- 10V), the device enters into Reset Mode. Watchdog in Flash Mode During flash mode operation, the watchdog can be set to a long time out period. Watchdog is timeout only and an INT pulse can be generated at 50% of the time window. Advance Watchdog Operation When the Advance watchdog is selected (at INIT Mode), the refresh of the watchdog must be done using a random number and with 1, 2, or 4 SPI commands. The number for the SPI command is selected in INIT mode. The software must read a random byte from the device, and then must return the random byte inverted to clear the watchdog. The random byte write can be performed in 1, 2, or 4 different SPI commands. If 1 command is selected, all 8 bits are written at once. If 2 commands are selected, first write command must include 4 of the 8 bits of the inverted random byte. The second command must include the next 4 bits. This complete the watchdog refresh. If 4 commands are selected, the first write command must include 2 of the 8 bits of the inverted random byte. The second command must include the next 2 bits, the 3rd command the next 2, and the last command, the last 2. This complete the watchdog refresh. When multiple writes are used, the most significant bits are send first. The latest SPI command needs to be done inside the open window time frame, if window watchdog is selected.

Analog Integrated Circuit Device Data

36 Freescale Semiconductor

FUNCTIONAL DEVICE OPERATION WATCHDOG OPERATION DETAIL SPI OPERATION AND SPI COMMANDS FOR ALL WATCHDOG TYPES. In INIT mode, the W/D type (window, time out, advance and number of SPI commands) is selected using register Init W/D, bits 1, 2 and 3. The W/D period is selected via TIM_A register. The W/D period selection can also be done in Normal mode or in Normal Request mode. Transition from INIT mode to Normal Mode or from Normal Request mode to Normal mode is done via a single W/D refresh command (SPI 0x 5A00). While in Normal mode, the W/D refresh command depends upon the W/D type selected in INIT mode. They are detailed in the paragraph below: Simple W/D: refresh commands is 0x5A00. It can be send any time within the W/D period if the time out W/D operation is selected (INIT-W/D register, bit 1 WD N/Win =0). It must be send in the open window (second half of the period) if the Window Watchdog operation was selected (INIT-W/D register, bit 1 WD N/Win =1). Advance Watchdog: The first time device enters in Normal mode (entry on Normal mode using the 0x5A00 command), RND code must be read using SPI command 0x1B00. Device returns on MISO second byte the RND code. The full 16 bits MISO is called 0x XXRD. RD is the complement of the RD byte. Advance Watchdog, refresh by 1 SPI command: The refresh command is 0x5ARD. During each refresh command device returns on MISO a new Random Code. This new random code must be inverted and send along with the next refresh command and so on. It must be done in the open window if the Window operation was selected. Advance Watchdog, refresh by 2 SPI commands: The refresh command is splitted in 2 SPI commands. The first partial refresh command is 0x5Aw1, and the second is 0x5Aw2. Byte w1 contains the first 4 inverted bits of the RD byte plus the last 4 bits equal to zero. Byte w2 contains 4 bits equal to zero plus the last 4 inverted bits of the RD byte. During this second refresh command device return on MISO a new Random Code. This new random code must be inverted and send along with the next 2 refresh commands and so on. The second command must be done in the open window if the Window operation was selected. Advance Watchdog, refresh by 4SPI commands: The refresh command is splitted in 4 SPI commands. The first partial refresh command is 0x5Aw1, the second is 0x5Aw2, the third is 0x5Aw3 and the last is 0x5Aw4. Byte w1 contains the first 2inverted bits of the RD byte plus the last 6 bits equal to zero. Byte w2 contains 2 bits equal to zero plus the next 2 inverted bits of the RD byte plus 4 bits equal to zero. Byte w3 contains 4bits equal to zero plus the next 2 inverted bits of the RD byte plus 2 bits equal to zero. Byte w4 contains 6bits equal to zero plus the next 2 inverted bits of the RD byte. During this fourth refresh command device return on MISO a new Random Code. This new random code must be inverted and send along with the next 4 refresh commands. The fourth command must be done in the open window if the Window operation was selected. PROPER RESPONSE TO INT A device detect, that upon an INT, the software handles the INT in a timely manner: Access of the INT register is done within 2 watchdog periods. Such feature must be enabled by SPI via the INIT WD register bit 7

The 5V-CAN default is ON when the device is powered-up and set in Debug Mode. It is fully controllable via the SPI command. ILLUSTRATION OF DEVICE MODE TRANSITIONS. Figure 19. Power Up Normal and Low Power Modes Table 6. Device Block Operation for Each State internal 30k pull up active.

1. With limited current capability
2. 5V-CAN is ON in Debug mode.

38 Freescale Semiconductor

ILLUSTRATION OF DEVICE MODE TRANSITIONS. Figure 20. Wake-up from Low Power Modes

the contact pull up resistor. from 3 to 512ms (selection in timer B). state of I/O-0 prior to enter in low power mode. of them is high, the device will detect a wake up. (Figure 21). Figure 21. Cyclic Sense operation - switch to gnd, wake up by open switch contact switches are closed. In LP mode, 1 contact switch is open. High level is detected on I/O-x, and device wakes up.

40 Freescale Semiconductor

the Crank bit and the 2 Vdd undervoltage reset thresholds. enable when Vsup1 is above Vsup th 1 parameters. Figure 22. Vdd start up versus Vsup1 tramp undervoltage reset selection. Bit 0 = 0 is the default state for this bit. (Vdd < 4.6V or Vdd < 3.2V typ, threshold selected by SPI). occurs for a Vsup approx 3V.

Figure 23. Vdd Behavior During Vsup1 Ramp Down

Analog Integrated Circuit Device Data

42 Freescale Semiconductor

BEHAVIOR AT POWER UP AND POWER DOWN FAIL SAFE OPERATION OVERVIEW Fail safe mode is entered when specific fail conditions occur. The “Safe state” condition is defined by the resistor connected at the DGB pin. Safe Mode is entered after additional event or conditions are met: time out for CAN communication and state at I/O-1 pin. Exit of the safe state is always possible by a wake-up event: in the safe state the device is automatically wakeable CAN and I/O (if configured as inputs). Upon wake-up, the device operation is resumed: enter in Reset Mode. FAIL SAFE FUNCTIONALITY Upon dedicated event or issue detected at a device pin (i.e RESET), the Safe mode can be entered. In this mode, the SAFE terminal is active low.

Description

Upon activation of the SAFE terminal, and if the failure condition that make the SAFE pin activated have not recovered, the device can help to reduce ECU consumption, assuming that the MCU is not able to set the whole ECU in low power mode. Two main cases are available: mode A: Upon SAFE activation, the MCU remains powered (Vdd stays ON), until the failure condition recovers (i.e S/W is able to properly control the device and properly refresh the W/D). modes B1, B2 and B3: Upon SAFE activation, the syst em continues to monitor external event, and disable the MCU supply (turn Vdd off). The external events monitored are: CAN traffic, I/O-1 low level or both of them. 3 sub cases exist, B1, B2 and B3. Note: no CAN traffic indicates that the ECU of the vehicle are no longer active, thus that the car is being parked and stopped. The I/O low level detection can also indicate that the vehicle is being shutdown, if the I/O-1 terminal is connected for instance to a switched battery signal (ignition key on/off signal). The selection of the monitored events is done by hardware, via the resistor connected at DBG pin, but can be over write by software, via a specific SPI command. By default, after power up the device detect the resistor value at DBG pin (upon transition from INIT to Normal mode), and, if no specific SPI command related to Debug resistor change is send, operates according to the detected resistor. The INIT MISC register allow to verify and change the device behaviour, to either confirm or change the hardware selected behaviour. Device will then operate according to the SAFE mode configured by SPI. Table below ( Table 7) illustrates the complete options available: Exit of Safe Mode Exit of the safe state with Vdd off is always possible by a wake-up event: in this safe state the device is automatically wakeable by CAN and I/O (if I/O wake up was enable by SPI prior to enter in SAFE mode). Upon wake-up, the device operation is resumed, and device enters in reset mode. The SAFE terminal remains active, until a proper read and clear of the SPI flags reporting the SAFE conditions. Table 7. Fail Safe Options B1 Turn OFF 8s after CAN traffic bus idle detection. B2 Turn OFF when I/O-1 low level detected. when I/O-1 low level detected.

Figure 24. Safe Operation Flow Chart is the case, the Safe Mode is entered. 5) detection of 8 consecutive W/D failures: no correct SPI W/D refresh command occurred for duration of 8 x 256ms. between RESET and NORMAL REQUEST mode, or INIT RESET and INIT modes. 7) 8 second timer for bus idle time out. I/O-1 high to low transition.

44 Freescale Semiconductor

Figure 25. SAFE Mode A Behavior Illustration

resistor or SPI configuration. Figure 26. SAFE Modes B1, B2 or B3 Behavior Illustration

46 Freescale Semiconductor

recessive level stabilization. Figure 27. CAN Interface Block Diagram The supply voltage for the CAN driver is the 5V-CAN pin. Mode to allow wake-up detection. the CAN interface current is sourced from the 5V-CAN pin. level, and the CAN bus state is reported on the RXD pin. biasing is provided on the SPLIT output pin. effect on CAN bus lines. The 5V-CAN regulator must be ON. Normal Mode and the TXD pin is recessive.

5V-CAN divided by 2, or approx. 2.5V. recessive and RXD is set high. dominant and RXD is set low. affected by the slew rate selection. error flag and its echo error flag). to a single bit time of: 300μs / 12 = 25μs. So the minimum Baud rate is 1 / 25μs = 40kBaud. Sleep Mode is a reduced current consumption mode. results in a device wake up if device was in Low Power Mode. Figure 28. Bus Signal in Tx/Rx and Low Power Mode

48 Freescale Semiconductor

Figure 29. Single Dominant Pulse Wake-up dominant pulses, by default when the CANWU bit is low. Figure 30. Pattern Wake-up - Multiple Dominant Detection

• Differential termination resistors between CANH and CANL lines.
• SPLIT termination concept, wi th the mid point of the differ- ential termination connected to GND through a capacitor and to the SPLIT pin.
• In application, device can also be used without termina - tion. CANL CANH Internal wake-up signal Dominant CAN Pulse # 1 Dominant Pulse # 2 Tcan wu1-f Can wake up detected bus Internal differential wake-up receiver signal CANL CANH Internal wake-up signal Dominant Internal differential wake-up receiver signal CAN Pulse # 1 Dominant Pulse # 2 Dominant Pulse # 3 Dominant Pulse # 4 Tcan wu3-f Tcan wu3-f Tcan wu3-f Tcan wu3-to Dominant Pulse # n: duration 1 or multiple dominant bits Can wake up detected bus

• The figure below illustrate so me of the most common ter- minations.

Figure 31. Typical Application and Bus Termination Options

50 Freescale Semiconductor

monitor the bus level in the recessive and dominant states. properly determine the failure and report it. Figure 32. CAN Bus Simplified Structure Truth Table for Failure Detection The following table indicates the state of the comparators in case of a bus failure, and depending upon the driver state. comparator is also close to zero. dominant cycles, the error is not reported. to internal 2.5V biasing or to GND (Sleep Mode). voltage between CANH and CANL, and RXD pin will be low. Table 8. Failure Detection Truth Table

Analog Integrated Circuit Device Data

52 Freescale Semiconductor

TXD TO RXD SHORT CIRCUIT: Principle In case TXD is shorted to RXD during incoming dominant information, RXD is set low. Consequently, the TXD pin is low and drives CANH and CANL into a dominant state. Thus the bus is stuck in dominant. No further communication is possible. Detection and Recovery The TXD permanent dominant timeout will be activated and release the CANL and CANH drivers. However, at the next incoming dominant bit, the bus will then be stuck in dominant again. The recovery condition is same as the TXD dominant failure IMPORTANT INFORMATION FOR BUS DRIVER REACTIVATION The driver stays disabled until the failure is/are removed (Tx and/or RX is no longer permanent dominant or recessive state or shorted) and the failure flags cleared (read). The CAN driver must be set by SPI in TxRx mode in order to re enable the CAN bus driver.

Analog Integrated Circuit Device Data Freescale Semiconductor 53 LIN BLOCK LIN INTERFACE DESCRIPTION LIN BLOCK LIN INTERFACE DESCRIPTION The physical interface is dedicated to automotive LIN sub- bus applications. The interface has 20kbps and 10kbps baud rates, and includes as well as a fast baud rate for test and programming modes. It has excellent ESD robustness and immunity against disturbance, and radiated emission performance. It has safe behavior in case of a LIN bus short-to-ground, or a LIN bus leakage during low power mode. Digital inputs are related to device Vdd terminal. POWER SUPPLY PIN (VSUP) The VSUP-2 terminal is the supply pin for the LIN interface. To avoid a false bus message, an under-voltage on VSUP disables the transmission path (from TXD to LIN) when VSUP falls below 6.1 V. GROUND PIN (GND) In case of a ground disconnection at the module level, the LIN interface do not have significant current consumption on the LIN bus pin when in the recessive state. LIN BUS PIN (LIN1, LIN2) The LIN terminal represents the single-wire bus transmitter and receiver. It is suited for automotive bus systems, and is compliant to the LIN bus specification 2.1 and SAEJ2602-2. The LIN interface is only active during Normal mode. Driver Characteristics The LIN driver is a low side MOSFET with internal over- current thermal shutdown. An internal pull-up resistor with a serial diode structure is integrated so no external pull-up components are required for the application in a slave node. An additional pull-up resistor of 1.0 kΩ must be added when the device is used in the master node. The 1.0 kΩ pull resistor can connected to LIN term or to ECU battery supply. The LIN pin exhibits no reverse current from the LIN bus line to VSUP, even in the event of a GND shift or VSUP disconnection. The transmitter has a 20 kbps, 10 kbps and fast baud rate, which are selected by SPI. Receiver Characteristics The receiver thresholds are ratiometric with the device Vsup2 voltage. If the Vsup2 voltage goes below typ 6.1V, the LIN bus enters into a recessive state even if communication is sent on TXD. If LIN driver temperature reached over temperature threshold, the transceiver and receiver are disabled. When the temperature falls below the over temperature threshold, LIN driver and receiver will be automatically enabled. DATA INPUT PIN (TXDL1, TXDL2) The TXDl1 (TXDL2) input pin is the MCU interface to control the state of the LIN output. When TXDL is LOW (dominant), LIN output is LOW. When TXDL is HIGH (recessive), the LIN output transistor is turned OFF. This pin has an internal pull-up current source to Vdd to force the recessive state if the input pin is left floating. If the pin stays low (dominant sate) more than t TXDDOM, the LIN transmitter goes automatically in recessive state. This is reported by flag in LIN register. DATA OUTPUT PIN (RXDL1, RXDL2) The RXDl output pin is the MCU interface, which reports the state of the LIN bus voltage. LIN HIGH (recessive) is reported by a high voltage on RXD, LIN LOW (dominant) is reported by a low voltage on RXD. LIN OPERATIONAL MODES The LIN interface have two operational modes, Transmit receiver and LIN disable modes. TRANSMIT RECEIVE In the TxRx mode, the LIN bus can transmit and receive information. When the 20kbps baud rate is selected, the slew rate and timing are compatible with LIN protocol specification 2.1. When the 10kbps baud rate is selected, the slew rate and timing are compatible with J2602-2. When the fast baud rate is selected, the slew rate and timing are much faster than the above specification and allow fast data transition. SLEEP MODE This mode is selected by SPI, and the transmission path is disabled. Supply current for LIN block from VSUP2 is very low (typ 3uA). LIN bus is monitor to detect wake-up event. In the Sleep Mode, the internal 725 kOhm pull-up resistor is connected and the 30 kOhm disconnected.

54 Freescale Semiconductor

detection of LIN bus activity. detected, the event is reported to the device state machine. will restart if device was in LP Vdd off mode. The wake up can be enable or disable by SPI. Table 9. LIN Block Failure

56 Freescale Semiconductor

Table 10 summarizes the various SPI operation, depending upon bit 15, 14 and 8. coded on 5 bits (bits 13 to 9). device operation or set default value or behavior. Table 10. SPI Operations (bits 8, 14 & 15)

00 Read back of register

1 Bit 8 must be set to 1, independently of the parity function

01 Write to register address,

0 If bit 8 is set to “0”: means parity not selected OR

10 Reserved

11 Read of device flags form

address, coded with bits 13 to 9. Table 11. Device Registers with Corresponding Address 0_0000 Analog Multiplexer MUX 1) Write “device control bits” to register address. 0_0001 Memory byte A RAM_A 1) Write “data byte” to register address. 0_0101 Initialization Regulators Init REG 1) Write “device initialization control bits” to register address. 0_1010 Timer_A: W/D & Low Power MCU consumption TIM_A 1) Write “timing values” to register address. 2) Read back register “control bits”. 3) Read device flags from each of the register addresses.

58 Freescale Semiconductor

options. Both MOSI and MISO information are described. of the write command except bit 8). Bit 8 must be set to 0 if the number of 1 is odd. Bit 8 must be set to 1if the number of 1 is even. because the command contains 7 bits with logic 1. because the command contains 4 bits with logic 1. then Parity bits in all SPI commands (bit 8) must be “0”. Table 12. SPI Capabilities with Options address (bit 13-9), and sub address (bit 7). from the selected address and sub-address.

Table 13. MUX Register

011 Device internal temperature sensor voltage

100 Voltage at I/O-0. Attenuation or gain is selected by bit 3. 101 Voltage at I/O-1. Attenuation or gain is selected by bit 3. 0 Internal 2 kohm resistor disable. An external resistor must be connected between AMUX and GND. 1 Internal 2 kohm resistor enable.

0 Gain is approx 2 for device with VDD =5V (Ref to electrical table for exact gain value)

1 Attenuation is approx 6 for device with VDD =5V (Ref to electrical table for exact attenuation value)

Table 14. Internal Memory Registers A, B, C and D, RAM_A, RAM_B, RAM_C and RAM_D

60 Freescale Semiconductor

Table 15. Initialization Regulator Registers, INIT REG (note: register can be written only in INIT mode)

0 I/O-1 sense anytime

1 I/O-1 sense during I/O-0 activation

1 VAUX = 5

Table 16. Initialization Watchdog Registers, INIT W/D (note: register can be written only in INIT mode) 0 Function disable. No constraint between INT occurrence and INT source read. 1 INT source read must occur before the remaining of the current W/D period plus 2 complete W/D periods. W/D + 00 In Low Power VDD ON Mode, VDD current > VDD_OC_LP threshold has no effect. W/D refresh must occur by SPI command. W/D + 01 In Low Power VDD ON Mode, VDD current > VDD_OC_LP threshold has no effect. W/D refresh must occur by SPI command. W/D + 10 In Low Power VDD ON Mode, VDD over-current for a time > 100μs (typ) is a wake-up event.

0 SAFE terminal is set low at the time of the RESET terminal low activation

1 SAFE terminal is set low at the second consecutive time RESET pulse

00 Simple Watchdog selection: W/D refresh done by a 8bits or 16 bits SPI

01 Enhanced 1: Refresh is done using the Random Code, and by a single 16 bits. 10 Enhanced 2: Refresh is done using the Random Code, and by two 16 bits command. 11 Enhanced 4: Refresh is done using the Random Code, and by four 16 bits command.

0 Watchdog operation is TIME OUT, W/D refresh can occur anytime in the period

1 Watchdog operation is WINDOW, W/D refresh must occur in the open window (second half of period)

0 Vdd disable when Vsup1 is below typ 4V (parameter Vsup-th1), and device in Reset mode

1 Vdd kept ON when Vsup1 is below typ4V (parameter Vsup_th1)

62 Freescale Semiconductor

Table 17. Initialization LIN and I/O registers, INIT LIN I/O (note: register can be written only in INIT mode) 1 Enable I/O-1 turn off, in case VDD or VAUX over-voltage condition is detected.

00 Terminal is OFF

01 Terminal operation as LIN Master Terminal switch

10 Terminal operation as I/O: high side switch and wake-up input

11 N/A

0 Disable high side and low side drivers of terminal I/O-1. I/O-1 can only be used as input. 1 Enable high side and low side drivers of terminal I/O-1. Terminal can be used as input and output driver. 0 Disable high side and low side drivers of terminal I/O-0. I/O-0 can only be used as input. 1 Enable high side and low side drivers of terminal I/O-0. Terminal can be used as input and output driver. side and low side drivers OFF). the opposite (High side or low side driver is turned on).

Table 18. Initialization Miscellaneous Functions, INIT MISC (note: register can be written only in INIT mode)

0 Function disable: the Low Power mode can be entered without usage of Random Code

1 Function enabled: the Low Power mode is entered using the Random Code

0 Function disable: the parity is not used. The parity bit must always set to logic 0. 1 Function enable: the parity is used, and parity must be calculated.

0 INT terminal will assert a low level pulse, duration selected by bit [b4]

1 INT terminal assert a permanent low level (no pulse)

0 INT pulse duration is typ 100μs. Ref to dynamic parameter table for exact value. 1 INT pulse duration is typ 25μs. Ref to dynamic parameter table for exact value. Function enable: an INT pulse will occur at 50% of the Watchdog Period when device in flash mode.

1. Bits b2,1 and 0 allow the following operation:

register (ref to device flag table).

64 Freescale Semiconductor

• Go to INIT mode, using the Secure SPi command.
• Activate the SAFE terminal by S/W.

Table 19. Specific Mode Register, SPE_MODE b7, b6 Sel_Mod[1], Sel_Mod[0] - Mode selection: these 2 bits are used to select which mode the device will enter upon a SPI command.

00 RESET mode

01 INIT mode

10 FLASH mode

Table 20. Timer Register A, Low Power Vdd over current & Watchdog Period Normal mode, TIM_A Table 21. Timer Register B, Cyclic Sense and Cyclic INT, in Device Low Power Mode, TIM_B

66 Freescale Semiconductor

Table 22. Timer Register C, Watchdog LP Mode or Flash Mode and Forced Wake-up Timer, TIM_C Table 23. Typical Timing Values

Table 24. Watchdog refresh register, W/D

1. The Simple Watchdog Refresh command is in hexadecimal: 5A00. This command is used to refresh the W/D and also to transition

Table 25. MODE Register, MODE

68 Freescale Semiconductor

flags must be cleared or read. uses a write to “Normal Request Mode”, 0x5C10. 14] and bit [7]. Note that bit [8] is always set to 1. allow to decode the device current mode. Table 27. Device Modes Read device current Mode, Leave debug mode. Release SAFE terminal (turn OFF). Read device current Mode, Leave debug mode. Release SAFE terminal (turn OFF). Table 28. MISO bits 7-0 Table 29. SAFE and DEBUG status

0 SAFE terminal OFF, not activated

1 FLASH

0 DEBUG mode OFF

1 DEBUG mode Active

Table 30. (25)REGULATOR register, REG

00 Regulator OFF

detected after 1.0ms blanking time. 01 Regulator ON. Thermal protection active. Under-voltage (UV) and Over-current (OC) monitoring flags not reported. 10 Regulator ON. Thermal protection active. Under-voltage (UV) and Over-current (OC) monitoring flags active. in case UV or UV detected after 25μs blanking time.

0 External VDD ballast disable

1 External VDD ballast Enable

0 Disable the automatic activation of the external ballast

1 Enable the automatic activation of the external ballast, if VDD > typ 60mA

0 Disable Usage of Low Power VDD OFF Mode

1 Enable Usage of Low Power VDD OFF Mode

1. The first time the device is set in Normal mode, the CAN is in Sleep wake-up enable (10). The next time the device is set in Normal

mode, the CAN state is controlled by the bit 7 and bit6 states.

70 Freescale Semiconductor

Table 31. CAN Register, CAN 00 CAN interface in Sleep Mode, CAN wake-up disable. 01 CAN interface in receive only mode, CAN driver disable. CAN wake-up is reported by device wake-up. In device normal mode, CAN wake-up reported by INT. 11 CAN interface in transmit and receive mode.

00 FAST

01 MEDIUM

10 SLOW

11 SLOW

1 Single dominant pulse wake-up mechanism

1 Select INT generation as soon as a bus failure is detected, event if not fully identified

Table 32. I/O Register, I/O

00 I/O-3 driver disable, Wake-up capability disable

01 I/O-3 driver disable, Wake-up capability enable. 10 I/O-3 High Side driver enable. 11 I/O-3 High Side driver enable.

00 I/O-2 driver disable, Wake-up capability disable

01 I/O-2 driver disable, Wake-up capability enable. 10 I/O-2 High Side driver enable. 11 I/O-2 High Side driver enable.

00 I/O-1 driver disable, Wake-up capability disable

01 I/O-1 driver disable, Wake-up capability enable. 10 I/O-1 Low Side driver enable. 11 I/O-1 High Side driver enable.

00 I/O-0 driver disable, Wake-up capability disable

01 I/O-0 driver disable, Wake-up capability enable. 10 I/O-0 Low Side driver enable. 11 I/O-0 High Side driver enable.

72 Freescale Semiconductor

Table 33. INT Register, INT

0 INT disable

Table 34. LIN 1 Register, LIN1

00 LIN1 disable, wake-up capability disable

10 LIN1 disable, wake-up capability enable

11 LIN1 Transmit Receive mode

00 Slew rate for 20kbit/s baud rate

01 Slew rate for 10kbit/s baud rate

10 Slew rate for fast baud rate

11 Slew rate for fast baud rate

0 LIN 1 termination OFF

1 LIN 1 termination ON

1 LIN continues operation below Vsup2 6V, until 5V-CAN is disabled.

74 Freescale Semiconductor

Table 35. LIN 2 Register, LIN2

00 LIN2 disable, wake-up capability disable

10 LIN2 disable, wake-up capability enable

11 LIN2 Transmit Receive mode

0 LIN 2 temination OFF

1 LIN 2 temination ON

1 LIN continues operation below Vsup2 6V, until 5V-CAN is disabled.

Analog Integrated Circuit Device Data Freescale Semiconductor 75 SERIAL PERIPHERAL INTERFACE FLAGS FLAGS The table below is the summary of the device flags, I/O real time level and device Identification. They are obtained using the following commands. This command is composed of the following: bits 15 and 14: [1 1] for failure flags, or [0 0] for I/O real time status or device identification.

• bit 13 to 9 are the register address from which the flags is to be read.
• bit 8 = 1 (this is not parity bit function, as this is a read command).

Table 36. Device Flag, I/O real time and Device Identification

1 CAN_UF CAN_F CANL

1 I/O-1-3

76 Freescale Semiconductor

Table 37. Flag Descriptions Vaux_low Description Reports that VAUX regulator output voltage is lower than the VAUX_UV threshold. Description Report that current out of VAUX regulator is above VAUX_OC threshold. Set / Reset condition Set: Current above threshold for t >100μs. Reset: Current below threshold and flag read by SPI. Description Report that the 5V-can regulator has reached over temperature threshold. Description Reports that 5V-can regulator output voltage is lower than the 5V-can UV threshold. Description Report that the CAN driver output current is above threshold. Description Reports that Vsense terminal is lower than the Vsense low threshold. Description Reports that Vsup1 terminal is lower than the Vsup1 low resoled. Description Report that current out of Vdd pin is higher that Idd-oc threshold, while device is in Normal mode. Description Report that the Vdd has reached over temperature threshold, and was turned off. Description Report that the device voltage at Vsup1 pin was below BATFAIL threshold. Description Report that the CAN interface has reach over temperature threshold. RxD low Description Report that Rx pin is shorted to gnd. Rxd high Description Report that Rx pin is shorted to recessive voltage. TxD dom Description Report that Tx pin is shorted to gnd.

Description Report that the CAN current is above CAN over current threshold. Description Report SPI parity error was detected. VSUP2-UV Description Report that VSUP2 is below VSUP2-UV threshold. VSUP1-OV Description Report that VSUP1 is above VSUP1-OV threshold. I/O-O thermal Description Report that the I/O-0 high side switch has reach over temperature threshold. Description Report that the W/D period has reach 50% of its value, while device is in Flash mode. SPI wake-up Description Report that wake up source is SPI command, in Low Power VDD ON Mode.

78 Freescale Semiconductor

Description Report that INT time out error detected. Set / Reset condition Set: INT service time out expired. Reset: flag read. Description Report that Low Power VDD OFF Mode was selected, prior wake up occurred. Reset request Description Report that RST source is an request from a SPI command (go to RST mode). Set / Reset condition Set: device leave debug mode due to Hardware cause. Reset: flag read. INT request Description Report that INT source is an INT request from a SPI command. RST high Description Report that RST pin is shorted to high voltage. Set / Reset condition Set: RST failure detection. Reset: flag read. DBG resistor Description Report that the resistor at DBG pin is different from expected (different from SPI register content). Set / Reset condition Set: failure detected. Reset: correct resistor and flag read (SPI). Description Report that the Vdd has reached over temperature pre warning threshold. VDD UV Description Reports that VDD terminal is lower than the VDDUV threshold. function is selected in INIT register. this function is selected in INIT register. VDD low Description Report that Vdd is below Vdd undervoltage threshold. Description Report that the more than 8 consecutive reset pulses occurred, due to missing or wrong W/D refresh. Description Report that a wrong or missing W/D failure occurred.

Description Report that the LIN1 or LIN 2 interface has reach over temperature threshold. RxD1 low Description Report that RxD1 / RxD2 pin is shorted to gnd. RxD1 high Description Report that RxD1 / RxD2 pin is shorted to recessive voltage. TxD1 dom Description Report that TxD1 / RxD2 pin is shorted to gnd. Table 38. status bits description INT Indicate that an INT has occurred and that INT flags are pending to be read. WU Indicate that an Wake Up has occurred and that Wake Up flags are pending to be read. RST Indicate that an Reset has occurred and that the flags that report the Reset source are pending to be read. CAN-G The INT, or WU or RST source is CAN interface. CAN local or CAN bus source. I/O-G The INT, or WU or RST source is I/O interfaces. CAN-LOC The INT, or WU or RST source is CAN interface. CAN local source. CAN-BUS The INT, or WU or RST source is CAN interface. CAN bus source.

80 Freescale Semiconductor

Figure 36. 33905D Typical Application Schematic

1. Cap > 10uF required to pass EMC requirement according to

Figure 37. 33905S Typical Application Schematic

1. Cap > 10uF required to pass EMC requirement according to

82 Freescale Semiconductor

Figure 38. 33904A Typical Application Schematic

1. Cap > 10uF required to pass EMC requirement according to

without using the VAUX regulator are illustrated as well. Figure 39. Application Options Optimized solution for cranking pulses. C1 is sized for MCU power supply buffer only. delivered by internal path transistor.

Analog Integrated Circuit Device Data

84 Freescale Semiconductor

SOIC 32 PACKAGE DIMENSIONS PACKAGING SOIC 32 PACKAGE DIMENSIONS For the most current package revision, visit www.freescale.com and perform a keyword search using the “98A” listed below. EK SUFFIX (PB-FREE) 32-PIN SOIC WIDE BODY EXPOSED PAD 98ASA10556D REVISION D

Analog Integrated Circuit Device Data Freescale Semiconductor 85 PACKAGING SOIC 32 PACKAGE DIMENSIONS EK SUFFIX (PB-FREE) 32-PIN SOIC WIDE BODY EXPOSED PAD 98ASA10556D REVISION D

Analog Integrated Circuit Device Data

86 Freescale Semiconductor

SOIC 32 PACKAGE DIMENSIONS EK SUFFIX (PB-FREE) 32-PIN SOIC WIDE BODY EXPOSED PAD 98ASA10556D REVISION D

Analog Integrated Circuit Device Data Freescale Semiconductor 87 PACKAGING SOIC 54 PACKAGE DIMENSIONS SOIC 54 PACKAGE DIMENSIONS EK SUFFIX (PB-FREE) 54-PIN SOIC WIDE BODY EXPOSED PAD 98ASA10506D REVISION D

Analog Integrated Circuit Device Data

88 Freescale Semiconductor

SOIC 54 PACKAGE DIMENSIONS EK SUFFIX (PB-FREE) 54-PIN SOIC WIDE BODY EXPOSED PAD 98ASA10506D REVISION D

Analog Integrated Circuit Device Data Freescale Semiconductor 89 PACKAGING SOIC 54 PACKAGE DIMENSIONS EK SUFFIX (PB-FREE) 54-PIN SOIC WIDE BODY EXPOSED PAD 98ASA10506D REVISION D

Analog Integrated Circuit Device Data

90 Freescale Semiconductor

REVISION HISTORY

REVISION DATE DESCRIPTION OF CHANGES 1.0 11/2009 • Initial Release 2.0 1/2010 • Updated LIN 2.0 to LIN 2.1 throughout document

• Changed Pin VC to VE
• Changed Pin VBASE to VB
• Added note to Simplified Application and Typical Application drawings for Q1 to be optional.
• Updated Parameters Tables.; Timing accuracy added, CAN wake and CANL/CANH input current.
• Changed default setting of: INIT Reg register, bit7, I/Ox sync - INIT W/D register, bit 6 MCU_OC and bit 1 W/D N/Win 3.0 2/2010 • Re-arranged the order of the devices.

How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. Technical Information Center, EL516

2100 East Elliot Road

Tempe, Arizona 85284 1-800-521-6274 or +1-480-768-2130 www.freescale.com/support Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7

81829 Muenchen, Germany

+44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) www.freescale.com/support Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo 153-0064 Japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com Asia/Pacific: Freescale Semiconductor China Ltd. Exchange Building 23F No. 118 Jianguo Road Chaoyang District Beijing 100022 China +86 10 5879 8000 support.asia@freescale.com For Literature Requests Only: Freescale Semiconductor Literature Distribution Center P.O. Box 5405 Denver, Colorado 80217 1-800-441-2447 or +1-303-675-2140 Fax: +1-303-675-2150 LDCForFreescaleSemiconductor@hibbertgroup.com Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2010. All rights reserved. MC33904_5 Rev. 3.0 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”, must be validated for each customer application by customer’s technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part.