33902 FREESCALE | Alldatasheet
Document overview
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Technical content
Features
- High speed CAN interface for baud rates of 40 kb/s to 1.0 Mb/s
- Compatible to ISO11898 standard
- Single supply from battery. No need for a 5.0 V supply for CAN interface
- I/O compatible from 2.75 V to 5.5 V via a dedicated input terminal (3.3 V or 5.0 V logic compatible)
- Low Power mode with remote CAN wake-up and local wake-up recognition and reporting
- CAN bus failure diagnostics and TXD/RXD pin monitoring, cold start detection, wake-up sources reported through the ERR pin
- Enhanced diagnostics for bus, TXD, RXD and supply pins available through Pseudo SPI via existing terminals EN, STBY and ERR.
- Split terminal for bus recessive level stabilization
- INH output to control external voltage regulator
- Pb-free packaging designated by suffix code EF
Figure 1. MC33902 Simplified Application Diagram
ORDERING INFORMATION
Range (TA) Package MCZ33902EF/R2 -40°C to 125°C 14 SOIC SPLIT VSUP GNDINH WAKE MCU Voltage I/O Tx Rx VDD CAN bus CANL CANH RXD STBY EN ERR TXDCAN Controller VDD 33902 VBAT Bus Driver Bus 5V Reg INH VIO I/O & Control Diag. & Receiver Regulator
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Figure 2. 33902 Simplified Internal Block Diagram
5.0 V Regulator
Figure 3. 33902 Pin Connections Table 1. 33902 Pin Definitions
1 TXD Input Transmit data CAN bus transmit data input pin
2 GND Output Ground Ground termination
4 RXD Output Receive data CAN bus receive data output pin, wake-up flag in Low Power mode
5 VIO Input Voltage supply for I/O Input supply for the digital input output pins
6 EN Input Enable Enable input for device static mode control. MOSI (Master Out, Slave In) during P_SPI operation.
7 INH Output Inhibit Inhibit output for control of an external power supply regulator
8 ERR Output Active low Error Pin for static error and wake-up flag reporting
MISO (Master In, Slave Out) during P_SPI operation.
9 WAKE Input Wake Wake input
10 VSUP Input Voltage supply Battery supply pin
11 SPLIT Output Split Output for connection of the CAN bus termination middle point
12 CANL Input/output CAN LOW CAN low pin
13 CANH Input/output CAN HIGH CAN high pin
14 STBY Input Standby Standby input for device static mode control. CLK (Clock) during P_SPI operation.
1 STBY
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ELECTRICAL CHARACTERISTICS
Table 2. Maximum Ratings permanent damage to the device.
Analog Integrated Circuit Device Data Freescale Semiconductor 5 33902 STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics values noted reflect the approximate parameter means at TA = 25°C under nominal conditions, unless otherwise noted.
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STATIC ELECTRICAL CHARACTERISTICS LOGIC INPUT PINS (EN, STBY, TXD) High Level Input Voltage VIH 0.7 VIO - - V Low Level Input Voltage VIL - - 0.3 VIO V Pull-down Current, EN, STBY, VIN = VIO IPD EN-STBY 1.0 4.0 10 µA Pull-up Current, TXD, VIN = 0 V IPD TXD - -250 - µA DATA OUTPUT PINS (RXD) AND (ERR) Low Level Output Voltage I = 5.0 mA VOUTLOW 0.0 - 0.3 VIO V High Level Output Voltage I = -3.0 mA VOUTHIGH 0.7 VIO - VIO V High Level Output Current V = VIO - 0.4 V IOUTHIGH -12 -5.0 -2.0 mA Low Level Output Current V = 0.4 V IOUTLOW 2.0 5.0 12 mA OUTPUT PIN (INH) Output Drop Voltage (IINH), IOUT = 100 uA) INHDROP 0.05 0.2 0.8 V leakage Current (Sleep mode) INHLEAK - - 5.0 µA INPUT PIN (WAKE) Low level threshold voltage WAKELTH 2.0 2.5 3.0 V High level threshold voltage WAKEHTH 2.0 2.7 3.5 V Input Current VWAKE = -0.2 to 18 V IWAKEIN -10 0 10 µA LOGIC INPUT/OUTPUT PINS (CANH, CANL) Bus pins common mode voltage for full functionality VCOM -12 - 12 V Differential input voltage, recessive state at RXD VCANH-VCANL-R - - 500 mV Differential input voltage, dominant state at RXD VCANH-VCANL-D 900 - mV Differential input hysteresis (RXD) VDIFF-HYST - 100 - mV Input resistance RIN 5.0 - 50 kΩ Differential input resistance RIND 10 - 100 kΩ Common mode input resistance matching RINM -3.0 0.0 3.0 % CANH output voltage(45 Ω < RBUS < 65 Ω) TX dominant state TX recessive state VCANH 2.75 2.0 3.5 2.5 4.5 3.0 V CANL output voltage(45 Ω < RBUS < 65 Ω) TX dominant state TX recessive state VCANL 0.5 2.0 1.5 2.5 2.25 3.0 V Differential output voltage(45 Ω < RBUS < 65 Ω) TX dominant state TX recessive state VOH-VOL 1.5 -500 2.0 0.0 3.0 V mV values noted reflect the approximate parameter means at TA = 25°C under nominal conditions, unless otherwise noted.
Analog Integrated Circuit Device Data Freescale Semiconductor 7 33902 STATIC ELECTRICAL CHARACTERISTICS LOGIC INPUT/OUTPUT PINS (CANH, CANL) (CONTINUED) CANH output current capability - Dominant state ICANH - - -25 mA CANL output current capability - Dominant state ICANL 25 - - mA CANL over-current detection - Error reported in register ICANL-OC 75 120 195 mA CANH over-current detection - Error reported in register ICANH-OC -195 -120 -75 mA CANH, CANL input resistance device supplied and in Sleep mode, VCANH, VCANL from 0 V to 5.0 V RINSLEEP 5.0 - 50 kΩ CANL, CANH output voltage in Sleep and Standby modes (45 Ω < RBUS < 65 Ω) VCANLP -0.1 0.0 0.1 V CANH, CANL input current, device un supplied, VSUP and VIO connected to GND (ref. fig.) VCANH, VCANL = 5.0 V VCANH, VCANL = -2.0 to + 7.0 V ICAN 250 400 µA CANH AND CANL DIAGNOSTIC INFORMATION CANL to GND detection threshold VLG - 1.75 - V CANH to GND detection threshold VHG - 1.75 - V CANL to VBAT detection threshold, valid if VSUP > 7.0 V VLVB - VSUP-2.0 - V CANH to VBAT detection threshold, valid if VSUP > 7.0 V VHVB - VSUP-2.0 - V CANL to VDD detection threshold VL5 - VDD-0.43 - V CANH to VDD detection threshold VH5 - VDD-0.43 - V SPLIT Output voltage Loaded condition Isplit =+- 500 µA Unloaded condition Rmeasure > 1.0 MΩ VSPLIT
0.3 VDD
0.45 VDD
0.5 VDD
0.7 VDD
0.55 VDD
V Leakage current -12 V < VSPLIT< +12 V -22 V < VSPLIT< +35 V ILSPLIT 0.0 5.0 µA values noted reflect the approximate parameter means at TA = 25°C under nominal conditions, unless otherwise noted.
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DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 4. Dynamic Electrical Characteristics values noted reflect the approximate parameter means at TA = 25°C under nominal conditions, unless otherwise noted.
Analog Integrated Circuit Device Data Freescale Semiconductor 9 33902 Figure 4. P_SPI Timing Figure 5. Propagation Loop Delay TXD to RXD values noted reflect the approximate parameter means at TA = 25°C under nominal conditions, unless otherwise noted.
0.3 VIO
0.7 VIO
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Figure 6. Propagation Delays TXD to CAN and CAN to RXD Figure 7. Test Circuit for Timing Characteristics
Analog Integrated Circuit Device Data Freescale Semiconductor 11 33902 FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION TRANSMIT DATA (TXD) This input is the CAN transmit data pin. It is the interface from the MCU to the output on the CAN bus. If TxD is low (dominant), then the signal on the CAN bus will be dominant (CANH is ~5.0 V and CANL is ~0 V). If TxD is high (recessive), then the signal on the CAN bus will be recessive (CANH and CANL will be ~2.5 V). The TxD thresholds are 3.3 V and 5.0 V compatible (depending on VIO voltage) to accommodate the implementation of various MCUs. There are three slew rates available, which are selected via the Pseudo SPI. GROUND (GND) Ground termination pin. VOLTAGE DIGITAL DRAIN (VDD) This is the dedicated embedded supply voltage for the CAN interface. A capacitor must be connected to this pin. CAN interface current is sourced from this pin if device is in transmit and receive mode. In low power modes, current for the CAN interface is sourced directly from the VSUP pin. RECEIVE DATA (RXD) This output pin is the CAN receive data. It is the interface to the MCU, which reports the state of the CAN bus. If the CAN bus is recessive (CANH and CANL ~2.5 V), then the signal on RxD will be high (recessive). If the CAN bus is dominant (CANH is ~5.0 V and CANL is ~0 V), then the signal on RxD will be low (dominant). This pin is also an active-low wake-up flag in low power, which reports a wake- up event to the MCU. RxD thresholds are 3.3 V and 5.0 V compatible (depending on the VIO voltage) to accommodate the implementation of various MCUs. VOLTAGE SUPPLY FOR I/O (VIO) This is the dedicated input supply pin to determine voltage thresholds for the digital input/output pins. The VIO thresholds range from 2.75 V to 5.5 V to accommodate the implementation of 3.3 V or 5.0 V MCUs. ENABLE (EN) This is the enable input pin for device static mode control. This pin is connected to the MCU to place transceiver in the desired mode. Functional voltage thresholds are determined by VIO voltage to accommodate the implementation of 3.3 V or 5.0 V MCUs. MOSI (Master Out, Slave In) during Pseudo SPI communication. INHIBIT (INH) The inhibit output pin controls an external power supply regulator. When the INH output is low, the external regulator is expected to shut down, which would then turn off the MCU and any other device that is powered up by the external regulator. This should considerably decrease the module’s current consumption. ACTIVE LOW ERROR (ERR) The dedicated active low flag reporting pin reports any static errors, flags and wake-ups to the MCU depending on devices operating state. MISO (Master In, Slave Out) during Pseudo SPI communication. WAKE (WAKE) The Wake input pin is used to wake-up the device from sleep mode after a Battery to Gnd, or Gnd to Battery transition. This pin is usually connected to an external switch in the application module, and SHOULD NOT be left open. If Wake pin functionality is not being used, it should be connected to GND to avoid false wake-ups. This pin exhibits a high-impedance for low input current when implemented below 18 V. If voltage exceeds 18V at the pin, a series resistor should be used to limit the amount of current that the device will start sinking. VOLTAGE SUPPLY (VSUP) This is the power supply input pin. The DC operating voltage for the device is 5.5 V to 27 V. A reverse battery protection diode should be implemented. This pin is able to sustain automotive transient conditions, such as 40 V load dumps and 27 V jump start conditions. The device’s quiescent sleep current is typically around 10 μA. SPLIT (SPLIT) This is the output pin for middle point connection of CANH and CANL when implementing split termination. Pin voltage is typically around half of VDD (2.5 V) with or without loads. This pin must be left open if split CAN termination is not implemented. CAN HIGH (CANH) This is the CAN High input/output pin. CANH circuitry is design to work as a high side switch connected to VDD. In the recessive state, this switch is turned off and CANH is then biased to SPLIT voltage or GND, depending on device’s operating state. In the dominant state, the switch is turned on and CANH is biased to VDD voltage. The CANH pin is protected and diagnostics reporting is available against short to Battery, Gnd, and 5.0 V (VDD).
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FUNCTIONAL PIN DESCRIPTION CAN LOW (CANL) This is the CAN Low input/output pin. CANL circuitry is design to work as a low side switch connected to GND. In the recessive state, this switch is turned off and CANL is then biased to SPLIT voltage or Gnd, depending on device’s operating state. In the dominant state, the switch is turned on and CANL is biased to GND voltage. The CANL pin is protected and diagnostics reporting is available against short to Battery, Gnd, and 5.0 V (VDD). STANDBY (STBY) This is the standby input pin for device static mode control. This pin is connected to the MCU to place transceiver in the desired mode. Functional voltage thresholds are determined by VIO voltage to accommodate the implementation of 3.3 V or 5.0 V MCUs. CLK (Clock) during Pseudo SPI communication.
Figure 8. State Diagram
- If V I/O is still switched on
- If batfail flag and wake-up flag are cleared. An attempt to enter Sleep mode without batfail and wake-up flag cleared has no effect
- Limited current capability, to maintain the capacitor at V DD charged.
- A high level on INH will report a wake-up in Sleep mode
- After 4 TXD pulses rising edge
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Figure 9. VDD Low Illustration Table 5. Functional Table
- Report local failure, VDD low, Bat fail 1 1 Normal ON High Driver and Receiver: ON
- wake-up source (10)
- BUS failures, VDD low Notes 8. With limited current capability, in order to maintain the capacitor at VDD pin charged 9. Provided if V IO > 2.5 V. 10. Before 4th TX pulse rising edge VSUP ~3.0 V 5.0 V
5.0 VVDD
VDD low illustration, cranking pulse VSUP < VSUP low (VSUP < 5.8 V) and CRANK bit low in P_SPI register. 2) VDD is re enabled when VSUP recovers (VSUP low flag goes from H to L) or by a mode change via EN and STBY input.
Standby mode is a reduced current consumption mode. on VIO should be maintained. fast transition to Normal mode and fast CAN communication. voltage drop can be observed. See Figure 10. Figure 10. VDD Regulator Start-up In Normal mode, both the CAN driver and receiver are ON. and the CAN bus state is reported on the RXD pin. provided on the SPLIT output pin. Normal mode will clear the BATFAIL flag. the ERR pin reports the BATFAIL flag. 2.5 V biasing is provided on the SPLIT output pin. pin is deactivated, INH is high-impedance. mode, as well as in Sleep mode if VIO is present.
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as well as in Sleep mode if VIO is present. indicate a local wake-up, and high to indicate CAN wake-up. ERR pin coming from Normal mode. above VSUV, the CRANK bit has no effect. by changing modes and observing ERR staying low. and in Listen Only mode. However, this is unlikely to occur. is above VDD low threshold, plus the P_SPI reading. threshold. (refer to crank pulse illustration). device is controlled in a static manner. Table 6. “Static” Diagnostic Flags TXD pin) Leaving Normal mode, or by setting BATFAIL flag. Local Failure Listen Only mode (coming from Normal mode) Entering Normal mode or TXD high while RXD low. and has exited low power modes (TLP-NP parameter).
Figure 11 shows the meaning of the ERR pin versus the device state, the state transition and the events on TXD. Figure 11. ERR versus device state the CAN interface current is sourced from the VDD pin. Normal mode and the TXD pin is recessive. VDD divided by 2, approx. 2.5 V. low and CANH is pulled high. recessive and RXD is set high. dominant and RXD is set low. The CAN signal slew rate selection is done via the P_SPI. affected by the slew rate selection. error flag and its echo error flag). to a single bit time of: 300 μs / 12 = 25 μs. So the minimum Baud rate is 1 / 25 μs = 40 kBaud.
5.0 V or VBAT => ERR low
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- Differential termination resistors between CANH and CANL lines
- Split termination concept, with the mid point of the differen- tial termination connected to GND through a capacitor, and to the SPLIT pin
- Refer to Typical Application and Bus Termination Options and WAKE Pin Configuration on page 27 Low Power Mode In low power mode, the CAN is internally supplied from the VSUP pin. In low power mode, the CANH and CANL drivers are disabled, and the receiver is also disabled. CANH and CANL have a typical 40 kΩ impedance to GND. The wake-up receiver can be activated if wake-up is enabled by the P_SPI command. The SPLIT pin is high-impedance. When the device is set back into Normal mode, CANH and CANL are set back into the recessive level. This is illustrated in the following diagram.
Figure 12. Bus Signal in Normal and Low Power Mode the wake-up is reported by the ERR and RXD pin low level. signal is detected. This is illustrated in Figure 13. Figure 13. Pattern Wake-up
GND, VBAT, and the internal application circuit board 5.0 V. Figure 14. CAN Bus Simplified Structure Truth Table for Failure Detection Table 7 indicates the state of the comparators in case of a bus failure, and depending upon the driver state. comparator is also close to zero. dominant cycles, the error is not reported. to an internal 2.5 V biasing or to GND (Sleep mode). Table 7. Failure Detection Truth Table
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will help to determine such failure situation. high transition of the differential receiver. level at the Bus as shown in Figure 16. Figure 16. RX Path Simplified Schematic, Rx Short to VDD Detection The RX flag is not the RXPR bit in the LPC register, and neither is the CANF in the INTR register.
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Distinction Between P_SPI and Traditional Operation. level and device state diagram. operation should be faster than (1 / (2 * tDEV-TR). should be 1,1 at end of the P_SPI command. transition of the next message. mode. It is not operating in Standby and Sleep modes. Table 8 is the mapping of the P_SPI register. Table 8. P_SPI Bit Mapping
0 BATFA
Analog Integrated Circuit Device Data Freescale Semiconductor 23 33902 FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES LxWU Description Wake-up event occurred on the WAKE pin Set In low power mode, by a local wake pin transition Reset Exit Normal mode or P_SPI reading (Listen Only and Normal mode) Action Avoid entering Go To Sleep mode. Set ERR low in low power modes CANWU Description Wake-up event occurred on CAN bus Set In low power mode, by CAN wake-up Reset Exit Normal mode or P_SPI reading (Listen Only and Normal mode) Action Avoid entering Go To Sleep mode. Set ERR and RXD low in low power modes VMONF Description Voltage monitoring flag: OR of VSOV, VSUV, VIO, VDDLOW, VDD prewarning Temp Set In normal and listen only modes: OR of VSOV, VSUV, VIO, VDDLOW, VDD prewarning Temp Reset Entering low power mode or (Failure removed + P_SPI reading (Listen Only and Normal mode)) Action If ERR_EXT is set, ERR pin set low. ERR is low for the VDD low flag, despite the ERR-EXT bit. CANF Description Failure on the CAN bus. OR of CANF2, CANF1, CANF0 bits Set In Normal and Listen Only modes: OR of TXDPD, RXDPR, CANcur, CAN bus failures Reset Entering low power mode or (Failure removed + P_SPI reading (Listen Only and Normal mode)) Action Depending upon failure. ref to detail flag description WILS Description Real time WAKE input level. Low is WAKE below threshold, high is WAKE above threshold. Set WAKE pin higher than threshold Reset WAKE pin lower than threshold Action No action SPIerr Description Pseudo SPI error: Incomplete transmission error during start of P_SPI Set When P_SPI frame does not have 8 clock pulses Reset Entering low power mode or P_SPI reading (Listen Only and Normal mode) Action P_SPI wrong command is ignored ERR_EXT Description ERR pin operation report all flags Configure By P_SPI Reset Entering low power mode Action When high, extend the ERR output pin to report all flags (when available) in any modes. When low (default) ERR reports default flags.
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FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES CANSR (1,0) Description 00: CAN slew rate 0 11: CAN slew rate 0 01: CAN slew rate 1 10: CAN slew rate 2 Configure By P_SPI in Listen Only and Normal mode Reset Entering low power mode Action Change CAN slew rate (ref to parametric). Default is 00. CAN WU - pattern Description Select between 2 wake-up mechanisms Configure By P_SPI in Listen Only and Normal mode Reset Leaving low power mode Action When high wake-up occurs after 1 pulse of a minimum of 4.0 μs (parameter). When low, (default) wake- up occurs after 3 pulses of a minimum of 600ns (parameters). CRANK Description When this flag is set, the VDD low condition does not disable CAN and VDD regulator, if VSUV flag is set. Configure By P_SPI in Normal and Listen Only modes Reset Entering low power mode or P_SPI write (Listen Only and Normal mode) Action No disable of CAN and VDD regulator in case of a VDD low condition, and the VSUV flag is set. ERR reports a VDD low condition. The P_SPI VDD low flag is set. PASS ID(1,0), METID(1,0) Set Report device internal identification Reset Action BUS dom Description Detect a bus voltage dominant for a time longer than tDOM. Set This flag is set if the bus is detected to be in dominant for more than tDOM Reset Entering low power mode, bus recessive P_SPI reading (Listen Only and Normal mode) Action No action, set ERR low in Normal mode CAN cur Description Over-current occurred on the CANH or CANL driver Set In Normal mode, if the CANH or CANL current exceed the threshold (parameter) Reset Entering low power mode, the CAN current below threshold + P_SPI reading (Listen Only and Normal mode) Action By default no action. If the ERR-EXT bit is set, the ERR is set low.
Analog Integrated Circuit Device Data Freescale Semiconductor 25 33902 FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES RX-PR Description RXD short to high (recessive level) Set In Normal and Listen Only modes, if the RXD permanent recessive condition is detected Reset Entering low power mode, the RXD recovery condition reached + P_SPI reading (Listen Only and Normal mode) Action Set the local failure flag, disable the CAN driver, set ERR low in Listen Only mode coming from Normal mode TX-PD Description TXD permanent dominant Set In NORMAL modes, if TXD permanent dominant condition detected Reset Entering low power mode, TXD recovery condition reached + P_SPI reading (Listen Only and Normal mode) Action Set the local failure flag, disable the CAN driver, set ERR low in Listen Only mode coming from Normal mode CANF (2,1,0) Description 0 0 0: No CAN bus failure 0 0 1:CANL short to GND 0 1 0: CANL short to VDD 0 1 1: CANL short to VBAT 1 0 1: CANH short to GND 1 1 0: CANH short to VDD 1 1 1: CANH short to VSUP Set In Normal modes, if CAN failure condition detected Reset Entering low power mode, CAN failure recovery condition reached + P_SPI reading (Listen Only and Normal mode) Action Set the bus failure flag, set the ERR low in Normal mode after 4 Tx pulses VDD temp Description VDD regulator reaches temperature prewarning Set In Normal mode or Listen Only mode, if the VDD temperature reaches the prewarning threshold Reset Real time report, reset if the temperature falls below the prewarning threshold Action By default no action. If the ERR-EXT bit is set, ERR is set low. VSOV Description VSUP over-voltage detected Set In Normal and Listen Only modes, if the VSUP over-voltage threshold condition detected Reset Entering low power mode, VSUP over-voltage threshold condition recovered + P_SPI reading (Listen Only and Normal mode) Action By default no action. If the ERR-EXT bit is set, the ERR is set low.
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FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES VSUV Description VSUP under-voltage detected Set In Normal and Listen Only modes, if the VSUP under-voltage threshold condition detected Reset Entering low power mode, VSUP under-voltage threshold condition recovered + P_SPI reading (Listen Only and Normal mode) Action When VSUP voltage rises above the VSUS threshold, the VDD regulator is re-enabled if disabled previously by a VDD low condition VIO low Description VIO low detected Set In all modes, if VIO under-voltage threshold condition detected Reset Entering low power mode, VIO under-voltage threshold condition recovered + P_SPI reading (listen only and normal mode) Action After 10ms, set the device in Sleep mode, if VSUV low (don’t enter Sleep mode during crank and power up phase). VDD low Description VDD voltage < VDDLOW flag threshold Set In all modes, if VDD under-voltage threshold condition detected Reset Entering low power mode, VDD under-voltage threshold condition recovered + P_SPI reading (Listen Only and Normal mode), mode change between Normal and Listen Only if VDD regulator was turned off previously by a VDD low condition for more than 50ms. Action After 10 ms, disable the CAN, after 50 ms disable the regulator, if CRANK bit is set low (default).
Figure 18. Typical Application and Bus Termination Options and WAKE Pin Configuration
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COMPARISON WITH COMPETITION 14 PIN HIGH SPEED CAN TRANS- CEIVER COMPARISON WITH COMPETITION 14 PIN HIGH SPEED CAN TRANSCEIVER The table below is a comparison between the MC33902 and the competition 14 pin high speed CAN transceiver having no embedded power supply. Item MC33902 Competition w/o Embedded Regulator VDD pin Output. Requires local decoupling capacitor(s). No extra load should be connected. Input. Requires connection to a 5.0 V supply. Wake pin Fixed threshold typ 3.0 V with hysteresis. No pull-up or pull-down. High-impedance input. Connect to GND when not used. Threshold VBAT -3.0 V. Active pull-up when input is above threshold. Active pull-down when input is below threshold. ERR pin Active low, reports flags, or used as MISO during P_SPI communication. Strong driver (capability typ. 3.0 mA). Active low, reports flags, weak driver, requiring 8.0 μs stabilization time EN and STBY pins Input used for static mode control. Used as CLOCK and MOSI during P_SPI communication. Input used for mode control. Bus dom failure flag Failure reported on ERR pin in Normal mode (considered as a bus failure => reported in Normal mode) Failure reported on the ERR pin in Listen Only mode (considered as a local failure) VDD low flag No effect on device mode. Failure on CAN transceiver supply should not affect the complete ECU. VDD is disabled “locally” to reduce current consumption. The ERR pin is set low in Normal and Listen Only mode. VDD low threshold set at 4.25 V Set the device into Sleep mode. INH is turned OFF. If the ECU regulator is controlled by INH, ECU is turned OFF. VIO low flag Same Same Wake-up time From Sleep or Standby mode, device needs 35 μs typ. to be ready. No need for a delay for device ready. Transition time At least 8.0 μs, to differentiate between a static transition and P_SPI communication Immediate transition. However, the ERR pin has weak driver and an 8.0 μs stabilization time is required. When the device is switched between Normal and Listen Only mode to check the fail flag, a delay of 8.0 μs is needed.
Analog Integrated Circuit Device Data Freescale Semiconductor 29 33902 PACKAGING PACKAGE DIMENSIONS PACKAGING PACKAGE DIMENSIONS For the most current package revision, visit www.freescale.com and perform a keyword search using the 98ASB42565B listed below. EF-PIN (PB-FREE) 98ASB42565B ISSUE H
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REVISION HISTORY
REVISION DATE DESCRIPTION OF CHANGES 3.0 8/2009 • Initial Release
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