33889 FREESCALE | Alldatasheet
Document overview
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Technical content
Features
VDD1: 5.0 V low drop voltage regulator, current limitation, overtemperature detection, monitoring and reset function with total current capability 200 mA V 2: tracking function of VDD1 regulator; control circuitry for external bipolar ballast transistor for high flexibility in choice of peripheral voltage and current supply Four operational modes Low standby current consumpt ion in Stop and Sleep modes Built-in low speed 125 kbps fault tolerant CAN physical interface. External high voltage wake-up input, associated with HS1 VBAT switch 1 5 0 mA output current capability for HS1 VBAT switch allowing drive of external switches pull-up resistors or relays Pb-Free Packaging Designated by Suffix Code EG Figure 1. 33889 Simplified Application Diagram
ORDERING INFORMATION
Range (TA) Package MC33889BDW/R2 -40°C to 125°C 28 SOICW MCZ33889BEG/R2 MC33889DDW/R2 *MCZ33889DEG/R2 DW SUFFIX EG SUFFIX (PB-FREE) PLASTIC PACKAGE 98ASB42345B 28-PIN SOICW Local Module Supply Safe Circuits 33889 V MOSI SCLK MISO SPI CS Wake-Up Inputs 5.0 V MCU VPWR CAN Bus Twisted Pair HS1 WDOG VDD1 INT RST MOSI SCLK MISO TXD RXD GND VSUP V2CTRL CANH CANL RTH RTL CS
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Table 1. Device Variations Between the 33889D and 33889B Versions (1)
- This datasheet uses the term 33889 in t he inclusive sense, referring to both the D version (33889D) and the B version (33689B).
- The 33889D and 33889B versions are nearly identical. However, where variations in characteristic occur, these items will be separated
Analog Integrated Circuit Device Data Freescale Semiconductor 3 33889 INTERNAL BLOCK DIAGRAM INTERNAL BLOCK DIAGRAM CAN H CAN L RTH RTL TX RX Oscillator Mode Control HS1 Control Fault Tolerant CAN Transceiver Programmable Wake-Up Inputs SPI Interface Interrupt Watchdog Reset Dual Voltage Regulator VSUP Voltage Monitor VDD1 Voltage Monitor VDD1 INT WDOG VSUP HS1 CS MOSI MISO SCLK GND VSUP RST V2CTRL
33889 Internal Block Diagram
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Figure 2. 33889 Pin Connections Table 2. Pin Definitions A functional description of each pin can be found in the Functional pin description section page 24.
1 RX Output Receiver Data CAN bus receive data output pin
2 TX Input Transmitter Data CAN bus receive data input pin
3 VDD1 Power
4 RST Output Reset This is the device reset output pin whose main function is to reset the
5 INT Output Interrupt This output is asserted LOW when an enabled interrupt condition
frame to provide a 33889-to-PCB thermal path.
11 VSUP Power
Voltage Supply Supply input pin. 12 HS1 Output High-Side Output Output of the internal high-side switch. 13 - 14 L0, L1 Input Level 0 - 1 Inputs Inputs from external switches or from logic circuitry. 16 RTH Output RTH Pin for connection of the bus termination resistor to CANH. 17 RTL Output RTL Pin for connection of the bus termination resistor to CANL. 18 CANH Output CAN High CAN high output pin. 19 CANL Output CAN Low CAN low output pin. 24 SCLK Input System Clock Clock input pin for the Serial Peripheral Interface (SPI).
is in the high impedance state. 26 MOSI Input Master Out/Slave In SPI data received by the 33889.
28 WDOG Output Watchdog The WDOG output pin is asserted LOW if the software watchdog is not
Table 2. Pin Definitions (continued) A functional description of each pin can be found in the Functional pin description section page 24.
Analog Integrated Circuit Device Data
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ELECTRICAL CHARACTERISTICS
Table 3. Maximum Ratings permanent damage to the device. external component per Figure 3.
Analog Integrated Circuit Device Data Freescale Semiconductor 7 33889 ESD voltage (HBM 100 pF, 1.5 k) (3) CANL, CANH, HS1, L0, L1 RTH, RTL All other pins VESDH ±4.0 ±3.0 ±2.0 kV ESD voltage (Machine Model) All pins, MC33889B (3) (4) VESD-MM ±200 V ESD voltage (CDM) All pins, MC33889D (4) Pins 1,14,15, & 28 All other pins VESD-CDM 750 500 V RTH, RTL Termination Resistance RT 500 to 16000 ohms THERMAL RATINGS Junction Temperature TJ -40 to 150 °C Storage Temperature TS -55 to 165 °C Ambient Temperature (for info only) TA -40 to 125 °C Thermal resistance junction to gnd pin (5) RTHJ/P 20 °C/W Notes: 3. Testing done in accordance with the Human Body Model (C ZAP=100 pF, RZAP=1500 ), Machine Model (CZAP=200 pF, RZAP=0 ). 4. ESD machine model (MM) is for MC33889B only. MM is now replaced by CDM (Charged Discharged model). Figure 3. Transient test pulse for L0 and L1 inputs Table 3. Maximum Ratings (continued) permanent damage to the device. Note: Waveform in accordance to ISO7637 part1, test pulses 1, 2, 3a and 3b.
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STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 4. Static Electrical Characteristics . values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
- V DD1 > 4.0 V, reset high, if RSTTH-2 selected and IOUT VDD1 reduced, logic pin high level reduced, device is functional.
- Current measured at V SUP pin.
- Device is fully functional. Al l modes available and operating, Watchdog, HS1 turn ON turn OFF, CAN cell operating, L0 and L1 inputs
operating, SPI read write operation. Over temperature may occur.
- Measured in worst case condition with 5.0 V at V2 pin (V2 pin tied to VDD1).
- Oscillator running means Forced Wake-U p or Cyclic Sense or Software Watchdog timer activated. Software Watchdog is
available in stop mode only.
- V DD1 is ON with 2.0 mA typical output current capability.
Analog Integrated Circuit Device Data Freescale Semiconductor 9 33889 STATIC ELECTRICAL CHARACTERISTICS Supply Fail Flag internal threshold VTHRESH 1.5 3.0 4.0 V Supply Fail Flag hysteresis (12) VDETHYST - 1.0 - V Battery fall early warning threshold In normal & standby mode BFEW 5.8 6.1 6.4 V Battery fall early warning hysteresis In normal & standby mode (12) BFEWH 0.1 0.2 0.3 V OUTPUT PIN (VDD1) (13) VDD1 Output Voltage IDD1 from 2.0 to 200mA
5.5 V < VSUP < 27 V
4.5 V < VSUP < 5.5 V VDD1OUT 4.9 4.0 5.0 5.1 V Drop Voltage VSUP > VDDOUT IDD1 = 200 mA VDD1DROP - 0.2 0.5 V Drop Voltage VSUP > VDDOUT, limited output current IDD1 = 50 mA
4.5 V < VSUP < 27 V
VDD1DP2 - 0.1 0.25 V IDD1 Output Current Internally limited IDD1 200 270 350 mA VDD1 Output Voltage in stop mode Iout < 2.0 mA VDDSTOP 4.75 5.00 5.25 V IDD1 stop output current to wake-up SBC Default value after reset. (14) IDD1S-WU1 2.0 3.5 6.0 mA IDD1 stop output current to wake-up SBC (14) IDD1S-WU2 10 14 18 mA IDD1 over current wake deglitcher (with IDD1S-WU1 selected) (12) IDD1-DGIT11 40 55 75 µs IDD1 over current wake deglitcher (with IDD1S-WU2 selected) (12) IDD1-DGIT2 - 150 - µs Thermal Shutdown Normal or standby mode TSD 160 - 190 °C Over temperature pre warning VDDTEMP bit set TPW 130 - 160 °C Temperature Threshold difference TSD-TPW 20 - 40 °C Notes 12. Guaranteed by design 13. I DD1 is the total regulator output current. VDD specification with external capacitor C ≥ 22µF and ESR < 1O ohm. 14. Selectable by SPI Table 4. Static Electrical Characteristics (continued). values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
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STATIC ELECTRICAL CHARACTERISTICS Reset threshold 1 Default value after reset. (15) VRST-TH1 4.5 4.6 4.7 V Reset threshold 2 (15) VRST-TH2 4.1 4.2 4.3 V Reset duration RESET-DUR 0.85 1.0 2.0 ms VDD1 range for Reset Active VDD 1.0 - - V Reset Delay Time Measured at 50% of reset signal. (16) tD 5.0 - 20 µs Line Regulation
9.0 V < VSUP < 18, IDD = 10 mA
LR1 - 5.0 25 mV Line Regulation
5.5 V < VSUP < 27 V, IDD = 10 mA
1 mA < IIDD < 200 mA LD - 25 75 mV Thermal stability VSUP = 13.5 V, I = 100 mA THERMS - 5.0 - mV V2 REGULATOR (V2) (17) V2 Output Voltage I2 from 2.0 to 200 mA V2 0.99 1.0 1.01 VDD1 I2 output current (for information only) Depending on the external ballast transistor I2 200 - - mA V2 CTRL sink current capability I2CTRL 10 - - mA V2LOW flag threshold V2LTH 3.75 4.0 4.25 V Internal V2 Supply Current (CAN and SBC in Normal Mode). TX = 5.0 V, CAN in Recessive State IV2RS 3.8 5.6 6.8 mA Internal V2 Supply Current (CAN and SBC in Normal Mode). TX = 0.0 V, No Load, CAN in Dominant State IV2DS 4.0 5.8 7.0 mA Internal V2 Supply Current (CAN in Receive Only Mode, SBC in Normal mode). VSUP = 12 V IV2R 80 120 µA Internal V2 Supply Current (CAN in Bus TermVbat mode, SBC in normal mode), V SUP = 12 V IV2BT 35 60 µA Notes 15. Selectable by SPI 16. Guaranteed by design 17. V2 TRACKING VOLTAGE REGULATOR - V2 specification with external capacitor - option 1: C ≥ 22 µF and ESR < 10 ohm. Using a resistor of 2 kohm or less between the base and emitter of the external PNP is recommended. - option2: 1.0 µF < C < 22 µF and ESR < 10 ohm. In this case depending on the ballast transistor gain an additional resistor and capacitor network between emitter and base of PNP ballast transistor might be required. Refer to Freescale application information or contact your local technical support. - option 3: 10uF < C < 22uF ESR > 0.2 ohms: a resistor of 2 kohm or less is required between the base and emitter of the external PNP. values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Analog Integrated Circuit Device Data Freescale Semiconductor 11 33889 STATIC ELECTRICAL CHARACTERISTICS LOGIC OUTPUT PINS (MISO) Low Level Output Voltage IOUT = 1.5 mA VOL - - 1.0 V High Level Output Voltage IOUT = -250 µA VOH VDD1-0.9 - - V Tri-state MISO Leakage Current
0.0 V < Vmiso < VDD
IHZ -2.0 - +2.0 µA LOGIC INPUT PINS (MOSI, SCLK, CS) High Level Input Voltage VIH 0.7VDD1 - VDD1+0.3V Low Level Input Voltage VIL -0.3 - 0.3 VDD1 V Input Current on CS VI = 4.0 V VI = 1.0 V IIH IIL -100 - -20 µA Low Level Input Current CS VI = 1.0 V IIL -100 - -20 µA MOSI, SCLK Input Current 0.0 < VIN < VDD IIN -10 - 10 µA RESET PIN (RST) High Level Output current 0.0 < Vout < 0.7 VDD IOH -350 -250 -150 µA Low Level Output Voltage (I0 = 1.5 mA) 5.5 v < VSUP < 27 V
1.0 V < VDD1
0.0 0.0 0.9 0.9 V Reset pull down current IPDW 2.3 - 5.0 mA WATCHDOG PIN (WDOG) Low Level Output Voltage (I0 = 1.5 mA) VOL 0.0 - 0.9 V High Level Output Voltage (I0 = -250 µA) VOH VDD1 -0.9 - VDD1 V INTERRUPT PIN (INT) Low Level Output Voltage (I0 = 1.5 mA) VOL 0.0 - 0.9 V High Level Output Voltage (I0 = -250 µA) VOH VDD1 -0.9 - VDD1 V HIGH-SIDE OUTPUT PIN (HS1) RDSON at Tj = 25°C, and IOUT -150 mA VSUP>9V RDSON25 - - 2.5 Ohms values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
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STATIC ELECTRICAL CHARACTERISTICS RDSON at Tj = 125°C, and IOUT -150 mA VSUP > 9.0 V RDSON125 - - 5.0 Ohms RDSON at Tj = 125°C, and IOUT -120 mA 5.5 V < VSUP < 9.0 V RDON125-2 - 4.0 5.5 Ohms Output current limitation ILIM 160 - 500 mA Over temperature Shutdown OVT 155 - 190 °C Leakage current ILEAK - - 10 µA Output Clamp Voltage at IOUT = -1.0 mA (18) no inductive load drive capability VCL -1.5 - -0.3 V INPUT PINS (L0 AND L1) L0 Negative Switching Threshold 5.5 V < VSUP < 6.0 V
6.0 V < VSUP < 18 V
18 V < VSUP < 27 V
1.7 2.0 2.0 2.0 2.4 2.5 3.0 3.0 3.1 V L0 Positive Switching Threshold 5.5 V < VSUP < 6.0 V 2.2 2.5 2.5 2.75 3.4 3.5 4.0 4.0 4.1 V L1 Negative Switching Threshold 5.5 V < VSUP < 6.0 V 2.0 2.5 2.7 2.5 3.0 3.2 3.0 3.7 3.8 V L1 Positive Switching Threshold 5.5 V < VSUP < 6.0 V
6.0 V < VSUP < 18V
2.7 3.0 3.5 3.3 4.0 4.2 3.8 4.7 4.8 V Hysteresis VHYST 0.6 1.0 1.3 V Input current -0.2 V < VIN < 40 V IIN -10 - 10 µA CAN MODULE SPECIFICATION (TX, RX, CANH, CANL, RTH, AND RTL) DC Voltage On Pins TX, RX VLOGIC -0.3 VDD1 + 0.3 V DC voltage at V2 (V2INT) V2INT 0.0 5.25 V DC Voltage On Pins CANH, CANL VBUS -20 +27 V Notes 18. Refer to HS1 negative maximum rating voltage limitation of -0.2V. values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Analog Integrated Circuit Device Data Freescale Semiconductor 13 33889 STATIC ELECTRICAL CHARACTERISTICS Transient Voltage At Pins CANH, CANL 0.0 < V2-INT < 5.5 V; VSUP ≥ 0.0; T < 500 ms VCANH/VCANL -40 40 V Transient Voltage On Pins CANH, CANL (Coupled Through 1.0 nF Capacitor) VTR -150 100 V Detection Threshold For Short-circuit To Battery Voltage (Term VBAT Mode) MC33889B VCANH VSUP/2+3 VSUP/2+5 V Detection Threshold For Short-circuit To Battery Voltage (Term VBAT Mode) MC33889D VCANH VSUP/2+3 VSUP/ 2+4.55 V DC Voltage On Pins RTH, RTL VRTL, VRTH -0.3 +27 V Transient Voltage At Pins RTH, RTL 0.0 < V2-INT < 5.5 V; VSUP ≥ 0.0; T < 500 ms VRTH/VRTL -0.3 40 V TRANSMITTER DATA PIN (TX) High Level Input Voltage VIH 0.7*V2 V2+0.3V V Low Level Input Voltage VIL -0.3 0.3 * V2 V TX High Level Input Current (VI = 4.0 V) ITXH -100 -50 -25 µA TX Low Level Input Current (VI = 1.0 V) ITXL -100 -50 -25 µA RECEIVE DATA PIN (RX) High Level Output Voltage RX (I0 = -250 µA) VOH V2-INT - 0.9 V2-INT V Low Level Output Voltage (I0 = 1.5 mA) VOL 0.0 0.9 V CAN HIGH AND CAN LOW PINS (CANH, CANL) Differential Receiver, Recessive To Dominant Threshold (By Definition, VDIFF = VCANH-VCANL) For 33889D For 33889B VDIFF1 -3.5 -3.2 -3.0 -2.6 -2.5 -2.1 V Differential Receiver, Dominant To Recessive Threshold (Bus Failures 1, 2, 5) For 33889D For 33889B VDIFF2 -3.5 -3.2 -3.0 -2.6 -2.5 -2.1 V CANH Recessive Output Voltage TX = 5.0 V; R(RTH) < 4.0 k VCANH 0.2 V CANL Recessive Output Voltage TX = 5.0 V; R(RTL) < 4.0 k VCANL V2-INT - 0.2 V values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
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STATIC ELECTRICAL CHARACTERISTICS CANH Output Voltage, Dominant TX = 0.0 V; ICANH = -40 mA; Normal Operating Mode (19) VCANH V2 - 1.4 V CANL Output Voltage, Dominant TX = 0.0 V; ICANL = 40 mA; Normal Operating Mode (19) VCANL 1.4 V CANH Output Current (VCANH = 0; TX = 0.0) For 33889D For 33889B ICANH 100 130 110 mA CANL Output Current (VCANL = 14 V; TX = 0.0) For 33889D For 33889B ICANL 140 170 135 mA Detection Threshold For Short-circuit To Battery Voltage (Normal Mode) VCANH, VCANL 7.3 7.9 8.9 V Detection Threshold For Short-circuit To Battery Voltage (Term VBAT Mode), MC33889B VcanH Vsup/2+3 Vsup/2+5 V Detection Threshold For Short-circuit To Battery Voltage (Term VBAT Mode), MC33889D VcanH Vsup/2+3 Vsup/ 2+4.55 V CANH Output Current (Term VBAT Mode; VCANH = 12 V, Failure3) ICANH 5.0 10 µA CANL Output Current (Term VBAT Mode; VCANL = 0.0 V; VBAT = 12 V, Failure 4) ICANL 0.0 2.0 µA CANL Wake-Up Voltage Threshold VWAKE,L 2.5 3.0 3.9 V CANH Wake-Up Voltage Threshold VWAKE,H 1.2 2.0 2.7 V Wake-Up Threshold Difference (Hysteresis) VWAKEL- VWAKEH 0.2 V CANH Single Ended Receiver Threshold (Failures 4, 6, 7) VSE, CANH 1.5 1.85 2.15 V CANL Single Ended Receiver Threshold (Failures 3, 8) VSE, CANL 2.8 3.05 3.4 V CANL Pull Up Current (Normal Mode) ICANL,PU 45 75 90 µA CANH Pull Down Current (Normal Mode) ICANH,PD 45 75 90 µA Receiver Differential Input Impedance CANH / CANL RDIFF 100 300 kohm Differential Receiver Common Mode Voltage Range (20) VCOM -10 10 V CANH To Ground Capacitance CCANH 50 pF CANL To Ground Capacitance CCANL 50 pF CCANL to CCANH Capacitor Difference DCCAN 10 pF CAN Driver Thermal Shutdown tCSD 150 160 °C Notes 19. For MC33889B, after 128 pulses on TX and no bus failure. 20. Guaranteed by design values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Analog Integrated Circuit Device Data Freescale Semiconductor 15 33889 STATIC ELECTRICAL CHARACTERISTICS BUS TERMINATION PINS (RTH, RTL) RTL to V2 Switch On Resistance (IOUT < -10 mA; Normal Operating Mode) RRTL 10 30 90 ohms RTL to BAT Switch Series Resistance (term VBAT Mode) RRTL 8.0 12.5 20 kohm RTH To Ground Switch On Resistance (IOUT < 10 mA; Normal Operating Mode) RRTH 10 30 90 ohm values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
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DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 5. Dynamic Electrical Characteristics noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Analog Integrated Circuit Device Data Freescale Semiconductor 17 33889 DYNAMIC ELECTRICAL CHARACTERISTICS Internal low power oscillator frequency Sleep and Stop modes (22) OSC-F2 - 100 - kHz Watchdog period 1 Normal and standby modes WD1 8.58 9.75 10.92 ms Watchdog period 2 Normal and standby modes WD2 39.6 45 50.4 ms Watchdog period 3 Normal and standby modes WD3 88 100 112 ms Watchdog period 4 Normal and standby modes WD4 308 350 392 ms Watchdog period accuracy Normal and standby modes F1ACC -12 - 12 % Normal request mode timeout Normal request mode NRTOUT 308 350 392 ms Watchdog period 1 - stop Stop mode WD1STOP 6.82 9.75 12.7 ms Watchdog period 2- stop Stop mode WD2STOP 31.5 45 58.5 ms Watchdog period 3 - stop Stop mode WD3STOP 70 100 130 ms Watchdog period 4 - stop Stop mode WD4STOP 245 350 455 ms Stop mode watchdog period accuracy Stop mode F2ACC -30 - 30 % Cyclic sense/FWU timing 1 Sleep and stop modes CSFWU1 3.22 4.6 5.98 ms Cyclic sense/FWU timing 2 Sleep and stop modes CSFWU2 6.47 9.25 12 ms Notes 22. Guaranteed by design Table 5. Dynamic Electrical Characteristics (continued) noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
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DYNAMIC ELECTRICAL CHARACTERISTICS Cyclic sense/FWU timing 3 Sleep and stop modes CSFWU3 12.9 18.5 24 ms Cyclic sense/FWU timing 4 Sleep and stop modes CSFWU4 25.9 37 48.1 ms Cyclic sense/FWU timing 5 Sleep and stop modes CSFWU5 51.8 74 96.2 ms Cyclic sense/FWU timing 6 Sleep and stop modes CSFWU6 66.8 95.5 124 ms Cyclic sense/FWU timing 7 Sleep and stop modes CSFWU7 134 191 248 ms Cyclic sense/FWU timing 8 Sleep and stop modes CSFWU8 271 388 504 ms Cyclic sense On time in sleep and stop modes tON 200 300 400 µs Cyclic sense/FWU timing accuracy in sleep and stop mode tACC -30 - +30 % Delay between SPI command and HS1 turn on (23) Normal or standby mode, VSUP > 9.0 V tS-HSON - - 22 µs Delay between SPI command and HS1 turn off (23) Normal or standby mode, VSUP > 9.0 V tS-HSOFF - - 22 µs Delay between SPI and V2 turn on (23) Standby mode tS-V2ON 9.0 - 25 µs Delay between SPI and V2 turn off (23) Normal modes tS-V2OFF 9.0 - 25 µs Delay between Normal Request and Normal mode, after W/D trigger command Normal request mode tS-NR2N 15 35 70 µs Notes 23. State Machine Timing - Delay starts at rising edge of CS (end of SPI command) and start of Turn on or Turn off of HS1 or V2. noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Analog Integrated Circuit Device Data Freescale Semiconductor 19 33889 DYNAMIC ELECTRICAL CHARACTERISTICS Delay between SPI and CAN normal mode SBC Normal mode (24) tS-CANN - - 10 µs Delay between SPI and CAN sleep mode SBC Normal mode (24) tS-CANS - - 10 µs Delay between CS wake-up (CS low to high) and SBC normal request mode (VDD1 on & reset high) SBC in stop mode tW-CS 15 40 90 µs Delay between CS wake-up (CS low to high) and first accepted SPI command SBC in stop mode tW-SPI 90 - - µs Delay between INT pulse and 1st SPI command accepted In stop mode after wake-up tS-1STSPI 20 - - µs Delay between two SPI messages addressing the same register For 33889D only t2SPI 25 - - µs INPUT PINS (L0 AND L1) Wake-up Filter Time (enable/disable option on L0 input) (If filter enabled) tWUF 8.0 20 38 µs PIN AC CHARACTERISTICS (CANH, CANL, RX, TX) CANL and CANH Slew Rates (25% to 75% CAN signal). (25) Recessive to Dominant state Dominant to Recessive state tSLDR 2.0 2.0 8.0 9.0 V/µs Propagation Delay TX to RX Low. -40°C < T ≤ 25°C. (26) TX to RX Low. 25°C < T < 125°C. (26) tONRX 1.2 1.1 1.6 1.8 µs Propagation Delay TX to RX High. (26) tOFFRX 1.8 2.2 µs Notes 24. Guaranteed by design 25. Dominant to recessive slew rate is dependant upon the bus load characteristics. 26. AC Characteristics measur ed according to schematic Figure 4 noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Analog Integrated Circuit Device Data
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DYNAMIC ELECTRICAL CHARACTERISTICS Loop time Tx to Rx, no bus failure, MC33889D only ((27), Figure 5) (ISO ICT test series 10) Tx high to low transition (dominant edge) Tx low to high transition (recessive edge) tLOOPRD 1.15 1.45 1.5 1.5 µs Loop time Tx to Rx, with bus failure, MC33889D only ((27), Figure 6) (ISO ICT test series 10) Tx high to low transition (dominant edge) Tx low to high transition (recessive edge) tLOOPRD-F 1.9 1.9 µs Loop time Tx to Rx, with bus failure and +-1.5V gnd shift, 5 nodes network, MC33889D,((28), Figure 7, ISO ICT tests series 11) tLOOPRD/DR-F+GS 3.6 µs Min. Dominant Time For Wake-up On CANL or CANH (Term Vbat; VSUP = 12V) Guaranteed by design. MC33889B MC33889D tWAKE 8.0 16 30 µs Failure 3 Detection Time (Normal Mode) tDF3 10 30 80 µs Failure 3 Recovery Time (Normal Mode) tDR3 160 µs Failure 6 Detection Time (Normal Mode) tDF6 50 200 500 µs Failure 6 Recovery Time (Normal Mode) tDR6 150 200 1000 µs Failure 4, 7 Detection Time (Normal Mode) tDF47 0.75 1.5 4.0 ms Failure 4, 7 Recovery Time (Normal Mode) tDR47 10 30 60 µs Failure 3a, 8 Detection Time (Normal Mode) tDF8 0.75 1.7 4.0 ms Failure 3a, 8 Recovery Time (Normal Mode) tTDR8 0.75 1.5 4.0 ms Failure 4, 7 Detection Time, (Term VBAT; VSUP = 12 V) tDR47 0.8 1.2 8.0 ms Failure 4, 7 Recovery Time (Term VBAT; VSUP = 12 V) tDR47 1.92 ms Failure 3 Detection Time (Term VBAT; VSUP = 12 V) tDR3 3.84 ms Failure 3 Recovery Time (Term VBAT; VSUP = 12 V) tDR3 1.92 ms Failure 3a, 8Detection Time (Term VBAT; VSUP = 12 V) tDR8 2.3 ms Failure 3a, 8 Recovery Time (Term VBAT; VSUP = 12 V) tDR8 1.2 ms Notes 27. AC characteristic according to ISO11898-3, tested per figure 5 and 6. Guaranteed by design, room temperature only. 28. AC characteristic according to ISO11898-3, tested per figure 7. Max reported is the typical measurement under the worst condition (gnd shift, dominant/recessive edge, at source or destination node. ref to ISO test specification). Guaranteed by design, room temperature only. noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Analog Integrated Circuit Device Data
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DYNAMIC ELECTRICAL CHARACTERISTICS Figure 7. Test Set Up for Propagation Delay with GND Shift in a 5 Node Configuration
Analog Integrated Circuit Device Data
24 Freescale Semiconductor
The MC33889 is an integrated circuit dedicated to automotive applications. It includes the following functions: One full protected voltage regulator with 200 mA total output current capability. Driver for external path transistor for V2 regulator function. Reset, programmable watchdog function Four operational modes Wake-up capabilities: Forced wake-up, cyclic sense and wake-up inputs, CAN and the SPI Can low speed fault tolerant physical interface. FUNCTIONAL PIN DESCRIPTION RECEIVE AND TRANSMIT DATA (RX AND TX) The RX and TX pins (receive data and transmit data pins, respectively) are connected to a microcontrollers CAN protocol handler. TX is an input and controls the CANH and CANL line state (dominant when TX is LOW, recessive when TX is HIGH). RX is an output and reports the bus state (RX LOW when CAN bus is dominant, HIGH when CAN bus is recessive). VOLTAGE REGULATOR ONE (VDD1) The VDD1 pin is the output pin of the 5.0 V internal regulator. It can deliver up to 200 mA. This output is protected against overcurrent and overtemperature. It includes an overtemperature pre-warning flag, which is set when the internal regulator temperature exceeds 130°C typical. When the temperature exceeds the overtemperature shutdown (170°C typical), the regulator is turned off. VDD1 includes an undervoltage reset circuitry, which sets the RST pin LOW when VDD is below the undervoltage reset threshold. RESET (RST) The Reset pin RST is an output that is set LOW when the device is in reset mode. The RST pin is set HIGH when the device is not in reset mode. RST includes an internal pullup current source. When RST is LOW, the sink current capability is limited, allowing RST to be shorted to 5.0 V for software debug or software download purposes. INTERRUPT (INT) The Interrupt pin INT is an output that is set LOW when an interrupt occurs. INT is enabled using the Interrupt Register (INTR). When an interrupt occurs, INT stays LOW until the interrupt source is cleared. INT output also reports a wake-up event by a 10 sec. typical pulse when the device is in Stop mode. GROUND (GND) This pin is the ground of the integrated circuit. V2CTRL (V2CTRL) The V2CTRL pin is the output drive pin for the V2 regulator connected to the external series pass transistor. VOLTAGE SUPPLY (VSUP) The VSUP pin is the battery supply input of the device. HIGH-SIDE OUTPUT 1 (HS1) The HS pin is the internal high-side driver output. It is internally protected against overcurrent and overtemperature. LEVEL 0-1 INPUTS (L0: L1) The L0: L1 pins can be connected to contact switches or the output of other ICs for external inputs. The input states can be read by the SPI. These inputs can be used as wake- up events for the SBC when operating in the Sleep or Stop mode. VOLTAGE REGULATOR TWO (V2) The V2 pin is the input sense for the V2 regulator. It is connected to the external series pass transistor. V2 is also the 5.0 V supply of the internal CAN interface. It is possible to connect V2 to an external 5.0 V regulator or to the VDD output when no external series pass transistor is used. In this case, the V2CTRL pin must be left open. RTH (RTH) Pin for the connection of the bus termination resistor to CANH RTL (RTL) Pin for the connection of the bus termination resistor to CANL CAN HIGH AND CAN LOW OUTPUTS (CANH AND CANL) The CAN High and CAN Low pins are the interfaces to the CAN bus lines. They are controlled by TXD input level, and the state of CANH and CANL is reported through RXD output. SYSTEM CLOCK (SCLK) SCLK is the Serial Data Clock input pin of the serial peripheral interface.
Analog Integrated Circuit Device Data Freescale Semiconductor 25 33889 FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION MASTER IN/SLAVE OUT (MISO MISO is the Master In Slave Out pin of the serial peripheral interface. Data is sent from the SBC to the microcontroller through the MISO pin. MASTER OUT/SLAVE IN (MOSI) MOSI is the Master Out Slave In pin of the serial peripheral interface. Control data from a microcontroller is received through this pin. CHIP SELECT (CS) CS is the Chip Select pin of the serial peripheral interface. When this pin is LOW, the SPI port of the device is selected. WATCH DOG (WDOG) The Watchdog output pin is asserted LOW to flag that the software watchdog has not been properly triggered. FUNCTIONAL INTERNAL BLOCK DESCRIPTION DEVICE SUPPLY The device is supplied from the battery line through the VSUP pin. An external diode is required to protect against negative transients and reverse battery. It can operate from 4.5 V and under the jump start condition at 27 V DC. This pin sustains standard automotive voltage conditions such as load dump at 40 V. When VSUP falls below 3.0 V typical, the MC33889 detects it and stores the information in the SPI register, in a bit called BATFAIL. This detection is available in all operation modes. VDD1 VOLTAGE REGULATOR VDD1 Regulator is a 5.0 V output voltage with total current capability of 200 mA. It includes a voltage monitoring circuitry associated with a reset function. The VDD1 regulator is fully protected against overcurrent, short-circuit and has overtemperature detection warning flags and shutdown with hysteresis. V2 REGULATOR V2 Regulator circuitry is designed to drive an external path transistor in order to increase output current flexibility. Two pins are used: V2 and V2CTRL. Output voltage is 5.0 V and is realized by a tracking function of the VDD1 regulator. A recommended ballast transistor is the MJD32C. Other transistors might be used, however depending upon the PNP gain, an external resistor capacitor network might be connected between the emitter and base of the PNP. The use of external ballast is optional (refer to simplified typical application). The state of V2 is reported into the IOR register (if V2 is below 4.5 V typical, or in cases of overload or short- circuit). HS1 VBAT SWITCH OUTPUT HS1 output is a 2.0 ohm typical switch from the VSUP pin. It allows the supply of external switches and their associated pullup or pull-down circuitry, for example, in conjunction with the wake-up input pins. Output current is limited to 200 mA and HS1 is protected against short-circuit and has an over temperature shutdown (reported into the IOR register). The HS1 output is controlled from the internal register and the SPI. It can be activated at regular intervals in sleep mode thanks to an internal timer. It can also be permanently turned on in normal or stand-by modes to drive external loads, such as relays or supply peripheral components. In case of inductive load drive, external clamp circuitry must be added. SPI The complete device control as well as the status report is done through an 8 bit SPI interface. Refer to the SPI paragraph. CAN The device incorporates a low speed fault tolerant CAN physical interface. The speed rate is up to 125 kBauds. The state of the CAN interface is programmable through the SPI. Reference the CAN transceiver description on page 30. PACKAGE AND THERMAL CONSIDERATION The device is proposed in a standard surface mount SO28 package. In order to improve the thermal performances of the SO28 package, 8 pins are internally connected to the lead frame and are used for heat transfer to the printed circuit board.
Analog Integrated Circuit Device Data
26 Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES INTRODUCTION The device has four modes of operation, normal, stand-by, sleep and stop modes. All modes are controlled by the SPI. An additional temporary mode called normal request mode is automatically accessed by the device (refer to state machine) after wake-up events. Special mode and configurations are possible for software application debug and flash memory programming. NORMAL MODE In this mode both regulators are ON, and this corresponds to the normal application operation. All functions are available in this mode (watchdog, wake-up input reading through the SPI, HS1 activation, and CAN communication). The software watchdog is running and must be periodically cleared through the SPI. STANDBY MODE Only the Regulator 1 is ON. Regulator 2 is turned OFF by disabling the V2CTRL pin. The CAN cell is not available, as powered from V2. Other functions are available: wake-up input reading through the SPI and HS1 activation. The watchdog is running. SLEEP MODE Regulators 1 and 2 are OFF. In this mode, the MCU is not powered. The device can be awakened internally by cyclic sense via the wake-up input pins and HS1 output, from the forced wake function, the CAN physical interface, and the SPI CS pin). STOP MODE Regulator 2 is turned OFF by disabling the V2CTRL pin. Regulator 1 is activated in a special low power mode which allows it to deliver 2.0 mA. The objective is to supply the MCU of the application while it is turned into a power saving condition (i.e stop or wait mode). Stop mode is entered through the SPI. Stop mode is dedicated to powering the Microcontroller when it is in low power mode (stop, pseudo stop, wait etc.). In these modes, the MCU supply current is less than 1.0 mA. The MCU can restart its software application very quickly without the complete power up and reset sequence. When the application is in stop mode (both MCU and SBC), the application can wake-up from the SBC side (ex cyclic sense, forced wake-up, CAN message, wake-up inputs) or the MCU side (key wake-up etc.). When Stop mode is selected by the SPI, stop mode becomes active 20 µs after end of the SPI message. The go to stop instruction must be the last instruction executed by the MCU before going to low power mode. In Stop mode, the Software watchdog can be running or not running depending on the selection by the SPI. Refer to the SPI description, RCR register bit WDSTOP. If the W/D is enabled, the SBC must wake-up before the W/D time has expired, otherwise a reset is generated. In stop mode, the SBC wake-up capability is identical as in sleep mode. STOP MODE: WAKE-UP FROM SBC SIDE, INT PIN ACTIVATION When an application is in stop mode, it can wake-up from the SBC side. When a wake-up is detected by the SBC (CAN, Wake-up input, forced wake-up, etc.), the SBC turns itself into Normal request mode and activates the VDD1 main regulator. When the main regulator is fully active, then the wake-up is signalled to the MCU through the INT pin. The INT pin is pulled low for 10 µs and then returns high. Wake-up events can be read through the SPI registers. STOP MODE: WAKE-UP FROM MCU SIDE When the application is in stop mode, the wake-up event may come to the MCU. In this case, the MCU has to signal to the SBC that it has to go into Normal mode in order for the VDD1 regulator to be able to deliver full current capability. This is done by a low to high transition of the CS pin. The CS pin low to high activation has to be done as soon as possible after the MCU. The SBC generates a pulse at the INT pin. Alternatively the L0 and L1 inputs can also be used as wake- up from the Stop mode. STOP MODE CURRENT MONITORING If the current in Stop mode exceeds the IDD1S-WU threshold, the SBC jumps into Normal request mode, activates the VDD1 main regulator, and generates an interrupt to the MCU. This interrupt is not maskable and a not bit are set into the INT register. SOFTWARE WATCHDOG IN STOP MODE If the watchdog is enabled (register MCR, bit WDSTOP set), the MCU has to wake-up independently of the SBC before the end of the SBC watchdog time. In order to do this, the MCU has to signal the wake-up to the SBC through the SPI wake-up ( CS pin low to high transition to activated the SPI wake-up). Then the SBC wakes up and jumps into the normal request mode. The MCU has to configure the SBC to go to either into normal or standby mode. The MCU can then choose to go back into stop mode. If no MCU wake-up occurs within the watchdog timing, the SBC will activate the reset pin and jump into the normal request mode. The MCU can then be initialized.
Analog Integrated Circuit Device Data Freescale Semiconductor 27 33889 FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES NORMAL REQUEST MODE This is a temporary mode automatically accessed by the device after a wake-up event from sleep or stop mode, or after device power up. In this mode, the VDD1 regulator is ON, V2 is off, and the reset pin is high. As soon as the device enters the normal request mode, an internal 350 ms timer is started. During these 350 ms, the microcontroller of the application must address the SBC via the SPI and configure the watchdog register (TIM1 register). This is the condition for the SBC to leave the Normal request Mode and enter the Normal mode, and to set the watchdog timer according to the configuration done during the Normal Request mode. The BATFAIL flag is a bit which is triggered when VSUP falls below 3.0 V. This bit is set into the MCR register. It is reset by the MCR register read. INTERNAL CLOCK This device has an internal clock used to generate all timings (reset, watchdog, cyclic wake-up, filtering time RESET PIN A reset output is available in order to reset the microcontroller. Reset causes are: V DD1 falling out of range: if VDD1 falls below the reset threshold (parameter RST-TH), the reset pin is pulled low until VDD1 returns to the nominal voltage. Power on reset: at device power on or at device wake-up from sleep mode, the reset is maintained low until VDD1 is within its operation range. Watchdog timeout: if the watc hdog is not cleared, the SBC will pull the reset pin low for the duration of the reset duration time (parameter: RESET-DUR). For debug purposes at 25°C, the reset pin can be shorted to 5.0 V. SOFTWARE WATCHDOG (SELECTABLE WINDOW OR TIMEOUT WATCHDOG) The software watchdog is used in the SBC normal and stand-by modes for monitoring the MCU. The watchdog can be either a window or timeout. This is selectable by the SPI (register TIM, bit WDW). Default is the window watchdog. The period of the watchdog is selectable by the SPI from 5.0 to 350 ms (register TIM, bits WDT0 and WDT1). When the window watchdog is selected, the closed window is the first half of the selected period, and the open window is the second half of the period. The watchdog can only be cleared within the open window time. An attempt to clear the watchdog in the closed window will generate a reset. The Watchdog is cleared through the SPI by addressing the TIM register. Refer to table for reset pin operations operation in mode WAKE-UP CAPABILITIES Several wake-up capabilities are available for the device when it is in sleep or stop mode. When a wake-up has occurred, the wake-up event is stored into the WUR or CAN registers. The MCU can then access the wake-up source. The wake-up options are selectable through the SPI while the device is in normal or standby mode, and prior to entering low power mode (sleep or stop mode). WAKE-UP FROM WAKE-UP INPUTS (L0, L1) WITHOUT CYCLIC SENSE The wake-up lines are dedicated to sense external switch states, and when changes occur to wake-up the MCU (In sleep or stop modes). The wake-up pins are able to handle V DC. The internal threshold is 3.0 V typical, and these inputs can be used as an input port expander. The wake-up inputs state can be read through the SPI (register WUR). L0 has a lower threshold than L1 in order to allow a connection and wake-up from a digital output such as a CAN physical interface. CYCLIC SENSE WAKE-UP (CYCLIC SENSE TIMER AND WAKE-UP INPUTS L0, L1) The SBC can wake-up from a state change of one of the wake-up input lines (L0, L1), while the external pullup or pulldown resistor of the switc hes associated to the wake-up input lines are biased with HS1 VSUP switch. The HS1 switch is activated in sleep or stop mode from an internal timer. Cyclic sense and forced wake-up are exclusive. If Cyclic sense is enabled, the forced wake-up can not be enabled. INFO FOR CYCLIC SENSE + DUAL EDGE SELECTION In case the Cyclic sense and Lx both level sensitive conditions are use together, the initial value for Lx inputs are sampled in two cases: 1) When the register LPC[D3 and D0] are set and 2) At cyclic sense event, that is when device is in sleep or stop mode and HS1 is active. The consequence is that when the device wake up by Lx transition, the new value is sampled as default, then when the device is set back into low power again, it will automatically wake up. The user should reset the LPC bits [D3 and D0] to 0 and set them again to the desired value prior to enter sleep or stop mode. FORCED WAKE-UP The SBC can wake-up automatically after a predetermined time spent in sleep or stop mode. Forced wake-up is enabled by setting bit FWU in the LPC register. Cyclic sense and forced wake-up are exclusive. If forced wake-up is enabled, the Cyclic sense can not be enabled.
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At power up the device automatically wakes up. voltage is below the 6.1 V typical. This interrupt is maskable. Stand-by modes. VBAT low state reports in the IOR register. operations. Reset is active at device power up and wake-up. not properly re-activated by the SPI. is properly addressed through the SPI. Figure 10. Reset and WDOG Function Diagram SOFTWARE DEBUG WITH THE SBC. directly to VDD1 by a jumper. The software watchdog can be disabled through the SPI.
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Figure 12. Simplified Block Diagram of the CAN Transceiver of the MC33889 as well as an over temperature shutdown. automatically reenables the associated driver. value should be between 500 and 16000 ohms. voltage between CANH and CANL line is >2.2V (3.6V-1.4V).
Analog Integrated Circuit Device Data Freescale Semiconductor 31 33889 FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES Receiver Function In normal operation (no bus failures), RX is the image of the differential bus voltage. The differential receiver inputs are connected to CANH and CANL. The device incorporates single ended comparators connected to CANH and CANL in order to monitor the bus state as well as detect bus failures. Failures are reported via the SPI. In normal operation when no failure is present, the differential comparator is active. Under a fault condition, one of the two CANH or CANL pins can be become non- operational. The single ended comparator of either CANH or CANL is activated and continues to report a bus state to Rx pin. The device permanently monitors the bus failure and recovery, and as soon as fault disappears, it automatically switches back to differential operation. CAN interface operation Mode The CAN has 3 operation modes: TxRx (Transmit- Receive), Receive Only, and Term-VBAT (Terminated to VBAT). The mode is selected by the SPI. As soon as the MC33889 mode is sleep or stop (selected via MCR register), the CAN interface automatically enters Tem-Vbat mode. Tx Rx mode: In this mode, the CAN drivers and receivers are enabled, and the device is able to send and receive messages. Bus failures are detected and managed, this means that in case of a bus failure, one of the CAN drivers can be disabled, but communication continues via the remaining drivers. Receive Only mode: In this mode, the transmitter path is disabled, so the device does not drive the bus. It maintains CANL and CANH in the recessive state. The receiver function operates normally. TermVbat mode: In this mode, the transmitter and receiver functions are disabled. The CANL pin is connected to VSUP through the RTL resistor and internal pull up resistor of 12.5kOhms. In this mode, the device monitors the bus activity and if a wake up conditions is encountered on the CAN bus, it will wakes up the MC33889. The device will enter into a normal request mode if low power mode was in sleep, or generates an INT. It enters into Normal request mode if low power mode was in stop mode. If the device was in normal or stand by mode, the Rx pin will report a wake up (feature not available on the MC33889B). See Rx pin behavior. Bus Failure Detection General description: The device permanently monitors the bus lines and detects faults in normal and receive only modes. When a fault is detected, the device automatically takes appropriate actions to minimize the system current consumption and to allow communication on the network. Depending on the type of fault, the mode of operation, and the fault detected, the device automatically switches off one or more of the following functions: CANL or CANH line driver, RTL or RTH termination resistors, or internal switches. These actions are detailed in the following table. The device permanently monitors the faults and in case of fault recovery, it automatically switches back to normal operation and reconnects the open functions. Fault detection and recovery circuitry have internal filters and delays timing, detailed in the AC characteristics parameters. The failure list identification and the consequence on the device operation are described in following table. The failure detection, and recovery principle, the transceiver state after a failure detected, timing for failure detection and recovery can be found in the ISO11898-3 standard. The following table is a summary of the failure identifications and of the consequences on the CAN driver and receiver when the CAN is in Tx Rx mode.
Analog Integrated Circuit Device Data
32 Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES Open wire detection operation: Description: The CANH and CANL open wire failures are not described in the ISO document. Open wire is only diagnostic information, as no CAN driver or receiver state will change in case of an open wire condition. In case one of the CAN wires are open, the communication will continue through the remaining wire. In this situation the MC33889 will receive information on one wire only and the consequences are as follows: when the bus is set in dominant: - The differential receiver will toggle - Only one of the single ended receivers CANH or of CANL will toggle The following figure illustrates the CAN signal during normal communication and in the example of a CANH open wire. The single ended receiver is sampled at the differential receiver switching event, in a window of 1µs. Bus failure identification Description Consequence on CAN driver Consequence on Rx pin no failure default operation: CAN H and CANL driver active, RTH and RTL termination switched ON default operation: Report differential receiver output
1 CANH open wire default operation default operation
5 CANH shorted to gnd default operation default operation
8, 3a CANH shorted to Vdd (5V) CANH driver turn OFF. RTH termination switched OFF Rx report CANL single ended receiver 3 CANH shorted to Vbat CANH driver turn OFF. RTH termination switched OFF Rx report CANL single ended receiver
2 CANL open wire default operation default operation
4, 7 CANL shorted to gnd or CANL shorted to CANH CANL driver is OFF. RTL termination switched OFF Rx report CANH single ended receiver 9 CANL shorted to Vdd (5V) CANL driver is ON. RTL termination active default operation 6 CANL shorted to Vbat CANL driver is OFF. RTL termination switched OFF Rx report CANH single ended receiver
Analog Integrated Circuit Device Data
34 Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES In application, with CAN communication, a recovery condition is detected after 4 acknowledge bits are sent by the MC33889B. MC33889D: When detection is complete, the counter is decremented by sampling the dominant pulse (recovery pulse) on S-H (S- L), and incremented (up to 4) by sampling the recessive pulse (detection pulses) on S-H (S-L). It is necessary to get 4 consecutive dominant samples (recovery pulse) to get to zero. When reaching zero, the failure is recovered. In application with real CAN communication, a recovery condition will not be detected by a single acknowledge bit send by MC33889D, but requires a complete CAN message (at least 4 dominant bits) send in dual wire mode, without reception of any bit in single wire mode. Tx permanent dominant detection: In addition to the previous list, the MC33889 detects a permanent low state at the TX input which results in a permanent dominant bus state. If TX is low for more than 0.75-4ms, the bus output driver is disabled. This avoids blocking communication between other nodes of the network. TXD is reported via the SPI (RCR register bit D1: TXFAILURE). Tx permanent dominant recovery is done with TX recessive for more than typ 32us. Rx pin behavior while CAN interface is in TermVbat. The MC33889D is able to signal bus activity on Rx while the CAN interface is in TermVbat and the SBC in normal or standby mode. When the bus is driven into a dominant state by another sending node, each dominant state is reported at Rx by a low level, after a delay of T WAKE. The bus state report is done through the CAN interface wake up comparator on CANL and CANH, and thus operates also in case of bus failure. This is illustrated in the following figure.
Figure 15. Bus State Report of the CAN Interface Wake-Up Comparator on CANL and CANH bits of 8us each results in a 40us bus dominant.
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The following table summarizes the device behavior when a CAN Wake Up event occurs. should be done by software (e.g. several trials). Table 6. Summary of RX Pin Operations for Wake up Signaling
- pulse duration is bus dominant duration minus Twake.
Table 7. 33889 Table of Operations The table below describe the SBC operation modes.
Figure 16. Simplified State Machine Low Not active No Running Term Vbat. The table below describe the SBC operation modes. W/D: Trigger means TIM1 register write operation.
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Figure 17. Behavior at SBC Power Up Figure 18. Transitions to Enter Debug Modes
Figure 19. Simplified State Machine in Debug Mode (1) If stop mode entered, it is entered without watchdog, no matter the WDSTOP bit. (E) debug mode entry point (step 5 of the debug mode entering sequence). (R) represents transitions to reset mode due to Vdd1 low.
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Figure 20. Data Format Description are data send from MCU to SBC or read back from SBC to MCU. During write operation state of MISO has no signification. Following tables describe the SPI register list, and register bit meaning. to be set at the reset value.
Table 8. List of Registers Table 9. MCR Register Table 10. Control bits extended modes, filter at L0 input. Write: HS1 (high-side switch) control in normal and standby mode. TIM $1 0 1 Timing register Write: TIM1, Watchdog timing control, window or Timeout mode. leave debug mode, BATFAIL must be at 0.
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(1): Bit BATFAIL cannot be set by SPI. BATFAIL is set when VSUP falls below 3V. (2): Watchdog ON or OFF depends on the RCR register bit D3. (3): Before entering sleep mode, bit NOSTOP in RCR register must be previously set to 1. Table 11. Status bits Table 12. RCR register
Table 13. Control bits Table 14. CAN register
1 Watchdog runs in stop mode
1 Sleep mode is default low power mode
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Table 15. CAN Transceiver Modes Table 16. CAN transceiver extended modes (CAN with CEXT bit =1 is not recommended) Note1: CEXT Bit should be set at 0. The CAN operation in extended mode is not recommended. Note: if DFIS bit is set to 1, WUR register must be read before going into sleep or stop mode in order to clear the wake-up flag. During read out L0 must be at high level and should stay high when entering sleep or stop.
0 Enable (LO wake threshold selectable by WUR register)
1 Disable (L0 wake-up threshold is low level only, no matter D0 and D1 bits set in WUR register).
Table 17. Status bits CS2 bit at 0 = open failure. CS2 bit at 1 = short failure. (CS3 bit at 0 and (CS1 = 1 or CS2 =1)) = CANH failure. CS3 bit at 1 = CANL failure. CS1 and CS0 bits: short type failure coding (gnd, VDD or VBAT). In case of multiple failures, the last failure is reported.
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Table 18. IOR register. Table 19. Control bits Table 20. Gnd shift selection
0 HS1 switch turn OFF
1 HS1 switch turn ON
0 Gnd shift value is lower than the level selected by the GSLR1 and GSLR2 bit
1 Gnd shift value is higher than the level selected by the GSLR1 and GSLR2 bit
Table 21. Status bits Table 22. WUR Register Table 23. Control bits:.
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Table 24. Status bits Description: This register is split into 2 sub registers, TIM1 and TIM2. TIM1 controls the watchdog timing selection as well as the window or timeout option. TIM1 is selected when bit D3 is 0. TIM2 is used to define the timing for the cyclic sense and forced wake-up function. TIM2 is selected when bit D3 is 1. Table 25. TIM Register. 0 0 0 No wake-up occurred at L0 (sleep or stop mode). 1 1 0 Wake-up occurred at L0 (sleep or stop mode). to xx00 before sleep or stop mode. 0 0 No wake-up occurred at L1 (sleep or stop mode). 1 1 Wake-up occurred at L1 (sleep or stop mode).
Table 26. Watch dog Table 27. jWatchdog operation (window and timeout) Table 28. TIM2 Register
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Table 29. Cyclic Sense Timing
- Enable or disable the sense of the wake-up inputs (LX) at sampling point of the cyclic sense period (LX2HS1 bit).
Table 30. LPC Register
Table 31. INTR register Table 32. Control bits: When the mask bit has been set, INT pin goes low if the appropriate condition occurs.
0 X no
1 X Yes, LX inputs sensed at sampling point
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Table 33. Status bits: Bit D2 = 0: INT source is V2LOW. however INTR register contain remains at 0000 (not bit set into the INTR register).
Analog Integrated Circuit Device Data
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Important For the most current revision of the package, visit www.freescale.com and do a keyword search on the 98A number listed below. DW SUFFIX EG SUFFIX (PB-FREE) 28-PIN PLASTIC PACKAGE 98ASB42345B ISSUE G
Analog Integrated Circuit Device Data Freescale Semiconductor 55 33889 PACKAGING PACKAGE DIMENSIONS DW SUFFIX EG SUFFIX (PB-FREE) 28-PIN PLASTIC PACKAGE 98ASB42345B ISSUE G
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application, and packaging information is provided in the datasheet. simulation according to the standards listed below. Figure 23. Surface Mount for SOIC Wide Body REFER TO THE 33889 DEVICE DATASHEET. Table 34. Thermal Performance Comparison
- Per JEDEC JESD51-2 at natural convection, still air
- 2s2p thermal test board per JEDEC JESD51-7.
- Per JEDEC JESD51-8, with the board temperature on the
center trace near the center lead.
- Single layer thermal test board per JEDEC JESD51-3.
- Thermal resistance between the die junction and the
surface and remaining surfaces insulated.
20 Terminal SOICW
Figure 24. Thermal Test Board
33889 Pin Connections
Table 35. Thermal Resistance Performance
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Figure 25. Device on Thermal Test Board RθJA Figure 26. Transient Pin Resistance RθJA
Analog Integrated Circuit Device Data Freescale Semiconductor 59 33889
REVISION HISTORY
REVISION DATE DESCRIPTION OF CHANGES 7.0 5/2006 Implemented Revision History page Added EG PB-Free package type Removed MC33889DW version, and added MC33889B and MC33889D versions Converted to the Freescale format, and updated to the prevailing form and style Modified Device Variations Between the 33889D and 33889B Versions (1) on page 2 Added Thermal Addendum (rev 2.0) on page 56 Changed the Maximum Ratings on page 6 to the standard format Added CAN transceiver description section 8.0 6/2002 Corrected two instances where pin LO had an overline, and one instance where pin WDOG did not. 9.0 8/2006 Removed MC33889BEG/R2 and MC338 89DEG/R2 and replaced them with MCZ33889BEG/R2 and MCZ33889DEG/R2 in the Ondering Information block 10.0 9/2006 Replaced the label Logic Inputs with Logic Signals (RX, TX, MOSI, MISO, CS, SCLK, RST, WDOG, INT) on page 6 Changed CS to CS at various places in the document 11.0 12/2006 Made changes to Supply Current in Stand-by Mode (7),(9) on page 8 and Supply Current in Normal Mode (7) on page 8 12.0 3/2007 Added the EG suffix to the included thermal addendum
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