33888A

33888 FREESCALE | Alldatasheet

Document overview

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Technical content

Features

• D u a l 1 0 mΩ High Side, Dual 40 mΩ High Side, Octal 600 mΩ Low Side
• Full Operating Voltage of 6.0 V to 27 V
• SPI Control of High-Side Overcurrent Limit, High-Side Current Sense, Output OFF Open Load Detection, Output ON/OFF Control, Watchdog Timeout
• SPI Reporting of Program Status and Fault
• High-Side Analog Current Feedback with Selectable Ratio
• Enhanced 16 V Reverse Polarity VPWR Protection

Figure 1. 33888 Simplified Application Diagram

ORDERING INFORMATION

Range (TA) Package MC33888APNB/R2 -40°C to 125°C

36 PQFN

+5.0 V +5.0 V FSI FS MCU A/D A/D CSNS0-1 CSNS2-3 WDIN SPI IHS0:IHS3 ILS RST VDD4 GND VPWR LS4:LS11 HS3 HS2 HS1 HS0 Loads 8 x Relay or LED 33888 VPWR

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Table 1. Features Comparison: 33888 and 33888A

Figure 2. 33888 Simplified Internal Block Diagram

3.0 MHz

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Figure 3. 33888 Pin Connections for PQFN Table 2. 33888 Pin Definitions for PQFN A functional description of each pin can be found in the Functional Pin Description section beginning on page 18.

1 FS Output Fault Status

fault mode is detected by the device.

15 GND

24 VPWR

36 WDIN

13 VDD Input Digital Drain Voltage

This is an external input pin used to supply power to the SPI circuit.

14 SO Output Serial Output This is an output pin connected to the SPI Serial Data Input pin of the

MCU or to the SI pin of the next device in a daisy chain.

16 CS Input Chip Select

17 SCLK Input Serial Clock This input pin is connected to the SCLK pin of the master MCU, which is

a bit (shift) clock for the SPI port.

18 SI Input Serial Input This input pin is connected to the SPI Serial Data Output pin of the MCU

from which it receives output command data.

19 ILS Input Low-Side Input This input pin is used to directly control a number of the low-side devices

state of the internal logic. delivers current through the connected loads. delivers current through the connected loads.

33 WAKE Input Wake This pin is used to input a logic [1] signal in order to enable the watchdog

34 RST Input Reset (Active Low) This input pin is used to initialize the device configuration and fault

registers, as well as place the device in a low current standby mode.

35 FSI Input Fail-Safe Input The Fail-Safe input pin level determines the state of the outputs after a

watchdog timeout occurs. This pin has an internal pullup.

36 WDIN Input Watchdog Input This input pin is a CMOS logic level input that is used to monitor system

Table 2. 33888 Pin Definitions for PQFN (continued) A functional description of each pin can be found in the Functional Pin Description section beginning on page 18.

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Figure 4. 33888 Pin Connections for PQFP Table 3. 33888 Pin Definitions for PQFP A functional description of each pin can be found in the Functional Pin Description section beginning on page 18.

1 FSI Input Fail-Safe Input The Fail-Safe input pin level determines the state of the outputs after a

watchdog timeout occurs. This pin has an internal pullup.

2 WDIN Input Watchdog Input This input pin is a CMOS logic level input that is used to monitor system

3 FS Output Fault Status

fault mode is detected by the device. shorted together on the board. must be shorted together on the board.

17 VDD Input Digital Drain Voltage

This is an external input pin used to supply power to the SPI circuit.

18 SO Output Serial Output This is an output pin connected to the SPI Serial Data Input pin of the

MCU or to the SI pin of the next device in a daisy chain.

19 CS Input Chip Select

20 SCLK Input Serial Clock This input pin is connected to the SCLK pin of the master MCU, which is

a bit (shift) clock for the SPI port.

21 SI Input Serial Input This input pin is connected to the SPI Serial Data Output pin of the MCU

from which it receives output command data.

22 ILS Input Low-Side Input This input pin is used to directly control a number of the low-side devices

delivers current through the connected loads. NC N/A Not Connected These pins are not connected internally. delivers current through the connected loads.

63 WAKE Input Wake This pin is used to input a logic [1] signal in order to enable the watchdog

64 RST Input Reset (Active Low) This input pin is used to initialize the device configuration and fault

registers, as well as place the device in a low current standby mode. Table 3. 33888 Pin Definitions for PQFP (continued) A functional description of each pin can be found in the Functional Pin Description section beginning on page 18.

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Table 4. Maximum Ratings permanent damage to the device.

1. Exceeding voltage limits on SCLK, SI, CS, WDIN, RST, IHS, FSI, or ILS pins may cause a malfunction or permanent damage to the
2. Continuous low-side output current rating so long as maximum j unction temperature is not exceeded. Operation at 125°C ambient

temperature will require calculation of maximum output current using package thermal resistance.

1. Continuous high-side output current rating so long as maximum j unction temperature is not exceeded. Operation at 125°C ambient

temperature will require calculation of maximum output current using package thermal resistance.

1. Active HS0 and HS1 clamp energy using the fo llowing conditions: single nonrepetitive pulse, VPWR = 16.0 V, L = 40 mH, TJ = 150°C.
2. Active HS2 and HS3 clamp energy using the fo llowing conditions: single nonrepetitive pulse, VPWR = 16.0 V, L = 10 mH, TJ = 150°C.
3. Active low-side clamp energy using the following conditions: single nonrepetitive pulse, 450 mA, TJ = 150°C.
4. ESD1 testing is performed in accordance with the Human Body Model (C ZAP = 100 pF, RZAP = 1500 Ω), ESD2 testing is performed in

accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 Ω).

1. Pin soldering temperature limit is for 10 seconds maximum dura tion. Not designed for immersion soldering. Exceeding these limits may

cause malfunction or permanent damage to the device.

1. Freescale’s Package Reflow capability meets Pb-free requi rements for JEDEC standard J-STD-020C. For Peak Package Reflow

Table 4. Maximum Ratings (continued) permanent damage to the device.

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Table 5. Static Electrical Characteristics Characteristics noted under conditions 6.0 V ≤ VPWR ≤ 27 V, 4.5 V ≤ VDD ≤ 5.5 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.

1. This parameter is tested at 125°C with a maximum value of 10 µA.
2. SPI/IO and internal logic oper ational. Outputs will recover in instructed state when VPWR voltage level returns to normal as long as the

level does not go below VPWRUV.

1. Output OFF Open Load Detection Current is the current required to flow through the load for the purpose of detecting the existence of

an open load condition when the specific output is commanded OFF. Table 5. Static Electrical Characteristics (continued) Characteristics noted under conditions 6.0 V ≤ VPWR ≤ 27 V, 4.5 V ≤ VDD ≤ 5.5 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.

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1. Output fault detection threshold with outputs programmed OFF. For the Low-Side Outputs, fault detection thresholds are the same for

output open and battery shorts.

1. Guaranteed by design. Not production tested.
2. Output OFF Open Load Detection Current is the current required to flow through the load for the purpose of detecting the existence of

an open load condition when the specific output is commanded OFF.

1. Output fault detection threshold with outputs programmed OFF.
2. Guaranteed by design. Not production tested.

Characteristics noted under conditions 6.0 V ≤ VPWR ≤ 27 V, 4.5 V ≤ VDD ≤ 5.5 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.

1. Output OFF Open Load Detection Current is the current required to flow through the load for the purpose of detecting the existence of

an open load condition when the specific output is commanded OFF.

1. Output fault detection threshold with outputs programmed OFF. For the low-side outputs, fault detection thresholds are the same for

output open and battery shorts.

1. Guaranteed by design. Not production tested.

Characteristics noted under conditions 6.0 V ≤ VPWR ≤ 27 V, 4.5 V ≤ VDD ≤ 5.5 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.

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1. Upper and lower logic threshold voltage range applies to SI, CS, SCLK, RST, IHS[0:3], ILS, WAKE, and WDIN input signals. The WAKE,

FSI, and RST signals are derived from an internal supply.

1. Parameter is guaranteed by de sign but is not production tested.
2. The current must be limited by a series resistor when using voltages higher than the W ICV.
3. Input capacitance of SI, CS, SCLK, RST, IHS[0:3], ILS, WAKE, and WDIN. This parameter is guaranteed by process monitoring but is

Characteristics noted under conditions 6.0 V ≤ VPWR ≤ 27 V, 4.5 V ≤ VDD ≤ 5.5 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.

Table 6. Dynamic Electrical Characteristics Characteristics noted under conditions 6.0 V ≤ VPWR ≤ 27 V, 4.5 V ≤ VDD ≤ 5.5 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.

9.0 V < VPWR < 16 V

16 V < VPWR < 27 V

1. High-side output rise and fall fast slew rates measured across a 5.0 Ω resistive load at high-side output = 0.5 V to VPWR - 3.0 V

(see Figure 5, page 17). These parameters are guaranteed by process monitoring.

1. High-side output rise and fall slow slew rates measured across a 5.0 Ω resistive load at high-side output = 0.5 V to VPWR - 3.0 V

(see Figure 5, page 17). These parameters are guaranteed by process monitoring.

1. High-side output turn-ON delay time meas ured from 50% of the rising IHS to 0.5 V of output OFF with RL = 27 Ω resistive load
2. High-side output turn-OFF delay time m easured from 50% of the falling IHS to VPWR - 2.0 V of the output OFF with RL = 27 Ω resistive

load (see Figure 5, page 17).

1. Low-side output rise and fall slew rates measured across a 5.0 Ω resistive load at low-side output = 10% to 90% (see Figure 6, page 17).
2. Low-side output turn-ON delay time measured from 50% of the rising ILS to 90% of V OUT with RL = 27 Ω resistive load (see Figure 6,
3. Low-side output turn-OFF delay time measured from 50% of the falling ILS to 10% of V OUT with RL = 27 Ω resistive load (see Figure 6,

page 17). These parameters are guaranteed by process monitoring.

1. Propagation time of Short Fault Disabl e Report Delay measured from rising edge of CS to output disabled, low-side = 5.0 V, and device

configured for low-side output overcurrent latch-off using CLOCCR.

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1. Watchdog timeout delay is measur ed from the rising edge of WAKE or RST from the sleep state to the HS[0:1] turn-ON with the outputs

driven OFF and the FSI floating. The accuracy of t WDTO is maintained for all configured watchdog time-outs.

1. t PCT measured from the rising edge of CS to 90% of ILIMPKHS[x,x] when the peak current limit is enabled.
2. This frequency is a typical value. Maxi mum switching frequencies are dictated by the turn-ON delay, turn-OFF delay, output rise and fall

times, and the maximum allowable junction temperature.

1. Symmetrical 50% duty cycl e SCLK clock period of 333 ns.
2. RST low duration measured with outputs enabled and going to OFF or disabled condition.
3. Maximum setup time required for the 33888 is the minimum guaranteed time needed from the MCU.
4. Rise and fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
5. Time required for output status data to be available for use at SO. 1.0 kΩ pullup on CS.
6. Time required for output status data to be terminated at SO. 1.0 kΩ pullup on CS.
7. Time required to obtain valid data out from SO following the rise of SCLK.

Table 6. Dynamic Electrical Characteristics (continued) Characteristics noted under conditions 6.0 V ≤ VPWR ≤ 27 V, 4.5 V ≤ VDD ≤ 5.5 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.

Analog Integrated Circuit Device Data

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This 33888 is a single-package combination of a power die with four discrete high-side MOSFETs and an integrated IC control die consisting of eight low-side drivers with appropriate control, protection, and diagnostic features. The high-side drivers are useful for both internal and external vehicle lighting applications as well as capable of driving inductive solenoid loads. The low-side drivers are capable of controlling low-current on/off type inductive loads, such as relays and solenoids as well as LED indicators and small lamps (see Figure 2, page 3). The device is useful in body control, instrumentation, and other high-power switching applications and systems. The 33888 is available in two packages: a power- enhanced 12 x 12 non-leaded Power QFN package with exposed tabs and a 64-lead Power QFP plastic package. Both packages are intended to be soldered directly onto the printed circuit board. The 33888 differs from the 33888A as explained in Table 1, page 2. FUNCTIONAL PIN DESCRIPTION FAULT STATUS (FS) This output pin is an open drain indication that goes active low when a fault mode is detected by the device. Specific device fault indication is given via the SO pin. POSITIVE POWER SUPPLY (VPWR) These pin connects to the positive power supply and are the source input of operational power for the device. LOW-SIDE OUTPUT (LS4, LS6, LS8, LS10) Each low-side pin is one 0.6 Ω low-side output MOSFET drain, which pulls current through the connected loads. Each of the outputs is actively clamped at 53 V. These outputs are current and thermal overload protected. Maximum steady state current through each of these outputs is 500 mA. GROUND (GND) These pins serve as the ground for the source of the low- side output transistors as well as the logic portion of the device. LOW-SIDE OUTPUT (LS5, LS7, LS9, LS11) Each low-side pin is one 0.6 Ω low-side output MOSFET drain, which pulls current through the connected loads. Each of the outputs is actively clamped at 53 V. These outputs are current and thermal overload protected. Maximum steady state current through each of these outputs is 800 mA. DIGITAL DRAIN VOLTAGE (VDD) This is an external input pin used to supply power to the SPI circuit. SERIAL OUTPUT (SO) This is an output pin connected to the SPI Serial Data Input pin of the MCU or to the SI pin of the next device in a daisy chain. This output will remain tri-stated unless the device is selected by a low CS pin. The output signal generated will have CMOS logic levels and the output data will transition on the rising edges of SCLK. The serial output data provides fault information for each output and is returned MSB first when the device is addressed. OD11 through OD0 are output fault bits for outputs 11 through 0, respectively. CHIP SELECT (CS) This is an input pin connected to a chip select output of a microcontroller (MCU). This IC controls which device is addressed (selected) by pulling the CS pin of the desired device logic Low, enabling the SPI communication with the device, while other devices on the serial link keep their serial outputs tri-stated. This input has an internal active pullup and requires CMOS logic levels. SERIAL CLOCK (SCLK) This input pin is connected to the SCLK pin of the master MCU, which is a bit (shift) clock for the SPI port. It transitions one time per bit transferred at an operating frequency, fSPI, and is idle between command transfers. It is 50% duty cycle and has CMOS logic levels. This signal is used to shift data to and from the 33888. SERIAL INPUT (SI) This input pin is connected to the SPI Serial Data Output pin of the MCU from which it receives output command data. This input has an internal active pull-down and requires CMOS logic levels. The serial data transmitted on this line is a 16-bit control command sent MSB first, which controls the twelve output channels. Bits D3 : D0 control the high-side outputs HS3 : HS0, respectively. Bits D11: D4 control the low- side outputs LS11: LS4, respectively. The MUC will ensure that data is available on the falling edge of SCLK. LOW-SIDE INPUT (ILS) This input pin is used to directly control a number of the low-side devices as configured by SPI. This pin may or may not be activated depending on the configured state of the internal logic.

Analog Integrated Circuit Device Data Freescale Semiconductor 19 33888 FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION HIGH-SIDE INPUT (IHS3, IHS2, IHS0, IHS1) Each high-side input pin is used to directly control only one designated high-side output. These inputs may or may not be activated depending on the configured state of the internal logic. CURRENT SENSE (2-3, 0-1) These pins deliver a metered amount of the high-side output current that can be used to generate signal ground referenced output voltages for use by the MCU. Each respective CSNS pin can be configured via SPI to deliver current from either of the two assigned outputs, or the currents could be the sum of the two. Current from HS0 and/ or HS1 are sensed via CSNS0 - 1. Current from HS2 and/or HS3 are sensed via CSNS2 - 3. HIGH SIDE OUTPUT (HS3, HS2) Each pin is the source of a 40 mΩ MOSFET high-side driver, which delivers current through the connected loads. These outputs can be controlled via SPI or using the IHS pins depending on the internal configuration. These outputs are current limited and thermally protected. During fail-safe mode, output HS2 will be turned on until the device is re- initialized and then immediately followed by normal operation. HIGH SIDE OUTPUT (HS1, HS0) Each pin is the source of a 10 mΩ MOSFET high-side driver, which delivers current through the connected loads. These outputs can be controlled via SPI or using the IHS pins depending on the internal configuration. These outputs are current limited and thermally protected. During fail-safe mode, output HS0 will be turned on until the device is re initialized and then immediately followed by normal operation. WAKE (WAKE) This pin is used to input a logic [1] signal in order to enable the watchdog timer function. An internal clamp protects the pin from high voltages when current is limited with an external resistor. This input has a passive internal pulldown. RESET (RST) This input pin is used to initialize the device configuration and fault registers, as well as place the device in a low current standby mode. This pin also starts the watchdog timeout when transitioned from logic [0] to logic [1]. This pin should not be allowed to be at logic [1] until VDD is in regulation. This input has an internal passive pulldown. FAIL-SAFE INPUT (FSI) The Fail-Safe input pin level determines the state of the outputs after a watchdog timeout occurs. This pin has an internal pullup. If the FSI pin is left to float to a logic [1], then HS0 and HS2 will turn on when in the Fail-Safe state. If the FSI pin is tied to GND, the watchdog circuit and fail-safe operation will be disabled, thus allowing operation without a watchdog signal. WATCHDOG INPUT (WDIN) This input pin is a CMOS logic level input that is used to monitor system operation. If the incoming watchdog signal does not transition within the normal watchdog timeout range, the device will operate in the Fail-Safe mode. This input has an active internal pulldown.

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series limiting resistance that limits the internal clamp current. the device is re initialized (if the FSI pin is left disconnected). and therefore fail-safe operation, will be disabled. the 33888 with the direct inputs in the absence of an SPI.

• Overtemperature Fault
• Overvoltage Fault
• Open Load Fault
• Overcurrent Fault With the exception of the overvoltage, these faults are output specific. The overvoltage fault is a global fault. The overcurrent fault is only reported for the low-side outputs. The 33888 low-side outputs incorporate an internal fault filter, t DLY(FS). The fault timer filters noise and switching transients for overcurrent faults when the output is ON and open load faults when the output is OFF. All faults are latched and indicated by a logic [1] for each output in the 33888 status word (Table 10, page 25). If the fault is removed, the status bit for the faulted output will be cleared by a rising edge on CS.

Table 7. Fail-Safe Operation and Transitions to Other

33888 Modes

S = State determined by SPI and/or direct input configurations.

shutdown circuitry into each individual output structure. depending on the logic configuration. until action is taken by the MCU to shut the output(s) OFF. status register can be cleared by a rising edge on CS. Figure 7. Low-Side Output OFF Open Load Detection LS11, and 800 mA minimum value for LS4, LS6, LS8, LS10).

33888 VPWR

Analog Integrated Circuit Device Data

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FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS retried output will latch off after the fault timer expires and the fault bit will remain set in the status register. For the low-side output of interest, if a D11 : D4 bit was set to a logic [0] in the OLCR register, the output experiencing an overcurrent condition is not disabled until an overtemperature fault threshold has been reached. The specific output goes into an analog current limit mode of operation, I LIM. The 33888 uses overtemperature shutdown to protect all outputs in this mode of operation. If the overcurrent condition is removed before the output has reached its overtemperature limit, the output will function as if no fault has occurred. Note that each pair of low-side drivers, LS4 : LS5, LS6 : LS7, LS8 : LS9, and LS10 : LS11, consists of a 500 mA and a 800 mA output. Each pair of outputs shares ground bond wires. The bond wires are not rated to handle both outputs in current limit mode simultaneously. OVERCURRENT FAULT REQUIREMENTS: HIGH- SIDE OUTPUT For the high-side output of interest, the output current is limited to one of four levels depending on the type of high- side output, the amount of time that has elapsed since the output was switched on, and the state of the CLOCCR register. Assuming that bits D3 : D0 of the CLOCCR register are at logic [0], the current limit levels of the outputs will be initially at their peak levels as specified by the ILIM(PK)HS[0:3]. After the high-side output is switched on, the peak current timer starts. After a period of time t PCT, the current limit level changes to the sustain levels ILIMSUSHS[x,x]. For the high-side output of interest, if a D3 : D0 bit of the CLOCCR is at logic [1], then the assigned output will only current limit at the sustain level specified by ILIMSUSHS[x,x]. Current is limited until the overtemperature circuitry shuts OFF the device. The device turns ON automatically when the temperature fails below the TLIM(HYS). This cycle continues indefinitely until action is taken by the master to shut the output(s) OFF. LOGIC COMMANDS AND REGISTERS SPI INTERFACE AND PROTOCOL DESCRIPTION The SPI interface has full duplex, three-wire synchronous data transfer and has four I/O lines associated with it: Serial Clock (SCLK), Serial Input (SI), Serial Output (SO), and Chip Select (CS). The SI/SO pins of the 33888 follow a first-in first-out (D15 / D0) protocol with both input and output words transferring the most significant bit first. All inputs are compatible with 5.0 V CMOS logic levels. During SPI output control, a logic [0] in a message word will result in the designated output being turned off. Similarly, a logic [1] will turn on a corresponding output. The SPI lines perform the following functions: Serial Clock (SCLK) The SCLK pin clocks the internal shift registers of the 33888. The serial input (SI) pin accepts data into the input shift register on the falling edge of the SCLK signal while the serial output pin (SO) shifts data information out of the SO line driver on the rising edge of the SCLK signal. It is important that the SCLK pin be in a logic [0] state whenever the chip select (CS) makes any transition. For this reason, it is recommended that the SCLK pin be kept in a logic [0] state as long as the device is not accessed (CS in logic [1] state). SCLK has an active internal pulldown, IDWN. When CS is logic [1], signals at the SCLK and SI pins are ignored and SO is tri-stated (high impedance). (See Figures 8 and 9 on page 23.) Serial Interface (SI) This is a serial interface (SI) command data input pin. Each SI bit is read on the falling edge of SCLK. A 16-bit stream of serial data is required on the SI pin, starting with D15 to D0. The 12 outputs of the 33888 are configured and controlled using the 3-bit addressing scheme and the 12 assigned data bits designed into the 33888. SI has an active internal pulldown, IDWN. Serial Output (SO) The SO data pin is a tri-stateable output from the shift register. The SO pin remains in a high-impedance state until the CS pin is put into a logic [0] state. The SO data report the status of the outputs as well as provide the capability to reflect the state of the direct inputs. The SO pin changes states on the rising edge of SCLK and reads out on the falling edge of SCLK. When an output is ON or OFF and not faulted, the corresponding SO bit, OD11: OD0, is a logic [0]. If the output is faulted, the corresponding SO state is a logic [1]. SO OD14 : OD12 reflect the state of six various inputs (three at a time) depending upon the reported state of the previously written watchdog bit OD15. Chip Select (CS) The CS pin enables communication with the master microcontroller (MCU). When this pin is in a logic [0] state, the 33888 is capable of transferring information to and receiving information from the MCU. The 33888 latches in data from the input shift registers to the addressed registers on the rising edge of CS. The 33888 transfers status information from the power outputs to the shift registers on the falling edge of CS. The output driver on the SO pin is enabled when CS is logic [0]. CS is only transitioned from a logic [1] state to a logic [0] state when SCLK is a logic [0]. CS has an active internal pullup, IUP. The 33888 is capable of communicating directly with the MCU via the 16-bit SPI protocol as described in the next section.

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addresses and their impact on device operation. register (if ILS is enabled). D9 Used to configure Low-Side Output LS9. D8 Used to configure Low-Side Output LS8. D7 Used to configure Low-Side Output LS7. D6 Used to configure Low-Side Output LS6. Table 8. SI Message Bit Assignment (continued) D3 Used to configure High-Side Output HS3. D2 Used to configure High-Side Output HS2. D1 Used to configure High-Side Output HS1. LSB D0 Used to configure High-Side Output HS0. Table 9. Serial Input Address and Configuration Bit Map

the watchdog timeout and the CSNS0-1 and CSNS2-3 pins. The watchdog timeout is configured using bits D4 and D5. logic [1] will result in a watchdog timeout of WDTO ÷ 2. programmed at the beginning of a new count sequence. useful to diagnose output shorts to battery (for HS). off if the current exceeds ILIM after a timeout of t DLY(FS). accessible via SPI during normal operation. data is clocked into the SI pin. daisy chaining devices as well as message verification. able to accept new fault status information. Table 10. Serial Output Bit Assignment previously clocked-in message. bit will reflect the state of IHS2. bit will reflect the state of IHS3. reflect the state of the input WAKE. OD11 Reports the absence or presence of a fault on LS11. OD10 Reports the absence or presence of a fault on LS10. OD9 Reports the absence or presence of a fault on LS9. OD8 Reports the absence or presence of a fault on LS8. OD7 Reports the absence or presence of a fault on LS7. OD6 Reports the absence or presence of a fault on LS6.

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• Over voltage
• Open Load
• Over temperature In the event of an occurrence of faults, the bits clocked out of the device will indicate the presence of a fault with a logic [1] on the output dedicated bit, prior to and since the last SPI communication, or at the time of the CSB pin going to logic [0]. Each type of fault can be differentiated from the others as follows: OVER VOLTAGE An over voltage occurrence can be inferred if all twelve bits representing each of the outputs are logic [1] at the same time. OPEN LOAD An open load condition is only detected when the output is off and the open load detection for the output of concern is enabled. The first SPI read after the output is commanded on will clear the fault bit for this output. OVER TEMPERATURE An over temperature condition is indicated and latched into the fault register if the output is on and the indicating output experienced an over temperature event since the last SPI write. Each output has a dedicated temperature sensor. The high side drivers will turn off after the over temperature shutdown level is reached until the temperature falls below the specified hysteresis level and then will turn back on automatically, unless the output has been commanded off. In either case, a fault indication for the faulted output will be present for the next SPI read. CURRENT LIMIT An output which current limits will not indicate a fault unless the limitation results in enough power dissipation to increase the temperature of the limiting transistor to its over temperature shutdown level. Each of these faults are indicated real time by the FLTB pin, which could be used as an initial indication of the presence of a fault within the device. Determining the actual faulted output would requires an analysis of the fault bits provided by the device via the SO pin. Note that the very first SPI read after the battery falls below 6V may not be correct, if the VDD remained in specification and a reset was not generated by the MCU. PROTECTION AND DIAGNOSTIC FEATURES REVERSE BATTERY REQUIREMENTS The low-side and high-side outputs survive the application of reverse battery as low as -16 V. GROUND DISCONNECT PROTECTION In the event that the 33888 ground is disconnected from load ground, the device protects itself and safely turns OFF the outputs, regardless of the state of the output at the time of disconnection. OD5 Reports the absence or presence of a fault on LS5. OD4 Reports the absence or presence of a fault on LS4. OD3 Reports the absence or presence of a fault on HS3. OD2 Reports the absence or presence of a fault on HS2. OD1 Reports the absence or presence of a fault on HS1. LSB OD0 Reports the absence or presence of a fault on HS0. LSB OD0 Reports the absence or presence of a fault on HS0.

Table 10. Serial Output Bit Assignment (continued)

Figure 10. Low-Side Short Circuit Detection and Analog Current Limit

5.0 V, then the internal logic is re initialized and the device is

an inductive load connected to HS pins. Figure 11. Low-Side Output Voltage Clamping

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1. 55W bulb driven with 10 milliohm outputs, and 21W

plus 5W lamps with 40 milliohm outputs. Figure 12. 33888 Typical Application Diagram considered constant in the loads.

8 X Relay or LED

Figure 13. Figure 13 – MC33888 power dissipation calculator Automotive lamps do not tolerate high voltages very well. the transition between the fully-on and PWMing modes. be adjusted to (13/18)², or 52%, when the battery is at 18V. and LS[4:11]) per ISO 7637-2 standard. Table 11. Results of Fast Transient Pulses on VPWR

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A: Device fully operational after test without any degradation. C: One or more function is (are) unavailable during the test and after it. A: Device fully operational after test without any degradation. C: One or more function is (are) unavailable during the test and after it. Table 12. Rating of Fast Transient Pulses on VPWR Table 13. Results of Fast Transient Pulses on HS1 and HS3 Table 14. Results of Fast Transient Pulses on LS4 and LS5 Table 15. Rating of Fast Transient Pulses on HS1, HS3, LS4, and LS5

Analog Integrated Circuit Device Data Freescale Semiconductor 31 33888 PACKAGING PACKAGE DIMENSIONS PACKAGING PACKAGE DIMENSIONS For the most current package revision, visit www.freescale.com and perform a keyword search using the “98A” listed below. PNB SUFFIX APNB SUFFIX 36-PIN NON-LEADED PACKAGE 98ARL10544D ISSUE E

Analog Integrated Circuit Device Data

32 Freescale Semiconductor

Analog Integrated Circuit Device Data Freescale Semiconductor 33 33888 PACKAGING PACKAGE DIMENSIONS FB SUFFIX 64-PIN PLASTIC PACKAGE 98ARH99043A ISSUE D

Analog Integrated Circuit Device Data

34 Freescale Semiconductor

application, and packaging information is provided in the datasheet. TJ1 and TJ2, and a thermal resistance matrix with RθJAmn. temperature while only heat source 1 is heating with P1. The stated values are solely for a thermal performance comparison of one package to another in a standardized environment. values were obtained by measurement and simulation according to the standards listed below. Figure 14. Surface Mount for Power PQFN the 33888 device data sheet. Table 16. Thermal Performance Comparison

1. Per JEDEC JESD51-2 at natural convection, still air
2. 2s2p thermal test board per JEDEC JESD51-7and
3. Per JEDEC JESD51-8, with the board temperature on the

center trace near the power outputs.

1. Single layer thermal test board per JEDEC JESD51-3 and
2. Thermal resistance between the die junction and the

exposed pad, “infinite” heat sink attached to exposed pad.

36 Freescale Semiconductor

Figure 15. Thermal Test Board where the junction temperature is sensed.

33888 Pin Connections

Table 17. Thermal Resistance Performance

Analog Integrated Circuit Device Data

38 Freescale Semiconductor

REVISION HISTORY

REVISION DATE DESCRIPTION OF CHANGES 5.0 7/2006 • Implemented Revision History page

• Converted to Freescale format and updated to the prevailing form and style
• Added Thermal Addendum
• Added last sentence to Open Load Fault on page 21
• Added Fault Reporting Description, following Table 10. Serial Output Bit Assignment on page 25
• Made numerous changes and description additions to Typical Applications on page 28 6.0 2/2007 • Removed Part Number MC33888PNB/R2 from Ordering Information Block on page 1.
• Added Shaffner information and tables to the Typical Applications section of the data sheet, beginning on page 28.
• Added titles to Table 11 - Results of Fast Transient Pulses on VPWR on page 29, Table 12 - Rating of Fast Transient Pulses on VPWR on page 30, Table 13 - Results of Fast Transient Pulses on HS1 and HS3 on page 30, Table 14 - Results of Fast Transient Pulses on LS4 and LS5 on page 30, and Table 15 - Rating of Fast Transient Pulses on HS1, HS3, LS4, and LS5 on page 30
• Removed Peak Package Reflow Temperature During Reflow (solder reflow) parameter from Maximum Ratings table on page 9. Added note with instructions from www.freescale.com.

Analog Integrated Circuit Device Data Freescale Semiconductor 39 33888

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