33887

33887_08 FREESCALE | Alldatasheet

Document overview

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Technical content

Features

• Fully specified operation 5.0 V to 28 V
• Limited operation with reduced performance up to 40 V
• 1 2 0 mΩ RDS(ON) Typical H-Bridge MOSFETs
• TTL/CMOS Compatible Inputs
• PWM Frequencies up to 10 kHz
• Active Current Limiting (Regulation)
• Fault Status Reporting
• Sleep Mode with Current Draw ≤50 μA (Inputs Floating or Set to Match Default Logic States)
• Pb-Free Packaging Designated by Suffix Codes VW and EK

Figure 1. 33887 Simplified Application Diagram

ORDERING INFORMATION

Range (TA) Package MC33887DH/R2 -40°C to 125°C

20 HSOPMC33887VW/R2

54 SOICW-EPMCZ33887EK/R2

VW SUFFIX (Pb-FREE) 98ASH70273A 20-PIN HSOP Bottom View DWB SUFFIX EK SUFFIX (Pb-FREE) 98ASA10506D 54-PIN SOICW-EP PNB SUFFIX 98ASA10583D 36-PIN PQFN 33887 H-BRIDGE 33887 CCP IN1 IN2 EN FS MCU PGND MOTOR OUT1 OUT2 AGND FB 6.0 V FB IN OUT OUT OUT OUT OUT A/D

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Figure 2. 33887 Simplified Internal Block Diagram

Figure 3. 33887 Pin Connections Table 1. 33887 HSOP PIN DEFINITIONS A functional description of each pin can be found in the Functional Pin DescriptionS section, page 21. 1 AGND Analog Ground Low-current analog signal ground. 3 IN1 Logic Input Control 1 Logic input control of OUT1 (i.e., IN1 logic HIGH = OUT1 HIGH). 6 , 7 OUT1 H-Bridge Output 1 Output 1 of H-Bridge.

8 FB Feedback for H-Bridge Current sensing feedback output providing ground referenced 1/375th

(0.00266) of H-Bridge high-side current. 9 – 12 PGND Power Ground High-current power ground.

13 D2 Disable 2 Active LOW input used to simultaneously tri-state disable both H-Bridge

outputs. When D2 is Logic LOW, both outputs are tri-stated. 14 , 15 OUT2 H-Bridge Output 2 Output 2 of H-Bridge. 17 CCP Charge Pump Capacitor External reservoir capacitor connection for internal charge pump capacitor.

18 D1 Disable 1 Active HIGH input used to simultaneously tri-state disable both H-Bridge

outputs. When D1 is Logic HIGH, both outputs are tri-stated. 19 IN2 Logic Input Control 2 Logic input control of OUT2 (i.e., IN2 logic HIGH = OUT2 HIGH). Exposed pad thermal interface for sinking heat from the device. impedance path to prevent injection of spurious signals into IC substrate.

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Figure 4. 33887 Pin Connections Table 2. PQFN PIN DEFINITIONS A functional description of each pin can be found in the Functional Pin DescriptionS section, page 21. NC No Connect No internal connection to this pin.

2 D1 Disable 1 Active HIGH input used to simultaneously tri-state disable both H-Bridge

outputs. When D1 is Logic HIGH, both outputs are tri-stated. 3 IN2 Logic Input Control 2 Logic input control of OUT2 (i.e., IN2 logic HIGH = OUT2 HIGH). 5, 6, 12, 13, 34, 35 V+ Positive Power Supply Positive supply connections. 8 AGND Analog Ground Low-current analog signal ground. 11 IN1 Logic Input Control 1 Logic input control of OUT1 (i.e., IN1 logic HIGH = OUT1 HIGH). 14, 15, 17, 18 OUT1 H-Bridge Output 1 Output 1 of H-Bridge.

20 FB Feedback for H-Bridge Current feedback output providing ground referenced 1/375th ratio of

21– 26 PGND Power Ground High-current power ground.

27 D2 Disable 2 Active LOW input used to simultaneously tri-state disable both H-Bridge

outputs. When D2 is Logic LOW, both outputs are tri-stated. 29, 30, 32, 33 OUT2 H-Bridge Output 2 Output 2 of H-Bridge.

36 CCP Charge Pump Capacitor External reservoir capacitor connection for internal charge pump

Exposed pad thermal interface for sinking heat from the device.

19 NC10NC

Figure 5. 33887 Pin Connections Table 3. SOICW-EP PIN DEFINITIONS A functional description of each pin can be found in the Functional Pin DescriptionS section, page 21. 1– 4, 51– 54 PGND Power Ground High-current power ground. NC No Connect No internal connection to this pin.

8 D2 Disable 2 Active LOW input used to simultaneously tri-state disable both H-Bridge

outputs. When D2 is Logic LOW, both outputs are tri-stated. 10 – 13 OUT2 H-Bridge Output 2 Output 2 of H-Bridge. 15 – 18, 37 – 40 V+ Positive Power Supply Positive supply connections.

23 CCP Charge Pump Capacitor External reservoir capacitor connection for internal charge pump

24 D1 Disable 1 Active HIGH input used to simultaneously tri-state disable both H-Bridge

outputs. When D1 is Logic HIGH, both outputs are tri-stated. 25 IN2 Logic Input Control 2 Logic input control of OUT2 (i.e., IN2 logic HIGH = OUT2 HIGH). 30 AGND Analog Ground Low-current analog signal ground. 32 IN1 Logic Input Control 1 Logic input control of OUT1 (i.e., IN1 logic HIGH = OUT1 HIGH).

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42 – 45 OUT1 H-Bridge Output 1 Output 1 of H-Bridge.

47 FB Feedback for H-Bridge Current feedback output providing ground referenced 1/375th ratio of

Exposed pad thermal interface for sinking heat from the device. A functional description of each pin can be found in the Functional Pin DescriptionS section, page 21.

Analog Integrated Circuit Device Data Freescale Semiconductor 7 33887

ELECTRICAL CHARACTERISTICS

All voltages are with respect to ground unless otherwise noted. Rating Symbol Value Unit ELECTRICAL RATINGS Supply Voltage (1) V+ -0.3 to 40 V Input Voltage (2) VIN - 0.3 to 7.0 V FS Status Output (3) V FS -0.3 to 7.0 V Continuous Current (4) IOUT 5.0 A DH Suffix HSOP ESD Voltage (5) Human Body Model Each Pin to AGND Each Pin to PGND Each Pin to V+ Each I/O to All Other I/Os Machine Model VESD1 VESD1 VESD1 VESD1 VESD2 ±1000 ±1500 ±2000 ±2000 ±200 V VW Suffix HSOP, SOICW-EP, and PQFN ESD Voltage (5) Human Body Model Machine Model VESD1 VESD2 ± 2000 ± 200 V THERMAL RATINGS Storage Temperature TSTG - 65 to 150 °C Operating Temperature (6) Ambient Junction TA TJ - 40 to 125 - 40 to 150 Peak Package Reflow Temperature During Reflow (7), (8) TPPRT Note 8. °C Notes 1 Performance at voltages greater than 28V is degraded.See Electrical Performance Curves on page 18 and 19 for typical performance. Extended operation at higher voltages has not been fully characterized and may reduce the operational lifetime. 2 Exceeding the input voltage on IN1, IN2, EN, D1, or D2 may cause a malfunction or permanent damage to the device. 3 Exceeding the pull-up resistor voltage on the open Drain FS pin may cause permanent damage to the device. 4 Continuous current capability so long as junction temperature is ≤ 150°C. 5 ESD1 testing is performed in accordance with the Human Body Model (C ZAP = 100 pF, RZAP = 1500 Ω), ESD2 testing is performed in accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 Ω). 6 The limiting factor is junction temperatur e, taking into account the power dissipation, thermal resistance, and heat sinking provided. Brief nonrepetitive excursions of junction temperature above 150°C can be tolerated as long as duration does not exceed 30 seconds maximum. (nonrepetitive events are defined as not occurring more than once in 24 hours.) 7 Pin soldering temperature limit is for 10 seconds maximum durat ion. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. 8. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), MC33xxxD enter 33xxx), and review parametrics.

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THERMAL RESISTANCE (AND PACKAGE DISSIPATION) RATINGS (9), (10), (11), (12) Junction-to-Board (Bottom Exposed Pad Soldered to Board) HSOP (6.0 W) PQFN (4.0 W) SOICW-EP (2.0 W) RθJB ~7.0 ~8.0 ~9.0 °C/W Junction-to-Ambient, Natural Convection, Single-Layer Board (1s) (13) HSOP (6.0 W) PQFN (4.0 W) SOICW-EP (2.0 W) RθJA ~ 41 ~ 50 ~ 62 °C/W Junction-to-Ambient, Natural Convection, Four-Layer Board (2s2p) (14) HSOP (6.0 W) PQFN (4.0 W) SOICW-EP (2.0 W) RθJMA ~ 18 ~ 21 ~ 23 °C/W Junction-to-Case (Exposed Pad) (15) HSOP (6.0 W) PQFN (4.0 W) SOICW-EP (2.0 W) RθJC ~ 0.8 ~1.2 ~2.0 °C/W Notes 9 The limiting factor is junction temperatur e, taking into account the power dissipation, thermal resistance, and heat sinking. 10 Exposed heatsink pad plus the power and ground pins comp rise the main heat conduction paths. The actual RθJB (junction-to-PC board) values will vary depending on solder thickness and composition and copper trace thickness. Maximum current at maximum die temperature represents ~ 16 W of conduction loss heating in the diagonal pair of output MOSFETs. Therefore, the RθJC-total must be less than 5.0 °C/W for maximum load at 70°C ambient. Module thermal design must be planned accordingly. 11 Thermal resistance between the die and the printed circuit boar d per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 12 Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 13 Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board (JESD51-3) horizontal. 14 Per JEDEC JESD51-6 with the board horizontal. 15 Indicates the maximum thermal resistance between the die and the ex posed pad surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1) with the cold plate temperature used for the case temperature. MAXIMUM RATINGS (continued) All voltages are with respect to ground unless otherwise noted. Rating Symbol Value Unit

Analog Integrated Circuit Device Data Freescale Semiconductor 9 33887 STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 4. STATIC ELECTRICAL CHARACTERISTICS noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.

8.0 V ≤ V+ ≤ 28 V

the See Functional Description on page 21 for information about operation outside of this range. 17 I Q (sleep) is with sleep mode function enabled.

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STATIC ELECTRICAL CHARACTERISTICS POWER OUTPUTS (OUT1, OUT2) Output ON-Resistance (18)

5.0 V ≤ V+ ≤ 28 V, TJ = 25°C

8.0 V ≤ V+ ≤ 28 V, TJ = 150°C

RDS(ON) 120 225 300 mΩ Active Current Limiting Threshold (via Internal Constant OFF-Time PWM) on Low-Side MOSFETs (19) ILIM 5.2 6.5 7.8 A High-Side Short Circuit Detection Threshold ISCH 11 – – A Low-Side Short Circuit Detection Threshold ISCL 8.0 – – A Leakage Current (20) VOUT = V+ VOUT = Ground IOUT(LEAK) 100 200 μA Output MOSFET Body Diode Forward Voltage Drop IOUT = 3.0 A VF – – 2.0 V Overtemperature Shutdown Thermal Limit Hysteresis TLIM THYS 175 225 HIGH-SIDE CURRENT SENSE FEEDBACK Feedback Current I OUT = 0 mA I OUT = 500 mA I OUT = 1.5 A I OUT = 3.0 A I OUT = 6.0 A I FB 1.07 3.6 7.2 14.4 1.33 4.0 8.0 600 1.68 4.62 9.24 18.48 μA mA mA mA mA FAULT STATUS (21) Fault Status Leakage Current (22) V FS = 5.0 V I FS(LEAK) – – 10 μA Fault Status SET Voltage (23) I FS = 300 μA V FS(LOW) – – 1.0 V Notes 18 Output-ON resistance as measured from output to V+ and ground. 19 Active current limitation applies only for the low-side MOSFETs. 20 Outputs switched OFF with D1 or D2. 21 Fault Status output is an open Drain output requiring a pull-up resistor to 5.0 V. 22 Fault Status Leakage Current is measured with Fault Status HIGH and not SET. 23 Fault Status Set Voltage is measured with Fault Status LOW and SET with I FS = 300 μA. noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.

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Figure 6. Output Delay Time Figure 7. Disable Delay Time Figure 8. Output Switching Time Figure 9. Active Current Limiting Versus Temperature (Typical)

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TYPICAL SWITCHING WAVEFORMS TYPICAL SWITCHING WAVEFORMS Important For all plots, the following applies:

• C h 2 = 2.0 A per division
• L LOAD = 533 μH @ 1.0 kHz
• L LOAD = 530 μH @ 10.0 kHz
• R LOAD = 4.0 Ω

Figure 12. Output Voltage and Current vs. Input Voltage at V+ = 24 V, Figure 13. Output Voltage and Current vs. Input Voltage at V+ = 24 V,

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TYPICAL SWITCHING WAVEFORMS Figure 16. Output Voltage and Current vs. Input Voltage at V+ = 24 V, Figure 17. Output Voltage and Current vs. Input Voltage at V+ = 24 V,

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ELECTRICAL PERFORMANCE CURVES ELECTRICAL PERFORMANCE CURVES Figure 20. Typical High-Side RDS(ON) Versus V+ Figure 21. Typical Low-Side RDS(ON) Versus V+

Analog Integrated Circuit Device Data Freescale Semiconductor 19 33887 ELECTRICAL PERFORMANCE CURVES Figure 22. Typical Quiescent Supply Current Versus V+

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ELECTRICAL PERFORMANCE CURVES Table 6. Truth Table H = HIGH, X = HIGH or LOW, and Z = High impedance (all output power transistors are switched off). status is reset automatically or automatically cleared and the outputs are restored to their original operating condition. signals and the fault status flag is SET logic LOW.

Analog Integrated Circuit Device Data Freescale Semiconductor 21 33887 FUNCTIONAL DESCRIPTION INTRODUCTION FUNCTIONAL DESCRIPTION INTRODUCTION Numerous protection and operational features (speed, torque, direction, dynamic braking, PWM control, and closed- loop control), in addition to the 5.0 A current capability, make the 33887 a very attractive, cost-effective solution for controlling a broad range of small DC motors. In addition, a pair of 33887 devices can be used to control bipolar stepper motors. The 33887 can also be used to excite transformer primary windings with a switched square wave to produce secondary winding AC currents. FUNCTIONAL PIN DESCRIPTIONS POWER GROUND AND ANALOG GROUND (PGND AND AGND) Power and analog ground pins should be connected together with a very low impedance connection. POSITIVE POWER SUPPLY (V+) V+ pins are the power supply inputs to the device. All V+ pins must be connected together on the printed circuit board with as short as possible traces offering as low impedance as possible between pins. V+ pins have an undervoltage threshold. If the supply voltage drops below a V+ undervoltage threshold, the output power stage switches to a tri-state condition and the fault status flag is SET and the Fault Status pin voltage switched to a logic LOW. When the supply voltage returns to a level that is above the threshold, the power stage automatically resumes normal operation according to the established condition of the input pins and the fault status flag is automatically reset logic HIGH. As V+ increases in value above 28 V, the charge pump performance begins to degrade. At +40 V, the charge pump is effectively non-functional. Operation at this high voltage level will result in the output FETs not being enhanced when turned on. This means that the voltage on the output will be VOUT = (V+) – VGS. This increased voltage drop under load will produce a higher power dissipation. FAULT STATUS (FS) The FS pin is the device fault status output. This output is an active LOW open drain structure requiring a pull-up resistor to 5.0 V. Refer to Table 6, Truth Table, page 20. LOGIC INPUT CONTROL AND DISABLE (IN1, IN2, D1, AND D2) These pins are input control pins used to control the outputs. These pins are 5.0 V CMOS-compatible inputs with hysteresis. The IN1 and IN2 independently control OUT1 and OUT2, respectively. D1 and D2 are complementary inputs used to tri-state disable the H-Bridge outputs. When either D1 or D2 is SET (D1 = logic HIGH or D2 = logic LOW) in the disable state, outputs OUT1 and OUT2 are both tri-state disabled; however, the rest of the circuitry is fully operational and the supply I Q (standby) current is reduced to a few milliamperes. Refer to Table 6, Truth Table, and STATIC ELECTRICAL CHARACTERISTICS table, page 9. H-BRIDGE OUTPUT (OUT1 AND OUT2) These pins are the outputs of the H-Bridge with integrated output MOSFET body diodes. The bridge output is controlled using the IN1, IN2, D1, and D2 inputs. The low-side MOSFETs have active current limiting above the ILIM threshold. The outputs also have thermal shutdown (tri-state latch-OFF) with hysteresis as well as short circuit latch-OFF protection. A disable timer (time t b) USED to detect currents that are higher than current limit is activated at each output activation to facilitate hard short detection (see Figure 11, page 13). Charge Pump Capacitor (CCP) A filter capacitor (up to 33 nF) can be connected from the charge pump output pin and PGND. The device can operate without the external capacitor, although the C CP capacitor helps to reduce noise and allows the device to perform at maximum speed, timing, and PWM frequency. ENABLE (EN) The EN pin is used to place the device in a sleep mode so as to consume very low currents. When the EN pin voltage is a logic LOW state, the device is in the sleep mode. The device is enabled and fully operational when the EN pin voltage is logic HIGH. An internal pull-down resistor maintains the device in sleep mode in the event EN is driven through a high impedance I/O or an unpowered microcontroller, or the EN input becomes disconnected. FEEDBACK FOR H-BRIDGE (FB) The 33887 has a feedback output (FB) for “real time” monitoring of H-Bridge high-side current to facilitate closed- loop operation for motor speed and torque control. The FB pin provides current sensing feedback of the H-Bridge high-side drivers. When running in forward or reverse direction, a ground referenced 1/375th (0.00266) of load current is output to this pin. Through an external resistor to ground, the proportional feedback current can be converted to a proportional voltage equivalent and the controlling microcontroller can “read” the current proportional

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FUNCTIONAL PIN DESCRIPTIONS voltage with its analog-to-digital converter (ADC). This is intended to provide the user with motor current feedback for motor torque control. The resistance range for the linear operation of the FB pin is 100 < RFB < 200 Ω. If PWM-ing is implemented using the disable pin inputs (either D1 or D2), a small filter capacitor (1.0 μF or less) may be required in parallel with the external resistor to ground for fast spike suppression.

Analog Integrated Circuit Device Data Freescale Semiconductor 23 33887 FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES The 33887 Simplified Internal Block Diagram shown in Figure 2, page 2, is a fully protected monolithic H-Bridge with Enable, Fault Status reporting, and High-Side current sense feedback to accommodate closed-loop PWM control. For a DC motor to run, the input conditions need be as follows: Enable input logic HIGH, D1 input logic LOW, D2 input logic HIGH, FS flag cleared (logic HIGH), one IN logic LOW and the other IN logic HIGH (to define output polarity). The 33887 can execute dynamic braking by simultaneously turning on either both high-side MOSFETs or both low-side MOSFETs in the output H-Bridge; e.g., IN1 and IN2 logic HIGH or IN1 and IN2 logic LOW. The 33887 outputs are capable of providing a continuous DC load current of 5.0 A from a 28 V V+ source. An internal charge pump supports PWM frequencies to 10 kHz. An external pull-up resistor is required at the FS pin for fault status reporting. The 33887 has an analog feedback (current mirror) output pin (the FB pin) that provides a constant- current source ratioed to the active high-side MOSFET. This can be used to provide “real time” monitoring of load current to facilitate closed-loop operation for motor speed/torque control. Two independent inputs (IN1 and IN2) provide control of the two totem-pole half-bridge outputs. Two disable inputs (D1 and D2) provide the means to force the H-Bridge outputs to a high-impedance state (all H-Bridge switches OFF). An EN pin controls an enable function that allows the 33887 to be placed in a power-conserving sleep mode. The 33887 has undervoltage shutdown with automatic recovery, active current limiting, output short-circuit latch- OFF, and overtemperature latch-OFF. An undervoltage shutdown, output short-circuit latch-OFF, or overtemperature latch-OFF fault condition will cause the outputs to turn OFF (i.e., become high impedance or tri-stated) and the fault output flag to be set LOW. Either of the Disable inputs or V+ must be “toggled” to clear the fault flag. Active current limiting is accomplished by a constant OFF- time PWM method employing active current limiting threshold triggering. The active current limiting scheme is unique in that it incorporates a junction temperature-dependent current limit threshold. This means the active current limiting threshold is “ramped down” as the junction temperature increases above 160°C, until at 175°C the current will have been decreased to about 4.0 A. Above 175°C, the overtemperature shutdown (latch-OFF) occurs. This combination of features allows the device to remain in operation for 30 seconds at junction temperatures above 150°C for nonrepetitive unexpected loads.

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FUNCTIONAL DEVICE OPERATION PROTECTION AND DIAGNOSTIC FEATURES PROTECTION AND DIAGNOSTIC FEATURES SHORT CIRCUIT PROTECTION If an output short circuit condition is detected, the power outputs tri-state (latch-OFF) independent of the input (IN1 and IN2) states, and the fault status output flag is SET logic LOW. If the D1 input changes from logic HIGH to logic LOW, or if the D2 input changes from logic LOW to logic HIGH, the output bridge will become operational again and the fault status flag will be reset (cleared) to a logic HIGH state. The output stage will always switch into the mode defined by the input pins (IN1, IN2, D1, and D2), provided the device junction temperature is within the specified operating temperature range. ACTIVE CURRENT LIMITING The maximum current flow under normal operating conditions is internally limited to ILIM (5.2 A to 7.8 A). When the maximum current value is reached, the output stages are tri-stated for a fixed time (t a) of 20 μs typical. Depending on the time constant associated with the load characteristics, the current decreases during the tri-state duration until the next output ON cycle occurs (see Figures 11 and 14, page 13 and page 15, respectively). The current limiting threshold value is dependent upon the device junction temperature. When -40°C ≤ TJ ≤ 160°C, ILIM is between 5.2 A to 7.8 A. When TJ exceeds 160°C, the ILIM current decreases linearly down to 4.0 A typical at 175°C. Above 175°C the device overtemperature circuit detects TLIM and overtemperature shutdown occurs (see Figure 9, page 12). This feature allows the device to remain operational for a longer time but at a regressing output performance level at junction temperatures above 160°C. Output Avalanche Protection An inductive fly-back event, namely when the outputs are suddenly disabled and V+ is lost, could result in electrical overstress of the drivers. To prevent this the V+ input to the 33887 should not exceed the maximum rating during a fly- back condition. This may be done with either a zener clamp and/or an appropriately valued input capacitor with sufficiently low ESR. OVERTEMPERATURE SHUTDOWN AND HYSTERESIS If an overtemperature condition occurs, the power outputs are tri-stated (latched-OFF) and the fault status flag is SET to logic LOW. To reset from this condition, D1 must change from logic HIGH to logic LOW, or D2 must change from logic LOW to logic HIGH. When reset, the output stage switches ON again, provided that the junction temperature is now below the overtemperature threshold limit minus the hysteresis. Note Resetting from the fault condition will clear the fault status flag.

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Figure 24. PCB Test Layout

Analog Integrated Circuit Device Data Freescale Semiconductor 27 33887 PACKAGING PACKAGING DIMENSIONS PACKAGING DIMENSIONS Important For the most current revision of the package, visit www.freescale.com and perform a keyword search on the 98A drawing number below DH SUFFIX VW SUFFIX 20-PIN HSOP PLASTIC PACKAGE 98ASH70273A ISSUE E

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Analog Integrated Circuit Device Data Freescale Semiconductor 29 33887 PACKAGING PACKAGING DIMENSIONS PNB (Pb-FREE) SUFFIX 36-PIN PQFN Pb-Free PACKAGE 98ASA10583D ISSUE C

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PNB (Pb-FREE) SUFFIX 36-PIN PQFN Pb-Free PACKAGE 98ASA10583D ISSUE C

Analog Integrated Circuit Device Data Freescale Semiconductor 31 33887 PACKAGING PACKAGING DIMENSIONS DWB SUFFIX EK SUFFIX (PB-FREE) 54-PIN SOICW EXPOSED PAD PLASTIC PACKAGE 98ASA10506D ISSUE C

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EK SUFFIX (PB-FREE) 54-PIN SOICW EXPOSED PAD PLASTIC PACKAGE 98ASA10506D ISSUE C

application, and packaging information is provided in the data sheet. The MC33887 is offered in a 20 pin HSOP exposed pad, single die package. simulation according to the standards listed below. 1.Per JEDEC JESD51-2 at natural convection, still air condition. 2.2s2p thermal test board per JEDEC JESD51-5 and JESD51-7. Figure 25. Thermal Land Pattern for Direct Thermal the 33887 device data sheet. Table 7. Thermal Performance Comparison

20 Terminal HSOP-EP

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Figure 26. Thermal Test Board

33887 Pin Connections

Table 8. Thermal Resistance Performance

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REVISION HISTORY

10.0 7/2005 • Added Thermal Addendum & Converted to Freesc ale format, Revised PQFN drawing, made several minor spelling correction. Added 33887A 11.0 11/2006 • Updated Ordering information block with new epp information

• Changed the supply/ operating voltage from 40 V to 28 V
• Updated all package drawings to the current revision
• Adjusted to match device performance characteristics
• Updated the document to the prev ailing Freescale form and style
• Removed Peak Package Reflow Temperature Duri ng Reflow (solder reflow) parameter from Maximum Ratings on page 7.
• Added note (8)
• Added MCZ33887EK/R2 to the Ordering Information on Page 1
• Removed the 33887A from the data sheet and dele ted Product Variation section now that is no longer needed. 12.0 1/2007 • Changed the third paragraph of the introduction on page 1
• Altered feature number 1 on page 1
• Added feature number 2 on page 1
• Changed Maximum Supply Voltage (1) to 0.3 to 40 V
• Added note (1)
• Changed note (16)
• Added a third paragraph to Positive Power Supply (V+) on page 21
• R e p l a c e d Figure 20, Figure 21, and Figure 22 with updated information. 13.0 10/2008 • Added Part Number MC33887AVW/R2 to Ordering Information Table on page 1.

Rev. 13.0 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”, must be validated for each customer application by customer’s technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc., 2007 - 2008. All rights reserved. RoHS-compliant and/or Pb-free versions of Freescale products have the functionality and electrical characteristics of their non-RoHS-compliant and/or non-Pb-free counterparts. For further information, see http://www.freescale.com or contact your Freescale sales representative. For information on Freescale’s Environmental Products program, go to http:// www.freescale.com/epp. How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. Technical Information Center, EL516

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