33886 FREESCALE | Alldatasheet
Document overview
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Technical content
Features
- 5 . 0 V to 40 V Continuous Operation
- 1 2 0 mΩ RDS(ON) H-Bridge MOSFETs
- T T L / CMOS Compatible Inputs
- PWM Frequencies up to 10 kHz
- Active Current Limiting via Internal Constant OFF-Time PWM (with Temperature-Dependent Threshold Reduction)
- Output Short Circuit Protection
- Undervoltage Shutdown
- Fault Status Reporting
- Pb-Free Packaging Designated by Suffix Code VW
Figure 1. 33886 Simplified Application Diagram
ORDERING INFORMATION
Range (TA) Package MC33886DH/R2 - 40°C to 125°C 20 HSOP MC33886VW/R2 5.0 V MOTOR MCU OUT2 OUT1 V+CCP AGND FS IN1 IN2 33886 IN OUT OUT OUT OUT PGND
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Figure 2. 33886 Simplified Internal Block Diagram
Figure 3. 33886 Pin Connections Table 1. 33886 Pin Definitions A functional description of each pin can be found in the Functional Pin Description section beginning on page 15. 1 AGND Analog Ground Low-current analog signal ground.
2 FS Fault Status for H-
Open drain active Low Fault Status output requiring a pull-up resistor to 5.0 V. 3 IN1 Logic Input Control 1 True logic input control of OUT1 (i.e., IN1 logic High = OUT1 logic High). 4, 5, 16 V+ Positive Power Supply Positive supply connections. 6, 7 OUT1 H-Bridge Output 1 Output 1 of H-Bridge. 8, 20 DNC Do Not Connect Either do not connect (leave floating) or connect these pins to ground in the application. They are test mode pins used in manufacturing only. 9 –12 PGND Power Ground Device high-current power ground. D2 is logic Low, both outputs are tri-stated. 14, 15 OUT2 H-Bridge Output 2 Output 2 of H-Bridge. 17 CCP Charge Pump Capacitor External reservoir capacitor connection for internal charge pump capacitor. D1 is logic High, both outputs are tri-stated. 19 IN2 Logic Input Control 2 True logic input control of OUT2 (i.e., IN2 logic High = OUT2 logic High).
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ELECTRICAL CHARACTERISTICS
Table 2. Maximum Ratings permanent damage to the device.
- Exceeding the input voltage on IN1, IN2, D1, or D2 may cause a malfunction or permanent damage to the device.
- Exceeding the pull-up resistor voltage on the open drain FS pin may cause permanent damage to the device.
- Continuous current capability so lo ng as junction temperature is ≤ 150°C.
- ESD1 testing is performed in accordance with the Human Body Model (C ZAP = 100 pF, RZAP = 1500 Ω).
- ESD2 testing is performed in ac cordance with the Machine Model (CZAP = 200 pF, RZAP = 0 Ω).
- All pins are capable of Human Body Model ESD voltages of ±2000 V with two exceptions pertaining only to the DH suffix package: (1) D2
to PGND is capable of ±1500 V and (2) OUT1 to AGND is capable of ±1000 V.
- The limiting factor is junction temperat ure, taking into account the power dissipation, thermal resistance, and heatsinking.
- Pin soldering temperature limit is for 10 seconds maximum dur ation. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
- Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow
MC33xxxD enter 33xxx), and review parametrics.
- Exposed heatsink pad plus the power and ground pins comprise the main heat conduction paths. The actual RθJB (junction-to-PC board)
values will vary depending on solder thickness and composition and copper trace.
Analog Integrated Circuit Device Data Freescale Semiconductor 5 33886 STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
8.0 V ≤ V+ ≤ 40 V
- Specifications are characterized over the range of 5.0 V ≤ V+ ≤ 28 V. Operation > 28 V will cause some parameters to exceed listed
min/max values. Refer to typical operating curves to extrapolate values for operation > 28 V but ≤ 40 V.
- Inputs IN1, IN2, and D1 have independent internal pull-up current sources.
- The D2 input incorporates an active internal pull-down current sink.
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STATIC ELECTRICAL CHARACTERISTICS POWER OUTPUTS (OUT1, OUT2) Output-ON Resistance (14)
5.0 V ≤ V+ ≤ 28 V, TJ = 25°C
8.0 V ≤ V+ ≤ 28 V, TJ = 150°C
RDS(ON) 120 225 300 mΩ Active Current Limiting Threshold (via Internal Constant OFF-Time PWM) (15) ILIM 5.2 6.5 7.8 A High-Side Short Circuit Detection Threshold ISCH 11 – – A Low-Side Short Circuit Detection Threshold ISCL 8.0 – – A Leakage Current (16) VOUT = V+ VOUT = GND IOUT(leak) 100 200 µA Output FET Body Diode Forward Voltage Drop (17) IOUT = 3.0 A VF – – 2.0 V Switch-OFF Thermal Shutdown Hysteresis TLIM THYS 175 FAULT STATUS (18) Fault Status Leakage Current (19) V FS = 5.0 V I FS(leak) – – 10 µA Fault Status Set Voltage (20) I FS = 300 µA V FS(LOW) – – 1.0 V Notes 14. Output-ON resistance as measured from output to V+ and ground. 15. Product with date codes of December 2002, week 51, will exhibit the values indicated in this table. Product with earlier date codes may exhibit a minimum of 6.0 A and a maximum of 8.5 A. 16. Outputs switched OFF with D1 or D2. 17. Parameter is guaranteed by design but not production tested. 18. Fault Status output is an open drain output requiring a pull-up resistor to 5.0 V. 19. Fault Status Leakage Current is measured with Fault Status High and not set. 20. Fault Status Set Voltage is measured with Fault Status Low and set with I FS = 300 µA. reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Analog Integrated Circuit Device Data Freescale Semiconductor 7 33886 DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 4. Dynamic Electrical Characteristics reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
- The outputs can be PWM controlled from an external source. This is typically done by holding one input high while applying a PWM
frequency. Refer to Typical Switching Waveforms, Figures 10 through 17, pp. 10–11.
- The Maximum Switching Frequency during active current limiting is internally implemented. The internal control produces a constant
OFF-time PWM of the output. The output load current effects the Maximum Switching Frequency.
- Output Delay is the time duration from the midpoint of the IN 1 or IN2 input signal to the 10% or 90% point (dependent on the transition
the 10% point of the output response signal. See Figure 4, page 8.
- Rise Time is from the 10% to the 90% level and Fall Time is from the 90% to the 10% level of the output signal. See Figure 6, page 8.
- Parameter is guaranteed by design but not production tested.
- Disable Delay Time is the time duration from the midpoint of the D (disable) input signal to 10% of the output tri-state response. See
- Increasing currents will become limited at I LIM. Hard shorts will breach the ISCH or ISCL limit, forcing the output into an immediate tri-
latch-OFF will occur. See Figure 7, page 8.
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Figure 4. Output Delay Time Figure 5. Disable Delay Time Figure 6. Output Switching Time Figure 7. Active Current Limiting Versus Temperature (Typical)
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- C h 2 = 2.0 A per division
- L LOAD = 533 µH @ 1.0 kHz
- L LOAD = 530 µH @ 10.0 kHz
- R LOAD = 4.0 Ω
Figure 10. Output Voltage and Current vs. Input Voltage Figure 11. Output Voltage and Current vs. Input Voltage Figure 12. Output Voltage and Current vs. Input Voltage Figure 13. Output Voltage and Current vs. Input Voltage
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Table 5. Truth Table H = High, X = High or Low, and Z = High impedance (all output power transistors are switched off).
- In the case of an undervoltage condition, the outputs tri-st ate and the fault status is set logic Low. Upon undervoltage recovery, fault
status is reset automatically or automatically cleared and the outputs are restored to their original operating condition.
- When a short circuit or overtemperatur e condition is detected, the power outputs are tri-state latched-OFF independent of the input
signals and the fault status flag is set logic Low.
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Figure 20. Typical Quiescent Supply Current Versus V+
Analog Integrated Circuit Device Data Freescale Semiconductor 15 33886 FUNCTIONAL DESCRIPTION INTRODUCTION FUNCTIONAL DESCRIPTION INTRODUCTION Numerous protection and operational features (speed, torque, direction, dynamic braking, and PWM control), in addition to the 5.0 A current capability, make the 33886 a very attractive, cost-effective solution for controlling a broad range of fractional horsepower DC motors. A pair of 33886 devices can be used to control bipolar stepper motors in both directions. In addition, the 33886 can be used to control permanent magnet solenoids in a push-pull variable force fashion using PWM control. The 33886 can also be used to excite transformer primary windings with a switched square wave to produce secondary winding AC currents. As shown in Figure 2, Simplified Internal Block Diagram, page 2, the 33886 is a fully protected monolithic H-Bridge with Fault Status reporting. For a DC motor to run the input conditions need be as follows: D1 input logic Low, D2 input logic High, FS flag cleared (logic High), with one IN logic Low and the other IN logic High to define output polarity. The 33886 can execute dynamic braking by simultaneously turning on either both high-side MOSFETs or both low-side MOSFETs in the output H-Bridge; e.g., IN1 and IN2 logic High or IN1 and IN2 logic Low. The 33886 outputs are capable of providing a continuous DC load current of 5.0 A from a 40 V V+ source. An internal charge pump supports PWM frequencies up to 10 kHz. An external pull-up resistor is required for the open drain FS pin for fault status reporting. Two independent inputs (IN1 and IN2) provide control of the two totem-pole half-bridge outputs. Two disable inputs (D1 and D2) are for forcing the H-Bridge outputs to a high impedance state (all H-Bridge switches OFF). The 33886 has undervoltage shutdown with automatic recovery, active current limiting, output short-circuit latch- OFF, and overtemperature latch-OFF. An undervoltage shutdown, output short circuit latch-OFF, or overtemperature latch-OFF fault condition will cause the outputs to turn OFF (i.e., become high impedance or tri-stated) and the fault output flag to be set Low. Either of the Disable inputs or V+ must be “toggled” to clear the fault flag. The short circuit / overtemperature shutdown scheme is unique and best described as using a junction temperature- dependent active current “fold back” protection scheme. When a short circuit condition is experienced, the current limited output is “ramped down” as the junction temperature increases above 160°C, until at 175°C the current has decreased to about 2.5 A. Above 175°C, overtemperature shutdown (latch-OFF) occurs. This feature allows the device to remain in operation for a longer time with unexpected loads, while still retaining adequate protection for both the device and the load. FUNCTIONAL PIN DESCRIPTION POWER/ANALOG GROUNDS (PGND AND AGND) Power and analog ground pins. The power and analog ground pins should be connected together with a very low impedance connection. POSITIVE POWER SUPPLY (V+) V+ pins are the power supply inputs to the device. All V+ pins must be connected together on the printed circuit board with as short as possible traces offering as low impedance as possible between pins. V+ pins have an undervoltage threshold. If the supply voltage drops below a V+ undervoltage threshold, the output power stage switches to a tri-state condition and the fault status flag is set and the Fault Status pin voltage switched to a logic Low. When the supply voltage returns to a level that is above the threshold, the power stage automatically resumes normal operation according to the established condition of the input pins and the fault status flag is automatically reset logic High. FAULT STATUS (FS) This pin is the device fault status output. This output is an active Low open drain structure requiring a pull-up resistor to 5.0 V. Refer to Table 5, Truth Table, page 12. LOGIC INPUT 1, 2 AND DISABLE1, 2 (IN1, IN2, D1, AND D2) These pins are input control pins used to control the outputs. These pins are 5.0 V CMOS-compatible inputs with hysteresis. The IN1 and IN2 independently control OUT1 and OUT2, respectively. D1 and D2 are complimentary inputs used to tri-state disable the H-Bridge outputs. When either D1 or D2 is set (D1 = logic High or D2 = logic Low) in the disable state, outputs OUT1 and OUT2 are both tri-state disabled; however, the rest of the device circuitry is fully operational and the supply IQ (standby) current is reduced to a few milliamperes. Refer to Table 5, Truth Table, and Static Electrical Characteristics table, page 5.
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FUNCTIONAL PIN DESCRIPTION H-BRIDGE OUTPUT 1, 2 (OUT1 AND OUT2) These pins are the outputs of the H-Bridge with integrated output FET body diodes. The bridge output is controlled using the IN1, IN2, D1, and D2 inputs. The outputs have active current limiting above 6.5 A. The outputs also have thermal shutdown (tri-state latch-OFF) with hysteresis as well as short circuit latch-OFF protection. A disable timer (time t b) incorporated to detect currents that are higher than active current limit is activated at each output activation to facilitate detecting hard output short conditions (see Figure 9, page 9). CHARGE PUMP CAPACITOR (CCP) Charge pump output pin. A filter capacitor (up to 33 nF) can be connected from the CCP pin and PGND. The device can operate without the external capacitor, although the CCP capacitor helps to reduce noise and allows the device to perform at maximum speed, timing, and PWM frequency.
Analog Integrated Circuit Device Data Freescale Semiconductor 17 33886 FUNCTIONAL DEVICE OPERATION FUNCTIONAL PIN DESCRIPTION FUNCTIONAL DEVICE OPERATION SHORT CIRCUIT PROTECTION If an output short circuit condition is detected, the power outputs tri-state (latch-OFF) independent of the input (IN1 and IN2) states, and the fault status output flag is set logic Low. If the D1 input changes from logic High to logic Low, or if the D2 input changes from logic Low to logic High, the output bridge will become operational again and the fault status flag will be reset (cleared) to a logic High state. The output stage will always switch into the mode defined by the input pins (IN1, IN2, D1, and D2), provided the device junction temperature is within the specified operating temperature. ACTIVE CURRENT LIMITING The maximum current flow under normal operating conditions is internally limited to ILIM (5.2 A to 7.8 A). When the maximum current value is reached, the output stages are tri-stated for a fixed time (t a) of 20 µs typical. Depending on the time constant associated with the load characteristics, the current decreases during the tri-state duration until the next output ON cycle occurs (see Figures 9 and 12, page 9 and page 10, respectively). The current limiting threshold value is dependent upon the device junction temperature. When -40°C < TJ < 160°C, ILIM is between 5.2 A and 7.8 A. When TJ exceeds 160°C, the ILIM current decreases linearly down to 2.5 A typical at 175°C. Above 175°C the device overtemperature circuit detects TLIM and overtemperature shutdown occurs (see Figure 7, page 8). This feature allows the device to remain operational for a longer time but at a regressing output performance level at junction temperatures above 160°C. OVERTEMPERATURE SHUTDOWN AND HYSTERESIS If an overtemperature condition occurs, the power outputs are tri-state (latched-OFF) independent of the input signals and the fault status flag is set logic Low. To reset from this condition, D1 must change from logic High to logic Low, or D2 must change from logic Low to logic High. When reset, the output stage switches ON again, provided that the junction temperature is now below the overtemperature threshold limit minus the hysteresis. Note Resetting from the fault condition will clear the fault status flag. MAIN DIFFERENCES COMPARED TO MC33186DH1
- COD pin has been removed. Pin 8 is now a Do Not Connect (DNC) pin.
- Pin 20 is no longer connected in the 20 HSOP package. It is now a DNC pin.
- R DS(ON) max at TJ = 150°C is now 225 mΩ per each output transistor.
- Maximum temperature opera tion is now 160°C, as minimum thermal shutdown temperature has increased.
- Current regulation limiting foldback is implemented above 160°C TJ.
- Thermal resistance junction to case has been increased from ~2.0°C/W to ~5.0°C/W.
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(see Figure 21); grid array of 24 vias 0.3 mm in diameter. Figure 21. PCB Test Layout soldered on to the test PCB described in Figure 21. Figure 22. 33886 Thermal Response
Figure 23. 33886 Typical Application Schematic
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Important For the most current revision of the package, visit www.freescale.com and perform a keyword search on 98ASH70702A listed below. SEATING PLANE DATUM PLANE BOTTOM VIEW A X 45 E D h e 18X BMbbb C 1110 /C0095 NOTES: 1. CONTROLLING DIMENSION: MILLIMETER. 2. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DATUM PLANE –H– IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.150 PER SIDE. DIMENSIONS D AND E1 DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE –H–. 5. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 TOTAL IN EXCESS OF THE b DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. DATUMS –A– AND –B– TO BE DETERMINED AT DATUM PLANE –H–. 7. DIMENSION D DOES NOT INCLUDE TIEBAR PROTRUSIONS. ALLOWABLE TIEBAR PROTRUSIONS ARE 0.150 PER SIDE. ÇÇÇ ÇÇÇ ÉÉÉ ÉÉÉ SECTION W–W b c AMaaa C EXPOSED HEATSINK AREA A B C H PIN ONE ID 10X Y GAUGE PLANE DETAIL Y (1.600) L W W /C0113bbb C DIM MIN MAX MILLIMETERS A 3.000 3.400 A1 0.100 0.300 A2 2.900 3.100 A3 0.00 0.100 D 15.800 16.000 D1 11.700 12.600 D2 0.900 1.100 E 13.950 14.450 E1 10.900 11.100 E2 2.500 2.700 E3 6.400 7.200 E4 2.700 2.900 L 0.840 1.100 L1 0.350 BSC b 0.400 0.520 b1 0.400 0.482 c 0.230 0.320 c1 0.230 0.280 e 1.270 BSC h ––– 1.100 /C0113 0 8 aaa 0.200 bbb 0.100 /C0095/C0095 e/2 DH SUFFIX VW (Pb-FREE) SUFFIX 20-PIN HSOP PLASTIC PACKAGE 98ASH70702A ISSUE A
5.0 A H-BRIDGE
electrical, application, and packaging information is provided in the data sheet. The MC33186 is offered in a 20 pin HSOP exposed pad, single die package. simulation according to the standards listed below. 1.Per JEDEC JESD51-2 at natural convection, still air condition. 2.2s2p thermal test board per JEDEC JESD51-5 and JESD51-7. remaining surfaces insulated. Figure 24. Thermal Land Pattern for Direct Thermal the 33886 device data sheet. Table 6. Thermal Performance Comparison
20 Terminal HSOP-EP
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Figure 25. Thermal Test Board
33886 Pin Connections
Table 7. Thermal Resistance Performance
Figure 26. Device on Thermal Test Board RθJA Figure 27. Transient Thermal Resistance RθJA
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REVISION HISTORY
REVISION DATE DESCRIPTION OF CHANGES 7.0 7/2005 • Implemented Revision History page
- Added Thermal Addendum
- Converted to Freescale format 8.0 2/2007 • Updated data sheet format
- Removed Peak Package Reflow Temperature Duri ng Reflow (solder reflow) parameter from Maximum Ratings on page 4. Added note with instructions to obtain this information from www.freescale.com.
Rev 8.0 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”, must be validated for each customer application by customer’s technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc., 2007. All rights reserved. RoHS-compliant and/or Pb-free versions of Freescale products have the functionality and electrical characteristics of their non-RoHS-compliant and/or non-Pb-free counterparts. For further information, see http://www.freescale.com or contact your Freescale sales representative. For information on Freescale’s Environmental Products program, go to http:// www.freescale.com/epp. How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. Technical Information Center, EL516
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