33880 FREESCALE | Alldatasheet

Document overview

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Technical content

Features

  • Designed to Operate 5.5 V < VPWR < 24.5 V
  • 8-Bit SPI for Control and Fault Reporting, 3.3 V/ 5.0 V Compatible
  • Outputs Are Current Limited (0.8 A to 2.0 A) to Drive Incandescent Lamps
  • Output Voltage Clamp Is +45 V (Typical) (Low-Side Drive) and -

20 V (Typical) (High-Side Drive) During Inductive Switching

  • Internal Reverse Battery Protection on V PWR
  • Loss of Ground or Supply Will Not Energize Loads or Damage IC
  • Maximum 5.0 µA IPWR Standby Current at 13 V VPWR up to 95°C
  • R DS(ON) of 0.55 Ω at 25°C Typical
  • Short Circuit Detect and Current Limit with Automatic Retry
  • Independent Overtem perature Protection
  • 32-Pin SOICW Has Pins 8, 9, 24, and 25 Grounded for Thermal Performance
  • Pb-Free Packaging Designated by Suffix Code EG and EW

Figure 1. 33880 Simplified Application Diagram

ORDERING INFORMATION

Range (TA) Package MC33880DW/R2 -40°C to 125°C

28 SOICW

32 SOICW

EW SUFFIX (PB-FREE) 98ARH99137A 32-PIN SOICW All Output Switches are High- or Low-Side Configurable V PWR 33880 SPI I/O PWM MCU MOT High-Side H-Bridge Low-Side 5.0 V 5.0 V V S EN VDD VPWR GND CS SCLK DI DO IN5 IN6

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Figure 2. 33880 Simplified Internal Block Diagram

Figure 3. 98ASB42345B SOICW 28-Pin Connections Table 1. SOICW 28-Pin Definitions 2 VDD Logic supply voltage. Logic supply must be switched off for low current mode (VDD below 3.9 V). 3, 4 S8 Output 8 MOSFET source pins. 5 D8 Output 8 MOSFET drain pin. 6 S2 Output 2 MOSFET source pin. 7 D2 Output 2 MOSFET drain pin. 8 S1 Output 1 MOSFET source pin. 9 D1 Output 1 MOSFET drain pin. 10 D6 Output 6 MOSFET drain pin. 11 S6 Output 6 MOSFET source pin. 12 IN6 PWM direct control input pin for output 6. IN6 is “OR” with SPI bit. 13 EN Enable input. Allows control of outputs. Active high. 14 SCLK SPI control clock input pin. 15 DI SPI control data input pin from MCU to the 33880. Logic [1] activates output. 16 CS SPI control chip select input pin from MCU to the 33880. Logic [0] allows data to be transferred in. 17 IN5 PWM direct control input pin for output 5. IN5 is “OR” with SPI bit. 18 S5 Output 5 MOSFET source pin. 19 D5 Output 5 MOSFET drain pin. 20 D3 Output 3 MOSFET drain pin. 21 S3 Output 3 MOSFET source pin. 22 D4 Output 4 MOSFET drain pin. 23 S4 Output 4 MOSFET source pin. 24 D7 Output 7 MOSFET drain pin. 25, 26 S7 Output 7 MOSFET source pins. 27 VPWR Power supply pin to the 33880. VPWR has internal reverse battery protection. 28 DO SPI control data output pin from the 33880 to the MCU. DO = 0 no fault, DO = 1 specific output has fault.

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Figure 4. 98ARH99137A SOICW 32-Pin Connections Table 2. SOICW 32-Pin Definitions 2 VDD Logic supply voltage. Logic supply must be switched off for low current mode (VDD below 3.9 V). 3, 4 S8 Output 8 MOSFET source pins. 5 D8 Output 8 MOSFETdrain pin. 6 S2 Output 2 MOSFET source pin. 7 D2 Output 2 MOSFET drain pin. 10 S1 Output 1 MOSFET source pin. 11 D1 Output 1 MOSFET drain pin. 12 D6 Output 6 MOSFETdrain pin. 13 S6 Output 6 MOSFET source pin. 14 IN6 PWM direct control input pin for output 6. IN6 is “OR” with SPI bit. 15 EN Enable input. Allows control of outputs. Active high. 16 SCLK SPI control clock input pin. 17 DI SPI control data input pin from MCU to the 33880. Logic [1] activates output. 18 CS SPI control chip select input pin from MCU to the 33880. Logic [0] allows data to be transferred in. 19 IN5 PWM direct control input pin for output 5. IN5 is “OR” with SPI bit. 20 S5 Output 5 MOSFET source pin. 21 D5 Output 5 MOSFET drain pin. 22 D3 Output 3 MOSFET drain pin. 23 S3 Output 3 MOSFET source pin. 26 D4 Output 4 MOSFET drain pin. 27 S4 Output 4 MOSFET source pin. 28 D7 Output 7 MOSFET drain pin. 29, 30 S7 Output 7 MOSFET source pins. 31 VPWR Power supply pin to the 33880. VPWR has internal reverse battery protection. 32 DO SPI control data output pin from the 33880 to the MCU. DO = 0 no fault, DO = 1 specific output has fault.

Analog Integrated Circuit Device Data Freescale Semiconductor 5 33880

ELECTRICAL CHARACTERISTICS

Table 3. Maximum Ratings permanent damage to the device.

28 SOIC, Case 751F-05

32 SOIC, Case 1324-02

  1. Exceeding these limits may cause malf unction or permanent damage to the device.
  2. Configured as low-side driver wi th 300 mA load as current limit.
  3. Configured as high-side driver with 300 mA load as current limit.
  4. With outputs OFF and 10 mA of test current for low-side driver, 30 mA test current for high-side driver.
  5. Maximum output clamp energy capability at 150 °C junction temperature using single non-repetitive pulse method.
  6. ESD1 testing is performed in accordance with the Human Body Model (C ZAP = 100 pF, RZAP = 1500 Ω), and ESD2 testing is performed

in accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 Ω).

  1. Maximum power dissipation with no heatsink used.

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STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 4. Static Electrical Characteristics noted. Typical values, where applicable, reflect the parameter’s approximate average value with VPWR = 13 V, TA = 25°C.

  1. Output Fault Detect Thresholds with outputs programmed OFF. Output fault detect threshold are the same for output open and shorts.
  2. This parameter is guaranteed by design but is not production tested.

Analog Integrated Circuit Device Data Freescale Semiconductor 7 33880 STATIC ELECTRICAL CHARACTERISTICS DIGITAL INTERFACE Input Logic Voltage Thresholds (10) VINLOGIC 0.8 – 2.2 V IN5, IN6, and EN Input Logic Current IN5, IN6, EN = 0 V IIN5, IN6, EN -10 – 10 µA IN5, IN6, and EN Pull-Down Current

0.8 V to VDD

IIN5, IN6, EN 30 45 100 µA SCLK, DI, and Tri-State DO Input

0 V to VDD

ISCK, SI, TriSO -10 – 10 µA CS Input Current CS = VDD IICS -10 – 10 µA CS Pull-Up Current CS = 0 V IICS -30 – -100 µA DO High-State Output Voltage IDO-HIGH = -200 µA VDOHIGH VDD - 0.8 – VDD V DO Low-State Output Voltage IDO-HIGH = 1.6 mA VDOLOW – – 0.4 V Input Capacitance on SCLK, DI, Tri-State DO, IN5, IN6, EN (11) CIN – – 20 pF Notes 10. Upper and lower logic threshold voltage levels apply to DI, CS, SCLK, IN5, IN6, and EN. 11. This parameter is guaranteed by design but is not production tested. Table 4. Static Electrical Characteristics (continued) noted. Typical values, where applicable, reflect the parameter’s approximate average value with VPWR = 13 V, TA = 25°C.

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DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 5. Dynamic Electrical Characteristics noted. Typical values, where applicable, reflect the parameter’s approximate average value with VPWR = 13 V, TA = 25°C.

  1. Output Rise and Fall time res pectively measured across a 620 Ω resistive load at 10 to 90 percent and 90 to 10 percent voltage points.
  2. Output turn ON and OFF delay time measured from 50 percent rising edge of CS to 90 and 10 percent of initial voltage.
  3. Duration of fault before fault bit is set. Duration between access times must be greater than 300 µs to read faults.
  4. This parameter is guaranteed by design but is not production tested.
  5. Rise and Fall time of incoming DI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
  6. Time required for output status data to be available for use at DO pin.
  7. Time required for output status data to be terminated at DO pin
  8. Time required to obtain valid data out from DO following the rise of SCLK.

Analog Integrated Circuit Device Data Freescale Semiconductor 9 33880 Figure 5. SPI Timing Diagram Figure 6. Valid Data Delay Time Figure 7. Enable and Disable Time Test Circuit Figure 8. Switching Time Test Circuit

0.7 VDD

0.2 VDD

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Figure 9. Valid Data Delay Time and Valid Time Figure 10. Enable and Disable Time Waveforms Figure 11. Turn-ON/OFF Waveforms

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TYPICAL ELECTRICAL CHARACTERISTICS Figure 18. Open Load Detect Current vs. Temperature Figure 19. Open Load Detect Current vs. VPWR Figure 20. Sleep State Output Leakage vs. VPWR

Analog Integrated Circuit Device Data Freescale Semiconductor 13 33880 FUNCTIONAL DESCRIPTION INTRODUCTION FUNCTIONAL DESCRIPTION INTRODUCTION The 33880 is an eight-output hardware configurable power switch with 8-bit serial control. The 33880 incorporates SMARTMOS™ 5 technology with CMOS logic, bipolar/MOS analog circuitry, and independent double diffused DMOS power output transistors. Many benefits are realized as a direct result of using this mixed technology. A simplified internal block diagram of the 33880 is shown in Figure 2, page 2. The 33880 device uses high-efficiency updrain power DMOS output transistors exhibiting low drain-to-source ON resistance values (RDS(ON) ≤ 0.55 Ω at 25°C) and dense CMOS control logic. All outputs have independent voltage clamps to provide fast inductive turn-off and transient protection. Operational bias currents of less than 4.0 mA on VDD and 12 mA on VPWR with any combination of outputs ON are a direct result of using SMARTMOS™ 5 technology. FUNCTIONAL PIN DESCRIPTION CHIP SELECT (CS) The system MCU selects the 33880 to communicate through the use of the CS pin. Whenever the pin is in a logic low state, data can be transferred from the MCU to the 33880 device and vice versa. Clocked-in data from the MCU is transferred from the 33880 shift register and latched into the power outputs on the rising edge of the CS signal. On the falling edge of the CS signal, output status information is transferred from the power outputs status register into the device's shift register. The falling edge of CS enables the DO output driver. Whenever the CS pin goes to a logic low state, the DO pin output is enabled, thereby allowing information to be transferred from the 33880 to the MCU. To avoid any spurious data, it is essential the high-to-low transition of the CS signal occurs only when SCLK is in a logic low state. SYSTEM CLOCK (SCLK) The system clock pin (SCLK) clocks the internal shift registers of the 33880. The serial data input (DI) is latched into the input shift register on the falling edge of the SCLK. The serial data output pin (DO) shifts data out of the shift register on the rising edge of the SCLK signal. False clocking of the shift register must be avoided to guarantee validity of data. It is essential the SCLK pin be in a logic low state whenever chip select pin ( CS) makes any transition. For this reason, it is recommended the SCLK pin is commanded to a logic low state when the device is not accessed (CS in logic high state). When the CS is in a logic high state, any signal at the SCLK and DI pin is ignored and the DO is tri-stated (high impedance). DATA INPUT (DI) This pin is used for serial instruction data input. DI information is latched into the input register on the falling edge of SCLK. A logic high state present on DI will program a specific output on. The specific output will turn on with the rising edge of the CS signal. Conversely, a logic low state present on the DI pin will program the output off. The specific output will turn off with the rising edge of the CS signal. To program the eight outputs of the 33880 device on or off, enter the DI pin beginning with Output 8, followed by Output 7, Output 6, and so on to Output 1. For each falling edge of the SCLK while CS is logic low, a data bit instruction (on or off) is loaded into the shift register per the data bit DI state. Eight bits of entered information fills the shift register. To preserve data integrity, do not transition DI as SCLK transitions from a high to low logic state. DATA OUTPUT (DO) The serial data output (DO) pin is the output from the shift register. The DO pin remains tri-state until the CS pin goes to a logic low state. All faults on the 33880 device are reported as logic [1] through the DO data pin. Regardless of the configuration of the driver, open loads and shorted loads are reported as logic [1]. Conversely, normal operating outputs with non-faulted loads are reported as logic [0]. The first positive transition of SCLK will make output eight status available on DO pin. Each successive positive clock will make the next output status available. The DI/DO shifting of data follows a first-in-first-out protocol with both input and output words transferring the most significant bit (MSB) first. ENABLE (EN) The EN pin on the 33880 device either enables or disables the internal charge pump. The EN pin must be high for this device to enhance the gates of the output drivers, perform fault detection, and reporting. Active outputs during a low transition of the EN pin will become active again when the EN transitions high. If this feature is not required, it is recommended the EN pin be connected to VDD. COMMAND INPUT (IN5 AND IN6) The IN5 and IN6 pins command inputs allowing outputs five and six to be used in PWM applications. IN5 and IN6 pins are ORed with the SPI communication input. For SPI control of outputs five and six, the IN5 and IN6 pins should be grounded or held low by the microprocessor. In the same manner, when using the PWM feature the SPI port must command the outputs off. Maximum PWM frequency for each output is 2.0 kHz.

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LOGIC POWER (VDD) The VDD pin supplies logic power to the 33880 device and is used for power-on reset (POR). To achieve low standby current on VPWR supply, power must be removed from the VDD pin. The device will be in reset with all drivers off when VDD is below 3.9 VDC. OPEN DRAIN OUTPUT (D1 – D8) The D1 – D8 pins are the open drain outputs of the 33880. For High-Side Drive configurations, the drain pins are connected to battery supply. In Low-Side Drive configurations, the drain pins are connected to the low side of the load. All outputs may be configured individually as desired. When Low-Side Drive is used, the 33880 limits the positive transient for inductive loads to 45 SOURCE OUTPUT (S1 – S8) The S1 – S8 pins are the source outputs of the 33880. For High-Side Drive configurations, the source pins are connected directly to the load. In Low-Side Drive configurations the source is connected to ground. All outputs may be configured individually as desired. When High-Side drive is used, the 33880 will limit the negative transient for inductive loads to -20

Figure 21. SPI Interface with Microcontroller Figure 22. 33880 SPI System Daisy Chain Figure 23. Parallel Input SPI Control

8 Outputs 8 Outputs 8 Outputs

8 Outputs

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Figure 24. Data Transfer Timing

Analog Integrated Circuit Device Data Freescale Semiconductor 17 33880 FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES POWER CONSUMPTION The 33880 device has been designed with one sleep and one operational mode. In the sleep mode (VDD ≤ 2.0 V), the current consumed by the VPWR pin is less than 25 µA. To place the 33880 in the sleep mode, turn all outputs off, then remove power from VDD and the EN (enable) input pin. Prior to removing power from the device, it is recommended all control inputs from the microcontroller are low. During normal operation, 4.0 mA will be drawn from the VDD supply and 12 mA from the VPWR supply. PARALLELING OF OUTPUTS Using MOSFETs as output switches allows the connection of any combination of outputs together. RDS(ON) of MOSFETs have an inherent positive temperature coefficient, providing balanced current sharing between outputs without destructive operation. The device can even be operated with all outputs tied together. This mode of operation may be desirable in the event the application requires lower power dissipation or the added capability of switching higher currents. Performance of parallel operation results in a corresponding decrease in R DS(ON) while the outputs OFF open load detect currents and the output current limits increase correspondingly (by a factor of eight if all outputs are paralleled). Paralleling outputs from two or more different IC devices are possible but not recommended. FAULT LOGIC OPERATION Fault logic of the 33880 device has been greatly simplified over other devices using SPI communications. As command word one is being written into the shift register, a fault status word is being simultaneously written out and received by the MCU. Regardless of the configuration, with no outputs faulted, all status bits being received by the MCU will be zero. When outputs are faulted (off state open circuit or on state short circuit / overtemperature), the status bits being received by the MCU will be one. The distinction between open circuit fault and short circuit / overtemperature is completed via the command word. For example, when a zero command bit is sent and a one fault is received in the following word, the fault is open / short-to-battery for high-side drive or open / short to ground for low-side drive. In the same manner, when a one command bit is sent and a one fault is received in the following word the fault is a short-to-ground / overtemperature for high-side drive or short-to-battery / overtemperature for low-side drive. The timing between two write words must be greater than 300 µs to allow adequate time to sense and report the proper fault status. SPI INTEGRITY CHECK It is recommended that one check the integrity of the SPI communication with the initial power-up of the VDD and EN pins. After initial system start-up or reset, the MCU will write one 16-bit pattern to the 33880. The first eight bits read by the MCU will be the fault status of the outputs, while the second eight bits will be the first byte of the bit pattern. Bus integrity is confirmed by the MCU receiving the same bit pattern it sent. Please note that the second byte the MCU sends to the device is the command byte and will be transferred to the outputs with rising edge of CS. OVERTEMPERATURE FAULT Overtemperature detect and shutdown circuits are specifically incorporated for each individual output. The shutdown following an overtemperature condition is independent of the system clock or any other logic signal. Each independent output shuts down at 155°C to 185°C. When an output shuts down due to an overtemperature fault, no other outputs are affected. The MCU recognizes the fault by a one in the fault status register. After the 33880 device has cooled below the switch point temperature and 15°C hysteresis, the output will activate unless told otherwise by the MCU via SPI to shut down. OVERVOLTAGE FAULT An overvoltage condition on the VPWR pin will cause the device to shut down all outputs until the overvoltage condition is removed. When the overvoltage condition is removed, the outputs will resume their previous state. This device does not detect an overvoltage on the VDD pin. The overvoltage threshold on the VPWR pin is specified as 25 V to 30 V with 1.0 V typical hysteresis. A VPWR overvoltage detect is global, causing all outputs to be turned OFF. OUTPUT OFF OPEN LOAD FAULT An output OFF open load fault is the detection and reporting of an open load when the corresponding output is disabled (input bit programmed to a logic low state). The output OFF open load fault is detected by comparing the drain-to-source voltage of the specific MOSFET output to an internally generated reference. Each output has one dedicated comparator for this purpose. An output off open load fault is indicated when the drain- to-source voltage is less than the output threshold voltage (VTHRES) of 1.0 V to 3.0 V. Hence, the 33880 will declare the load open in the OFF state when the VDS is less than 1.0 V. This device has an internal 650 µA current source connected from drain to source of the output MOSFET. This prevents either configuration of the driver from having a floating output. To achieve low sleep mode quiescent currents, the open load detect current source of each driver is switched off when VDD is removed. During output switching, especially with capacitive loads, a false output OFF open load fault may be triggered. To prevent this false fault from being reported, an internal fault filter of 100 µs to 300 µs is incorporated. A false fault reporting is a function of the load impedance, RDS(ON) , COUT of the MOSFET, as well as the supply voltage, VPWR. The rising edge of CS triggers the built-in fault delay timer. The timer will time out before the fault comparator is enabled and the fault is detected. Once the condition causing the open load fault is removed, the device will resume normal operation. The open load fault however, will be latched in the output DO register for the MCU to read.

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the device to current limit (linear short).

  1. The device’s output current is monitored in an analog
  2. The device’s output thermal limit is sensed and when

command bit instructs the output off. FS register will resume normal operation. and 9.0 V, the output will operate per the command word. energy to be 50 mJ at 150°C junction temperature per output. Figure 25. Output Voltage Clamping used in serial SPI or parallel SPI with the 33291 and 33298. information, contact Analog Products Division.

On each SPI communication, an 8-bit command word is sent to the 33880 and an 8-bit fault word is received from the 33880. The Most Significant Bit (MSB) is sent and received first (see below). Table 6. Fault Operation Overtemperature Fault reported by Serial Output (DO) pin. Overcurrent DO pin reports short to battery/supply or overcurrent condition. Output ON Open Load Fault Not reported. Output OFF Open Load Fault DO pin reports output OFF open load condition. Overvoltage Total device shutdown at VPWR = 25 V to 30 V. Resumes normal operation with proper voltage. All outputs assuming the previous state upon recovery from overvoltage. upon recovery from overtemperature.

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For the most current package revision, visit www.freescale.com and perform a keyword search using “98ASB42345B”. DW SUFFIX EG SUFFIX (PB-FREE) 28-PIN PLASTIC PACKAGE 98ASB42345B REV G

Analog Integrated Circuit Device Data Freescale Semiconductor 21 33880 PACKAGING PACKAGE DIMENSIONS PACKAGE DIMENSIONS (CONTINUED) DW SUFFIX EG SUFFIX (PB-FREE) 28-PIN PLASTIC PACKAGE 98ASB42345B REV G

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PACKAGE DIMENSIONS (CONTINUED) DWB SUFFIX EW SUFFIX (PB-FREE) 32-PIN PLASTIC PACKAGE 98ASB42345B REV B

Analog Integrated Circuit Device Data Freescale Semiconductor 23 33880 PACKAGING PACKAGE DIMENSIONS PACKAGE DIMENSIONS (CONTINUED) DWB SUFFIX EW SUFFIX (PB-FREE) 32-PIN PLASTIC PACKAGE 98ASB42345B REV B

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REVISION HISTORY

REVISION DATE DESCRIPTION OF CHANGES 4.0 6/2006 • Implemented Revision History page

  • Converted to Freescale format and adjusted content to prevailing form and style 5.0 6/2007 • Removed MC33880EG/R2 and MC33880EK/R2 from the ordering information and added MCZ33880EG/R2 and MCZ33880EW/R2.
  • Added Peak Package Reflow Temperature During Reflow (5), (6)
  • Updated data sheet to current format.

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