33879

33879_09 FREESCALE | Alldatasheet

Document overview

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• PDF pages: 23

Technical content

Features

• Designed to operate 5.5 V < VPWR < 26.5 V
• 16-Bit SPI for control and fault reporting, 3.3 V / 5.0 V compatible
• Outputs are current limited (0.6 A to 1.2 A) to drive incandescent lamps
• Output voltage clamp, + 45 V (Low Side) and - 20 V (High Side) during inductive switching
• On/Off control of open load detect current (LED application)
• Internal reverse batt ery protection on VPWR
• Loss of ground or supply will not energize loads or damage IC
• Maximum 5.0 μA IPWR standby current at 13 V VPWR
• R DS(ON) of 0.75 Ω at 25°C typical
• Short-circuit detect and current limit with automatic retry
• Independent over-temperature protection
• Pb-free packaging designated by suffix code EK

Figure 1. 33879 Simplified Application Diagram

ORDERING INFORMATION

Range (TA) Package MC33879EK/R2 -40°C to 125°C 32 SOICW-EPMCZ33879EK/R2 MCZ33879AEK/R2 VBAT M VBAT VPWR 33879 Low-Side Drive GND EN DI SCLK CS DO IN5 IN6 MCU MOSI SCLK CS MISO PWM1 PWM2 VDD VPWR +5.0 V H-Bridge Configuration VBAT High-Side Drive

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Table 1. Device Variations (Optional Table)

Figure 2. 33879 Simplified Internal Block Diagram

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Figure 3. 33879 Pin Connections Table 2. 33879 Pin Definitions A functional description of each pin can be found in the Functional Pin Description section beginning on page 14. 1 GND Ground Ground Digital ground.

2 VDD Input Logic Supply

3 S8 Output Source Output 8 Output 8 MOSFET source pin. Not Connected No internal connection to this pin. 5 D8 Output Drain Output 8 Output 8 MOSFET drain pin. 6 S2 Output Source Output 2 Output 2 MOSFET source pin. 7 D2 Output Drain Output 2 Output 2 MOSFET drain pin. 10 S1 Output Source Output 1 Output 1 MOSFET source pin. 11 D1 Output Drain Output 1 Output 1 MOSFET drain pin. 12 D6 Output Drain Output 6 Output 6 MOSFET drain pin. 13 S6 Output Source Output 6 Output 6 MOSFET source pin. 14 IN6 Input Command Input 6 PWM direct control input pin for output 6. IN6 is “OR” with SPI bit. 15 EN Input Enable Input IC Enable. Active high. With EN low, the device is in Sleep mode. 16 SCLK Clock SPI Clock SPI control clock input pin. 17 DI Input Serial Data Input SPI control data input pin from MCU to the 33879. Logic [1] activates output. 19 IN5 Input Command Input 5 PWM direct control input pin for output 5. IN5 is “OR” with SPI bit. 20 S5 Output Source Output 5 Output 5 MOSFET source pin.

21 D5 Output Drain Output 5 Output 5 MOSFET drain pin. 22 D3 Output Drain Output 3 Output 3 MOSFET drain pin. 23 S3 Output Source Output 3 Output 3 MOSFET source pin. 26 D4 Output Drain Output 4 Output 4 MOSFET drain pin. 27 S4 Output Source Output 4 Output 4 MOSFET source pin. 28 D7 Output Drain Output 7 Output 7 MOSFET drain pin. 29 S7 Output Source Output 7 Output 7 MOSFET source pin. DO = 1 specific output has fault.

33 EP Ground Exposed Pad Device will perform as specified with the Exposed Pad un-terminated

to pin 1 (GND) and system ground. Table 2. 33879 Pin Definitions (continued) A functional description of each pin can be found in the Functional Pin Description section beginning on page 14.

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ELECTRICAL CHARACTERISTICS

Table 3. 33879 Maximum Ratings permanent damage to the device.

1. Exceeding these limits may cause malf unction or permanent damage to the device.
2. Maximum output clamp energy capability at 150 °C junction temperature using single non-repetitive pulse method with I = 350 mA.
3. ESD1 testing is performed in accor dance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω), ESD2 testing is performed in

accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 Ω).

1. Maximum power dissipation at T A = 25°C with no heatsink used.
2. Pin soldering temperature limit is for 10 seconds maximum dura tion. Not designed for immersion soldering. Exceeding these limits may

cause malfunction or permanent damage to the device.

1. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow

and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.

Analog Integrated Circuit Device Data Freescale Semiconductor 7 33879 STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 4. Static Electrical Characteristics Characteristics noted under conditions 3.1 V ≤ VDD ≤ 5.5 V, 5.5 V ≤ VPWR ≤ 18 V, - 40°C ≤ TC ≤ 125°C, unless otherwise noted. Where applicable, typical values reflect the parameter’s approximate average value with VPWR = 13 V, TA = 25°C.

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STATIC ELECTRICAL CHARACTERISTICS POWER OUTPUT Drain-to-Source ON Resistance (IOUT = 0.350 A, VPWR = 13 V) TJ = 125°C TJ = 25°C TJ = -40°C RDS (ON) 0.75 1.4 Ω Output Self Limiting Current High Side and Low Side Configurations IOUT (LIM) 0.6 – 1.2 A Output Fault Detection Voltage Threshold(7) Outputs Programmed OFF VOUT(FLT-TH) 2.5 4.0 4.5 V Output Fault Detection Current @ Threshold, High Side Configuration Outputs Programmed OFF IOUT(FLT-TH) 35 55 90 μA Output Fault Detection Current @ Threshold, Low Side Configuration Outputs Programmed OFF IOUT(FLT-TH) 20 30 60 μA Output OFF Open Load Detection Current, High Side Configuration VDRAIN = 16 V, VSOURCE = 0 V, Outputs Programmed OFF, VPWR = 16 V IOCO 65 100 160 μA Output OFF Open Load Detection Current, Low Side Configuration VDRAIN = 16 V, VSOURCE = 0 V, Outputs Programmed OFF, VPWR =16 V IOCO 40 75 135 μA Output Clamp Voltage Low Side Drive ID = 10 mA VOC (LSD) 40 45 55 V Output Clamp Voltage High Side Drive IS = -10 mA VOC (HSD) -15 - 20 - 25 V Output Leakage Current High Side and Low Side Configurations VDD = 0 V, VDRAIN = 16 V, VSOURCE = 0 V IOUT (LKG) – – 5.0 μA Output Leakage Current Low Side Configuration VDD = 5.0 V, VDRAIN = 16 V, VSOURCE = 0 V, Open Load Detection Current Disabled IOUT (LKG) – – 5.0 μA Output Leakage Current High Side Configuration VDD = 5.0 V, VDRAIN = 16 V, VSOURCE = 0 V, Open Load Detection Current Disabled IOUT (LKG) – – 20 μA Over-temperature Shutdown(8) TLIM 155 – 185 °C Over-temperature Shutdown Hysteresis(8) TLIM (HYS) 5.0 10 15 °C Notes 7. Output fault detection thresholds with outputs programmed OFF. Output fault detect thresholds are the same for output open and shorts. 8. This parameter is guaranteed by desi gn; however, it is not production tested. Table 4. Static Electrical Characteristics (continued) Characteristics noted under conditions 3.1 V ≤ VDD ≤ 5.5 V, 5.5 V ≤ VPWR ≤ 18 V, - 40°C ≤ TC ≤ 125°C, unless otherwise noted. Where applicable, typical values reflect the parameter’s approximate average value with VPWR = 13 V, TA = 25°C.

Analog Integrated Circuit Device Data Freescale Semiconductor 9 33879 STATIC ELECTRICAL CHARACTERISTICS DIGITAL INTERFACE Input Logic High-voltage Thresholds(9) VIH 0.7 VDD – VDD + 0.3 V Input Logic Low-voltage Thresholds(9) VIL GND - 0.3 – 0.2 VDD V IN5, IN6, EN Input Logic Current IN5, IN6, EN = 0 V I IN5, I IN6, I EN -10 – 10 μA IN5, IN6 Pull-down Current 0.8 to 5.0 V I IN5, I IN6, 30 45 100 μA EN Pull-down Current EN = 5.0 V I EN 20 45 100 μA SCLK, DI Input, Tri-state DO Output 0 to 5.0 V I SCK, I DI, I TRI- DO -10 – 10 μA CS Input Current CS = VDD ICS -10 – 10 μA CS Pull-up Current CS = 0 V ICS -30 – -100 μA CS Leakage Current to VDD CS = 5.0 V, VDD = 0 V ICS(LKG) – – 10 μA DO High State Output Voltage IDO-HIGH = -1.6 mA VDOHIGH VDD - 0.4 – VDD V DO Low State Output Voltage IDO-LOW = 1.6 mA VDOLOW – – 0.4 V Input Capacitance on SCLK, DI, Tri-state DO, IN5, IN6, EN(10) CIN – – 20 pF Notes 9. Upper and lower logic threshold voltage levels apply to DI, CS, SCLK, IN5, IN6, and EN. 10. This parameter is guaranteed by desi gn; however, it is not production tested. Characteristics noted under conditions 3.1 V ≤ VDD ≤ 5.5 V, 5.5 V ≤ VPWR ≤ 18 V, - 40°C ≤ TC ≤ 125°C, unless otherwise noted. Where applicable, typical values reflect the parameter’s approximate average value with VPWR = 13 V, TA = 25°C.

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DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 5. Dynamic Electrical Characteristics Characteristics noted under conditions 3.1 V ≤ VDD ≤ 5.5 V, 5.5 V ≤ VPWR ≤ 18 V, - 40°C ≤ TC ≤ 125°C, unless otherwise noted. Where applicable, typical values reflect the parameter’s approximate average value with VPWR = 13 V, TA = 25°C.

1. Output slew rate respec tively measured across a 620 Ω resistive load at 10 to 90 percent and 90 to 10 percent voltage points.

CL capacitor is connected from Drain or Source output to Ground.

1. Output turn ON and OFF delay time measured from 50 percent rising edge of CS to the beginning of the 10 and 90 percent transition
2. Duration of fault before fault bit is set. Duration between access times must be greater than 300 μs to read faults.

Analog Integrated Circuit Device Data Freescale Semiconductor 11 33879 Figure 4. SPI Timing Diagram

1. Rise and Fall time of incoming DI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
2. Time required for output status data to be available for use at DO pin.
3. Time required for output status data to be terminated at DO pin.
4. Time required to obtain valid data out from DO following the rise of SCLK.

Table 5. Dynamic Electrical Characteristics (continued) Characteristics noted under conditions 3.1 V ≤ VDD ≤ 5.5 V, 5.5 V ≤ VPWR ≤ 18 V, - 40°C ≤ TC ≤ 125°C, unless otherwise noted. Where applicable, typical values reflect the parameter’s approximate average value with VPWR = 13 V, TA = 25°C.

0.7 VDD

0.2 VDD

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TYPICAL ELECTRICAL CHARACTERISTICS Figure 5. Valid Data Delay Time Figure 6. Valid Data Delay Time Figure 7. Enable and Disable Time Waveforms Figure 8. IPWR vs. Temperature Figure 9. Sleep State IPWR vs. Temperature

Analog Integrated Circuit Device Data Freescale Semiconductor 13 33879 TYPICAL ELECTRICAL CHARACTERISTICS Figure 10. Sleep State IPWR vs. VPWR Figure 11. RDS(ON) vs. Temperature at 350 mA Figure 12. RDS(ON) vs. VPWR at 350 mA Figure 13. Open Load Detection Current at Threshold Figure 14. Open Load Detection

1.4 TA = 25°C

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FUNCTIONAL PIN DESCRIPTION FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION CS PIN The system MCU selects the 33879 with which to communicate through the use of the chip select CS pin. Logic low on CS enables the data output (DO) driver and allows data to be transferred from the MCU to the 33879 and vice versa. Data clocked into the 33879 is acted upon on the rising edge of CS. To avoid any spurious data, it is essential the high-to-low transition of the CS signal occur only when SPI clock (SCLK) is in a logic low state. SCLK PIN The SCLK pin clocks the internal shift registers of the 33879. The serial data input (DI) pin is latched into the input shift register on the falling edge of the SCLK. The serial data output (DO) pin shifts data out of the shift register on the rising edge of the SCLK signal. False clocking of the shift register must be avoided to ensure validity of data. It is essential that the SCLK pin be in a logic low state when the CS pin makes any transition. For this reason, it is recommended the SCLK pin is commanded to a logic low state when the device is not accessed (CS in logic high state). With CS in a logic high state, signals present on SCLK and DI are ignored and the DO output is tri-state. DI PIN The DI pin is used for serial instruction data input. DI information is latched into the input register on the falling edge of SCLK. A logic high state present on DI will program a specific output on. The specific output will turn on with the rising edge of the CS signal. Conversely, a logic low state present on the DI pin will program the output off. The specific output will turn off with the rising edge of the CS signal. To program the eight outputs and Open Load Detection Current on or off, send the DI data beginning with the Open Load Detection Current bits, followed by output eight, output seven, and so on to output one. For each falling edge of the SCLK while CS is logic low, a data bit instruction (on or off) is loaded into the shift register per the data bit DI state. Sixteen bits of entered information is required to fill the input shift register. DO PIN The DO pin is the output from the shift register. The DO pin remains tri-state until the CS pin is in a logic low state. All faults on the 33879 device are reported as logic [1] through the DO data pin. Regardless of the configuration of the driver, open loads and shorted loads are reported as logic [1]. Conversely, normal operating outputs with non-faulted loads are reported as logic [0]. Outputs programmed with Open Load Detection Current disabled will report logic [0] in the off state. The first eight positive transitions of SCLK will report logic [0] followed by the status of the eight output drivers. The DI / DO shifting of data follows a first-in, first-out protocol with both input and output words transferring the most significant bit (MSB) first. EN PIN The EN pin on the 33879 enables the device. With the EN pin high, output drivers may be activated and open / short fault detection performed and reported. With the EN pin low, all outputs become inactive, Open Load Detection Current is disabled, and the device enters Sleep mode. The 33879 will perform Power-ON Reset on rising edge of the enable signal. IN5 AND IN6 PINS The IN5 and IN6 command inputs allow outputs five and six to be used in PWM applications. The IN5 and IN6 pins are OR-ed with the Serial Peripheral Interface (SPI) command input bits. For SPI control of outputs five and six, the IN5 and IN6 pins should be grounded or held low by the microprocessor. When using IN5 or IN6 to PWM the output, the control SPI bit must be logic [0]. Maximum PWM frequency for each output is 2.0 kHz. VDD PIN The VDD input pin is used to determine logic levels on the microprocessor interface (SPI) pins. Current from VDD is used to drive DO output and the pullup current for CS. VDD must be applied for normal mode operation. The 33879 device will perform Power-ON Reset with the application of V DD. VPWR PIN The VPWR pin is battery input and Power-ON Reset to the 33879 IC. The VPWR pin has internal reverse battery protection. All internal logic current is provided from the VPWR pin. The 33879 will perform Power-ON Reset with the application of V PWR. D1– D8 PINS The D1 to D8 pins are the open-drain outputs of the 33879. For high side drive configurations, the drain pins are connected to battery supply. In low side drive configurations, the drain pins are connected to the low side of the load. All outputs may be configured individually as desired. When configured as low side drive, the 33879 limits the positive inductive transient to 45 V. S1– S8 PINS The S1 to S8 pins are the source outputs of the 33879. For high side drive configurations, the source pins are connected directly to the load. In low side drive configurations, the

diagram of the 33879 is shown in Figure 2 on page 3. the basic SPI configuration between an MCU and one 33879. Figure 15. SPI Interface with Microcontroller operating outputs will provide a logic [0]. each device while the CS bit is commanded low by the MCU. register is then transferred to the output driver. Figure 16. 33879 SPI System Daisy Chain Figure 17. Parallel Input SPI Control

16 Bits16 Bits

8 Outputs 8 Outputs 8 Outputs

8 Outputs

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0 = Bits 0 to 7, Output commanded OFF. 0 = Bits 8 to 15, Open Load Detection Current OFF. 1 = Bits 0 to 7, Output commanded ON. 1 = Bits 8 to 15 Open Load Detection Current ON. 0 = Bits 0 to 7, No Fault at Output. Bits 8 to 15 will always return “0”. Table 6. Command Register Definition Table 7. Fault Register Definition Table 8. Fault Operation Over-temperature Fault reported by serial output (DO) pin. Over-current DO pin reports short to battery/supply or over-current condition. Output ON Open Load Fault Not reported. Output OFF Open Load Fault DO pin reports output OFF open load condition only with Open Load Detection Current enabled. DO pin will report “0” for Output OFF Open Load Fault with Open Load Detection Current disabled. outputs assuming the previous state upon recovery from over-voltage. recovery from over-temperature.

Analog Integrated Circuit Device Data Freescale Semiconductor 17 33879 FUNCTIONAL DESCRIPTION DEVICE OPERATION DEVICE OPERATION POWER SUPPLY The 33879 device has been designed with ultra-low Sleep mode currents. The device may enter Sleep mode via the EN pin or the VDD pin. In the Sleep mode (EN or VDD ≤ 0.8 V), the current consumed by the VPWR pin is less than 5.0 μA. Placing the 33879 in Sleep mode resets the internal registers to the Power-ON Reset state. The reset state is defined as all outputs off and Open Load Detection Current disabled. To place the 33879 in the Sleep mode, either command all outputs off and apply logic low to the EN input pin or remove power from the VDD supply pin. Prior to removing V DD from the device, it is recommended that all control inputs from the MCU be low. PARALLELING OF OUTPUTS Using MOSFETs as an output switch conveniently allows the paralleling of outputs for increased current capability. RDS(ON) of MOSFETs have an inherent positive temperature coefficient that provides balanced current sharing between outputs without destructive operation. This mode of operation may be desirable in the event the application requires lower power dissipation or the added capability of switching higher currents. Performance of parallel operation results in a corresponding decrease in R DS(ON) while the output OFF Open Load Detection Currents and the output current limits increase correspondingly. Paralleling outputs from two or more different IC devices is possible but not recommended. FAULT LOGIC OPERATION Fault logic of the 33879 device has been greatly simplified over other devices using SPI communications. As command word one is being written into the shift register, a fault status word is being simultaneously written out and received by the MCU. Regardless of the configuration, with no outputs faulted and Open Load Detection Current enabled, all status bits being received by the MCU will be zero. When outputs are faulted (off state open circuit or on state short-circuit / over-temperature), the status bits being received by the MCU will be one. The distinction between open circuit fault and short / over-temperature is completed via the command word. For example, when a zero command bit is sent and a one fault is received in the following word, the fault is open / short- to-battery for high side drive or open / short-to-ground for low side drive. In the same manner, when a one command bit is sent and a one fault is received in the following word, the fault is a short-to-ground / over-temperature for high side drive or short-to-battery/over-temperature for low side drive. The timing between two write words must be greater than 300 μs to allow adequate time to sense and report the proper fault status. SPI INTEGRITY CHECK Checking the integrity of the SPI communication with the initial power-up of the VDD and EN pins is recommended. After initial system start-up or reset, the MCU will write one 32-bit pattern to the 33879. The first 16 bits read by the MCU will be 8 logic [0]s followed by the fault status of the outputs. The second 16 bits will be the same bit pattern sent by the MCU. By the MCU receiving the same bit pattern it sent, bus integrity is confirmed. Please note the second 16-bit pattern the MCU sends to the device is the command word and will be transferred to the outputs with rising edge of CS. Important A SCLK pulse count strategy has been implemented to ensure integrity of SPI communications. SPI messages consisting of 16 SCLK pulses and multiples of 8 clock pulses thereafter will be acknowledged. SPI messages consisting of other than 16 + multiples of 8 SCLK pulses will be ignored by the device. OVER-TEMPERATURE FAULT Over-temperature detection and shutdown circuits are specifically incorporated for each individual output. The shutdown following an over-temperature condition is independent of the system clock or any other logic signal. Each independent output shuts down at 155 °C to 185°C. When an output shuts down owing to an over-temperature fault, no other outputs are affected. The MCU recognizes the fault by a one in the fault status register. After the 33879 device has cooled below the switch point temperature and °C hysteresis, the output will activate unless told otherwise by the MCU via SPI to shut down. OVER-VOLTAGE FAULT An over-voltage condition on the VPWR pin will cause the device to shut down all outputs until the over-voltage condition is removed. When the over-voltage condition is removed, the outputs will resume their previous state. This device does not detect an over-voltage on the V DD pin. The over-voltage threshold on the VPWR pin is specified as VPWR(OV) V, with 1.0 V typical hysteresis. A VPWR over- voltage detection is global, causing all outputs to be turned OFF. OUTPUT OFF OPEN LOAD FAULT An output OFF open load fault is the detection and reporting of an open load when the corresponding output is disabled (input bit programmed to a logic low state). The Output OFF Open Load fault is detected by comparing the drain-to-source voltage of the specific MOSFET output to an internally generated reference. Each output has one dedicated comparator for this purpose. An output OFF open load fault is indicated when the drain- to-source voltage is less than the output threshold voltage OUT(FLT-TH)) of 2.5 V to 4.0 V. Hence, the 33879 will

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to-source voltage is less than VOUT(FLT-TH). driver is switched off when VDD or EN is removed. output DO register for the MCU to read. experiencing a current greater than the current limit.

1. The device’s output current is monitored in an analog
2. The device’s output thermal limit is sensed and when

the device resumes normal operation. energy per output to be 50 mJ at 150°C junction temperature. Figure 18. Output Voltage Clamping with other devices in the Octal Serial Switch (OSS) family. Products Division or the local Freescale representative. circumstance, relays may energize and lamps will turn on. battery blocking diode must be placed in series with the load.

Analog Integrated Circuit Device Data Freescale Semiconductor 19 33879 PACKAGING PACKAGE DIMENSIONS PACKAGING PACKAGE DIMENSIONS Important: For the most current revision of the package, visit www.freescale.com and perform a keyword search using the “98A” drawing number listed below. DWB SUFFIX EK (Pb-FREE) SUFFIX 32-LEAD SOICW EXPOSED PAD 98ARL10543D ISSUE C

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PACKAGE DIMENSIONS (CONTINUED) DWB SUFFIX EK (Pb-FREE) SUFFIX 32-LEAD SOICW EXPOSED PAD 98ARL10543D ISSUE C

Analog Integrated Circuit Device Data Freescale Semiconductor 21 33879 PACKAGING PACKAGE DIMENSIONS DWB SUFFIX EK (Pb-FREE) SUFFIX 32-LEAD SOICW EXPOSED PAD 98ARL10543D ISSUE C

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REVISION HISTORY

REVISION DATE DESCRIPTION OF CHANGES 5.0 2/2006 • Page 2, Figure 1; An exposed pad internal block and EP pin have been added to the internal block diagram.

• Page 4, Table 1; Table 1 has been updated to reflect the Exposed pad pin and pin definition.
• Page 6, Table 3; Logic Supply Sleep State Hysteresis and Note 7 have been removed. The VDD Supply contains no hysteresis.
• Page 7, Table 3; Output Fault Detection Cu rrent @ Threshold, High-Side Configuration Max parameter has been increased from 70uA to 90uA.
• Page 7, Table 3; Output OFF Open Load Detection Current, High-Side Configuration has been updated to reflect the voltage of the VPWR pin during the parameter test.
• Page 7, Table 3; Output OFF Open Load Detection Current, Low-Side Configuration has been updated to reflect the voltage of the VPWR pin during the parameter test.
• Page 7, Table 3; Output Leakage Current High-Side and Low-Side Configuration Max parameter has been decreased from 7uA to 5uA.
• Page 15, Functional Pin Description; A description has been added for the Exposed Pad pin.
• Page 1, Device isometric; Corrected orientatio n of IC pin 1 from top left to bottom right.
• ALL Pages; Updated Data Sheet to reflect Freescale formatting. 6.0 6/2007 • Added 33879A version
• Added MCZ33879EK/R2 and MCZ33879AEK/R2 to the Ordering Information
• Added Device Variations on page 2
• Removed Peak Package Reflow Temperature During Reflow (solder reflow) parameter from Maximum Rations on page 6. Added note with instructions from www.freescale.com.
• Changed Output Fault Detection Voltage Threshold(7) on page 8
• Renumbered X axis on Figure 14 - Open Load Detection Threshold vs. Temperature on page 13
• Changed Over-voltage on page 16 and Over-voltage Fault on page 17 7.0 8/2008 • Updated package drawing. 8.0 10/2009 • Updated data sheet status from Advance Information to Technical Data
• Updated to the current Freescale form and style

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+44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) www.freescale.com/support Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo 153-0064 Japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com Asia/Pacific: Freescale Semiconductor China Ltd. Exchange Building 23F No. 118 Jianguo Road Chaoyang District Beijing 100022 China +86 10 5879 8000 support.asia@freescale.com For Literature Requests Only: Freescale Semiconductor Literature Distribution Center P.O. Box 5405 Denver, Colorado 80217 1-800-441-2447 or +1-303-675-2140 Fax: +1-303-675-2150 LDCForFreescaleSemiconductor@hibbertgroup.com Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. All rights reserved. MC33879 Rev. 8.0 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”, must be validated for each customer application by customer’s technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part.