33874

33874 FREESCALE | Alldatasheet

Document overview

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Technical content

Features

• Quad 35 mΩ High-Side Switches (at 25°C)
• Operating Voltage Range of 6.0 V to 27 V with Standby Current < 5.0 µA
• SPI Control of Overcurrent Limi t, Overcurrent Fault Blanking Time, Output OFF Open Load Detection, Output ON / OFF Control, Watchdog Timeout, Slew Rates, and Fault Status Reporting
• SPI Status Reporting of Overcurrent, Open and Shorted Loads, Overtemperature, Undervoltage and Overvoltage Shutdown, Fail-Safe Pin Status, and Program Status
• Analog Current Feedback with Selectable Ratio
• Analog Board Temperature Feedback
• Enhanced -16 V Reverse Polarity VPWR Protection
• Pb-Free Packaging Designated by Suffix Code PNA

Figure 1. 33874 Simplified Application Diagram

ORDERING INFORMATION

Range (TA) Package MC33874BPNA/R2 - 40°C to 125°C 24 PQFN 33874 HS0 HS1 GNDGND FSI CSNS HS2 HS3 MCU SCLK LOAD 0 LOAD 1 LOAD 2 LOAD 3 SCLK IN0I/O IN1 IN2 IN3 I/O SI SO I/O I/O A/D VPWRVDD VDD VPWR WAKE I/O I/O VDDVDD CSCS RST SO VPWR SI FS TEMPA/D

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Figure 2. 33874 Simplified Internal Block Diagram

3.0 MHz

Figure 3. 33874 Pin Connections Table 1. 33874 Pin Definitions A functional description of each pin can be found in the Functional Pin Description section beginning on page 15.

1 CSNS Output Output Current

side output pins, respectively.

4 TEMP Output Temperature

flag (pins 14, 17, 23). It is used by the MCU to monitor board temperature.

7 FS Output Fault Status

8 WAKE Input Wake This input pin controls the device mode and watchdog timeout feature if

9 RST Input Reset This input pin is used to initialize the device configuration and fault registers,

as well as place the device in a low-current sleep mode.

10 CS Input Chip Select

12 SI Input Serial Input This pin is a command data input pin connected to the SPI Serial Data Output

of the MCU or to the SO pin of the previous device of a daisy-chain of devices.

13 VDD Power Digital Drain Voltage

This pin is an external voltage input pin used to supply power to the SPI circuit.

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14, 17, 23 GND Ground Ground These pins are the ground for the logic and analog circuitry of the device. Output High-Side Outputs Protected 35 mΩ high-side power output pins to the load. 20 NC N/A No Connect This pin may not be connected.

24 FSI Input Fail-Safe Input The value of the resistance connected between this pin and ground

determines the state of the outputs after a Watchdog timeout occurs. Table 1. 33874 Pin Definitions (continued) A functional description of each pin can be found in the Functional Pin Description section beginning on page 15.

Analog Integrated Circuit Device Data Freescale Semiconductor 5 33874

ELECTRICAL CHARACTERISTICS

Table 2. Maximum Ratings permanent damage to the device.

1. Exceeding voltage limits on IN[0:3], RST, FSI, CSNS, TEMP, SI, SO, SCLK, CS, or FS pins may cause a malfunction or permanent
2. Continuous high-side output current rating so long as maximum junc tion temperature is not exceeded. Calculation of maximum output

current using package thermal resistance is required.

1. Active clamp energy usi ng single-pulse method (L = 2 mH, RL = 0 Ω, VPWR = 14 V, TJ = 150°C initial).
2. ESD testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω), Charge Device Model (CDM),
3. Device mounted on a 2s2p test board per JEDEC JESD51-2.
4. Pin soldering temperature limit is for 10 seconds maximum dura tion. Not designed for immersion soldering. Exceeding these limits may

cause malfunction or permanent damage to the device.

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STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics

3.0 MHz SPI Communication (7)

1. Not guaranteed in production.
2. The undervoltage fault condition is reported to SPI register as long as the external VDD supply is within specification and the VPWR

voltage level does not go below the undervoltage Power-ON Reset threshold.

1. This applies when the undervoltage fault is not latched (IN = [0:3]).

Analog Integrated Circuit Device Data Freescale Semiconductor 7 33874 STATIC ELECTRICAL CHARACTERISTICS OUTPUTS (HS0, HS1, HS2, HS3) Output Drain-to-Source ON Resistance (IHS = 5.0 A, TA = 25°C) VPWR = 6.0 V VPWR = 10 V VPWR = 13 V RDS(ON) mΩ Output Drain-to-Source ON Resistance (IHS = 5.0 A, TA = 150°C) VPWR = 6.0 V VPWR = 10 V VPWR = 13 V RDS(ON) mΩ Output Source-to-Drain ON Resistance (10) IHS = 1.0 A, TA = 25°C, VPWR = -12 V RSD(ON) – – 70 mΩ Output Overcurrent High Detection Levels (9.0 V < VPWR < 16 V) SOCH = 0 SOCH = 1 IOCH0 IOCH1 A Overcurrent Low Detection Levels (9.0 V < VPWR < 16 V) SOCL[2:0] : 000 SOCL[2:0] : 001 SOCL[2:0] : 010 SOCL[2:0] : 011 SOCL[2:0] : 100 SOCL[2:0] : 101 SOCL[2:0] : 110 SOCL[2:0] : 111 IOCL0 IOCL1 IOCL2 IOCL3 IOCL4 IOCL5 IOCL6 IOCL7 8.0 7.1 6.3 5.6 4.6 3.8 3.1 2.2 8.9 7.9 7.0 5.8 4.8 3.9 2.8 10.7 9.5 8.5 7.0 5.8 4.7 3.4 A Current Sense Ratio (9.0 V < VPWR < 16 V, CSNS < 4.5 V) DICR D2 = 0 DICR D2 = 1 CSR0 CSR1 Current Sense Ratio (CSR0) Accuracy Output Current

2.0 A to 10 A

CSR0_ACC -17 – 17 Notes 10. Source-Drain ON Resistance (Reverse Drain-to -Source ON Resistance) with negative polarity VPWR. Table 3. Static Electrical Characteristics (continued)

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STATIC ELECTRICAL CHARACTERISTICS OUTPUTS (HS0, HS1, HS2, HS3) (continued) Current Sense Ratio (CSR1) Accuracy Output Current

10 A to 20 A

CSR1_ACC -19 – 19 Current Sense Clamp Voltage CSNS Open; IHS[0:3] = 11 A VCL(CSNS) 4.5 6.0 7.0 V Open Load Detection Current (11) IOLDC 30 – 100 µA Output Fault Detection Threshold Output Programmed OFF VOFD(THRES) 2.0 3.0 4.0 V Output Negative Clamp Voltage 0.5 A < IHS[0:3] < 2.0 A, Output OFF VCL - 20 – -16 V Overtemperature Shutdown (12) TSD 155 175 190 °C Overtemperature Shutdown Hysteresis (12) TSD(HYS) 5.0 – 20 °C Notes 11. Output OFF Open Load Detection Current is the current required to flow through the load for the purpose of detecting the existence of an open load condition when the specific output is commanded OFF. 12. Guaranteed by process monitoring. Not production tested.

Analog Integrated Circuit Device Data Freescale Semiconductor 9 33874 STATIC ELECTRICAL CHARACTERISTICS CONTROL INTERFACE (SCLK, SI, SO, IN[0:3], RST, WAKE, FS, CS, FSI) Input Logic High Voltage (13) VIH 0.7 VDD – – V Input Logic Low Voltage (13) VIL – – 0.2 VDD V Input Logic Voltage Hysteresis (14) VIN(HYS) 100 850 1200 mV Input Logic Pulldown Current (SCLK, SI, IN[0:3], VIN>0.2 VDD) IDWN 5.0 – 20 µA RST Input Voltage Range VRST 4.5 5.0 5.5 V SO, FS Tri-State Capacitance (14) CSO – – 20 pF Input Logic Pulldown Resistor (RST) and WAKE RDWN 100 200 400 kΩ Input Capacitance (15) CIN – 4.0 12 pF Wake Input Clamp Voltage (16) ICL(WAKE) < 2.5 mA VCL(WAKE) 7.0 – 14 V Wake Input Forward Voltage ICL(WAKE) = -2.5 mA VF(WAKE) - 2.0 – - 0.3 V SO High-State Output Voltage IOH = 1.0 mA VSOH

0.8 VDD – –

V FS, SO Low-State Output Voltage IOL = -1.6 mA VSOL – 0.2 0.4 V SO Tri-State Leakage Current CS > 0.7 VDD, 0<VSO<VDD ISO(LEAK) - 5.0 0 5.0 µA Input Logic Pullup Current (17) CS, VIN < 0.7 VDD IUP 5.0 – 20 µA FSI Input pin External Pulldown Resistance (18) FSI Disabled, HS[0:3] state according to direct inputs state and SPI INx_SPI bits and A/O_s bit FSI Enabled, HS[0:3] OFF FSI Enabled, HS0 ON, HS[1:3] OFF FSI Enabled, HS0 and HS2 ON, HS1 and HS3 OFF RFS 6.0 6.5 Infinite 1.0 7.0 kΩ Temperature Feedback TA = 25°C TFEED 3.8 3.9 4.0 V Temperature Feedback Derating DTFEED -7.2 -7.5 -7.8 mV/°C Notes 13. Upper and lower logic threshold voltage range applies to SI, CS, SCLK, RST, IN[0:3], and WAKE input signals. The WAKE and RST signals may be supplied by a derived voltage referenced to VPWR. 14. No hysteresis on FSI and wake pins. Parameter is guar anteed by process monitoring but is not production tested. 15. Input capacitance of SI, CS, SCLK, RST, and WAKE. This parameter is guaranteed by process monitoring but is not production tested. 16. The current must be limited by a series resistance when using voltages > 7.0 V. 17. Pullup current is with CS OPEN. CS has an active internal pullup to VDD. 18. The selection of the RFS must take into consideration the tolerance, temperature coefficient and lifetime duration to assure that the resistance value will always be within the desired (specified) range.

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DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 4. Dynamic Electrical Characteristics

9.0 V < VPWR < 16 V

These parameters are guaranteed by process monitoring. parameters are guaranteed by process monitoring.

1. Turn-ON delay time measured from rising edge of any signal (IN[0 : 3], SCLK, CS) that would turn the output ON to VHS[0 : 3] = 0.5 V with
2. Turn-OFF delay time measured from falling edge of any signal (IN[0 : 3], SCLK, CS) that would turn the output OFF to VHS[0 : 3] = VPWR -

0.5 V with RL = 5.0 Ω resistive load.

1. This logical bit is not defined. Do not use.

Analog Integrated Circuit Device Data Freescale Semiconductor 11 33874 DYNAMIC ELECTRICAL CHARACTERISTICS POWER OUTPUT TIMING (HS0, HS1, HS2, HS3) (continued) Overcurrent High Detection Blanking Time tOCH 1.0 5.0 20 µs CS to CSNS Valid Time (24) t CNSVAL – – 10 µs Watchdog Timeout (25) WD[1:0] : 00 WD[1:0] : 01 WD[1:0] : 10 WD[1:0] : 11 t WDTO0 t WDTO1 t WDTO2 t WDTO3 446 223 1800 900 558 279 2250 1125 725 363 2925 1463 ms Direct Input Switching Frequency (DICR D3 = 0) fPWM - 300 - Hz SPI INTERFACE CHARACTERISTICS (RST, CS, SCLK, SI, SO) Maximum Frequency of SPI Operation f SPI – – 3.0 MHz Required Low State Duration for RST (26) t WRST – 50 350 ns Rising Edge of CS to Falling Edge of CS (Required Setup Time) (27) t CS – – 300 ns Rising Edge of RST to Falling Edge of CS (Required Setup Time) (27) t ENBL – – 5.0 µs Falling Edge of CS to Rising Edge of SCLK (Required Setup Time) (27) t LEAD – 50 167 ns Required High State Duration of SCLK (Required Setup Time) (27) t WSCLKh – – 167 ns Required Low State Duration of SCLK (Required Setup Time) (27) t WSCLKl – – 167 ns Falling Edge of SCLK to Rising Edge of CS (Required Setup Time) (27) t LAG – 50 167 ns SI to Falling Edge of SCLK (Required Setup Time) (28) t SI (SU) – 25 83 ns Falling Edge of SCLK to SI (Required Setup Time) (28) t SI (HOLD) – 25 83 ns SO Rise Time CL = 200 pF t RSO – 25 50 ns SO Fall Time CL = 200 pF t FSO – 25 50 ns SI, CS, SCLK, Incoming Signal Rise Time (28) t RSI – – 50 ns SI, CS, SCLK, Incoming Signal Fall Time (28) t FSI – – 50 ns Time from Falling Edge of CS to SO Low Impedance (29) t SO(EN) – – 145 ns Time from Rising Edge of CS to SO High Impedance (30) t SO(DIS) – 65 145 ns Time from Rising Edge of SCLK to SO Data Valid (31) 0.2 VDD ≤ SO ≤ 0.8 VDD, CL = 200 pF t VALID – 65 105 ns Notes 24. Time necessary for the CSNS to be with ±5% of the targeted value. 25. Watchdog timeout delay measured from the rising edge of WAKE or RST from a sleep state condition, to output turn-ON with the output driven OFF and FSI floating. The values shown are for WDR setting of [00]. The accuracy of t WDTO is consistent for all configured watchdog timeouts. 26. RST low duration measured with outputs enabled and going to OFF or disabled condition. 27. Maximum setup time required for the 33874 is the mi nimum guaranteed time needed from the microcontroller. 28. Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing. 29. Time required for output status data to be available for use at SO. 1.0 kΩ on pullup on CS. 30. Time required for output status data to be terminated at SO. 1.0 kΩ on pullup on CS. 31. Time required to obtain valid data out from SO following the rise of SCLK. Table 4. Dynamic Electrical Characteristics (continued)

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Figure 4. Output Slew Rate and Time Delays Figure 5. Overcurrent Shutdown

Analog Integrated Circuit Device Data Freescale Semiconductor 13 33874 Figure 6. Overcurrent Low and High Detection Figure 7. Input Timing Switching Characteristics

0.7 VDD

0.2 VDD

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Figure 8. SCLK Waveform and Valid SO Data Delay Time

Analog Integrated Circuit Device Data Freescale Semiconductor 15 33874 FUNCTIONAL DESCRIPTION INTRODUCTION FUNCTIONAL DESCRIPTION INTRODUCTION The 33874 is one in a family of devices designed for low- voltage automotive and industrial lighting and motor control applications. Its four low RDS(ON) MOSFETs (35 mΩ) can control the high sides of four separate resistive or inductive loads. Programming, control, and diagnostics are accomplished using a 16-bit SPI interface. Additionally, each output has its own parallel input for PWM control if desired. The 33874 allows the user to program via the SPI the fault current trip levels and duration of acceptable lamp inrush or motor stall intervals. Such programmability allows tight control of fault currents and can protect wiring harnesses and circuit boards as well as loads. The 33874 is packaged in a power-enhanced 12 x 12 nonleaded PQFN package with exposed tabs. FUNCTIONAL PIN DESCRIPTION OUTPUT CURRENT MONITORING (CSNS) The Current Sense pin sources a current proportional to the designated HS0 : HS3 output. That current is fed into a ground-referenced resistor and its voltage is monitored by an MCU's A/D. The output to be monitored is selected via the SPI. This pin can be tri-stated through SPI. SERIAL INPUTS (IN0, IN1, IN2, IN3) The IN0 : IN3 high-side input pins are used to directly control HS0 : HS3 high-side output pins, respectively. An SPI register determines if each input is activated or if the input logic state is OR ed or AND ed with the SPI instruction. These pins are to be driven with 5.0 V CMOS levels, and they have an active internal pulldown current source. TEMPERATURE FEEDBACK (TEMP) This pin reports an analog voltage value proportional to the temperature of the GND. It is used by the MCU to monitor board temperature. FAULT STATUS (FS) This pin is an open drain configured output requiring an external pullup resistor to VDD for fault reporting. If a device fault condition is detected, this pin is active LOW. Specific device diagnostic faults are reported via the SPI SO pin. WAKE This input pin controls the device mode and watchdog timeout feature if enabled. An internal clamp protects this pin from high damaging voltages when the output is current limited with an external resistor. This input has a passive internal pulldown. RESET (RST) This input pin is used to initialize the device configuration and fault registers, as well as place the device in a low- current sleep mode. The pin also starts the watchdog timer when transitioning from logic [0] to logic [1]. This pin should not be allowed to be logic [1] until VDD is in regulation. This pin has a passive internal pulldown. CHIP SELECT (CS) The CS pin enables communication with the master microcontroller (MCU). When this pin is in a logic [0] state, the device is capable of transferring information to, and receiving information from, the MCU. The 33874 latches in data from the Input Shift registers to the addressed registers on the rising edge of CS. The device transfers status information from the power output to the Shift register on the falling edge of CS. The SO output driver is enabled when CS is logic [0]. CS should transition from a logic [1] to a logic [0] state only when SCLK is a logic [0]. CS has an active internal pullup, IUP. SERIAL CLOCK (SCLK) The SCLK pin clocks the internal shift registers of the 33874 device. The serial input (SI) pin accepts data into the input shift register on the falling edge of the SCLK signal while the serial output (SO) pin shifts data information out of the SO line driver on the rising edge of the SCLK signal. It is important the SCLK pin be in a logic low state whenever CS makes any transition. For this reason, it is recommended the SCLK pin be in a logic [0] whenever the device is not accessed (CS logic [1] state). SCLK has an active internal pulldown. When CS is logic [1], signals at the SCLK and SI pins are ignored and SO is tri-stated (high impedance) (see Figure 9, page 17). SERIAL INPUT (SI) This is a serial interface (SI) command data input pin. Each SI bit is read on the falling edge of SCLK. A 16-bit stream of serial data is required on the SI pin, starting with D15 to D0. The internal registers of the 33874 are configured and controlled using a 5-bit addressing scheme described in Table 8, page 21. Register addressing and configuration are

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FUNCTIONAL PIN DESCRIPTION described in Table 9, page 21. The SI input has an active internal pulldown, IDWN. DIGITAL DRAIN VOLTAGE (VDD) This pin is an external voltage input pin used to supply power to the SPI circuit. In the event VDD is lost, an internal supply provides power to a portion of the logic, ensuring limited functionality of the device. GROUND (GND) This pin is the ground for the device. POSITIVE POWER SUPPLY (VPWR) This pin connects to the positive power supply and is the source of operational power for the device. The VPWR contact is the backside surface mount tab of the package. SERIAL OUTPUT (SO) The SO data pin is a tri-stateable output from the shift register. The SO pin remains in a high-impedance state until the CS pin is put into a logic [0] state. The SO data is capable of reporting the status of the output, the device configuration, and the state of the key inputs. The SO pin changes state on the rising edge of SCLK and reads out on the falling edge of SCLK. Fault and input status descriptions are provided in Table 16, page 25. HIGH-SIDE OUTPUTS (HS3, HS1, HS0, HS2) Protected 35 mΩ high-side power output pins to the load. FAIL-SAFE INPUT (FSI) The value of the resistance connected between this pin and ground determines the state of the outputs after a Watchdog timeout occurs. Depending on the resistance value, either all outputs are OFF or the output HSO only is ON. If the FSI pin is left to float up to a logic [1] level, then the outputs HS0 and HS2 will turn ON when in the Fail-Safe state. When the FSI pin is connected to GND, the Watchdog circuit and Fail-Safe operation are disabled. This pin incorporates an active internal pullup current source.

with 5.0 V CMOS logic levels. Figure 9. Single 16-Bit Word SPI Communication and RST inputs as defined in Table 5.

• V PWR and VDD are within the normal voltage range.
• RST pin is logic [1].
• No fault has occurred. FAIL-SAFE MODE FAIL-SAFE MODE AND WATCHDOG If the FSI input is not grounded, the watchdog timeout detection is active when either the WAKE or RST input pin transitions from logic [0] to logic [1]. The WAKE input is capable of being pulled up to VPWR with a series of limiting CSCSB SI SCLK SO D15 D1 D2 D3 D4 D5 D6 D7 D8 D9 D14 D13 D12 D11 D10 OD12 OD13 OD14 OD15 OD6OD7OD8OD9OD10OD11 OD1 OD2 OD3 OD4OD5 1. RSTB is in a logic H state during the above operation. 2. DO, D1, D2, ... , and D15 relate to the most recent ordered entry of program data into the LUX IC NOTES: OD0 CS device. 1. RST is a logic [1] state during the above operation. 2. D15:D0 relate to the most recent ordered entry of data into the device. 3. OD15:OD0 relate to the first 16 bits of ordered fault and status data out of the device. Notes

Table 5. Fail-Safe Operation and Transitions to Other

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overcurrent circuitry (with default value) are fully operational. from logic [1] to logic [0] or forcing the FSI pin to logic [0]. device from the latched Fail-Safe mode.

• Overtemperature fault
• Overvoltage and undervoltage fault
• Open load fault
• Overcurrent fault (high and low) The FS pin will automatically return to logic [1] when the fault condition is removed, except for overcurrent, overtemperature (in case of latching configuration) and in some cases of undervoltage. The FS pin reports all faults. For latched faults, this pin is reset by a new Switch ON command (via SPI or direct input IN). Fault information is retained in the fault register and is available (and reset) via the SO pin during the first valid SPI communication (refer to Table 17, page 25). PROTECTION AND DIAGNOSTIC FEATURES OVERTEMPERATURE FAULT (LATCHING OR NON-LATCHING) The 33874 incorporates overtemperature detection and shutdown circuitry for each output structure. The overtemperature is latched per default and can be unlatched through SPI with OT_latch_[0:3] bits. An overtemperature fault condition results in turning OFF the corresponding output. To remove the fault and be able to turn ON again the outputs, the failure must be removed and:
• in Normal Mode: the corresponding output must be commanded OFF and ON again in case of overtemperature latched (OT_latch bit = 0).
• in Normal Mode: the corresponding output turns ON automatically if the temperature is below TSD-TSD(HYS) in case of unlatched overtemperature (OT_latch bit = 1).
• in Fail-Safe Mode: the FSI input must be grounded and then set to its nominal voltage to switch ON the outputs. The overtemperature fault (one for each output) is reported by SPI. If the overtemperature is latched, the SPI reports OTF_s = [1] and OCLF_s = [1]. In case of non- latched, OTF_s = [1] only is reported. The fault bits will be cleared in the status register after either a valid SPI read command or a power on reset of the device. OVERCURRENT FAULT (LATCHING) The 33874 has eight programmable overcurrent low detection levels (IOCL) and two programmable overcurrent high detection levels (IOCH) for maximum device protection. The two selectable, simultaneously active overcurrent

Table 6. Output State During Fail-Safe Mode

6.0 All HS OFF

15 HS0 ON

Analog Integrated Circuit Device Data Freescale Semiconductor 19 33874 FUNCTIONAL DEVICE OPERATION PROTECTION AND DIAGNOSTIC FEATURES detection levels, defined by IOCH and IOCL, are illustrated in Figure 6, page 13. The eight different overcurrent low detect levels (IOCL0 : IOCL7) are illustrated in Figure 6. If the load current level ever reaches the selected overcurrent low detection level and the overcurrent condition exceeds the programmed overcurrent time period (tOCx), the device will latch the output OFF. If at any time the current reaches the selected IOCH level, then the device will immediately latch the fault and turn OFF the output, regardless of the selected tOCH driver. For both cases, the device output will stay off indefinitely until the device is commanded OFF and then ON again. OVERVOLTAGE FAULT (NON-LATCHING) The 33874 shuts down the output during an overvoltage fault (OVF) condition on the VPWR pin. The output remains in the OFF state until the overvoltage condition is removed. When experiencing this fault, the OVF fault bit is set in the bit D1 and cleared after either a valid SPI read or a power reset of the device. The overvoltage protection can be disabled through SPI (bit OV_DIS). When disabled, the returned SO bit OD13 still reflects any overvoltage condition (overvoltage warning). UNDERVOLTAGE SHUTDOWN (LATCHING OR NON-LATCHING) The output(s) will latch off at some battery voltage below 6.0 V. As long as the VDD level stays within the normal specified range, the internal logic states within the device will be sustained. In the case where battery voltage drops below the undervoltage threshold (VPWRUV) output will turn off, FS will go to logic 0, and the fault register UVF bit will be set to 1. Two cases need to be considered when the battery level recovers :

• If outputs command are low, FS will go to logic 1 but the UVF bit will remain set to 1 until the next read operation (warning report).
• If the output command is ON, then FS will remain at logic 0. The output must be turned OFF and ON again to re-enable the state of output and release FS. The UVF bit will remain set to 1 until the next read operation. The undervoltage protection can be disabled through SPI (bit UV_dis = 1). In this case, the FS does not report any undervoltage fault condition, UVF bit is set to 1, and the output state is not changed as long as the battery voltage does not drop any lower than 2.5 V. The daisy chain feature is available under VDD in nominal conditions.

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register will be cleared after reading the register. circuitry in case of a permanent disconnected load. enhanced to keep the junction temperature less than 150°C. prevent this pin to exceed its maximum ratings. digital supply against excessive current (10kΩ typical). Table 7. Device behavior in case of Undervoltage

2.5 V > VPWR > 0V Output State OFF OFF OFF OFF OFF OFF

∗∗ = While VDD remains within specified range. *** = IN_x is equivalent to IN_x direct input or IN_spi_s SPI input.

with the MSB D15 and ending with the LSB, D0 (Table 8). latch in a message that is not 16 bits will be ignored. configure the device and to control the state of the outputs. Table 9, page 21, summarizes the SI registers. addresses and their impact on device operation. Table 8. SI Message Bit Assignment MSB D15 Watchdog in: toggled to satisfy watchdog requirements. D12 : D11 Register address bits used in some cases for output selection. D10 : D8 Register address bits. D4 : D1 Used to configure the inputs, outputs, and the device protection features and SO status content. LSB D0 Used to configure the inputs, outputs, and the device protection features and SO status content. Table 9. Serial Input Address and Configuration Bit Map s = Output selection with the bits A1A0 as defined in Table 10.

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corresponding output switch and a logic [0] turns it OFF. CSNS pins of several devices share the same A /D converter. Table 13. Note that these timeouts apply only to the high level is reached, the device will latch off within 20 µs. Table 10. Output Selection Table 11. Overcurrent Low Detection Levels Table 12. Overcurrent High Detection Levels Table 13. Overcurrent Low Detection Blanking Time

01 Do not use

the state bits D12 : D11 (refer to Table 10, page 22). will disable the output from direct control. corresponding message bits when addressing the OCR0. default value [0] is used to select the low ratio (Table 14). [0] corresponds to the low speed slew rate. under- and overvoltage are active (default value). Table 14. Current Sense Ratio Table 15. Watchdog Timeout

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FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS Any bits clocked out of the Serial Output (SO) pin after the first 16 bits will be representative of the initial message bits clocked into the SI pin since the CS pin first transitioned to a logic [0]. This feature is useful for daisy-chaining devices as well as message verification. A valid message length is determined following a CS transition of [0] to [1]. If there is a valid message length, the data is latched into the appropriate registers. A valid message length is a multiple of 16 bits. At this time, the SO pin is tri-stated and the fault status register is now able to accept new fault status information. SO data will represent information ranging from fault status to register contents, user selected by writing to the STATR bits OD4, OD3, OD2, OD1, and OD0. The value of the previous bits SOA4 and SOA3 will determine which output the SO information applies to for the registers which are output specific; viz., Fault, SOCHLR, CDTOLR, and DICR registers. Note that the SO data will continue to reflect the information for each output (depending on the previous OD4, OD3 state) that was selected during the most recent STATR write until changed with an updated STATR write. The output status register correctly reflects the status of the STATR-selected register data at the time that the CS is pulled to a logic [0] during SPI communication, and/or for the period of time since the last valid SPI communication, with the following exceptions:

• The previous SPI communication was determined to be invalid. In this case, the status will be reported as though the invalid SPI communication never occurred.
• Battery transients below 6.0 V resulting in an under- voltage shutdown of the outputs may result in incorrect data loaded into the status register. The SO data transmitted to the MCU during the first SPI communication following an undervoltage VPWR condition should be ignored.
• The RST pin transition from a logic [0] to [1] while the WAKE pin is at logic [0] may result in incorrect data loaded into the Status register. The SO data transmitted to the MCU during the first SPI communication following this condition should be ignored. SERIAL OUTPUT BIT ASSIGNMENT The 16 bits of serial output data depend on the previous serial input message, as explained in the following paragraphs. Table 16, page 25, summarizes SO returned data for bits OD15 : OD0.
• Bit OD15 is the MSB; it reflects the state of the Watchdog bit from the previously clocked-in message.
• Bit OD14 remains logic [0] except when an undervoltage condition occurred.
• Bit OD13 remains logic [0] except when an overvoltage condition occurred.
• B i t s O D 1 2 : OD8 reflect the state of the bits SOA4 : SOA0 from the previously clocked in message.
• Bits OD7 : OD4 give the fault status flag of the outputs HS3 : HS0, respectively.
• The contents of bits OD3 : OD0 depend on bits D4 : D0 from the most recent STATR command SOA4 : SOA0 as explained in the paragraphs following Table 16.

programmed bits for outputs HS3 : HS0, respectively. previously selected with A1A0. CDTOLR register for the output selected with A1A0. DICR register for the output selected with A1A0. Table 16. Serial Output Bit Map Description

10 OD9 OD8 OD7 OD6 OD5 OD4 OD3 OD2 OD1 OD0

s = Output selection with the bits A1A0 as defined in Table 10, page 22. Table 17. Output-Specific Fault Register s = Selection of the output.

Analog Integrated Circuit Device Data

26 Freescale Semiconductor

FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS watchdog circuitry. If WDTO bit is logic [1], the watchdog has timed out and the device is in Fail-Safe mode. IF WDTO is logic [0], the device is in Normal mode (assuming the device is powered and not in the Sleep mode), with the watchdog either enabled or disabled. PREVIOUS ADDRESS SOA4 : SOA0 = 00110 The returned data OD3 and OD2 contain the state of the outputs HS2 and HS0, respectively, in case of Fail-Safe state. This information is stated with the external resistance placed at the FSI pin. OD1 indicates if the watchdog is enabled or not. OD0 returns the state of the WAKE pin. PREVIOUS ADDRESS SOA4 : SOA0 = 01110 The returned data OD3 : OD0 reflects the state of the direct pins IN3 : IN0, respectively. PREVIOUS ADDRESS SOA4 : SOA0 = 01111 The returned data OD3 -OD2 reports the overtemperature bits configuration of the outputs [3, 2] set through the WDR SPI register.

Analog Integrated Circuit Device Data Freescale Semiconductor 27 33874 PACKAGING SOLDERING INFORMATION PACKAGING SOLDERING INFORMATION The 33874 is packaged in a surface mount power package intended to be soldered directly on the printed circuit board. The 33874 was qualified in accordance with JEDEC standards JESD22-A113-B and J-STD-020A. The recommended reflow conditions are as follows:

• Convection: 235°C +5 .0/ -0°C
• Vapor Phase Reflow (VPR): 235°C +5.0 / -0°C
• Infrared (IR) / Convection: 235°C +5.0 / -0°C The maximum peak temperature during the soldering process should not exceed 240°C. The time at maximum temperature should range from 10 s to 40 s maximum. PACKAGE DIMENSIONS For the most current package revision, visit www.freescale.com and perform a keyword search using the 98ARL10596D listed below. PNA SUFFIX (PB-FREE) 24-PIN PQFN NONLEADED PACKAGE 98ARL10596D ISSUE C

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28 Freescale Semiconductor

The 33874 can be configured in several applications. The figure below shows the 33874 in a typical lighting application. 33874 I/O VDD VDD VPWR GND Microcontroller Voltage regulator VPWR 100nF HS2 HS0 HS1 HS3 VPWRVDD WAKE FS IN0 IN2 IN3 SCLK CS NC TEMP SI SO FSI RST IN1 10µF100nF I/O I/O I/O I/O I/O SCLK CS SI SO A/D 10k 10k 10k 10k 10k 10k 10k 10k 10k 1k R1 10k LOAD 0 LOAD 1 LOAD 2 LOAD 3 CSNSA/D VDD VDD VPWRVDD 21W 5 W 21W 5 W 21W 5 W 21W 5 W Automotive lamps do not tolerate high voltages very well. Tests of a few lamps indicate that failures can occur when 18V is applied for a few seconds. Consequently, PWM switching reduces the effective RMS voltage in order to drive bulbs safety. For example, to maintain the power dissipation associated with a 13V battery at 100% duty cycle, the duty cycle would be adjusted to (13/18)², or 52%, when the battery is at 18V. The loads must be chosen in order to guarantee the device normal operating condition as junction temperature from -40 to 150 °C. In case of permanent short-circuit conditions, the duration and number of activation cycles must be limited with a dedicated MCU fault management using the fault reporting through SPI.

provides an easy way to evaluate the main electrical features. runs with all parameters set to default. The input SPI pins and VDD must be connected to ground. default parameters are detailed next. Table 1. Available Functions Table 2. Default SPI-configurable parameters

30 Freescale Semiconductor

temperature, over current, under voltage, and over voltage. turned OFF then ON to disable the fault. functioning is safe because all protections are available. power load with full protection. Table 3. Diagnosis without SPI

Analog Integrated Circuit Device Data Freescale Semiconductor 31 33874 TYPICAL APPLICATION

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32 Freescale Semiconductor

application, and packaging information is provided in the datasheet. TJ1 and TJ2, and a thermal resistance matrix with RθJAmn. temperature while only heat source 1 is heating with P1. by measurement and simulation according to the standards listed below. Figure 10. Testboard According to JEDEC Table 18. Thermal Performance Comparison

1. Per JEDEC JESD51-2 at natural convection, still air
2. 2s2p thermal test board per JEDEC JESD51-7and
3. Per JEDEC JESD51-8, with the board temperature on the

center trace near the power outputs.

1. Single layer thermal test board per JEDEC JESD51-3 and
2. Thermal resistance between the die junction and the

exposed pad, “infinite” heat sink attached to exposed pad.

34 Freescale Semiconductor

Figure 11. Thermal Test Board where the junction temperature is sensed. Table 19. Thermal Resistance Performance

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36 Freescale Semiconductor

REVISION HISTORY

Revision Date Description of Changes 3.0 03/2006 • Implemented Revision History page

• Converted to Freescale format 4.0 04/2006 • Added ROHS logo
• Added “It is recommended to disable open load circ uitry in case of a permanent disconnected load.“to the Open Load Fault (Non-Latching) paragraph
• Changed 1k to 10k in the second paragraph of Ground Disconnect Protection
• Added the section StandAlone mode to Typical Application
• Updated Package Dimensions to Issue C
• Added Thermal Addendum (Rev 2.0) to Data Sheet 5.0 6/2002 • Corrected part number ordering information
• Modified Output Turn ON Delay Times on page 10 6.0 9/2006 • Changed status from Preliminary to Advance.
• Made changes the resistive loads on the Typi cal Applications diagram and added a paragraph describing the behavior of automotive lamps.
• Added new thermal curves to the Thermal Addendum (Rev 2.0) on page 33
• Made updates to Thermal Resistance Performance on page 34 7.0 9/2006 • Made changes to Thermal Addendum (Rev 2.0) relating to Figure 11, Table 19, Thermal Resistance Performance, Figure 12, and Figure 13 8.0 4/2007 • Added Direct Input Switching Frequency to Dy namic Electrical Characteristics Table

Rev. 8.0 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”, must be validated for each customer application by customer’s technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc., 2006. All rights reserved. How to Reach Us: Home Page: www.freescale.com E-mail: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7

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