33816

NXP Semiconductors

SD6 programmable solenoid controller for precision solenoid control applications Rev. 10.0, 2/2023

Manufacturer: NXP Semiconductors

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33816 NXP | Alldatasheet

Document overview

Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
PDF pages: 314

Technical content

Features

Battery voltage range, 5.0 V < VBATT < 32 V
Pre-drive operating voltage up to 72 V
High-side/ low-side pre-drive PWM capability up to 100 kHz–30 nC
All pre-drivers have four selectable slew rates
Eight selectable, pre-defined VDS monitoring thresholds
Encryption for microcode protection
Integrated 1.0 MHz back-up clock
Programmable integrated End-of-Injection (EOI) measurement function (MC33816MAE only)

Figure 1. MC33816 simplified application diagram

Applications

Automotive (12 V), truck and industrial (24 V) powertrain
Diesel and gasoline direct injection
Transmission VBATT VCC5 MOSI SCLK CSB MISO START1 START6 FLAG0 DRVEN IRQB B_HS1 G_HS1 S_HS1 B_HS5 G_HS5 S_HS5 VSENSEP1 G_LS7 VBOOST MOSI SCLK MISO GPIO MCU 33816 CSB ETPU FLAG2 ETPU VBAT VCCIO VCC2P5 VCCP 5.0 V CLK GPIO GPIO RESETB OA_1ADC OA_2ADC G_LS1 D_LS1 VSENSEN1 VSENSEP3 VSENSEN3 VSENSEP4 VSENSEN4 VBAT VBOOST G_LS6 D_LS6 VBAT/VBOOST GPIO GPIO GPIO Load

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1 Orderable parts

1.1 Cipher Key

Contact a NXP sales representative to obtain devices with a specific encryption key and the associated code encryptor. Table 1. Orderable part variations

To order parts in Tape & Reel, add the R2 suffix to the part number.

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2 Internal block diagram

2.1 Simplified internal diagram

Figure 2. 33816 simplified internal block diagram

3 Pin connections

3.1 Pinout diagram

Figure 3. 33816 64-Pin LQFP-EP pinout diagram

3.2 Pin definitions

Table 2. 33816 pin definitions

1 CLK Input External clock pin - internal weak pull-up (2)

2 DRVEN Input Driver enable pin - internal weak pull-down (4)

3 RESETB Input Device reset pin - internal weak pull-up (2)

10 FLAG0 Input/Output General purpose I/O/Flag_bus(0) - internal weak pull-down (4)

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11 FLAG1 Input/Output General purpose I/O/Flag_bus(1) - internal weak pull-down (4)

12 FLAG2 Input/Output General purpose I/O/Flag_bus(2) - internal weak pull-down (4)

13 CSB Input SPI chip select - internal pull-up (3)

14 MOSI Input SPI slave data input - internal weak pull-up (2)

15 MISO Output SPI slave data output

16 SCLK Input SPI clock - internal weak pull-up (2)

18 DBG Input/Output Debug pin/Flag_bus(12) - internal weak pull-up (2)

19 DGND Ground Digital ground

22 OA_1 Output Current sense analog output pin/Flag_bus(10) - internal weak pull-down (4)

23 OA_2 Output Current sense analog output pin/Flag_bus(11) - internal weak pull-down (4)

24 AGND Ground Analog ground

25 VSENSEN1 Input Current sense input comparator -

26 VSENSEP1 Input Current sense input comparator +

27 VSENSEN2 Input Current sense input comparator -

28 VSENSEP2 Input Current sense input comparator +

29 VSENSEN3 Input Current sense input comparator -

30 VSENSEP3 Input Current sense input comparator +

31 VSENSEN4 Input DC-DC current sense input comparator -

32 VSENSEP4 Input DC-DC current sense input comparator +

33 D_LS6 Input Low-side MOSFET drain pin monitor 6

34 D_LS5 Input Low-side MOSFET drain pin monitor 5

35 D_LS4 Input Low-side MOSFET drain pin monitor 4

36 D_LS3 Input Low-side MOSFET drain pin monitor 3

37 D_LS2 Input Low-side MOSFET drain pin monitor 2

38 D_LS1 Input Low-side MOSFET drain pin monitor 1

39 VBATT Input Battery input voltage

41 G_LS7 Output DC-DC low-side MOSFET gate pin actuator 7

42 G_LS6 Output Low-side MOSFET gate pin actuator 6

43 G_LS5 Output Low-side MOSFET gate pin actuator 5

44 G_LS4 Output Low-side MOSFET gate pin actuator 4

45 G_LS3 Output Low-side MOSFET gate pin actuator 3

46 G_LS2 Output Low-side MOSFET gate pin actuator 2

47 G_LS1 Output Low-side MOSFET gate pin actuator 1

48 VBOOST Input DC-DC feedback pin/Boost voltage monitor pin

49 B_HS5 - High-side MOSFET bootstrap pin 5

Table 2. 33816 pin definitions (continued)

50 G_HS5 Output High-side MOSFET gate pin actuator 5

51 S_HS5 Input High-side MOSFET source pin monitor 5

52 B_HS4 - High-side MOSFET bootstrap pin 4

53 G_HS4 Output High-side MOSFET gate pin actuator 4

54 S_HS4 Input High-side MOSFET source pin monitor 4

55 B_HS3 - High-side MOSFET bootstrap pin 3

56 G_HS3 Output High-side MOSFET gate pin actuator 3

57 S_HS3 Input High-side MOSFET source pin monitor 3

58 B_HS2 - High-side MOSFET bootstrap pin 2

59 G_HS2 Output High-side MOSFET gate pin actuator 2

60 S_HS2 Input High-side MOSFET source pin monitor 2

61 B_HS1 - High-side MOSFET bootstrap pin 1

62 G_HS1 Output High-side MOSFET gate pin actuator 1

63 S_HS1 Input High-side MOSFET source pin monitor 1

64 IRQB Input/Output Interrupt output/Flag_bus(9) - internal weak pull-down (4)

Internal weak pull-up to VCCIO is typically 480 k - Refer to the Internal pull-up and pull-down section.
Internal pull-up to VCCIO is typically 120 k - Refer to the Internal pull-up and pull-down section.
Internal weak pull-down to AGND is typically 480 k - Refer to the Internal pull-up and pull-down section.
Internal pull-down to AGND is typically 120 k - Refer to the Internal pull-up and pull-down section.

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4 General product characteristics

4.1 Maximum ratings

Table 3. Maximum ratings permanent damage to the device.

Steady-state
Unpowered device 0.0 V (7)(9) VBATT Battery voltage range (VBATT) -0.3 72 V (9) VCC5 VCC5 input pin -0.3 18 V VCCIO VCCIO input pin -0.3 18 V VCCP VCCP input/output pin -0.3 9.0 V VCC2P5 VCC2P5 output pin -0.3 3.0 V VMAX_LOGIC SPI interface and logic input and output voltage (CSB, MOSI, MISO, SCLK, CLK, RESETB, IRQB, DRVEN, START1, START2, START3, START4, START5, START6, FLAG0, FLAG1, FLAG2, DBG, OA_1, OA_2) -0.3 18 V VDGND Digital ground (DGND) -0.3 0.3 V VAGND Analog ground (AGND) -0.3 0.3 V VS_HSX Source high-side MOSFET pin (S_HS1, S_HS2, S_HS3, S_HS4, S_HS5)
Nominal
Transients t < 400 ns
Transients t < 800 ns
Unpowered device -3.0 -8.0 -6.0 VBOOSTMAX VBOOSTMAX VBOOSTMAX V (6) (6) (7) VB_HSX Bootstrap high-side MOSFET pin (B_HS1, B_HS2, B_HS3, B_HS4, B_HS5)
Nominal
Transients t < 400 ns
Transients t < 800 ns
Unpowered device -0.3 -4.0 -2.0 VS_HSX+ VBS_HSX_CL VS_HSX+ VBS_HSX_CL VS_HSX+ VBS_HSX_CL VS_HSX + VBS_HSX_CL V (9) (6) (6) (6)(7) VG_HSX Gate high-side MOSFET pin (G_HS1, G_HS2, G_HS3, G_HS4, G_HS5) VS_HSX - 0.3 VB_HSX + 0.3 V (7)(8) VG_LSX Gate high-side MOSFET pin (G_LS1, G_LS2, G_LS3, G_LS4, G_LS5, G_LS6, G_LS7)
Nominal
Transients t < 5.0 ns -0.3 -1.5 VCCP + 0.3 VCCP + 1.5 V (6)(10) VD_LSX Drain low-side MOSFET pin (D_LS1, D_LS2, D_LS3, D_LS4, D_LS5, D_LS6)
Nominal
Transients t < 400 ns
Unpowered device -3.0 -8.0 V (6) (6)(7)

Static at VCC5 < 10 V
Dynamic for max 5.0 s, 1.0 kHz repetition rate at VCC5 < 5.25 V
Dynamic for max 1.0 s at VCC5 < 5.25 V -2.5 -5.0 -15 2.5 5.0 V (6) (6) VSENSEN Current measurement negative input pin voltage (VSENSEN1, VSENSEN2, VSENSEN3)
Static at VCC5 < 10 V
Dynamic for max 5.0 s, 1.0 kHz repetition rate at VCC5 < 5.25 V
Dynamic for max 1.0 s at VCC5 < 5.25 V -1.0 -5.0 -15 1.0 5.0 V (6) (6) VSENSEP4 Current measurement four positive input pin voltage (VSENSEP4)
Static at VCC5 < 10 V
Dynamic for max 5.0 s, 1.0 kHz repetition rate at VCC5 < 5.25 V
Dynamic for max 1.0 s at VCC5 < 5.25 V -4.2 -5.0 -15 2.5 5.0 V (6) (6) VSENSEN4 Current measurement four negative input pin voltage (VSENSEN4)
Static at VCC5 < 10 V
Dynamic for max 5.0 s, 1.0 kHz repetition rate at VCC5 < 5.25 V
Dynamic for max 1.0 s at VCC5 < 5.25 V -3.0 -5.0 -15 1.0 5.0 V (6) (6) VESD1-1 VESD1-2 VESD1-3 VESD2-1 VESD2-2 ESD Voltage Human Body Model (HBM)
All pins
VBOOST, VBATT, S_HSx
D_LSx CDM
All pins
Corner pins (CLK, SCLK, VCCIO, VSENSEP4, D_LS6, VBOOST, B_HS5, IRQB) 2000 4000 8000 500 750 V (11) Notes 6. This parameter is derived mainly from simulation. 7. In case of application power-off just after the power-down all the system capacitors connected the pins VBATT, VBOOST, VS_HSx, VG_HSx and VD_LSx are slowly discharged due to highly resistive discharge paths. A voltage remains on these pins until full capacitor discharge. 8. Relative voltage is referenced to the corresponding pre-driver channel biasing. 9. The differential voltage VBOOST-VB_HSx must not exceed 40 V when the device is unpowered. 11. ESD testing is performed in accordance with the Human Body Model (HBM) (CZAP = 100 pF, RZAP = 1500 ), and the Charge Device Model (CDM), Robotic (CZAP = 4.0 pF).

Table 3. Maximum ratings (continued) permanent damage to the device.

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4.2 Thermal characteristics

Table 4. Thermal ratings

Ambient
Junction -40 -40 125 150 TSTG Storage Temperature -40 – 150 °C RJA Thermal Resistance
Junction-to-Ambient 24.3 27 29.7 °C/W (12) (13) TPPRT Peak Package Reflow Temperature During Reflow – – Note 14 °C (14) Notes 12. Considering four layer FR4 PCB and 5.5 x 5.5 mm², with the exposed pad connected to the inner ground layer through 16 vias (Outer diameter: 0.3 mm, Inner diameter: 0.25 mm). 13. This parameter is derived from simulation. 14. NXP’s package reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For peak package reflow temperature and moisture sensitivity levels (MSL), go to www.nxp.com, search by part number (remove prefixes/suffixes) and enter the core ID to view all orderable parts, and review parametrics.

4.3 Operating conditions

This section describes the operating conditions of the device. Conditions apply to all the following data, unless otherwise noted. Table 5. Operating conditions reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

Duration < 1.0 hour 16 – 18 V VBATT_CRANK VBATT power supply input voltage, Internal or external VCCP regulator, Cranking condition 5.0 – 9.0 V (16) VBATT_JSTART VBATT power supply input voltage, Internal VCCP regulator, Jump start condition
TA = 40 ºC, Duration < 2.0 min. 18 – 28 V VBATT_LOADDUMP VBATT power supply input voltage, Internal VCCP regulator, Load dump
Duration < 500 ms 18 – 40 V VBATT_EXT VBATT power supply input voltage, External VCCP regulator, Normal operation 9.0 – 32 V (17) VBATT_BR_EXT VBATT power supply input voltage, External VCCP regulator, Broken alternator regulator condition
Duration < 1 hour 32 – 36 V (17) VBATT_JSTART_EXT VBATT power supply input voltage, External VCCP regulator, Jump start condition
TA = 40 ºC, Duration < 15 min. 36 – 48 V (17) VBATT_LOADDUMP _EXT VBATT power supply input voltage, External VCCP regulator, Load dump
Duration < 500 ms 36 – 58 V (17), (18) VBOOST Boost output voltage 5.0 – VBOOSTMA X V Notes 15. This parameter is derived mainly from simulation and is guaranteed by design characterization on a small sample size of typical devices under typical conditions, unless otherwise noted. 16. Full device functionality is guaranteed under cranking condition. However some derating can be observed on gate driver switching times and other parameters. 17. For 24 V system applications, the VCCP voltage must be externally supplied to limit power dissipation within the MC33816. Moreover, the MOSFETs’ drain voltages must not exceed the high-side pre-driver pins max. ratings, even during transient conditions. 18. Implementation of a transient suppressor circuitry is highly recommended to avoid exceeding the max. rating.

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4.4 Supply currents

measurements are without output loads. Table 6. Current consumption summary reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

fSYS = 24 MHz, no microcore running
fSYS = 24 MHz, all microcores running 56 mA (19) IVCCIO VCCIO supply current
fSYS = 24 MHz, no microcore running
fSYS = 24 MHz, all microcores running 1.0 µA mA (19) IVBATT_QUIESC VBATT power supply current in reset state VCC5 = VCCIO = 0.0 V
VBATT = 13.5 V
VBATT = 40 V 180 800 µA IVBATT_OPER VBATT power supply current in normal operation VBATT = 16 V
DRVEN low, internal VCCP reg. off
DRVEN low, Internal VCCP reg. on
DRVEN high, VCCP max load 65 mA 1.7 4.4 69.7 2.5 6.0 mA IVBOOST_QUIESC Boost supply current in reset state VCC5 = VCCIO = 0 V
VBOOST = 13.5 V
VBOOST = 40 V
VBOOST = 65 V 150 250 280 450 µA IVBOOST_OPER Boost supply current in normal operation
VBOOST = 16 V
VBOOST = 48 V
VBOOST = 65 V 4.2 4.55 4.9 4.85 5.35 5.75 mA (20) Notes 19. This parameter is derived mainly from simulation and is guaranteed by design characterization on a small sample size of typical devices under typical conditions, unless otherwise noted. 20. The main current contributor is the charge pump, typically consuming 4.2 mA at VBOOST = 65 V

5 General description

5.1 Introduction

The 33816 is a mixed signal IC for engine injector and electrical valve control, which provides a cost effective, flexible, and smart, high- side and low-side MOSFET gate drivers. The device includes both individual charge pump outputs for each high-side pre-driver and high- voltage DC-DC converter pre-driver. Gate drive, diagnosis, and protection against external faults, are managed through four independent and concurrent digital microcores using an extensive set of 93 microcode instructions. Each of the two logic channels, comprised of two microcores, has its own Code RAM and Data RAM. The internal microcode is protected against theft via encryption and corruption via check sums. All functions are designed to minimize the number of external components required.

5.2 Features

High-side and low-side pre-drivers

Five high-side pre-drivers for logic level N-channel MOSFETs using four programmable slew rates
Six low-side pre-drivers for logic level N-channel MOSFETs using four programmable slew rates
Integrated bootstrap circuitry for each high-side pre-driver
Integrated charge pump circuitry for each high-side pre-driver with 100% duty cycle capability DC-DC converter
One low-side pre-driver, for a logic level N-channel MOSFET, can be optionally dedicated to providing a boost DC-DC converter with four programmable slew rates
Boost voltage monitoring (with integrated feedback) Current measurement and diagnostic
Four independent current measurement blocks, including A/D converters with programmable gain, which are based on 8-bit D/A converters
One current measurement (channel 4) is optionally configurable to support DC-DC converter with overload detection
Five high-side and six low-side pre-drivers with independent VDS monitoring (eight programmable values) for fault protection and diagnostics
Integrated load biasing to VBATT/2 for diagnosis (on all high-side sources and all low-side drains)
Capable of detecting missing ground connections Power supplies and monitoring
Integrated 7.0 V linear regulator (VCCP) for HS/LS power supply (optionally externally supplied for 24 V battery system), with undervoltage monitoring
Integrated 2.5 V linear regulator (VCC2P5) for digital core supply based on VCC5 input supply, with undervoltage monitoring
External 5.0 V supply (VCC5) with under/overvoltage monitoring
Temperature monitoring
Selectable VCCIO external supply (5.0 V or 3.3 V) for digital I/O Digital block
Four digital microcores, each with their own ALU, and full access to the system crossbar switch
Two memory banks: 1024 x 16-bit of code RAM with built-in error detection and 64 x 16-bit of data RAM
A system-wide crossbar switch for analog resources configuration
Memory BIST activated by the SPI, with pass/fail status PLL and backup clock
12 to 24 MHz PLL internal system clock based on 1.0 MHz input clock
Loss of clock protection by means of internal backup 1.0 MHz clock Control interface
16-bit slave SPI up to 10 MHz – two protocols – programmable slew rate
13 general purpose digital IOs – configurable through registers and microcode
Direct pre-driver inhibition input
Device reset input
Hardware interrupt output

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Built-in encryption for microcode protection
External digital I/O able to sustain voltages up to 18 V
High ESD performance
ESD strategy optimized for ESD System Level Stress (’System-efficient ESD Design’)
High ESD holding voltage (>80 V)
AEC-Q100 Rev G compliant
Heavy duty compliant
Enhanced analog testability based on JTAG

5.3 Block diagram

Figure 4. MC33816 - functional block diagram

5.4 Functional description

battery voltage and booster voltage level high-side configurations are supported. The chip communicates with the main controller through an SPI bus and a flexible set of direct interface signals. loaded via the SPI before or after the microcode download. (Flash_enable of channel 1 (0x100) and Flash_enable of channel 2 (0x120)). applied on the DRVEN pin to a logic one. The initial gate actuation sequence start is performed by bringing the appropriate STARTx input pin high. the MCU when a fault occurs.

6 Functional block description

6.1 Power up/down sequence

The recommended power up procedure to properly start up the MC33816 is shown in the following timing diagram. Figure 5. Power up sequence timing diagram The detailed power up sequence description is provided below. Table 7. Power up sequence description of the boost external circuitry. (2a) Once a stable voltage is applied to the VCC5 pin the internal bandgap starts. (2b) Once the internal bandgap output is stable the VREF2.5 reference voltage regulator starts. (2c) Once the VREF2.5 reference voltage output is stable the VCC2P5 voltage regulator starts. (3) Since VCC2P5 output voltage is in its expected output voltage range the POReset is released. (4a) (4b) The internal charge pump starts when POReset is released and the suitable voltage is applied to the VBOOST pin. since VCCIO and VCC voltage are supplied.

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During power up the voltage on VBATT pin can be higher than the voltage on the VBOOST pin. supplies. The only requirement is that the power supplies always remain below their maximum allowable values. VBATT external supplies while injection or actuation is not occurring. must be considered with care to avoid any injury or system damage.

6.2 Power supplies and monitoring

source, depending on the logic levels desired. connected to the LS7 pre-driver, and monitored by the current sense block 4 and the VBOOST monitor input. Table 8 provides an overview of the voltage supplies monitorings and capabilities. (6) Since a stable input signal at 1.0 MHz is applied to the CLK pin the internal PLL starts. (7) Since the internal PLL is stable and locked the main MCU can release the reset signal by setting the RESETB pin to the high state. POReset is released and tDIGIOREADY time is reached. Moreover the RESETB pin states must be high. pin. Moreover the internal charge pump must be operational for allowing the internal regulator VCCP to start. accordingly to signal applied the STARTx pin. Table 8. 33816 power supplies overview

MC33816 internal consumption.

Table 7. Power up sequence description (continued)

6.2.1 Band gap reference

to 2.0% over the full temperature range. The band gap input is supplied by the external 5.0 V supply. Figure 6. Bandgap reference overview switch on the VCC2P5 regulator and to enable the VCCP internal regulator. is used by all the DACs. The reference voltage has a precision of 1.0%. Table 9. Band gap reference electrical specifications

This parameter is derived mainly from simulation.

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6.2.2 VCC2P5 and power on reset (POR)

provides a Power On Reset to keep the logic reset until the VCC2P5 voltage is within the working range. Figure 7. VCC2P5 voltage regulator and power on reset overview signal (POResetB) is asserted to the logic core after a delay of tD_PORESETB. Figure 8. POResetB diagram from the SPI interface. The AND gate output RSTB is used to reset the logic core and all device internal modules.

either by sending any message to the device and checking for the control pattern on MISO during command word. In case of RSTB asserted the returned value is different from '0xA8'.
or by reading out any register with a reset value not equal to zero (example: Device Identification register (0x1D5)). In case of RSTB asserted the returned value is '0x00'. The logic core should be properly supplied with 2.5 V when 5.0 V is present at VCC5 pin (thus allowing logic core operations and communication with the microcontroller), even when no voltage is provided at the VBATT pin, and consequently no voltage is present on VCCP pin. /g1/g2/g2/g3/g4/g5 /g6/g7/g8/g9/g10/g11/g12/g13/g14 /g4/g15/g6/g7/g16/g7/g12/g17/g4/g13/g18/g7/g14/g19/g15/g20 /g6/g7/g16/g7/g12 /g1/g2/g2/g5 /g21/g22/g23/g24 /g25/g8/g26/g13/g27 /g1/g2/g2/g3/g4/g5 /g28/g4/g29/g6/g7/g16/g7/g12/g17 /g6/g30/g28/g30/g31/g17 /g6/g28/g31/g17 /g6/g7/g16/g7/g12/g17 /g2/g1/g2/g2/g3/g4/g5/g24/g22/g23/g24

6.2.3 VCC5 voltage

The VCC5 voltage is externally powered and internally monitored. It supplies the internal VCC2P5 regulator.

6.2.3.1 VCC5 overvoltage monitoring

Table 10. VCC2P5 AND POR electrical specifications

This parameter is derived mainly from simulation and is guaranteed by design characterization on a small sample size of typical devices under

typical conditions, unless otherwise noted. Table 11. VCC5 slew rate

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6.2.3.2 VCC5 undervoltage monitoring

register (0x1C5)) is issued to the microcontroller, as soon as uv_vcc5 is asserted. Table 12. VCC5 overvoltage monitoring electrical specifications

Differential input voltage = 1.0 V – – 1.0 µs (25) VOVVCC5_VCCP VCC5 overvoltage threshold for VCCP shutdown 6.2 6.9 7.5 V Note 25. This parameter is derived mainly from simulation and is guaranteed by design characterization on a small sample size of typical devices under typical conditions, unless otherwise noted.

Table 13. VCC5 undervoltage monitoring electrical specifications

Differential input voltage = 1.0 V – – 150 ns .(26) tFILTER_UVVCC5 VCC5 undervoltage anti-glitch filter delay time 0.8 1.3 2.0 µs (26) Note 26. This parameter is derived mainly from simulation and is guaranteed by design characterization on a small sample size of typical devices under typical conditions, unless otherwise noted.

6.2.4 VCCP LDO regulator

Figure 9. VCCP LDO regulator pin to provide the high peak currents required when charging a MOSFET gate. low VCC5, the regulator may be active, but with an increased dropout voltage. becomes active and enables the VCCP regulator. If VCC5 is not present or low, POResetB is active and the VCCP regulator is disabled. (0x1C5) to ‘1’, and using an external supply. is high, it is switched off to reduce quiescent current drawn from the VBATT pin.

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6.2.4.1 VCCP undervoltage monitoring

Figure 10. VCCP undervoltage monitoring driver outputs are automatically switched off by the digital core. The gate drivers are re-enabled after the VCCP voltage rises above the VUVVCCP+ upper threshold, and after a tFILTER_UVVCCP filter delay. When an undervoltage occurs, operations are stopped before insufficient gate driver supply voltage causes a malfunction. Driver_status register (0x1D2) is set high. Table 14. VCCP LDO regulator electrical specifications

0.0 mA < IVCCP < 65 mA 6.5 7.0 7.5 V (27) VCCP_EXT VCCP input voltage range (VCCP externally supplied) 5.0 – 9.0 V IVCCP VCCP output current (average during PWM operation)
9.0 V < VBATT < 18 V – – -65 mA (28) IVCCP_MAX VCCP output current limitation -100 -150 -200 mA VVCCP VBATT to VCCP voltage dropout
VBATT = 5.0 V and IVCCP = - 65 mA
VBATT = 5.0 V and IVCCP = - 50 mA
VBATT = 5.0 V and IVCCP = - 30 mA
VBATT = 5.0 V and IVCCP = - 10 mA 350 280 170 mV Note 27. Considering an external output capacitor CVCCP connected to PGND pin with a minimum value of 1.0 µF, a typically value of 4.7 µF, and a maximum value of 14 µF. 28. This parameter is derived mainly from simulation and is guaranteed by design characterization on a small sample size of typical devices under typical conditions, unless otherwise noted. /g1/g2/g2/g3/g4/g5/g6/g7 /g8/g9/g10/g11/g12/g13/g14/g15/g16/g1/g2/g2/g3/g4/g17/g1/g4 /g18/g15/g19/g20/g14/g15/g16/g20/g19/g10 /g3/g21/g22/g6 /g1/g2/g2/g3 /g11/g23/g24/g23/g25/g25/g26 /g2/g1/g2/g2/g3 /g27/g20/g12/g14/g9/g16 /g6/g9/g12/g13/g28 /g23/g25/g25/g26/g24/g9/g29/g14/g9/g16/g19/g13/g12/g24/g9/g19/g13/g30/g12/g9 /g3/g21/g22/g6

6.2.5 DC-DC converter

to create an output voltage up to 72V. Figure 11 shows one of two possible topologies that differ in how the boost capacitor is connected. Figure 11. Boost converter topology for fixed frequency mode greater than the input voltage. ls7_ovr bit of the Driver_config register (0x1C5) is set to ‘0’ (reset value is ‘1’). Table 15. VCCP undervoltage monitoring electrical specifications

1.0 V differential input voltage. – – 2.5 µs (29) tFILTER_UVVCCP VCCP UV anti-glitch filter delay time 0.8 1.3 2.0 µs (29) Note 29. This parameter is derived mainly from simulation and is guaranteed by design characterization on a small sample size of typical devices under typical conditions, unless otherwise noted.

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variable frequency mode only. The boost regulator operates in one of two hysteretic modes: ‘Variable Frequency’ and ‘Fixed Frequency’. Frequency’ and ‘Fixed Frequency’ modes control the power switch differently as described by the following.

6.2.5.1 Variable frequency mode

during boost injection phases. Figure 12. Boost converter topology for variable frequency mode manages the current modulation. beginning a new boost cycle.

6.2.5.2 Fixed frequency mode

the MOSFET in this topology, it is not necessary to suspend the boost conversion during boost injection phases.

the VBOOST threshold is reset to its lower level.

6.2.5.3 Boost start up sequence

unless the DRVEN pin controls LS7. In this case, the DRVEN must be set to high to start regulation. Boost_dac register (0x19B) in the microcode.

6.2.5.4 Low-side pre-driver for DC-DC converter (LS7)

in off state while the device is in a power on reset state (RSTB low).

The signal DrvEn issued from the DRVEN pin is added to the control signal for the driver. As long as the DrvEn signal is negated, the low-side pre-driver is switched off. The low-side pre-driver for the DC-DC converter includes a feature to override the switch off path via a DrvEn signal. As long as the ls7_en_ovr bit of the Driver_config register (0x1C5) is set to ‘1’, the pre-driver is not influenced by the DrvEn signal.
The VCCP undervoltage signals (uv_vccp) issue from the VCCP monitoring. During an undervoltage, the external MOSFET is switched off
The VCC5 undervoltage signals (uv_vcc5) issued from the VCC5 monitoring. During an undervoltage, the external MOSFET is switched off
The signal cksys_drven issued from the clock monitoring: In cases of a missing clock, the external MOSFET is switched off while the digital core has not switched to the internal backup clock. This condition can be optionally disabled by setting the bit cksys_missing_disable_driver of the Backup_clock_status_handle (0x1C7) register to ‘0’.
The logic command coming from channel logic (ls7_in) A truth table describing the status of the ls7_command signal is given in Table 16.

Table 16. Low-side seven pre-driver truth table

When ls7_command is low, the G_LS7 pin is driven low (pull-down to PGND voltage)
When ls7_command is high, the G_LS7 pin is driven high (pull-up to VCCP voltage)

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Table 17. Low-side pre-drivers on state electrical specifications

5.0 V < VBATT < 18 V 0.0 – 300 kHz (32) (33) (34) DCG_LS7 Duty cycle 0.0 – 100 % (32) (33) IG_LS7_PWM G_LS7 current (average during PWM operation)
QG = QG_LS7; fPWM = 300 kHz
QG = QG_LS7; fPWM = 100 kHz
QG = QG_LS7; fPWM = 50 kHz 9.0 3.0 1.5 22.5 7.5 3.75 mA (32) IG_LS7_SRC Peak source gate drive current – 680 – mA (32) IG_LS7_SRC Peak sink gate drive current at fastest slew rate setting with minimum RG_LS7 of 2.0  and VCCP/VGS = 7.0 V – 2200 – mA (32) tR_G_LS7 Turn on rise time at 1500 V/µs slew rate; 10%-90% of out voltage; VCCP = 7.0 V; at Open pin 3.5 – 11 ns (32) tF_G_LS7 Turn on fall time at 1500 V/µs slew rate; 10%-90% of out voltage; VCCP = 7.0 V; at Open pin 3.5 – 11 ns (32) tR_G_LS7 Turn on rise time at 300-25 V/µs slew rate; 10%-90% of out voltage; VCCP = 7.0 V; at Open pin 5.0 – 25 ns (32) tF_G_LS7 Turn on fall time at 300-25 V/µs slew rate; 10%-90% of out voltage; VCCP = 7.0 V; at Open pin 5.0 – 25 ns (32) tDON_G_LS7 Turn on propagation delay at 1500 V/µs slew rate; 10% of out voltage change; CLOAD = 4.7 nF; RG = 40.2 ; VCCP = 7.0 V 10 – 50 ns (32) tDOFF_G_LS7 Turn off propagation delay at 1500 V/µs slew rate; 10% of out voltage change; CLOAD = 4.7 nF; RG = 40.2 ; VCCP = 7.0 V 10 – 50 ns (32) tDON_G_LS7 Turn on propagation delay at 300 V/µs slew rate; 10% of out voltage change; CLOAD = 4.7 nF; RG = 40.2 ; VCCP = 7.0 V 10 – 70 ns (32) tDOFF_G_LS7 Turn off propagation delay at 300 V/µs slew rate; 10% of out voltage change; CLOAD = 4.7 nF; RG = 40.2 ; VCCP = 7.0 V 10 – 70 ns (32) tDON_G_LS7 Turn on propagation delay at 50 V/µs slew rate; 10% of out voltage change; CLOAD = 4.7 nF; RG = 40.2 ; VCCP = 7.0 V 15 – 100 ns (32) tDOFF_G_LS7 Turn off propagation delay at 50 V/µs slew rate; 10% of out voltage change; CLOAD = 4.7 nF; RG = 40.2 ; VCCP = 7.0 V 15 – 100 ns (32) tDOFF_G_LS7 Turn on propagation delay at 25 V/µs slew rate; 10% of out voltage change; CLOAD = 4.7 nF; RG = 40.2 ; VCCP = 7.0 V 15 – 120 ns (32) tDOFF_G_LS7 Turn off propagation delay at 25 V/µs slew rate; 10% of out voltage change; CLOAD = 4.7 nF; RG = 40.2 ; VCCP = 7.0 V 15 – 120 ns (32) Note 32. This parameter is derived mainly from simulation and is guaranteed by design characterization on a small sample size of typical devices under typical conditions, unless otherwise noted. 33. A series resistor to the MOSFET gate of 2.0  must be implemented if using the fastest slew rate setting. For all the other slew rate settings the minimum resistor is 0 . 34. The external low-side MOSFET gate charge must not exceed 75 nC. A gate charge of maximum 100 nC is admitted if the fPWM 225 kHz.

6.2.5.4.1 Low-side pre-driver slew rate control

of the bits slew rate_ls7_rising(1:0) and slew rate_ls7_falling(1:0) in the Ls_slew rate register (0x18F). The slew rate is determined by the PMOS and NMOS RDSON of the push/pull driver circuitry. Table 18. Low-side pre-drivers off state electrical specifications Table 19. Low-side seven pre-drivers PMOS slew rate settings Table 20. Low-side seven pre-drivers NMOS slew rate settings Table 21. Low-side seven pre-drivers slew rates characteristics parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

at external VGS = 2.5 V
at external VGS = 1.0 to 4.0 V; 3.0 2.6 5.0 8.6 10.7 RDS_HSx_n (00) G_HSx nMOS RDS_ON (00), 1500 V/µs, VCCP = 7.0 V
at external VGS = 2.5 V
at external VGS = 1.0 to 4.0 V; 0.6 0.5 1.1 2.0 2.9 RDS_HSx_p (01) G_HSx pMOS RDS_ON (01), 300 V/µs, VCCP = 7.0 V
at external VGS = 2.5 V
at external VGS = 1.0 to 4.0 V; 8.8 7.5 14.6 25.3 31.3 RDS_HSx_n (01) G_HSx nMOS RDS_ON (01), 300 V/µs, VCCP = 7.0 V
at external VGS = 2.5 V
at external VGS = 1.0 to 4.0 V; 3.4 2.5 5.9 11.1 16.5

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6.2.5.4.2 Safe state of DC-DC low-side pre-driver

capacitor. A low level output is guaranteed as long as a typical voltage greater than 1.1 V is available.

6.2.5.5 Current measurement for DC-DC converter

threshold comparator and concurrently provide an overcurrent supervision at the booster capacitor. able to provide a short delay from the VSENSEPx and VSENSENx inputs to the G_LS7 output. drives the G_LS7 pin. Refer to the Current measurement section for the detailed description and parameters. DC conversion section for the detailed description and parameters.

6.2.5.6 Boost voltage monitoring

to the VBOOST voltage measurement, if the VBOOST voltage is externally supplied, and when the block are in boost monitor mode
or a Battery undervoltage measurement in UV VBOOST mode when the VBOOST is connected to the device supplied (battery). RDS_HSx_p (10) G_HSx pMOS RDS_ON (10), 50 V/µs, VCCP = 7.0 V
at external VGS = 1.0 to 4.0 V; 61 85 115  RDS_HSx_n (10) G_HSx nMOS RDS_ON (10), 50 V/µs, VCCP = 7.0 V
at external VGS = 1.0 to 4.0 V; 23 35 50  RDS_HSx_p (11) G_HSx pMOS RDS_ON (11), 25 V/µs, VCCP = 7.0 V
at external VGS = 1.0 to 4.0 V; 122 170 230  RDS_HSx_n (11) G_HSx nMOS RDS_ON (11), 25 V/µs, VCCP = 7.0 V at external VGS = 1.0 to 4.0 V; 47 69 100  tSLR_HS Slew rate switching time
1 ck cycle at 6.0 MHz – – 166 ns (35) Note 35. This parameter is derived mainly from simulation and is guaranteed by design characterization on a small sample size of typical devices under typical conditions, unless otherwise noted.

Table 22. Boost voltage monitoring electrical characteristics Table 21. Low-side seven pre-drivers slew rates characteristics (continued) parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

6.2.6 Boost voltage monitoring mode

Boost voltage monitoring mode is mostly used in Direct Injection (DI) applications when boost voltage is required to drive the injectors. VBOOST exceeds the target value. The digital microcore acquires the comparator output for the boost voltage control and management. voltage range on the VBOOST pin is up to VBOOST max. A typical ratio of 1/32 is used for boost voltage monitoring. the DAC threshold, the comparator output boost_fbk is asserted, while it is set low if the VBOOST_DIV voltage is below the DAC threshold. The comparator output boost_fbk is connected to the digital microcore.

VBoost = DAC _Value * VVBOOST_DAC_LSB/GVBOOST_DIV DAC _Value is the decimal value of the DAC (dac_boost_value(7:0)). VVBOOST_DAC_LSB is the DAC resolution. GVBOOST_DIV is the VBOOST voltage divider ratio in boost monitor mode. Due to the compensation concept, values below 0x08 must not be used. Also, values higher than 0xE1 must not be used, because this would result in a boost voltage exceeding the input voltage range VBOOSTMAX. Practically, the boost voltage set point threshold must be set significantly below the VBOOSTMAX, due to dynamic effects such as a voltage drop in the boost capacitor. DAC value clamping to 0xD0 is highly recommended. fCVBOOST_DIV VBOOST analog filter cutoff frequency (boost monitor mode only) 50 100 200 kHz VVBOOST_REF DAC reference voltage 2.475 2.5 2.525 V VVBOOST_DAC_LSB DAC LSB – 9.77 – mV (36) VVBOOST_DAC_OUT _MIN DAC minimum output voltage
DAC code = 0x00 – 0.0 – V (36) VVBOOST_DAC_OUT _MAX DAC maximum output voltage
DAC code = 0xFF – 2.49 – V (36) EVBOOST_DAC Total DAC error – – 0.2 % VVBOOST_DIV_OFFS ET Total DAC error including comparator offset -20 – 20 mV VVBOOST_HYST Comparator hysteresis referred to VBOOST (boost monitor mode) 112 160 208 mV VUV_VBOOST_HYST Comparator hysteresis referred to VBOOST (UV Vboost mode) 10 20 30 mV tVBOOST_COMP Comparator switching time, Propagation delay + rise/fall time
50 mV differential input voltage – – 1.0 µs (36) EVBOOST VBOOST measurement total error
VBOOST = 40 V and divider ratio 1/32
VBOOST = 4.85 V and divider ratio 1/4 -2.0 -2.0 2.0 2.0 tVBOOST_DAC VBOOST DAC settling time – – 0.9 µs (36) Note 36. This parameter is derived mainly from simulation and is guaranteed by design characterization on a small sample size of typical devices under typical conditions, unless otherwise noted.

Table 22. Boost voltage monitoring electrical characteristics (continued)

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6.2.7 VBOOST UV monitoring mode

divider ratio can be changed from 1/32 to 1/4, by setting the signal vboost_mon_en to ’1’.

In this mode, the usable DAC range is limited from 0x08 to 0xF8 due to digital trimming.
In this mode, the comparator output signal boost_fbk should be used in the digital core to disable all the high-side pre-drivers.This shut-off path is enabled by the signal vboost_disable_en inside the digital core. The uv_vboost signal goes high as soon as the voltage at the VBOOST pin is below the threshold, if the VBOOST UV monitor is enabled (vboost_disable_en=1). The digital filter used for the VBOOST voltage measurement is activated for the VBOOST UV monitoring mode. The DAC set point value in this mode has to be chosen, considering the pre-drivers must not be disabled for a battery voltage above 5.0 V, and the device internal charge pump works properly down to a battery voltage of VUVVCC5+. This leads to a DAC set point value of 0x7C and the following values for UV VBOOST:
Undervoltage lower threshold (min.): 4.72 V
Undervoltage upper threshold (max.): 4.94 V The output signal uv_vboost (active high) of this undervoltage monitor is routed to all the high-side pre-drivers and combined with uv_vccp and uv_vcc5 signal to disable the pre-drivers. In the digital core, the bit uv_vboost the Driver_status register (0x1D2) is set when a VBOOST undervoltage event occurs. In addition, an interrupt request is issued to the microcontroller as soon as uv_vboost is asserted, if the bit vboost_irq_en of the Driver_config register (0x1C5) is set to ’1’. The VBOOST UV threshold can be calculated using the following formula.
VBOOST = DAC _Value * VVBOOST_DAC_LSB/GUV_VBOOST_DIV DAC _Value is the decimal value of the DAC. VVBOOST_DAC_LSB is the DAC resolution. GUV_VBOOST_DIV is the VBOOST voltage divider ratio in UV VBOOST mode.

Table 23. Boost voltage DAC value examples in boost monitor mode Table 24. Boost voltage DAC value examples in UV VBOOST mode

6.2.8 Ground disconnection

PGND is the substrate connection and it is only connected to the package exposed pad, to guarantee a low-impedance connection and get optimized EMC performances. PGND is the reference ground for the VCCP regulator, some analog functions, and all of the low-side pre-drivers. It is highly recommended to directly connect PGND to the ECU ground plane.
DGND is the reference ground for the digital logic core. It is highly recommended to directly connect DGND to the ECU ground plane.The microcontroller, as well as other logic devices communicating with the device should share the same reference ground connected to the ground plane to prevent noise.
AGND is the ground for all the noise sensitive analog blocks integrated into the device, such as the bandgap reference, the current sense circuitry, and the output amplifiers (OA_x pins). This pin should be connected to the analog ground of the ECU. A star connection is recommended to guarantee a clean analog signal acquisition of the OAX_x pins from the MCU. Due to their functionality, some analog functions are referred to PGND:
VDS monitors of the low-side drivers
VSRC monitors of the high-side drivers
The load biasing S_HSX regulator and the D_LSx pull-down All the ground pins of the device should be connected to the same ground voltage. Even during transient conditions, the voltage difference between PGND, DGND, and AGND must be limited to 0.3 V. The layout of the ground connection of the ECU should be carefully designed, to limit the ground noise generated as much as possible, for instance during fast switching of the external power MOSFETs. The decoupling and filter capacitors at the different supply voltage pins should be implemented as described by the following:
VCC5 to AGND
VCCIO to DGND
VCC2P5 to DGND
VCCP to PGND
VBATT to PGND
VBOOST to AGND or PGND

6.2.9 Detection of missing GND connections

The 33816 can detect any single or multiple missing connection of any ground pin (PGND, DGND, AGND) of the device. At least one ground must remain connected to allow the loss of ground detection. detection is filtered to allow the device to work in a proper way for a time of typically tMISS_GND_DCT_FLT via the uv_vccp signal. Table 25. Decoupling and filter capacitors specification Table 26. Missing ground detection specifications

This parameter is derived mainly from simulation and is guaranteed by design characterization on a small sample size of typical devices under

typical conditions, unless otherwise noted.

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6.2.10 Temperature monitoring

in the Driver _config register (0x1C5)) is issued to the microcontroller as soon as over_temp signal is asserted.

6.2.11 Shut off path via DRVEN and 18 V robustness

If the ECU detects a fault condition, it can disable all of the 33816’s output drivers via the driver enable pin DRVEN. can be read via the SPI by reading the Driver_status register (0x1D2). STARTx (6x), FLAGx (3x), and OA_x (2x). The DRVEN function works even if these pins or the supply pins increase to 18 V. blocks current into the digital I/O pin for each digital I/O, to clamp the voltage below 10 V.

6.3 High-side pre-drivers

The external FET can be connected to either VBATT or a higher voltage VBOOST. The high-side pre-drivers are supplied by an external bootstrap capacitor connected between the S_HSX and B_HSX pins. drivers have identical electrical characteristics. Any high-side pre-driver can also be used as a low-side pre-driver. Table 27. Temperature monitoring specifications Table 28. Shut off path specification

This parameter is derived mainly from simulation and is guaranteed by design characterization on a small sample size of typical devices under

typical conditions, unless otherwise noted.

Adding a SPI response checking routine is highly recommended, to check the SPI functionality after tDIGIOREADY time has elapsed.

Figure 13. High-side pre-driver block diagram

In the high-side pre-driver block, the signal DrvEn issued from the DRVEN pin is added to the control signal for the driver. As long as the DrvEn signal is low, the high-side pre-driver is switched off. The high-side pre-driver 5 includes a feature to override the switch off path via the DrvEn signal. As long as the hs5_ls36_en_ovr bit of the Driver_status register (0x1C5) is set to ‘1’, the pre- drivers are not influenced by DrvEn.
VCCP undervoltage signals (uv_vccp) issued from the VCCP monitoring: In case of an undervoltage, the external MOSFET is switched off.
VCC5 undervoltage signals (uv_vcc5) issued from the VCC5 monitor: In case of an undervoltage, the external MOSFET is switched off.
VBOOST undervoltage signals (uv_vboost) issued from the boost voltage monitor: In case of an undervoltage, the external MOSFET is switched off when this feature is enabled.
Signal cksys_drven issued from the clock monitor. In case of a missing clock (PLL not locked), the external MOSFET is switched off. This function is disabled by default and can be enabled by setting the cksys_missing_disable_driver bit high in the Backup_clock_status_reg register r(0x1C7)
Logic commands issued from logic channels (hsx_in). The truth table describing the status of hsx_command signal is given in Table 29.

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Table 29. High-side pre-drivers truth table

When hsx_command is low, the G_HSx pin is driven low (pull-down to PGND voltage)
When hsx_command is high, the G_HSx pin is driven high (pull-up to VCCP voltage)

Table 30. High-side pre-drivers on state electrical specifications

VS_HS = VBOOSTMAX
VS_HS = 13.5 V
VS_HS = 7.0 V
VS_HS = 4.0 V 1000 250 120 100 µA IS_HSX_SINK_ON HSX leakage current when pre-driver on (biasing switched off)
VS_HS = 7.0 V – – 220 µA IS_HSX_SINKDELTA S_HSX leakage current delta between pre-drivers off and on
VS_HS = 7.0 V 60 – 140 µA IHSX_SUPL High-side driver supply current during 100% DC
During constant off
During constant on, including maximum supply current for the RPD_HSX pull-down resistor µA fG_HSX_PWM PWM frequency
External VCCP 6.5 V
9.0 V VBATT
5 V  VBATT  9.0 V 0.0 0.0 0.0 100 100 KHz (42)(43)(4 DCG_HSX Duty cycle 0.0 – 100 % (42)

This parameter is derived mainly from simulation and is guaranteed by design characterization on a small sample size of typical devices under

typical conditions, unless otherwise noted.

The minimum admitted series resistor is 0 .
The external low-side MOSFET gate charge must not exceed 50 nC.A gate charge of maximum 75 nC is admitted if the fPWM 67 kHz.

Table 31. High-side pre-drivers off state electrical specifications

TJ = -40 to 150 °C 500 – 2000 k

Table 30. High-side pre-drivers on state electrical specifications (continued)

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6.3.1 High-side driver slew rate control

the falling edge such as to retain the same absolute slew rate. but with the possibility of rapidly changing to the highest slew rate with a microcode instruction (stslew). Table 32. High-side pre-drivers slew rate settings Table 33. High-side pre-drivers slew rates characteristics parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

at external VGS = 2.5 V
at external VGS = 1.0 to 4.0 V; 8.6 7.5 14.6 25.8 31.4 RDS_HSX_N (00) G_HSx nMOS RDS_ON (00), 300 V/µs, VCCP = 7.0 V
at external VGS = 2.5 V
at external VGS = 1.0 to 4.0 V 3.2 2.5 5.9 11.4 16.5 RDS_HSX_P (01) G_HSx pMOS RDS_ON (01), 50 V/µs, VCCP = 7.0 V
at external VGS = 1.0 to 4.0 V 61 85 115  RDS_HSX_N (01) G_HSx nMOS RDS_ON (01), 50 V/µs, VCCP = 7.0 V
at external VGS = 1.0 to 4.0 V 23 35 50  RDS_HSX_P (10) G_HSx pMOS RDS_ON (10), 25 V/µs, VCCP = 7.0 V
at external VGS = 1.0 to 4.0 V 122 169 230  RDS_HSX_N (10) G_HSx nMOS RDS_ON (10), 25 V/µs, VCCP = 7.0 V
at external VGS = 1.0 to 4.0 V 47 69 100  RDS_HSX_P (11) G_HSx pMOS RDS_ON (11), 12.5 V/µs, VCCP = 7.0 V
at external VGS = 1.0 to 4.0 V 245 337 460  RDS_HSX_N (11) G_HSx nMOS RDS_ON (11), 12.5 V/µs, VCCP = 7.0 V at external VGS = 1.0 to 4.0 V 94 138 199  tSLR_HS Slew rate switching time
1 ck cycle at 6.0 MHz, switching from slow to fast
4 ck cycles at 6.0 MHz, witching from fast to slow 166 666 ns (45) Note 45. This parameter is derived mainly from simulation and is guaranteed by design characterization on a small sample size of typical devices under typical conditions, unless otherwise noted.

6.3.2 Bootstrap diodes

operating limits, that is, the requirement to refresh the charge in the bootstrap capacitor limits the duty cycle and on-time. to 0.0 V and therefore the VB_HSX voltage drops below the VCCP voltage.

Turns on the bootstrap diode to load the bootstrap capacitor when the high-side driver’s source terminal is significantly below the VCCP voltage
Clamps the high-side gate voltage when the bootstrap capacitor is reaches the desired voltage
Prevents bootstrap capacitor discharge when the B_HSX pin voltage is higher than VCCP. Bootstrap operation can create charging currents sufficiently large that injector diagnostics can be affected. To avoid such disturbances, the digital core issues one signal for each high-side pre-driver (called hsx_bs_inb) that prevents the bootstrap switches from switching on at the end of the injection or during initialization, as long as no low-side pre-driver is switched on. It thereby prevents degradation of end of the injection monitoring performed when using the VSRC comparator of the pre-driver. Current flowing through each bootstrap diode is actively limited to avoid overloading them.

Table 34. Bootstrap diode electrical specifications

VCCP - VB_HSX = 0.25 V
VCCP - VB_HSX = 0.5 V
VCCP - VB_HSX = 0.75 V
VCCP - VB_HSX = 1.0 V
VCCP - VB_HSX = 1.5 V
VCCP - VB_HSX = 2.0 V
VCCP - VB_HSX > 2.0 V -38 -67 -83 -78 -79 -84 -95 -9.1 -18 -29 -39 -42 -43 -47 mA RDB_HSX Bootstrap path resistance
VCCP - VB_HSX < 1.0 V – – 30  VB_HSX_VCCP__TH Bootstrap path VB_HSX to VCCP voltage threshold when bootstrap voltage rising -150 – -30 mV VB_HSX_VCCP__TH Bootstrap path VB_HSX – VCCP voltage threshold when bootstrap voltage falling -165 – -40 mV VB_HSX_VCCP__TH _HYST Bootstrap path VB_HSX – VCCP threshold hysteresis 0.0 – 30 mV tDB_HSX_ON Bootstrap switch turn on delay during PWM
Delay from VB_HSx < VCCP to bootstrap switch ON including comparator delay and CP charge time. – – 450 ns (46) tMAXB_HSX_ON Bootstrap switch on time after switching
After this time the bootstrap switch NMOS transistor is switched off due to gate discharge currents. 100 – ms ms (46) IDB_HSX_LOW Bootstrap low current limit -570 -375 -280 µA Note 46. This parameter is derived mainly from simulation and is guaranteed by design characterization on a small sample size of typical devices under typical conditions, unless otherwise noted.

39 NXP Semiconductors

6.3.2.1 Bootstrap start-up default sequence

The typical way to startup the bootstrap capacitor for each high-side pre-driver requires the topology shown in Figure 14. Figure 14. Booststrap load current path during start-up default sequence The DBG pin must be set high or unconnected, as a weak high-side pull-up is internally implemented when the device was in reset. from S_HSx of the high-side pre-driver to at least one D_LSx pin or to GND.

The bootstrap diode current is limited
The VSRC threshold is forced, so it cannot be used during this phase
All low-side biasings are activated
All high-side biasings are disabled. This initialization phase is interrupted if one of the following conditions is reached individually for each high-side pre-driver:
B_HSx voltage is close to VCCP voltage (typically 7.0 V) and the S_HSx voltage is below 0.5 V, in a range of 36ms after the VCCP undervoltage threshold VUVVCCP+ was exceeded, then 1.0 V
The bootstrap voltage clamp is active and the S_HSx voltage is below 0.5 V, in a range of 36 ms after the VCCP undervoltage threshold VUVVCCP+ was exceeded, then 1.0 V
The low-side pre-driver affected to the high-side pre-driver is switched on by the microcores or by SPI
The low-side pre-driver to the high-side pre-driver association is disabled
The high-side pre-driver switched on The association described by the following is configured through the Hs12_ls_act register (0x1A6), the Hs34_ls_act register (0x1A7), and the Hs5_ls_act register (0x1A8). If two high-side pre-drivers are affected by a unique low-side pre-driver, the suitable blanking times must be applied to avoid unexpected interruption of the initialization phase from being interrupted before completion. During this blanking time none of the two high-side biasing must be turned on by the SPI or microcore.

Table 35. Bootstrap charge time up to 7.0 V during start-up default sequence

association in the Hs12_ls_act register (0x1A6), the Hs34_ls_act register (0x1A7), and the Hs5_ls_act register (0x1A8).

6.3.2.2 Bootstrap start-up sequence using the charge pump

be drawn from the B_HSx pin. Figure 15. Booststrap load current path during start-up sequence using charge pump supplied with VCC5, and the VBOOST pin voltage is greater than 4.7 V, and POResetB is deactivated. it can pre-charge the bootstrap capacitor at power up.

6.3.3 Charge pump

(for example, VBAT or VBOOST). charge pump sustains the voltage at each bootstrap capacitor when it is not being charged by low-side switching. bootstrap capacitor charged via independent current sources, to guarantee a minimum VGS voltage. current capacity is sufficient only for low frequency switching. in addition, VCC5 supplies the charge pump circuitry. Table 36. Bootstrap charge time up to 7.0 V using charge pump

41 NXP Semiconductors

Each current source charges its bootstrap capacitor as long as the voltage at its B_HSX pin is less than the charge pump output voltage. 4.7 V. The charge pump is not running as long as the POResetB reset signal is active.

6.3.4 Safe state of high-side pre-driver

voltage is greater than a typical voltage of 1.1 V.

6.3.5 High-side pre-drivers in low-side configuration

All high-side pre-drivers can be used as low-side pre-drivers. In this configuration, an external booststrap capacitor is still required. However, the VDS monitoring for this low-side MOSFET is not functional.

6.4 Low-side pre-drivers (LS1 - LS6)

6.4.1 General description

level MOSFETs. These pre-drivers are dedicated the load driving like injectors or solenoid and integrate diagnosis features. Table 37. Charge pump electrical specifications

0.0 V < V_S_HSX < VBOOST

VBOOST > 4.7 V; VS_HSx = 4.7 V
VBOOST > 6.0 V; VS_HSx = 6.0 V
VBOOST > 69 V; VS_HSx = 69 V
VBOOST > 72 V; VS_HSx = 72 V VS_HSX + 4 VS_HSX + 6 VS_HSX + 6 VS_HSX + 4 V Note 47. This parameter is derived mainly from simulation and is guaranteed by design characterization on a small sample size of typical devices under typical conditions, unless otherwise noted.

Figure 16. Low-side pre-driver block diagram power on reset state (RSTB low). MOSFET in low-side configuration. The logic command lsx_command, to switch the external MOSFET, is provided by the digital block.

The signal DrvEn is issued from the DRVEN pin. As long as the DrvEn signal is negated, the low-side pre-driver is switched off. The low-side pre-driver 3 and 6 includes a feature to override the switch off path via the DrvEn signal. As long as the hs5_ls36_en_ovr bit of the Driver_config register (0x1C5) is set to ‘1’, the pre-drivers are not influenced by DrvEn.
The VCCP undervoltage signals (uv_vccp) issued from the VCCP_ UV monitoring. In case of an undervoltage, the external MOSFET is switched off
The VCC5 undervoltage signals (uv_vcc5) issued from the VCC5_UV monitoring. In case of an undervoltage, the external MOSFET is switched off
The cksys_drven signal issued from the clock monitoring. In the event of a missing clock, the external MOSFET is switched off. This condition can be optionally disabled.
The logic command coming from channel logic (lsx_in) The truth table describing the status of lsx_command signal is given in Table 38.

Table 38. Low-side pre-driver truth table

When lsx_command is low, the G_LSx pin is driven low (pull-down to PGND voltage)
When lsx_command is high, the G_LSx pin is driven high (pull-up to VCCP voltage)

43 NXP Semiconductors

Table 39. Low-side pre-drivers on state electrical specifications

VD_LSx = 13.5 V
VD_LSx = 40 V 110 320 µA fG_LSX_PWM PWM frequency
Nominal
t < 50 µs - for short periods of 50 µs every 1.0 ms 0.0 0.0 100 200 kHz (50) (51) (52) DCG_LSX Duty cycle 0.0 – 100 % (50) IG_LSX_PWM G_LSX current (average during PWM operation)
QG = QG_LSX; fPWM = 100 kHz – 3.0 5.0 mA (50) IG_LSX_SRC Peak source gate drive current at fastest slew rate setting and VCCP = VGS = 7.0 V – 230 – mA (50) IG_LSX_SRC Peak sink gate drive current at fastest slew rate setting and VCCP = VGS = 7.0 V – 440 – mA (50) tR_G_LSX Turn on rise time, 10%-90% of output voltage; VCCP = 7.0 V; at Open pin 5.0 – 25 ns (50) tF_G_LSX Turn off fall time, 90%-10% of output voltage; VCCP = 7.0 V; at Open pin 5.0 – 25 ns (50) tDON_G_LSX Turn on propagation delay at 300V/µs slew rate; 10% of output voltage change; CLOAD = 4.7 nF; RG = 40.2 ; VCCP = 7.0 V 10 – 70 ns (50) tDOFF_G_LSX Turn off propagation delay at 300V/µs slew rate; 10% of output voltage change; CLOAD = 4.7 nF; RG = 40.2 ; VCCP = 7.0 V 10 – 70 ns (50) tDON_G_LSX Turn on propagation delay at 50 V/µs slew rate; 10% of output voltage change; CLOAD = 4.7 nF; RG = 40.2 ; VCCP = 7.0 V 10 – 80 ns (50) tDOFF_G_LSX Turn off propagation delay at 50 V/µs slew rate; 10% of output voltage change; CLOAD = 4.7 nF; RG = 40.2 ; VCCP = 7.0 V 10 – 80 ns (50) tDON_G_LSX Turn on propagation delay at 25 V/µs slew rate;10% of output voltage change; CLOAD = 4.7 nF; RG = 40.2 ; VCCP = 7.0 V 15 – 120 ns (50) tDOFF_G_LSX Turn off propagation delay at 25 V/µs slew rate; 10% of output voltage change; CLOAD = 4.7 nF; RG = 40.2 ; VCCP = 7.0 V 15 – 120 ns (50) tDON_G_LSX Turn on propagation delay at 12.5V/µs slew rate; 10% of output voltage change; CLOAD = 4.7 nF; RG = 40.2 ; VCCP = 7.0 V 15 – 150 ns (50) tDOFF_G_LSX Turn off propagation delay at 12.5V/µs slew rate; 10% of output voltage change; CLOAD = 4.7 nF; RG = 40.2 ; VCCP = 7.0 V 15 – 150 ns (50) Note 50. This parameter is derived mainly from simulation and is guaranteed by design characterization on a small sample size of typical devices under typical conditions, unless otherwise noted. 51. The minimum admitted series resistor is 0 . 52. The external low-side MOSFET gate charge must not exceed 50 nC. A gate charge of maximum 75 nC is admitted if the fPWM 67 kHz. A gate charge of maximum 100 nC is admitted if the fPWM 50 kHz.

6.4.2 Low-side pre-driver slew rate control

Each driver strength can be selected individually by the SPI registers within a set of values. There are four selectable driver strengths. such as to keep the same absolute slew rate. but with the possibility of rapidly changing to the highest slew rate with the microcode instruction stslew. Table 40. Low-side pre-drivers off state electrical specifications Table 41. Low-side pre-drivers slew rate settings Table 42. Low-side pre-drivers slew rates characteristics parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

at external VGS = 2.5 V
at external VGS = 1.0 to 4.0 V 8.8 7.5 14.6 25.3 31.3 W RDS_HSX_N (00) G_HSx nMOS RDS_ON (00), 300 V/µs, VCCP = 7.0 V
at external VGS = 2.5 V
at external VGS = 1.0 to 4.0 V 3.4 2.5 5.9 11.1 16.5 W RDS_HSX_P (01) G_HSx pMOS RDS_ON (01), 50 V/µs, VCCP = 7.0 V
at external VGS = 1.0 to 4.0 V 61 84 115 W RDS_HSX_N (01) G_HSx nMOS RDS_ON (01), 50 V/µs, VCCP = 7.0 V
at external VGS = 1.0 to 4.0 V 23 35 50 W RDS_HSX_P (10) G_HSx pMOS RDS_ON (10), 25 V/µs, VCCP = 7.0 V
at external = 1.0 to 4.0 V 122 170 230 W RDS_HSX_N (10) G_HSx nMOS RDS_ON (10), 25 V/µs, VCCP = 7.0 V
at external VGS = 1.0 to 4.0 V 47 69 100 W RDS_HSX_P (11) G_HSx pMOS RDS_ON (11), 12.5 V/µs, VCCP = 7.0 V
at external VGS = 1.0 to 4.0 V 245 337 460 W RDS_HSX_N (11) G_HSx nMOS RDS_ON (11), 12.5 V/µs, VCCP = 7.0 V
at external VGS = 1.0 to 4.0 V 94 138 199 W

45 NXP Semiconductors

6.4.3 Safe state of low-side pre-driver

buffer capacitor, and a low level output is guaranteed, as long as a typical voltage greater than 1.1 V is available.

6.5 VDS and VSRC monitor and load biasing

low-side pre-divers. The LS7 pre-driver dedicated to the DC-DC converter does not integrate this diagnosis feature. Moreover, a source voltage monitoring function VSRC populates each of the five high-side pre-drivers.

the voltage between the VBOOST or VBATT pin, and the source pin of the external MOSFET connected to the S_HSx device pin, for the HS2 and HS4 high-side pre-drivers
the voltage between the VBATT pin and the source pin of the external MOSFET connected to the S_HSx device pin, for the HS1, HS3, and HS5 high-side pre-drivers
the voltage between the drain pin of the external MOSFET connected to the D_LSx device pin and the PGND pin, for the low-side pre-drivers

Figure 17. VDS and VSRC monitors and load biasing

1 ck cycle at 6.0 MHz – – 166 ns (53) Note 53. This parameter is derived mainly from simulation and is guaranteed by design characterization on a small sample size from typical devices under typical conditions, unless otherwise noted.

Table 42. Low-side pre-drivers slew rates characteristics (continued) parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

Figure 18. VDS monitors and load biasing for HS2 and HS4 S_HSx device pin and the PGND pin.

the Vds_threshold_hs (0x18A) register for the high-side pre-drivers VDS threshold
the Vsrc_threshold_hs (0x18B) register for the high-side pre-drivers VSRC threshold
the Vds_threshlod_ls_1 (0x18C) and Vds_threshlod_ls_1 (0x18D) registers for the low-side pre-drivers VDS threshold These thresholds are selectable either by the SPI or by microcode (chth instruction). The VDS and VSRC monitor functions are available, since the corresponding pre-drivers are supplied. The high-side VDS and VSRC monitors can work in standalone mode without using the associated high-side pre-driver. In this case, the B_HSX and G_HSX outputs is not connected and the corresponding high-side driver cannot be used. The S_HSX input can be connected to any node, as long as the maximum is within the pin’s maximum rating range.

6.5.1 High-side VDS And VSRC monitoring

The high-side VDS and VSRC monitors are functionally independent from the bootstrap voltage of the high-side pre-driver. the S_HSX source pin and PGND (voltage across the freewheeling element, either a diode or a MOSFET). The instruction slfbk allows to select which of the two feedbacks hsx_vds_vboost_fbk or hsx_vds_vbatt_fbk, enables the microcores. eight values, according to the hsx_vds_threshold(2:0) and the hsx_src_threshold(2:0) signal, provided by the digital cores. Vds_regfile registers (0x18A and 0x18B).

47 NXP Semiconductors

to the nominal behavior in less than a typical 300 ns. a duration shorter than 400 ns at a very high MOSFET switch. Table 43. VDS and VSRC monitoring typical threshold selection for high-side pre-drivers Table 44. High-side VDS and VSRC monitoring electrical specifications

Transients t < 400 ns
Transients t < 800 ns -3.0 -8.0 -6.0 V (54) VVBATT_VDS High-side VDS/SRC monitoring functional range VBATT
VDS_HS_TH 3.5 V is at 3.0 V min. 5.5 5.0 5.5 V VVBOOST_VDS High-side VDS/SRC monitoring functional range VBOOST
VDS_HS_TH 3.5 V is at 3.0 V min. 5.5 5.0 5.5 V VDS_HS_TH High-side VDS threshold (000)
VVBATT_VDS = 5.0 V to 72 V
VVBOOST_VDS = 5.0 V to 72 V -0.1 0.0 0.1 V VDS_HS_TH High-side VDS threshold (001)
VVBATT_VDS = 5.0 V to 72 V
VVBOOST_VDS = 5.0 V to 72 V 0.4 0.5 0.6 V VDS_HS_TH High-side VDS threshold (010)
VVBATT_VDS = 5.0 V to 72 V
VVBOOST_VDS = 5.0 V to 72 V 0.9 1.0 1.1 V VDS_HS_TH High-side VDS threshold (011)
VVBATT_VDS = 5.0 V to 72 V
VVBOOST_VDS = 5.0 V to 72 V 1.35 1.5 1.65 V VDS_HS_TH High-side VDS threshold (100)
VVBATT_VDS = 5.0 V to 72 V
VVBOOST_VDS = 5.0 V to 72 V 1.8 2.0 2.2 V VDS_HS_TH High-side VDS threshold (101)
VVBATT_VDS = 5.0 V to 72 V
VVBOOST_VDS = 5.0 V to 72 V 2.29 2.45 2.61 V

VVBATT_VDS = 5.0 V to 72 V
VVBOOST_VDS = 5.0 V to 72 V 2.76 2.95 3.14 V VDS_HS_TH High-side VDS threshold (111)
VVBATT_VDS = 5.5 V to 72 V
VVBOOST_VDS = 5.5 V to 72 V
VVBATT_VDS = 5.0 V to 5.5 V
VVBOOST_VDS = 5.0 V to 5.5 V 3.23 3.23 3.0 3.0 3.5 3.5 3.45 3.45 3.67 3.67 3.67 3.67 V tTH_HSVDS High-side VDS/SRC threshold settling time
From HS_VDS/SRC_threshold(2:0) change to threshold stable – 0.4 1.0 µs (54) tD_HSVDS High-side VDS/SRC comparator switching time, Propagation delay + rise/fall time
At 100 mV overdrive
At 200 mV overdrive
At 300 mV overdrive 1.0 0.8 0.6 1.5 1.1 1.0 µs (54)(55) tR_HSVDS High-side VDS/SRC comparator recovery time after dVD/dt
Recovery time after dVD/dt is removed – – 300 ns (54) SRHSVDS High-side VDS/SRC comp. input voltage slew rate with good output at VDS_HS=0.75 V with VS_HSx from 13.5 V to 72 V and from 72 V to 13.5 V – – 100 V/µs (54) VSRC_HS_TH High-side VSRC threshold (000) -0.1 0.0 0.1 V VSRC_HS_TH High-side VSRC threshold (001) 0.4 0.5 0.6 V VSRC_HS_TH High-side VSRC threshold (010) 0.9 1.0 1.1 V VSRC_HS_TH High-side VSRC threshold (011) 1.35 1.5 1.65 V VSRC_HS_TH High-side VSRC threshold (100) 1.8 2.0 2.2 V VSRC_HS_TH High-side VSRC threshold (101) 2.38 2.55 2.72 V VSRC_HS_TH High-side VSRC threshold (110) 2.85 3.0 3.15 V VSRC_HS_TH High-side VSRC threshold (111) 3.33 3.5 3.68 V VSRC_HS_Th High-side VSRC threshold (000) including crosstalk -0.2 0.0 0.2 V (54)(56) VSRC_HS_Th High-side VSRC threshold (001) including crosstalk 0.3 0.5 0.7 V (54)(56) VSRC_HS_Th High-side VSRC threshold (010) including crosstalk 0.8 1.0 1.2 V (54)(56) VSRC_HS_Th High-side VSRC threshold (011) including crosstalk 1.25 1.5 1.75 V (54)(56) VSRC_HS_Th High-side VSRC threshold (100) including crosstalk 1.7 2.0 2.3 V (54)(56) VSRC_HS_Th High-side VSRC threshold (101) including crosstalk 2.28 2.55 2.82 V (54)(56) VSRC_HS_Th High-side VSRC threshold (110) including crosstalk 2.75 3.0 3.25 V (54)(56)

Table 44. High-side VDS and VSRC monitoring electrical specifications (continued)

49 NXP Semiconductors

6.5.2 Low-side VDS monitoring

and ground, the voltage drop on the resistor is included in the measurement. programmed through the SPI by accessing the Vds_regfile registers (0x18C and 0x18D). disturbance is applied, the function recovers from the disturbance removal to a nominal behavior in less than a typical 300 ns. source pin of a different load connected to the same bank, can go down to a typical -3.0 V. is not connected. The D_LSX input can be connected to any node within the pin maximum ratings voltage range.

This parameter is derived mainly from simulation and is guaranteed by design characterization on a small sample size of typical devices under

typical conditions, unless otherwise noted.

The high value is a worst case consideration on an overdrive of 100 mV.
To limit the amplitude of the crosstalk to the specified value, the sequence of monitor threshold switching must not exceed a certain number of

must be spread over a time window tM_D which meets the condition: tM_D  (M - 7) * 1.67 µs. Table 45. VDS monitoring typical threshold selection for low-side pre-drivers Table 46. Low-side VDS monitoring electrical specifications

Transients t < 400 ns -3.0 -8.0 – V (57) VDS_LS_TH Low-side VDS threshold (000) -0.1 0.0 0.1 V VDS_LS_TH Low-side VDS threshold (001) 0.4 0.5 0.6 V VDS_LS_TH Low-side VDS threshold (010) 0.9 1.0 1.1 V

6.5.3 Load biasing structures

load, during the idle phases.

the activation of each pull-up voltage source SRCPUX connected to each of the S_HSx pins. Each pull-up voltage source is supplied from VCC5.
the activation of each pull-down current sources SRCPDX connected to each of the D_LSx pins. Each pull-down voltage source referenced to ground. When the battery voltage VBATT is in the nominal range or greater, the external load is biased at a minimum voltage of typically 3.8V. In a low battery voltage condition (VBATT < 8.0 V), the load is biased at half the VBATT voltage, to guarantee symmetrical voltage margins to high-side and low-side VDS comparators. VDS_LS_TH Low-side VDS threshold (011) 1.35 1.5 1.65 V VDS_LS_TH Low-side VDS threshold (100) 1.8 2.0 2.2 V VDS_LS_TH Low-side VDS threshold (101) 2.38 2.5 2.63 V VDS_LS_TH Low-side VDS threshold (110) 2.85 3.0 3.15 V VDS_LS_TH Low-side VDS threshold (111) 3.33 3.5 3.68 V VDS_LS_Th Low-side VDS threshold (000) incl. crosstalk -0.2 0.0 0.2 V (57)(58) VDS_LS_Th Low-side VDS threshold (001) incl. crosstalk 0.3 0.5 0.7 V (57)(58) VDS_LS_Th Low-side VDS threshold (010) incl. crosstalk 0.8 1.0 1.2 V (57)(58) VDS_LS_Th Low-side VDS threshold (011) incl. crosstalk 1.25 1.5 1.75 V (57)(58) VDS_LS_Th Low-side VDS threshold (100) incl. crosstalk 1.7 2.0 2.3 V (57)(58) VDS_LS_Th Low-side VDS threshold (101) incl. crosstalk 2.28 2.5 2.73 V (57)(58) VDS_LS_Th Low-side VDS threshold (110) incl. crosstalk 2.75 3.0 3.25 V (57)(58) VDS_LS_Th Low-side VDS threshold (111) incl. crosstalk 3.23 3.5 3.78 V (57)(58) tTH_LSVDS Low-side VDS threshold settling time – 0.4 1.0 µs (57) tD_LSVDS Low-side VDS comparator switching time
From LS_VDS_TH(1:0) change to VDS_LSTH stable – 0.3 1.0 µs (57) tR_LSVDS Low-side VDS comparator recovery time after dVD/dt
Recovery time after dVD/dt is removed – – 300 ns (57) Note 57. This parameter is derived mainly from simulation and is guaranteed by design characterization on a small sample size of typical devices under typical conditions, unless otherwise noted. 58. To limit the amplitude of the crosstalk to the specified value, the sequence of monitor threshold switching must not exceed a certain number of switches in any given time window. Any sequence of n commands which increase a threshold of a low-side VDS or high-side VSRC monitor must be spread over a time window tN_I which meets the condition: tN_I >= (n - 7) * 1.67µs. Any sequence of m commands which decrease a threshold must be spread over a time window tM_D which meets the condition: tM_D >= (M - 7) * 1.67 µs.

Table 46. Low-side VDS monitoring electrical specifications (continued)

51 NXP Semiconductors

Figure 19. Biasing Voltage vs. VBATT the control signals hsx_bias, hsx_bias_strong, and lsx_bias. All the biasings can be enabled by the microcores using the bias instruction. To prevent overloading on VCC5, switching on all the high-side pull-up structures simultaneously is not possible. to generate the VBATT/2 reference is disconnected from the VBATT pin as soon as RSTB is activated. outputs can be connected to any node within the pin’s maximum rating voltage range. path, without switching on the low-side MOSFETs. In this case, the corresponding pull-up voltage sources must be disabled. Table 47. Load biasing HS2 and HS4 control table Table 48. Load biasing electrical specifications

Maximum current from VCC5 26 – – mA VBIAS_HS S_HSx bias voltage regulation
VBATT > 8.0 V, VCC5 > 4.75 V
VBATT < 8.0 V, VCC5 > 4.75 V 3.8 (VBATT/2) - 200 mV VBATT/2 VCC5 (VBATT/2) + 200 mV V (60)(60) VS_HS_BIAS S_HSx voltage range when load biasing is switched on (S_HSx current source is switched off automatically when S_HSx is above 5.0 V)
Transients t < 400 ns
Transients t < 800 ns -3.0 -8.0 -6.0 V (60) VD_LSX_BIAS D_LSx voltage range when load biasing is switched on
Transients t < 400 ns -3.0 -8.0 – V (60)

6.6 Current measurement

Three general purpose blocks
One extended mode block for DC-DC Converters

6.6.1 General purpose current measurement block

Figure 20. General purpose current measurement block diagram

VCC5 = 4.75 V, IBIAS_HS1/3/5 = 2.8 mA, IBIAS_HS_Max = 18.4 mA – – 0.95 V VBIAS_HS Voltage dropout across HS2/4 current source
VCC5 = 4.75 V, IBIAS_HS2/4 = 7.0 mA, IBias_HS_Max = 18.4 mA – – 0.95 V VBIAS_LS Voltage dropout across LS current source
IBIAS_LS = saturation current
IBIAS_LS = 500 µA
IBIAS_LS = 300 µA 2.5 700 400 V mV mV RBIAS_LS Equivalent resistance of LS current source CS_HSX S_HSx capacitive load to GND connected via, L = 2.0 nH… 200 nH and R = 2.0 m… 200 m 0.01 – 25 nF (60) Note 59. The VBIAS_HS value is specified with a load series resistor load and the corresponding low-side and high-side load biasing turned on. 60. This parameter is derived mainly from simulation and is guaranteed by design characterization on a small sample size of typical devices under typical conditions, unless otherwise noted.

Table 48. Load biasing electrical specifications (continued)

53 NXP Semiconductors

signal amplification. The gain can be changed at runtime by the microcore. The differential amplifier also adds a constant offset to its output. Therefore, the output of the amplifier is always positive. keep the voltage at the comparator input stable during the ADC conversion.

6.6.2 Current sense amplifier

VDA_SENSE = (VVSENSEPx - VVSENSENx) * GDA_DIFF + VDA_BIAS VDA_BIAS is the fixed voltage biasing applied to the differential amplifier output. The GDA_DIFF gain value is configurable at runtime (opampx_gain(1:0)). The allowed differential mode input voltages depend on the chosen gain value.
VDA_DIFF_IN = (VVSENSEPx - VVSENSENx) The amplifier can achieve even lower voltages than VDA_BIAS, when the differential input voltage is below zero, to make it able to measure small negative currents. The amplifier is fully operational down to an output voltage of typically 100 mV. The amplifier is not designed to be used with series resistors between shunt and VSENSEPx/VSENSENx inputs. Detection delay including comparators, is typically 50 to 500 ns, depending on gain setting, set point value, and input voltage slew rate.

Table 49. Overall current sense performance for positive current measurement parameter means at TA = 25 °C under nominal conditions, unless otherwise noted. after analog offset compensation.

at GDA_diff(00) = 5.79
at GDA_diff(01) = 8.68
at GDA_diff(10) = 12.53
at GDA_diff(11) = 19.25 at DAC range of 25%-75%, after analog offset compensation.
at GDA_diff(00) = 5.79
at GDA_diff(01) = 8.68
at GDA_diff(10) = 12.53
at GDA_diff(11) = 19.25 ±3.5 ±3.5 ±3.6 ±3.7 ±5.3 ±5.4 ±5.4 ±5.4 % (61) Note 61. All input tolerances from the device specification are assumed at 6.0 .

Table 50. Current sense amplifier overall gain selection table

Table 51. Differential amplifiers 1, 2, 3, 4H, and 4L electrical specifications even if the differential voltage at the input is < 0.0 V. even if the differential voltage at the input is < 0.0 V.

GDA_DIFF(10) = 12.53 -12 – 179 mV (62) VDA_DIFF_IN Differential input voltage range (11) GDA_DIFF(00) Differential voltage gain (00) 5.71 5.79 5.87 GDA_DIFF(01) Differential voltage gain (01) 8.55 8.68 8.81 GDA_DIFF(10) Differential voltage gain (10) 12.32 12.53 12.74 GDA_DIFF(11) Differential voltage gain (11) 18.92 19.25 19.58 tDA_GAIN_SW Gain switching settling time – – 2.0 µs (62) SRDA_DIFF_IN Differential input voltage maximum slew rate 140 – – mV/µs (62)(63) RVSENSENX_IN Input impedance VSENSENX (x = 1, 2, 3)
1.0 V common mode voltage 18 – 36 k RVSENSEPX_IN Input impedance VSENSEPX (x = 1, 2, 3)
1.0 V common mode voltage 18 – 36 k VDA_BIAS Output bias voltage 240 250 265 mV VDA_OUT_OFF Maximum output offset voltage error at maximum gain; Including amplifier input offset and bias voltage offset. Calculated using the highest gain of 19.25 -140 – 220 mV . VDA_OUT Differential amplifier x output voltage range 0.1 – 2.7 V SRDA Differential amplifier x output slew rate 2.8 – – V/µs (62) Note 62. This parameter is derived mainly from simulation and is guarantee by design characterization on a small sample size of typical devices under typical conditions, unless otherwise noted. 63. Considering an external output capacitor CVSENSE typically value of 330 pF. This external capacitor is recommended for improve EMI performances.

55 NXP Semiconductors

6.6.3 Current sense DAC

comparator (dacy_Value (7:0)). The current threshold can be calculated using the following formula.

I = (DAC_VALUE * VDAC LSB- VDA_BIAS)/(GDA_DIFF * RSENSEx) The DAC_VALUE is selected and changed at runtime by the digital microcore by means of the signal dacx_value (7:0). A DAC_VALUE below the hexadecimal value 0x0A, must be avoided, as the current sense differential amplifier does not operate with full performance at output voltages below 100 mV. VDAC LSB is the DAC resolution. VDA_BIAS is the fixed voltage biasing applied to the differential amplifier output. The Gain Value GDA_DIFF is configurable at runtime (opampx_gain(1:0)). RSENSEx is the external sense resistor of the current measurement channel x.

Table 52. Current sense DAC values examples

6.6.4 Current sense comparator

directly acquired by the digital microcore. The detection delay from current threshold, reached to the curx_fbk comparator output toggling, is provided in Table 55. Table 53. DAC 1, 2, 2, 4L and 4H electrical specifications

DAC code = 0x00 – 0.0 – V VDAC_OUT_MAX DAC maximum output voltage
DAC code = 0xFF – 2.49 – V EDAC_GAIN DAC maximum gain error; error of bandgap reference voltage -1.0 – 1.0 % EDAC_DNL DAC differential linearity error -0.5 – 0.5 LSB EDAC_INL DAC integral linearity error -1.0 – 1.0 LSB VDAC_OUT_OFF DAC maximum output offset 0.0 – 10 mV tDAC DAC settling time – – 0.9 µs (64) Note 64. This parameter is derived mainly from simulation and is guaranteed by design characterization on a small sample size of typical devices under typical conditions, unless otherwise noted.

Table 54. Comparator electrical specifications

This parameter is derived mainly from simulation and is guaranteed by design characterization on a small sample size of typical devices under

typical conditions, unless otherwise noted.

57 NXP Semiconductors

Table 55. Current measurement channel 1, 2, 3, and 4H and 4L detection delays specifications

GDA_DIFF(00) = 5.79
GDA_DIFF(01) = 8.68
GDA_DIFF(10) = 12.53
GDA_DIFF(11) = 19.25 100 130 140 260 270 320 400 ns (66) tD_CS_SLOW Detection delay coming from differential amplifier and comparator for set point value 400 mV to 2.35 V and input voltage slew rate of 2.0 mV/µs
GDA_DIFF(00) = 5.79
GDA_DIFF(01) = 8.68
GDA_DIFF(10) = 12.53
GDA_DIFF(11) = 19.25 110 140 260 280 300 350 ns (66) tD_CS_150_MID Detection delay coming from differential amplifier and comparator for set point value 150 mV and input voltage slew rate of 20 mV/µs
GDA_DIFF(00) = 5.79
GDA_DIFF(01) = 8.68
GDA_DIFF(10) = 12.53
GDA_DIFF(11) = 19.25 100 120 200 220 260 300 ns (66) tD_CS_MID Detection delay coming from differential amplifier and comparator for set point value 400 mV to 2.35 V and input voltage slew rate of 20 mV/µs
GDA_DIFF(00) = 5.79
GDA_DIFF(01) = 8.68
GDA_DIFF(10) = 12.53
GDA_DIFF(11) = 19.25 100 170 180 200 240 ns (66) tD_CS_150_FAST Detection delay coming from differential amplifier and comparator for set point value 150 mV and input voltage slew rate of 140 mV/µs
GDA_DIFF(00) = 5.79
GDA_DIFF(01) = 8.68
GDA_DIFF(10) = 12.53
GDA_DIFF(11) = 19.25 100 160 180 220 280 ns (66) tD_CS_FAST Detection delay coming from differential amplifier and comparator for set point value 400 mV to 2.35 V and input voltage slew rate of 140 mV/µs
GDA_DIFF(00) = 5.79
GDA_DIFF(01) = 8.68
GDA_DIFF(10) = 12.53
GDA_DIFF(11) = 19.25 100 115 130 160 200 ns (66) tD_CS_SLOW Detection delay transition 0 to 1 coming from differential amplifier and comparator for input voltage slew rate of 20 mV/µs
GDA_DIFF(00) = 5.79 and set point value of 300 mV to 2.35 V
GDA_DIFF(01) = 8.68 and set point value of 300 mV to 2.35 V
GDA_DIFF(10) = 12.53 and set point value of 300 mV to 2.35 V
GDA_DIFF(11) = 19.25 and set point value of 300 mV to 2.35 V 110 140 150 190 250 ns (66)

6.6.5 Current measurement offset compensation

the sense resistor of the related measurement channel. compensation sequence, the curx_fbk comparator output signal is always low. Each new offset compensation starts, based on the result of the previous offset compensation run, for this current measurement channel. aborted, maintaining the last compensation value reached when the procedure was interrupted. signal, and VCS_OAX_OFF when using the path to the OA_x amplifier input.

GDA_DIFF(00) = 5.79 and set point value of 300 mV to 2.35 V
GDA_DIFF(01) = 8.68 and set point value of 300 mV to 2.35 V
GDA_DIFF(10) = 12.53 and set point value of 300 mV to 2.35 V
GDA_DIFF(11) = 19.25 and set point value of 300 mV to 2.35 V 120 180 200 220 270 ns (66) tD_CS_FAST Detection delay transition 0 to 1 coming from differential amplifier and comparator for input voltage slew rate of 140 mV/µs
GDA_DIFF(00) = 5.79 and set point value of 300 mV to 2.35 V
GDA_DIFF(01) = 8.68 and set point value of 300 mV to 2.35 V
GDA_DIFF(10) = 12.53 and set point value of 300 mV to 2.35 V
GDA_DIFF(11) = 19.25 and set point value of 300 mV to 2.35 V 120 140 160 190 ns (66) tD_CS_FAST Detection delay transition 1 to 0 coming from differential amplifier and comparator for input voltage slew rate of 140 mV/µs
GDA_DIFF(00) = 5.79 and set point value of 300 mV to 2.35 V
GDA_DIFF(01) = 8.68 and set point value of 300 mV to 2.35 V
GDA_DIFF(10) = 12.53 and set point value of 300 mV to 2.35 V
GDA_DIFF(11) = 19.25 and set point value of 300 mV to 2.35 V 130 150 170 210 ns (66) Note 66. This parameter is derived mainly from simulation and is guaranteed by design characterization on a small sample size of typical devices under typical conditions, unless otherwise noted.

Table 56. Differential amplifier 1, 2, 3, 4L, and 4H analog offset compensation electrical specifications

GDA_DIFF(11) = 19.25, Offset DAC value = +31 150 – 310 mV VOFFDAC_OUT_MAX _NEGT Offset compensation voltage range referred to amplifier output offset at maximum gain
GDA_DIFF(11) = 19.25, Offset DAC value = -31 -310 – -150 mV

Table 55. Current measurement channel 1, 2, 3, and 4H and 4L detection delays specifications (continued)

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DAC code = 0x1A – 253.9 – mV (67) tOFFCOMP_STEP Offset compensation minimum step time
GDA_DIFF(11) = 19.25 – – 2.0 µs tOFFCOMP Offset compensation runtime to finish compensation Note 67. This parameter is derived mainly from simulation and is guaranteed by design characterization on a small sample size of typical devices under typical conditions, unless otherwise noted.

Table 56. Differential amplifier 1, 2, 3, 4L, and 4H analog offset compensation electrical specifications (continued)

6.7 Current measurement for DC-DC conversion

provide an overcurrent supervision at the booster capacitor. Figure 21. 4th current measurement block diagram able to provide a short delay from the VSENSE inputs to the G_LS7 output. has to be considered in the application. single topology implemented into the three other current measurement blocks.

6.7.1 Negative current differential amplifier

voltages are applied, the amplifier output behavior is monotonic. Table 57. Overall current sense performance for negative current measurement parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

at GDAneg_diff=-2.0 at DAC range of 25%-75%
at GDAneg_diff=-2.0 ±4.4 ±8.9 % (68) Note 68. All input tolerances from the device specification are assumed at 6.0 .

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6.7.2 Negative current DAC

I = (DACNEG_VALUE * VDACNEG_LSB - VDANEG_BIAS)/(GDANEG_DIFF * RSENSE4) DACNEG_VALUE is selected and changed at runtime by the digital microcore (dac4neg_values(3:0)) VDACNEG_LSB is the DAC resolution. VDANEG_BIAS is the fixed voltage biasing applied to the differential amplifier output. GDANEG_DIFF is the amplifier gain of the negative current measurement stage. RSENSE4 is the external sense resistor of the current measurement channel 4.

Table 58. Differential amplifier 4 negative

GDANEG_DIFF = -2.0 -1.125 – 0.0 V (69) GDANEG_DIFF Differential voltage gain -1.966 -2.0 -2.034 SRDANEG_DIFF_IN Differential input voltage maximum slew rate 140 – – mV/µs (69) RVSENSEN4_IN Input impedance VsenseN4
1.0 V common mode voltage 12 – 21 k RVSENSEP4_IN Input impedance VsenseP4
1.0 V common mode voltage 12 – 21 k VDANEG_IN_OFF Differential amplifier maximum input offset voltage -20 – 20 mV VDANEG_BIAS Output bias voltage 240 250 265 mV VDANEG_OUT_OFF Maximum output offset voltage error, including amplifier input offset and bias voltage offset. -60 – 60 mV VDANEG_OUT Differential amplifier x output voltage range 0.0 – 2.7 V (69) SRDANEG Differential amplifier x output slew rate 0.28 – – V/µs (69) Note 69. This parameter is derived mainly from simulation and is guaranteed by design characterization on a small sample size of typical devices under typical conditions, unless otherwise noted.

Table 59. Negative current sense DAC values examples

6.7.3 Negative current comparator

dedicated to the negative current comparator are described by the following. Table 60. DAC 4 neg. electrical characteristics

DAC code = 0x0 – 0.0 – V VDACNEG_OUT_MA X DAC maximum output voltage
DAC code = 0xF – 2.344 – V EDACNEG_GAIN DAC maximum gain error -1.0 – 1.0 % EDACNEG_DNL DAC differential linearity error -0.063 – 0.063 LSB EDACNEG_INL DAC integral linearity error -0.063 – 0.063 LSB VDACNEG_OUT_OFF DAC maximum output offset 0.0 – 10 mV tDACNEG DAC settling time – – 0.9 µs (70) Note 70. This parameter is derived mainly from simulation and is guaranteed by design characterization on a small sample size of typical devices under typical conditions, unless otherwise noted.

Table 61. Voltage comparator 4 neg. electrical characteristics

This parameter is derived mainly from simulation and is guaranteed by design characterization on a small sample size of typical devices under

typical conditions, unless otherwise noted.

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6.7.4 Negative current sense

output cur4h_fbk, cur4l_fbk, and cur4neg_fbk are directly acquired by the digital microcore.

6.7.5 Current measurement offset compensation

There is no analog offset compensation for the differential amplifier 4 negative.

6.8 OA_x output pin and multiplexer

6.8.1 General features

gain can be applied to this output signal, such as to rescale the signal and adapt it to an ADC input range of 3.3 or 5.0 V. Four values are available for the oa_gainx(1:0) gain. The maximum output voltage at the OA_x pins depends on the VCC5 value. Table 62. Current measurement channel 4 neg. detection delays

GDANEG_DIFF = -2.0 80 – 200 ns (72) tD_CSNEG_MID Detection delay coming from differential amplifier and comparator for set point value 400 mV to 2.35 V and input voltage slew rate of 20mV/ µs
GDANEG_DIFF = -2.0 75 – 160 ns (72) tD_CSNEG_150_FAST Detection delay coming from differential amplifier and comparator for set point value 150 mV and input voltage slew rate of 140 mV/µs
GDANEG_DIFF = -2.0 55 – 160 ns (72) tD_CSNEG_ FAST Detection delay coming from differential amplifier and comparator for set point value 400 mV to 2.35 V and input voltage slew rate of 140 mV/µs
GDANEG_DIFF = -2.0 50 – 120 ns (72) Note 72. This parameter is derived mainly from simulation and is guaranteed by design characterization on a small sample size of typical devices under typical conditions, unless otherwise noted.

Table 63. OA_x amplifier gain selection and output voltage

then added to the amplified signal. by the digital cores. The configuration tables are given in Table 64 and Table 65. register (0x1AA). Moreover, the output’s signal gains are set in these two registers. Table 64. OA_1 multiplexer logic table(73)

The current measurement 1 and 3 feedbacks can only be routed to the output OA_1. The

current measurement 2 and 4 feedbacks can only be routed to the output OA_2. Table 65. OA_2 multiplexer logic table (74)

The current measurement 1 and 3 feedbacks can only be routed to the output OA_1. The

current measurement 2 and 4 feedbacks can only be routed to the output OA_2.

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6.8.2 OA_x pin digital I/O function

input, the buffer is switched to high-impedance.

6.8.3 A/D multiplexer and OA_x output amplifier enablement

digital flag pin is configured as an input, and the corresponding OA_x output amplifier is switched to HiZ.

6.8.4 OA_x pin I/O voltage

based signal, so the I/O voltage is selected according to the gain value of the OA_x output amplifier.

6.8.5 Weak pull-down resistor

Table 66. OAx enable truth table Table 67. Multiplexer A/D truth table

1 Digital output function

Table 68. OA_x amplifier gain selection

6.8.6 OA_x output offset and offset error

amplified by the OA_x amplifier gain. In addition, a the OA_x amplifier adds input offset of 10 to 13.5 mV. Table 69. OAx input and output values Table 70. OAx output pin and multiplexer electrical characteristics

w/o series resistor, for digital function
RMIN = 50 Ohm
RMIN = 75 Ohm
RMIN = 100 Ohm
RMIN = 200 Ohm 5.0 1.0 100 5.0 pF nF nF nF nF (75) PSRROAX OA_x power supply rejection – – 103 dB (75) GOAX(00) OA_x output gain (00) 1.303 1.33 1.357 GOAX(01) OA_x output gain (01) 1.94 2.0 2.06 GOAX(10) OA_x output gain (10) 2.91 3.0 3.09 GOAX(11) OA_x output gain (11) 5.17 5.33 5.49 GOAX(ADC) OA_x output gain (ADC) 0.98 1.0 1.02 tOAX_GAIN OA_x output gain switching time – – 2.0 µs (75) VOAX_OFFSET OAx output offset voltage from OA_x amplifier
GOAx = 1.0
GOAx = 1.33
GOAx = 2.0
GOAx = 3.0
GOAx = 5.33 -14 -18 -28 -30 -53 mV

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2.0 V, impedance to GND 350 – – k tOAX_MUX OA_x multiplexer switching time – – 10.0 µs (75)(77) VOAx_Drift_ ADC OAx output voltage drift of T&H in ADC mode over time
at VOAx=1.5 V and after 20 µs -50 – 50 mV Notes 75. This parameter is derived mainly from simulation and is guaranteed by design characterization on a small sample size of typical devices under typical conditions, unless otherwise noted. 76. In the path of the current measurement output signal from the differential amplifier to the OA_x pin there is a parasitic low pass filter limiting the bandwidth of this path. 77. When switching the OAx multiplexer of one path this can introduce a glitch on the output signal of the other output. The worst case duration of the glitch is below 10 µs. Moreover the settling time of the switched path this prolonged.

Table 70. OAx output pin and multiplexer electrical characteristics (continued)

6.9 Measurement function electrical characteristics

(MC33816MAE only)

6.9.1 Input voltage and multiplexer S_HSx and D_LSx

6.9.2 Multiplexer OA_Cur and current/voltage

6.9.3 Differential amplifier and attenuation

Table 71: Multiplexer S_HSx and D_LSx characteristics –40 ºC < TAMBIENT < +125 ºC, unless otherwise specified. All voltages are referenced to the AGND pin. Symbol Parameter Min Typ Max Unit RS_HSX_IN S_HSx input impedance at VS_HSx = 10 V 100 — — kΩ RD_LSX_IN D_LSx input impedance at VD_LSx = 10 V 200 — — kΩ tS_HSX_MUX S_HSx multiplexer switching time (1) 1. Guaranteed by design — — 2.0 µs tD_LSX_MUX D_LSx multiplexer switching time (1) — — 2.0 µs Table 72: OA_cur and current/voltage multiplexers switching time –40 ºC < TAMBIENT < +125 ºC, unless otherwise specified. All voltages are referenced to the AGND pin. Symbol Parameter Min Typ Max Unit tOA_Cur_Switch OA_Cur multiplexer switching time — — 5 µs tCurVolt_Switch Current/Voltage multiplexer switching time — — 5 µs Table 73: Attenuation characteristics –40 ºC < TAMBIENT < +125 ºC, unless otherwise specified. All voltages are referenced to the AGND pin. Symbol Parameter Min Typ Max Unit AVOLTATT(000) VoltAtt output attenuation (000) ±10 % precision 27.0 30 33.0 — AVOLTATT(001) VoltAtt output attenuation (001) ±10 % precision 23.4 26 28.6 — AVOLTATT(010) VoltAtt output attenuation (010) ±10 % precision 19.8 22 24.2 — AVOLTATT(011) VoltAtt output attenuation (011) ±10 % precision 18.0 20 22.0 — AVOLTATT(100) VoltAtt output attenuation (100) ±10 % precision 16.2 18 19.8 — AVOLTATT(101) VoltAtt output attenuation (101) ±10 % precision 14.4 16 17.6 — AVOLTATT(110) VoltAtt output attenuation (110) ±10 % precision 12.6 14 15.4 — AVOLTATT(111) VoltAtt output attenuation (111) ±10 % precision 9.0 10 11.0 — MisVOLTATT VoltAtt voltage divider mismatch between D_LSx and S_HSx input divider — — 5.0 % VVOLTATT_OFFSET VoltAtt output offset at AVoltAtt = 10, for OA_Meas2 and, this offset is canceled by the HP filter. –10 — 25 mV tVOLTATT_SWITCH VoltAtt attenuation switching time — — 2.0 ms VVOLTATT_CLAMP VoltAtt output clamping voltage 2.75 — 2.97 V tVOLTATT_REC VoltAtt output clamping recovery time — — 0.5 ms CMRRVOLTATT VoltAtt differential input CMRR 33 — — dB

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6.9.4 Low-pass filter

6.9.5 High-pass filter

Table 74: Low-pass filter cut-off frequency –40 ºC < TAMBIENT < +125 ºC, unless otherwise specified. All voltages are referenced to the AGND pin. Symbol Parameter Min Typ Max Unit fC_LP0 LP cut-off frequency 0 (1) 1. Guaranteed by design 80 115 160 kHz GLP_PB LP passband gain ±1.0 % precision 0.99 1.0 1.01 — Table 75: High-pass filter cut-off frequency –40 ºC < TAMBIENT < +125 ºC, unless otherwise specified. All voltages are referenced to the AGND pin. Symbol Parameter Min Typ Max Unit fc_HP0 HP cut-off frequency 0 2.13 2.30 2.47 kHz fc_HP1 HP cut-off frequency 1 2.85 3.05 3.24 kHz fc_HP2 HP cut-off frequency 2 3.21 3.45 3.68 kHz fc_HP3 HP cut-off frequency 3 3.70 3.93 4.17 kHz fc_HP4 HP cut-off frequency 4 4.19 4.47 4.76 kHz fc_HP5 HP cut-off frequency 5 4.60 4.91 5.21 kHz fc_HP15 HP cut-off frequency 15 4.91 5.20 5.49 kHz fc_HP6 HP cut-off frequency 6 5.33 5.65 5.96 kHz fc_HP7 HP cut-off frequency 7 6.18 6.62 7.05 kHz fc_HP8 HP cut-off frequency 8 6.97 7.38 7.78 kHz fc_HP9 HP cut-off frequency 9 7.97 8.43 8.89 kHz fc_HP10 HP cut-off frequency 10 9.02 9.55 10.07 kHz fc_HP11 HP cut-off frequency 11 12.15 12.87 13.59 kHz fc_HP12 HP cut-off frequency 12 16.23 17.17 18.11 kHz fc_HP13 HP cut-off frequency 13 21.31 22.55 23.79 kHz fc_HP14 HP cut-off frequency 14 27.65 29.29 30.94 kHz GHP1_PB(000) HP1 passband gain 0 0.98 1.01 1.03 — GHP1_PB(001) HP1 passband gain 1 1.35 1.38 1.41 — GHP1_PB(010) HP1 passband gain 2 1.60 1.63 1.67 — GHP1_PB(011) HP1 passband gain 3 1.84 1.88 1.92 — GHP1_PB(100) HP1 passband gain 4 2.20 2.25 2.30 — GHP1_PB(101) HP1 passband gain 5 2.56 2.62 2.68 — GHP1_PB(110) HP1 passband gain 6 2.92 2.99 3.06 — GHP1_PB(111) HP1 passband gain 7 3.63 3.76 3.89 — GHP2_PB HP2 passband gain 4.86 5.00 5.14 — VHP_OFF(0) HP offset voltage 0 240 250 265 mV VHP_OFF(1) HP offset voltage 1 1210 1250 1290 mV tHP_FC_SWITCH HP cut-off frequency switching time — — 2.0 ms

6.9.6 Measurement function output noise

6.10 Measurement function (MC33816MAE only)

6.10.1 Multiplexer S_HSx

The S_HSx multiplexer is used to select between the five source high-side pins (S_HS1 to S_HS5) of the 33816 or AGND. The signal S_HSSel(2:0) controlling the multiplexer comes from the digital core using the stmfm instruction or from the SPI register. See Table 85. tHP_GAIN_SWITCH HP passband gain switching time — — 2.0 ms tHP_VALID HP filter output signal valid time — — 30 ms tHP_SETTLING HP filter output settling time — — 5.0 ms tHP_RECOVERY HP filter output recovery time — — 5.0 ms fC_HP_OUTPUTLP HP filter output LP 160 — 320 kHz Table 76: Measurement function output noise –40 ºC < TAMBIENT < +125 ºC, unless otherwise specified. All voltages are referenced to the AGND pin. Symbol Parameter Min Typ Max Unit Out_meas_noise Noise after LP filter output (1) 1. Guaranteed by design — 60 — µV Out_OAx_noise Noise at OAx output, GHP1_PB = 0.375

GOAx = 1.33
GOAx = 2.0
GOAx = 3.0
GOAx = 5.33 300 400 600 1100 µV Table 77: Multiplexer S_HSx truth table S_HSSel(2:0) Input selection 000 (reset value) AGND

001 S_HS1

010 S_HS2

011 S_HS3

100 S_HS4

101 S_HS5

110 AGND

111 AGND

Table 75: High-pass filter cut-off frequency –40 ºC < TAMBIENT < +125 ºC, unless otherwise specified. All voltages are referenced to the AGND pin. Symbol Parameter Min Typ Max Unit

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6.10.2 Multiplexer D_HSx

The D_LSx multiplexer is used to select between the six drain low-side pins (D_LS1 to D_LS6) of the 33816 or AGND. The signal D_LSSel (2:0) controlling the multiplexer comes from the digital core using the stmfm instruction (see Programming Guide and Instruction Set) or from the SPI register. See Table 85.

6.10.3 Differential amplifier and attenuation

A differential amplifier creates the signal D_LSx minus S_HSx or S_HSx minus D_LSx from the input signals. This can be configured with the VoltPol bit according to Table 46. A programmable attenuation (divider) block divides the voltage signal generated by the differential amplifier by one of eight selectable values. The inputs of the block doing the D_LSx minus S_HSx are limited to a maximum voltage of about 2.75 V. An attenuation value of 30 always provides a correct D_LSx minus result, as long as the D_LSx and S_HSx voltage stay below 70 V. The attenuation value shall be selected according to the voltage difference between D_LSx and S_HSx, when the injector closes.

6.10.4 Multiplexer current/voltage and OA current

The CurVolt multiplexer is used to select between processing the current signal coming directly from the output of the current measurement amplifier 1 to 4 or the differential voltage signal. Table 78: Multiplexer D_LSx truth table D_LSSel(2:0) Input selection 000 (reset value) AGND

001 D_LS1

010 D_LS2

011 D_LS3

100 D_LS4

101 D_LS5

110 D_LS6

Table 79: Attenuation values for differential voltage VoltAtt(2:0) Attenuation value Maximum differential input voltage for 2.5 V internal range/V Maximum S_HSx/D_LSx input voltage for 2.75 V clamp range/V 000 (reset value) 30 75.0 82.5 001 26 65.0 71.5 010 22 55.0 60.5 011 20 50.0 55.0 100 18 45.0 49.5 101 16 40.0 44.0 110 14 35.0 38.5 111 10 25.0 27.5 Table 80: Multiplexer CurVolt truth table CurVoltSel Input selection 0 (reset value) Differential voltage from VoltAtt block

1 Current measurement signal from OA_Cur multiplexer

The OA_Cur multiplexer is used to select between the four different current measurement amplifiers' output signals (OA_Cur1 to OA_Cur4). Both multiplexers must not be switched to a signal currently processed via another OAx analog output or an internal path. Switching the multiplexer can cause a glitch on the signal being processed.

6.10.5 Low-pass filter

A second order low-pass filter with a cut-off frequency of typical 115 kHz is used to suppress unwanted noise of the input signal. Due to tolerances, the cut-off frequency of the filter is in the range of 80 kHz to 160 kHz.

6.10.6 High-pass filter

The main characteristics of each high-pass filter are described by the following:

High-pass cutoff frequency: 2.3 kHz to 29.5 kHz
High-pass 1 passband gain: 1 to 3.75
High-pass 2 passband gain: 5.0
Recovery time from saturation of the output signal: < 5 s
Output offset voltage selectable between 250 mV and 1.25 V The cutoff frequency, the passband gain (HP1 only), and the offset voltage of the highpass filters can be configured using the SPI independently for each of the two filters. Table 86 shows the possible values.

6.10.7 OAx output multiplexer

The following block diagrams describe the details of each OAx multiplexer. All signals related to the measurement function are added. Table 81: Multiplexer OA_Cur truth table OACur(1:0) Input selection 00 (reset value) OA_Cur1

01 OA_Cur2

10 OA_Cur3

11 OA_Cur4

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Figure 22. Measurement function OA1 detail

33816 OA1 MUX

Figure 23. Measurement function OA2 detail

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6.10.7.1 Output multiplexer (MUX_OAx)

The output multiplexer (MUX_OAx) is used to either give the unprocessed current or voltage signal to the OAx pin of the 33816, the signal processed by the low-pass and one high-pass filter, or the signal processed by low-pass and both high-pass filter stages. The multiplexer must not be switched to a signal that is currently processed via another OAx analog output or an internal path. Switching the multiplexer can cause a glitch on the signal being processed. For example, if OA1 output is used to process OA_Meas1 signal, OA2 multiplexer must not be switched to OA_Meas1. This would introduce a glitch on the output signal of OA1.

6.10.7.2 OAx enable

With the signals OaEN1/2/3, it is possible to switch the OAx output to high impedance by setting the OAx enable low. This setting makes connecting two outputs of two 33816 devices and feeding them to only one ADC input of an MCU possible. As soon as the OAx pin is used as a digital input, the OAx output amplifier has to be disabled. This selection is independent for each OAx output and can be configured using the SPI. For more description of the OA2 and OA3 multiplexing, refer to the 33816 data sheet.

6.10.7.3 OAx gain and offset

The OAx output amplifier is used to adapt the device internal voltage range of 0 V to 2.5 V of the current measurements and the measurement function to the input voltage ranges of different AD converters. In addition, it provides a rather high gain value to amplify the signal even higher. The output voltage at the pin can be between 0 V and 5.0 V. The bias voltage (for HP 250 mV or 1.25 V, for current measurement 250 mV) of the input signal is removed before amplifying the signal and added again to the amplified signal afterwards, for the two higher gains of 3.0 and 5.33. This reduces the output bias voltage and the output bias voltage error for higher gains. The right voltage reference for the amplifier and therefore output bias voltage is chosen based on the selected HP2 output offset voltage. The user shall choose the proper HP2 output offset voltage, even if the HP2 signal is not used, with the HP1 signal or a signal coming from the current measurement. Table 82: Oax output multiplexer OASelx(2:0) Output Description

000 OA_Cur1/2 Output from current measurement 1 for OA1 respectively 2 for OA2

001 OA_Cur3/4 Output from current measurement 3 for OA1 respectively 4 for OA2

010 OA_Meas1 Unprocessed signal

011 OA_Meas2 Low-pass plus high-pass filtering

100 OA_Meas3 Low-pass plus two times high-pass filtering

101 VREF2P5 Fixed output voltage of 2.5 V

110 OA_Meas4 Low-pass only filtering

Table 83: OA_x amplifier gain selection and output voltage OaGainx (1:0) Gain value Output voltage Output bias voltage at 250 mV input bias voltage OffsetHP2Sel = 0 (used for current meas or HPx) Output bias voltage at 1.25 V input bias voltage OffsetHP2Sel = 1 (used for HPx only) d.c. 1 VIN * Gain 250 mV ± 29 mV 1.25 V ± 54 mV 00(1) 1. Use for 3.3 V ADC. 1.33 VIN * Gain 333 mV ± 38 mV 1.66 V ± 71 mV 01(2) 2. Use for 5.0 V ADC. 2.0 VIN * Gain 500 mV ± 58 mV 2.5 V ± 108 mV 10 3.0 (VIN – VBIAS) * Gain + VBIAS 250 mV ± 45 mV 1.25 V ± 70 mV 11 5.33 (VIN – VBIAS) * Gain + VBIAS 250 mV ± 68 mV 1.25 V ± 93 mV

6.10.7.4 Feedback of the OAx multiplexer signal to DAC (MUX_DACfbx)

With four additional multiplexers, it is possible to feed back the output signal of the OA1 or OA2 multiplexer to the comparators and DACs of the four 33816 current measurement channels. While one of these multiplexers is switched in a way that the OA1 or OA2 multiplexer output signal is routed to the comparator input. No current measurement with this channel is possible. The signal of the OAx multiplexer output is LP filtered before it is fed to the current measurement channel. A first order RC filter with a cut- off frequency of about 130 kHz is used. If the comparator and DAC are used in ADC mode a track and hold circuit keeps the comparator input voltage at a static level while the ADC conversion is performed. For channel 4 the OAx signal is feedback to DAC and comparator 4L.

6.10.7.5 Measurement function (MC33816MAE only)

These two registers configure the measurement function in order to detect the end of injection accurately.

oa_cur: select the current measurement channel
00: current measurement channel 1
01: current measurement channel 2
10: current measurement channel 3
11: current measurement channel 4
s_hs_sel: select the S_SHx pin to use as input
000: AGND
001: S_HS1
010: S_HS2
011: S_HS3
100: S_HS4
101: S_HS5
110: AGND
111: AGND
d_ls_sel: select the D_LSx pin to use as input
000: AGND
001: D_LS1
010: D_LS2
011: D_LS3
100: D_LS4
101: D_LS5
110: D_LS6 Table 84: Feedback of OA1/2 multiplexer signal to DAC DACfbSel(0) DACfbSel(1) DACfbSel(2) DACfbSel(3) Description 0 0 0 0 All current measurement work in current measurement mode 1 0 0 0 DAC/comp. of channel 1 is used to process OA1 signal 0 1 0 0 DAC/comp. of channel 2 is used to process OA2 signal 0 0 1 0 DAC/comp. of channel 3 is used to process OA1 signal 0 0 0 1 DAC/comp. of channel 4L is used to process OA2 signal Table 85: meas_func1 register (1ACh) Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name reserved dac_fb_sel cur_volt d_ls_sel s_hs_sel oa_cur R/W — r/w r/w r/w r/w r/w Lock — no no no no no Reset 000 0000 0 000 000 00

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111: AGND
cur_volt: selects between processing the current or differential voltage signal
0: differential voltage signal
1: current measurement channel signal
dac_fb_sel: select the measurement function feedback signal to DAC
0000: no current measurement channel used to process the signal
---1: DAC/comp. of channel 1 is used to process OA1 signal
--1-: DAC/comp. of channel 2 is used to process OA2 signal
-1--: DAC/comp. of channel 3 is used to process OA1 signal
1---: DAC/comp. of channel 4 is used to process OA2 signal
volt_att: select the attenuation for the differential voltage signal
000: 30
001: 26
010: 22
011: 20
100: 18
101: 16
110: 14
111: 10
fc_hp1/2_sel: select the cutoff frequency of HP1/2
0000: 2.30 kHz
0001: 3.06 kHz
0010: 3.47 kHz
0011: 3.96 kHz
0100: 4.49 kHz
0101: 4.92 kHz
0110: 5.65 kHz
0111: 6.54 kHz
1000: 7.37 kHz
1001: 8.46 kHz
1010: 9.57 kHz
1011: 12.9 kHz
1100: 17.3 kHz
1101: 22.8 kHz
1110: 29.5 kHz
1111: 5.20 kHz
gain_hp1_sel: select the gain of HP1
000: 1.0
001: 1.375
010: 1.625
011: 1.875
100: 2.25
101: 2.625
110: 3.0
111: 3.75
offset_hp1/2_sel: select the offset of HP1/2 Table 86: meas_func2 register (1ADh) Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name offset_hp2_sel offset_hp1_sel fc_hp2_sel gain_hp1_sel fc_hp1_sel volt_att R/W r/w r/w r/w r/w r/w r/w Lock no no no no no no Reset 0 0 0000 0 0000 0000

0: 250 mV
1: 1.25 V

6.11 PLL and backup clock

The digital logic is supplied by a clock (cksys) whose operating frequency can be set to 24MHz or 12 MHz. This selection can be achieve via a SPI configuration bit. After reset, the default operating frequency is set to 24 MHz. This clock is generated by a PLL, based on the external reference signal applied to the CLK pin. The internal PLL generates a typical 48 MHz or 24 MHz clock. Two internal clocks are derived from the PLL:

the main logic clock cksys
the code RAM clock cksys_cram inverted in respect to cksys
the Data RAM clock cksys_dram inverted in respect to cksys. If an unsuitable signal is applied on the CLK pin, the device automatically switches to the internal clock generated by an integrated backup oscillator. When a suitable signal is retrieved on the CLK pin, the MCU interfaced to the 33816 must request to switch back to the external reference clock through the SPI. The switch back to the external clock is not automatic. Around 25µs is required to lock the PLL the first time or to re-lock it. The PLL circuitry is supplied by the VCC5 pin. The PLL is started as soon as the supply voltages are stable and the input clock is present. The PLL works down to a VCC5 voltage of typically 4.0 V. The RESETB pin state has no effect on the PLL. The clock monitor detects an invalid PLL output clock, either by a missing PLL lock signal, or by supervising the output frequency of the PLL. Eight backup clock cycles are required to detect a wrong output clock frequency of the PLL. When switching from the external reference to the backup clock, it takes some additional time until the PLL is relocked. As long as the PLL output clock is not stable (PLL not locked), the signal cksys_missing is set to 1. This signal cksys_missing is used in the digital core to generate an interrupt. During a cksys_missing condition, there is the option to switch off all pre-drivers asynchronously by the cksys_drven signal. This configuration is done by setting to ‘1’ the bit cksys_miss_dis_drv of the Backup_status_clock_reg (0x1C7) The PLL output frequency can be modulated. Modulation activation is enabled by default, but can be disabled through the SPI in the PLL_config register (0x1C6).

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Table 87. PLL and back-up clock electrical characteristics

PLL operating frequency at VCC2P5 > 2.0 V
PLL operating frequency at VCC2P5 > 2.21 V 0.95 0.94 1.0 1.0 1.05 1.06 MHz (78) DCCLK CLK pin input duty cycle 45 50 55 % VCLK CLK pin voltage 0.0 – VCC5 V (79) VIH_CLK CLK pin high input voltage threshold 1.5 – 2.2 V VIL_CLK CLK pin low input voltage threshold 1.0 – 1.65 V VHYST_CLK CLK pin hysteresis 0.3 – – V tCLK_JITTER CLK pin clock edge jitter -25 – 25 ns (79) fCLK_BACK Backup oscillator clock frequency 0.95 1.0 1.05 MHz DCCLK_BACK Backup oscillator clock duty cycle 48 50 52 % fCKSYS24 cksys output clock frequency 24 MHz fCLK(_BACK) * 23.5 fCLK(_BACK) * 24 fCLK(_BACK) * 24.5 MHz fCKSYS_RAM24 cksys_c/dram output clock frequency 24 MHz fCLK(_BACK) * 23.5 fCLK(_BACK) * 24 fCLK(_BACK) * 24.5 MHz fCKSYS12 cksys output clock frequency 12 MHz fCLK(_BACK) * 11.75 fCLK(_BACK) * 12 fCLK(_BACK) * 12.25 MHz fCKSYS_RAM12 cksys_c/dram output clock frequency 12 MHz fCLK(_BACK) * 11.75 fCLK(_BACK) * 12 fCLK(_BACK) * 12.25 MHz MF_MOD_RATE cksys, cksys_c/dram output clock frequency modulation rate -2.08 – 2.08 % fCKSYS_MOD cksys, cksys_c/dram output clock frequency modulation frequency – 25 – kHz tPLL_LOCK PLL lock time (first lock), including digital filter time – 25 40 µs tPLL_RELOCK PLL lock time (re-lock), including digital filter time – 25 40 µs VCC5_PLLMIN PLL and Backup Clock minimum operating input voltage – – 4.0 V tPLL_LOCK_ FILTER PLL lock signal digital filter time – 10 – µs fCLK_LOSS24_L Digital clock monitor lower threshold frequency 24 MHz
Digital clock monitor threshold 127
Digital clock monitor threshold 163 20.11 25.81 21.17 27.17 22.23 28.53 MHz (79) fCLK_LOSS12_L Digital clock monitor threshold frequency 12 MHz
Digital clock monitor threshold 63
Digital clock monitor threshold 82 9.98 12.98 10.5 13.67 11.03 14.35 MHz (79) tCLK_LOSS Digital clock monitor detection time, digital clock monitor running on a 1.05 MHz internal clock – – 8.4 µs (79) Notes 78. The CLK pin input duty cycle minimum value is 45%, typical value is 50% and maximum value is 55%. 79. This parameter is derived mainly from simulation and is guaranteed by design characterization on a small sample size of typical devices under typical conditions, unless otherwise noted.

Figure 24. Timing diagrams for cksys, cksys_cram, and cksys_dram

6.12 Digital I/Os

6.12.1 General features

The digital I/Os ensure a way of communication to the MCU. The SPI interface allows register setup, Code RAM and Data RAM download. and OA_2) are analog pins that can optionally be configured as bidirectional flags. Table 88. Timing for cksys, cksys_cram, and cksys_dram

This parameter is derived mainly from simulation and is guaranteed by design characterization on a small sample size of typical devices under

typical conditions, unless otherwise noted. Table 89. Digital I/Os electrical characteristics

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IOUT > -50 µA, no higher current at other I/Os
IOUT > -1.0 mA, no higher current at other I/Os
IOUT > -2.0 mA, no higher current at other I/Os VCCIO - 0.05 VCCIO - 0.3 VCCIO - 0.6 V VOH_OAX Digital pins high output voltage (OA_x)
GOAx = 1.33, IOUT > -50 µA
GOAx = 1.33, IOUT > -1.0 mA
GOAx = 2.0, IOUT > -50 µA
GOAx = 2.0, IOUT > -1.0 mA 3.15 2.8 VCC5 -0.15 VCC5 -0.6 V (82) VOL_XXX Digital pins low output voltage (IRQB, MISO, STARTx, FLAGx, and DBG)
IOUT < 50 µA, no higher current at other I/Os
IOUT < 1.0 mA, no higher current at other I/Os
IOUT < 2.0 mA, no higher current at other I/Os 0.05 0.3 0.6 V VOL_OAX Digital pins low output voltage (OA_x) tR_XXX Digital pins output rise t. (IRQB, STARTx, FLAGx, and DBG)
CLOAD = 30 pF 3.0 – 12 ns (81) (82) tF_XXX Digital pins output fall t. (IRQB, STARTx, FLAGx, and DBG), 90%-10% of out voltage
CLOAD = 30 pF tD_XXX Digital pins output delay (IRQB, STARTx, FLAGx, and DBG), 10% of out voltage change
CLOAD = 30 pF tR_XXX Digital pins output rise t. (IRQB, STARTx, FLAGx, and DBG), 10%- 90% of out voltage
CLOAD = 30 pF, VCCIO = 3.3 V, TA = +50 °C
CLOAD = 30 pF, VCCIO = 5.0 V, TA = +50 °C 6.0 4.0 9.0 7.0 ns (81) (82) tF_XXX Digital pins output fall t. (IRQB, STARTx, FLAGx, and DBG), 90%-10% of out voltage
CLOAD = 30 pF, VCCIO = 3.3 V, TA = +50 °C
CLOAD = 30 pF, VCCIO = 5.0 V, TA = +50 °C 6.0 4.0 8.0 6.0 ns (81) (82) tD_XXX Digital pins output delay (IRQB, STARTx, FLAGx, and DBG), 10% of out voltage change
CLOAD = 30 pF, VCCIO = 3.3 V, TA = +50 °C
CLOAD = 30 pF, VCCIO = 5.0 V, TA = +50 °C 4.0 3.0 7.0 6.0 ns (81) (82) tDRF_XXX Digital pins delta between rise and fall time (IRQB, STARTx, FLAGx, and DBG), 10% of out voltage change
CLOAD = 30 pF, VCCIO = 3.3 V, TA = +50 °C
CLOAD = 30 pF, VCCIO = 5.0 V, TA = +50 °C -0.5 -0.3 1.6 1.0 ns (81) (82)

Table 89. Digital I/Os electrical characteristics (continued)

6.13 SPI interface

The device includes a SPI MISO driver with programmable slew rate control.

The driver is optimized to have a low tolerance in rise/fall time over temperature and process.
The rise time and fall time are auto-adapted regardless if 5.0 V or 3.3 V are supplied on the VCCIO pin.
The options and slew rate settings are described in Table 90. Two possible slew rates can be selection by means of the bit miso_slew rate of the SPI_config register (0x1C8). Refer to Spi_protocol block for the SPI protocol description. The two slew rate setting target two different baud rate ranges:
the fast slew rate addresses the max baud rate range of typically 8.0 Mbps to10 Mbps
the slow slew rate addresses the baud rate range of typically 3.5 Mbps to 8.0 Mbps tDD_XXX Digital pins delta between output delay for rising edge and falling edge (IRQB, STARTx, FLAGx, and DBG), 10% of out voltage change
CLOAD = 30 pF, VCCIO = 3.3 V, TA = +50 °C
CLOAD = 30 pF, VCCIO = 5.0 V, TA = +50 °C -0.3 -0.7 0.1 -0.3 ns (81) (82) tR_OAX Digital pins output rise time (OA_x), 10%-90% of out voltage
CLOAD = 30 pF, VCCIO = 3.3 V
CLOAD = 30 pF, VCCIO = 5.0 V 1.4 2.0 µs (81) (82) tF_OAX Digital pins output fall time (OA_x), 90%-10% of out voltage
CLOAD = 30 pF, VCCIO = 3.3 V
CLOAD = 30 pF, VCCIO = 5.0 V 1.4 3.2 µs (81) (82) tD_OAX Digital pins output delay (OA_x), 10% of out voltage change
CLOAD = 30 pF, VCCIO = 3.3 V
CLOAD = 30 pF, VCCIO = 5.0 V 2.7 3.0 µs (81) (82) CPIN_XXX Digital pins equivalent pin capacitance (IRQB, START1, START2, START3, START4, START5, START6, FLAG0, FLAG1, FLAG2, DBFG) – – 10 pF (81) CPIN_MISO Digital pins equivalent pin capacitance (MISO) – – 10 pF (81) CPIN_MOSI Digital pins equivalent pin capacitance (MOSI) – – 10 pF (81) Notes 81. This parameter is derived mainly from simulation and is guaranteed by design characterization on a small sample size of typical devices under typical conditions, unless otherwise noted. 82. Referenced to AGND pin

Table 90. SPI MISO slew rate settings

0 Slow 30 20 18

0 Slow 75 40 40

0 Slow 150 80 70

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Figure 25. SPI timing Table 91. General SPI electrical characteristics

This parameter is derived mainly from simulation and is guaranteed by design characterization on a small sample size of typical devices under

typical conditions, unless otherwise noted.

tDR/F_MISO is the rise time and fall time provide in Table 92 and Table 93.

Table 92. SPI electrical characteristics for VCCIO = 3.3 V

CL = 30 pF
CL = 75 pF
CL = 150 pF ns tF_MISO_S3.3 MISO fall time at 90%-10% of out voltage Slow setting
CL = 30 pF
CL = 75 pF
CL = 150 pF ns tR_MISO_F3.3 MISO rise time at 10%-90% of out voltage Fast setting
CL = 30 pF
CL = 75 pF
CL = 150 pF 1.5 2.7 4.4 4.9 8.4 14.8 ns tF_MISO_F3.3 MISO fall time at 90%-10% of out voltage Fast setting
CL = 30 pF
CL = 75 pF
CL = 150 pF 1.5 2.7 4.4 4.9 8.4 14.8 ns tDR_MISO_ S3.3 MISO pad total delay to 90% of out voltage (propagation delay plus rise time) Slow setting
CL = 30 pF
CL = 75 pF
CL = 150 pF ns tDF_MISO_ S3.3 MISO pad total delay to 10% of out voltage (propagation delay plus fall time) Slow setting
CL = 30 pF
CL = 75 pF
CL = 150 pF ns tDR_MISO_ F3.3 MISO pad total delay to 90% of out voltage (propagation delay plus rise time) Fast setting
CL = 30 pF
CL = 75 pF
CL = 150 pF 13.4 17.1 23.9 ns tDF_MISO_ F3.3 MISO pad total delay to 10% of out voltage (propagation delay plus fall time) Fast setting
CL = 30 pF
CL = 75 pF
CL = 150 pF 13.4 17.1 23.9 ns

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Table 93. SPI electrical characteristics for VCCIO = 5.0 V

CL = 30 pF
CL = 75 pF
CL = 150 pF 9.0 ns tF_MISO_S5.0 MISO fall time at 90%-10% of out voltage Slow setting
CL = 30 pF
CL = 75 pF
CL = 150 pF 9.0 ns tR_MISO_F5.0 MISO rise time at 10%-90% of out voltage Fast setting
CL = 30 pF
CL = 75 pF
CL = 150 pF 1.1 2.1 3.6 3.6 6.3 11.3 ns tF_MISO_F5.0 MISO fall time at 90%-10% of out voltage Fast setting
CL = 30 pF
CL = 75 pF
CL = 150 pF 1.1 2.1 3.6 3.6 6.3 11.3 ns tDR_MISO_ S5.0 MISO pad total delay to 90% of out voltage (propagation delay plus rise time) Slow setting
CL = 30 pF
CL = 75 pF
CL = 150 pF ns tDF_MISO_ S5.0 MISO pad total delay to 10% of out voltage (propagation delay plus fall time) Slow setting
CL = 30 pF
CL = 75 pF
CL = 150 pF ns tDR_MISO_ F5.0 MISO pad total delay to 90% of out voltage (propagation delay plus rise time) Fast setting
CL = 30 pF
CL = 75 pF
CL = 150 pF 9.6 12.5 17.8 ns tDF_MISO_ F5.0 MISO pad total delay to 10% of out voltage (propagation delay plus fall time) Fast setting
CL = 30 pF
CL = 75 pF
CL = 150 pF 9.6 12.5 17.8 ns

6.14 Internal pull-up and pull-down

specified and their characteristics are defined in the Table 94.

6.14.1 Startx pins pull-up and pull-down

The pull resistor direction for the STARTx pins can be configurable as pull-up or pull-down.

6.15 Unused pins connection

I/O signals, OA_1 and OA_2 pins, HS and LS pre-drivers and current measurement channels. The current measurement channels VSENSEPx and VSENSENx input pins can be connected both to GND. The table Table 96 details the recommended connections in case of unused pins. Table 94. Internal pin pull-up/pull-down resistor electrical specifications parameter means at TA = 25 °C under nominal conditions, unless otherwise noted. Table 95. STARTx pin pull resistor direction selection Table 96. Recommended unused pins connections

1 CLK Not connected- internal weak pull-up

2 DRVEN Not connected - internal weak pull-down

3 RESETB Not connected - internal weak pull-up

4 START1 Not connected - internal configurable pull-up/pull-down

5 START2 Not connected - internal configurable pull-up/pull-down

6 START3 Not connected - internal configurable pull-up/pull-down

7 START4 Not connected - internal configurable pull-up/pull-down

8 START5 Not connected - internal configurable pull-up/pull-down

9 START6 Not connected - internal configurable pull-up/pull-down

10 FLAG0 Not connected - internal weak pull-down

11 FLAG1 Not connected - internal weak pull-down

12 FLAG2 Not connected - internal weak pull-down

87 NXP Semiconductors

13 CSB Not connected - internal pull-up

14 MOSI Not connected - internal weak pull-up

15 MISO Not connected

16 SCLK Not connected - internal weak pull-up

17 VCCIO To be supplied - filtering capacitor required

18 DBG Not connected - internal weak pull-up

19 DGND Connection to ground required

20 VCC2P5 To be supplied - filtering capacitor required

21 VCC5 To be supplied - filtering capacitor required

22 OA_1 Not connected(85) - internal weak pull-down

23 OA_2 Not connected(85) - internal weak pull-down

24 AGND Connection to ground required

25 VSENSEN1 Not connected(86) (87)

26 VSENSEP1 Not connected(86) (87)

27 VSENSEN2 Not connected(86) (87)

28 VSENSEP2 Not connected(86) (87)

29 VSENSEN3 Not connected(86) (87)

30 VSENSEP3 Not connected(86) (87)

31 VSENSEN4 Not connected(86) (87)

32 VSENSEP4 Not connected(86) (87)

33 D_LS6 Not connected(87)

34 D_LS5 Not connected(87)

35 D_LS4 Not connected(87)

36 D_LS3 Not connected(87)

37 D_LS2 Not connected(87)

38 D_LS1 Not connected(87)

39 VBATT To be supplied

40 VCCP Filtering capacitor required

41 G_LS7 Not connected(88)

42 G_LS6 Not connected(88)

43 G_LS5 Not connected(88)

44 G_LS4 Not connected(88)

45 G_LS3 Not connected(88)

46 G_LS2 Not connected(88)

47 G_LS1 Not connected(88)

48 VBOOST To be supplied

49 B_HS5 Not connected(89)

50 G_HS5 Not connected(88)(89)

51 S_HS5 Not connected(87)(89)

52 B_HS4 Not connected(89)

53 G_HS4 Not connected(88)(89)

Table 96. Recommended unused pins connections (continued)

6.16 Internal digital signals description

The main digital signal used into the analog resources blocks are described into the Table 97.

54 S_HS4 Not connected(87)(89)

55 B_HS3 Not connected(89)

56 G_HS3 Not connected(88)(89)

57 S_HS3 Not connected(87)(89)

58 B_HS2 Not connected(89)

59 G_HS2 Not connected(88)(89)

60 S_HS2 Not connected(87)(89)

61 B_HS1 Not connected(89)

62 G_HS1 Not connected(88)(89)

63 S_HS1 Not connected(87)(89)

64 IRQB Not connected - internal weak pull-down

Setting the AO_x pin as flag output is recommended.
The VSENSEPx and VSENSENx pins can be connected to ground.
The crossbar switch must be set up such as to prevent the microcores to be enabled by the function.
The crossbar switch must be set up such as to prevent the microcores to enable the function.
Not connected if the related driver is not used.

Table 97. Main internal digital signal description undervoltage lockout threshold.

89 NXP Semiconductors

set in the Vboost UV Monitoring mode. This bit can be set in the driver_disable register (0x1C5). is reported in the Driver_status register (0x1D2). This signal is used to selected the boost voltage monitoring mode. According to its state the boost divider ratio is typically 1/4 or 1/32. This bit can be set in the Driver_config register (0x1C5). exceeded. This bit is reported in the Driver_status register (0x1D2). Table 97. Main internal digital signal description (continued)

in the Ls_slewrate register (0x18F). in the Ls_slewrate register (0x18F). Vds_threshold_hs register (0x18A). Vsrc_threshold_hs register (0x18B). Dacx_value registers (0x19E, 0x19F, 0x1A0, 0x1A1, 0x1A2).

91 NXP Semiconductors

set in the Dac4neg_value register (0x1A)). to its internal backup clock.

These signals or signal bus are individually provided to the five high-side pre-drivers (x= 1, 2, 3, 4, or 5).
These signals or signal bus are individually provided to the first six high-side pre-drivers. Low-side pre-driver seven is considered independently.
The strong biasings are only available on the high-side pre-drivers 2 and 4.
These signals or signal bus are individually provided to the four current measurement blocks (x= 1, 2, 3, or 4).
These signals re individually produced by the four current measurement blocks (x= 1, 2, 3, or 4).

6.17 Device logic block description

hierarchical top level of the digital part of the device. Figure 26. Device logic block hierarchic overview

clock_manager – this block is dedicated to the device clock management
rst_gen _ this block is in charge of device reset management
bist_interface – this block is in charge of managing the BIST function
act_channel – this block is in charge to handle two microcore and the associated functions like Code RAM access and dual sequencing.
channel_management – this block is dedicated to the act_channel blocks signal management, managing the common configuration setup and managing the communication interfaces of the 33816
input_output_interface (refer to IO interface section) /g1/g2/g3/g4/g5/g6/g7/g8/g8/g9/g10/g11/g12/g13/g10/g3/g5/g14 /g15/g10/g3/g5/g14/g4/g16/g7/g8/g7/g17/g9/g18/g12/g13/g10/g3/g5/g14 /g19/g11/g20/g4/g17/g9/g8/g12/g13/g10/g3/g5/g14 /g13/g21/g22/g1/g4/g23/g8/g20/g9/g18/g24/g7/g5/g9/g12/g13/g10/g3/g5/g14 /g25/g9/g26/g23/g5/g9/g12/g16/g9/g16/g3/g18/g27/g12/g7/g8/g28/g12/g18/g9/g17/g23/g11/g20/g9/g18/g11 /g15/g3/g28/g9/g12/g19/g29/g30/g12/g31 /g15/g3/g28/g9/g12/g19/g29/g30/g12/g32 /g25/g7/g20/g7/g12/g19/g29/g30/g12/g31 /g25/g7/g20/g7/g12/g19/g29/g30/g12/g32 /g15/g3/g8/g24/g23/g17/g33/g18/g7/g20/g23/g3/g8/g12/g19/g9/g17/g23/g11/g20/g9/g18/g11/g12/g3/g24/g12 /g15/g6/g7/g8/g8/g9/g10/g12/g31 /g15/g3/g8/g24/g23/g17/g33/g18/g7/g20/g23/g3/g8/g12/g19/g9/g17/g23/g11/g20/g9/g18/g11/g12/g3/g24/g12 /g15/g6/g7/g8/g8/g9/g10/g12/g32 /g25/g23/g7/g17/g8/g3/g11/g23/g11/g12/g15/g3/g8/g24/g23/g17/g33/g18/g7/g20/g23/g3/g8/g12 /g19/g9/g17/g23/g11/g20/g9/g18/g11 /g21/g34/g12/g15/g3/g8/g24/g23/g17/g33/g18/g7/g20/g23/g3/g8/g12/g19/g9/g17/g23/g11/g20/g9/g18/g11 /g30/g7/g23/g8/g12/g15/g3/g8/g24/g23/g17/g33/g18/g7/g20/g23/g3/g8/g12 /g19/g9/g17/g23/g11/g20/g9/g18/g11 /g22/g9/g10/g9/g5/g20/g23/g3/g8/g12/g19/g9/g17/g23/g11/g20/g9/g18 /g25/g9/g26/g23/g5/g9/g4/g10/g3/g5/g14/g12/g13/g10/g3/g5/g14 /g21/g28/g9/g8/g20/g23/g24/g23/g9/g18/g4/g7/g8/g28/g4/g18/g9/g26/g23/g11/g23/g3/g8 /g13/g10/g3/g5/g14 /g35/g10/g7/g17/g11/g4/g16/g7/g8/g7/g17/g9/g16/g9/g8/g20/g12/g13/g10/g3/g5/g14 /g13/g7/g5/g14/g33/g36/g4/g5/g10/g3/g5/g14/g4/g11/g20/g7/g20/g33/g11/g4/g6/g7/g8/g28/g10/g9/g12 /g13/g10/g3/g5/g14 /g15/g6/g7/g8/g8/g9/g10/g4/g16/g7/g8/g7/g17/g9/g16/g9/g8/g20/g12/g13/g10/g3/g5/g14 /g15/g23/g36/g6/g9/g18/g4/g33/g8/g23/g20/g12/g13/g10/g3/g5/g14 /g21/g18/g37/g4/g6/g7/g8/g28/g10/g9/g12/g13/g10/g3/g5/g14 /g15/g3/g16/g16/g33/g8/g23/g5/g7/g20/g23/g3/g8/g4/g23/g8/g20/g9/g18/g24/g7/g5/g9 /g13/g10/g3/g5/g14 /g38/g18/g9/g11/g5/g7/g10/g9/g18/g12/g13/g10/g3/g5/g14 /g22/g38/g21/g4/g11/g10/g7/g26/g9/g12/g13/g10/g3/g5/g14 /g25/g18/g23/g26/g9/g18/g4/g9/g8/g7/g39/g10/g9/g12/g13/g10/g3/g5/g14 /g22/g38/g21/g4/g7/g5/g5/g9/g11/g11/g4/g5/g3/g8/g20/g18/g3/g10/g12/g13/g10/g3/g5/g14 /g1/g18/g7/g5/g9/g4/g33/g8/g23/g20/g12/g13/g10/g3/g5/g14 /g30/g23/g5/g18/g3/g4/g23/g8/g20/g9/g18/g24/g7/g5/g9/g12/g13/g10/g3/g5/g14 /g22/g23/g17/g8/g7/g20/g33/g18/g9/g4/g33/g8/g23/g20/g12/g13/g10/g3/g5/g14 /g12/g15/g3/g28/g9/g4/g19/g29/g30/g12/g13/g10/g3/g5/g14 /g29/g5/g20/g4/g5/g6/g7/g8/g8/g9/g10/g12/g13/g10/g3/g5/g14/g12/g40/g31/g41 /g38/g7/g18/g7/g16/g9/g20/g9/g18/g11/g12/g13/g10/g3/g5/g14 /g25/g33/g7/g10/g4/g16/g23/g5/g18/g3/g5/g3/g18/g9/g4/g7/g18/g39/g23/g20/g9/g18/g12/g13/g10/g3/g5/g14 /g15/g6/g4/g16/g23/g5/g18/g3/g5/g3/g18/g9/g12/g13/g10/g3/g5/g14 /g15/g6/g4/g16/g23/g5/g18/g3/g5/g3/g18/g9/g12/g13/g10/g3/g5/g14 /g42/g28/g11/g4/g18/g9/g17/g24/g23/g10/g9/g12/g13/g10/g3/g5/g14 /g22/g10/g9/g2/g18/g7/g20/g9/g4/g18/g9/g17/g24/g23/g10/g9/g12/g13/g10/g3/g5/g14 /g13/g3/g3/g11/g20/g4/g28/g7/g5/g12/g13/g10/g3/g5/g14 /g13/g23/g7/g11/g4/g18/g9/g17/g24/g23/g10/g9/g12/g13/g10/g3/g5/g14 /g13/g3/g3/g11/g20/g4/g24/g23/g10/g20/g9/g18/g12/g13/g10/g3/g5/g14 /g21/g8/g36/g33/g20/g4/g3/g33/g20/g36/g33/g20/g4/g23/g8/g20/g9/g18/g24/g7/g5/g9/g12/g13/g10/g3/g5/g14 /g34/g7/g4/g3/g33/g20/g4/g5/g3/g8/g24/g23/g17/g12/g13/g10/g3/g5/g14 /g25/g7/g5/g4/g11/g2/g23/g20/g5/g6/g4/g39/g3/g43/g12/g13/g10/g3/g5/g14 /g13/g3/g3/g11/g20/g18/g7/g36/g4/g11/g2/g23/g20/g5/g6/g4/g5/g3/g8/g20/g18/g3/g10 /g13/g10/g3/g5/g14 /g25/g7/g5/g4/g11/g9/g20/g20/g10/g23/g8/g17/g4/g20/g23/g16/g9/g12/g13/g10/g3/g5/g14 /g22/g20/g7/g18/g20/g4/g16/g7/g8/g7/g17/g9/g16/g9/g8/g20/g12/g39/g10/g3/g5/g14 /g25/g36/g4/g18/g7/g16/g12/g39/g10/g3/g5/g14 /g30/g23/g5/g18/g3/g4/g23/g8/g20/g9/g18/g24/g7/g5/g9/g12/g39/g10/g3/g5/g14 /g34/g33/g20/g36/g33/g20/g4/g18/g3/g33/g20/g23/g8/g17/g12/g13/g10/g3/g5/g14 /g44/g18/g18/g3/g18/g4/g6/g7/g8/g28/g10/g9/g18/g12/g13/g10/g3/g5/g14 /g34/g33/g20/g36/g33/g20/g4/g11/g2/g23/g20/g5/g6/g4/g39/g3/g43/g12/g13/g10/g3/g5/g14 /g34/g33/g20/g36/g33/g20/g4/g7/g5/g5/g9/g11/g11/g12/g13/g10/g3/g5/g14 /g25/g5/g28/g5/g4/g5/g3/g8/g26/g9/g18/g20/g4/g5/g3/g8/g20/g18/g3/g10/g12/g13/g10/g3/g5/g14 /g29/g33/g20/g3/g16/g7/g20/g23/g5/g4/g28/g23/g7/g17/g8/g3/g11/g23/g11/g12/g13/g10/g3/g5/g14 /g35/g23/g10/g20/g9/g18/g4/g23/g8/g36/g33/g20/g12/g13/g10/g3/g5/g14 /g15/g6/g7/g8/g8/g9/g10/g4/g5/g6/g9/g5/g14/g12/g13/g10/g3/g5/g14 /g22/g38/g21/g4/g23/g8/g20/g9/g18/g24/g7/g5/g9/g4/g11/g10/g7/g26/g9/g12/g13/g10/g3/g5/g14 /g22/g38/g21/g4/g23/g8/g20/g9/g18/g24/g7/g5/g9/g4/g11/g10/g7/g26/g9/g12/g39/g10/g3/g5/g14 /g22/g38/g21/g4/g36/g18/g3/g20/g3/g5/g3/g10/g12/g39/g10/g3/g5/g14 /g22/g38/g21/g4/g5/g3/g8/g24/g23/g17/g12/g39/g10/g3/g5/g14 /g22/g38/g21/g4/g9/g18/g18/g3/g18/g12/g39/g10/g3/g5/g14 /g30/g23/g5/g18/g3/g4/g23/g8/g20/g9/g18/g24/g7/g5/g9/g12/g13/g10/g3/g5/g14 /g22/g23/g17/g8/g7/g20/g33/g18/g9/g4/g33/g8/g23/g20/g12/g13/g10/g3/g5/g14 /g12/g15/g3/g28/g9/g4/g19/g29/g30/g12/g13/g10/g3/g5/g14 /g29/g5/g20/g4/g5/g6/g7/g8/g8/g9/g10/g12/g13/g10/g3/g5/g14/g12/g40/g32/g41 /g38/g7/g18/g7/g16/g9/g20/g9/g18/g11/g12/g13/g10/g3/g5/g14 /g25/g33/g7/g10/g4/g16/g23/g5/g18/g3/g5/g3/g18/g9/g4/g7/g18/g39/g23/g20/g9/g18/g12/g13/g10/g3/g5/g14 /g15/g6/g4/g16/g23/g5/g18/g3/g5/g3/g18/g9/g12/g13/g10/g3/g5/g14 /g15/g6/g4/g16/g23/g5/g18/g3/g5/g3/g18/g9/g12/g13/g10/g3/g5/g14 /g22/g20/g7/g18/g20/g4/g16/g7/g8/g7/g17/g9/g16/g9/g8/g20/g12/g39/g10/g3/g5/g14 /g25/g36/g4/g18/g7/g16/g12/g39/g10/g3/g5/g14 /g30/g23/g5/g18/g3/g4/g23/g8/g20/g9/g18/g24/g7/g5/g9/g12/g39/g10/g3/g5/g14

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Figure 27. Two_channels block overview

Configuration Registers of Channel 1 and Channel 2- These register areas are dedicated to the logic channels 1 and 2 setup.
Diagnosis Configuration Registers – These registers are used to setup the automatic diagnosis parameters and the diagnostic option.
IO Configuration Registers – These registers are basically used to setup the crossbar switch and all the current and voltage thresholds used by the analog resources.
Main Configuration registers – these registers are dedicated to the logic block functionality setup, like the clock management, the flags properties, SPI management, the trace management, and the other peripheral functions. All the registers and their corresponding addresses are listed in the Device address map table. 6.17.1 33816 address map

Table 98. Device address map

Table 98. Device address map (continued)

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6.17.2 Clock_manager block

selecting between the two input references for the PLL.
providing a loss_of_clock signal to channel_management.This signal is ‘1’ when the backup reference is supplied to the PLL, a ‘0’ otherwise. This status can be read back through the SPI in the Backup_clock_status_reg register (0x1C7).
providing a cksys_missing signal to channel_management. This signal is ‘1’ when the PLL provides no valid clock signal, a ‘0’ otherwise. This signal is used to generate an interrupt request to the microcores and to the external microcontroller through the IRQB pin. The signal cksys_missing can also be used to disable the output drivers if the bit cksys_missing_disable_driver bit is set to ‘1’ in Backup_clock_status_reg register (0x1C7). Considering the MCU might not be able to provide a stabilized clock to the CLK pin of the device during its reset the clock manager, FSM is disabled for 100 µs. After that, the RESETB pin signal is set to High. While in this state, the external reference is provided to the PLL input and no check is performed on the PLL output. The loss_of_clock and cksys_missing signals are deactivated. After filter time is reached, the clock monitor is enabled and can detect a low frequency or missing clock input reference, or a PLL malfunction. This sub-block monitors the PLL output to detect any output clock frequency out of the expected range. This is achieved by counting the number of pll_output_clock cycles inside six periods of the backup reference clock (6 period of 1.0 MHz clock = 6.0 µs). The expected number depends on the selected PLL multiplication factor:
when the factor is 24, it detects an invalid clock condition when it is possible to count more than 165 or less than 125 pll_output_clock cycles.
when the factor is 12, it detects an invalid clock condition when it is possible to count more than 84 or less than 61 pll_output_clock cycles. If an invalid clock condition is detected, the fsm clock_manager goes to the ’Locking onto Backup Reference’ state. In this state, the backup reference is supplied to the PLL and both loss_of_clock and cksys_missing signals are set. When the PLL locks onto the backup reference, the fsm clock_manager goes to the ’Use Backup Reference’ state. In this state, the loss_of_clock signal is still set while the cksys_missing signal is reset. While the fsm clock_manager is in ’Use Backup Reference’ state, it is possible to recheck the external clock reference. The check is not performed automatically, but must be requested by writing to the Backup_clock_status_reg register (0x1C7). When the switch back is requested (’Switch to clock pin’), the cksys_missing is asserted, the loss of clock is reset, and the clock monitor is disabled again for 250µs. The cksys_missing signal is active at least until the PLL is locked onto the external clock reference. The PLL is considered locked again if one of two conditions are verified: ’100’/ext_sel_mcr 474 0x1DA Reserved Main Configuration Registers 475 0x1DB Reserved 476 0x1DC no BIST_interface 477 0x1DD Reserved 478 0x1DE Reserved 479 0x1DF 33 reserved addresses… – 511 0x1FF 512 0x200 511 reserved addresses… – 1022 0x3FE 1023 0x3FF no Selection register (Selection_reg register) Notes 96. The memory areas and register can be locked according to the table column Lock = Yes by means of the Device_lock register (0x1CD).

A falling edge followed by a rising edge on the pll_out_valid signal, which includes the information from the frequency counter and the filtered pll_lock signal.
A fixed time of 100 µs has passed since the switch has been made and the pll_out_valid signal was always active. When one of the conditions is verified, the cksys_missing signal is reset and the fsm goes to ’Use External reference’ state. After requesting the switch back to the external clock reference, the device cannot be accessed via the SPI for about:
100 µs, if there is a valid external clock available
290 µs, if there is no valid input clock available and the device has to return to the backup clock. The SPI word transmitted to set the switch to clock pin bit has to be the last word within a SPI burst.

6.17.2.1 PLL configuration register

PLL_factor: if set to ‘0’, the PLL multiplication factor is 12, otherwise it is 24
PLL_spread_disable: if set to ‘0’ spread is applied to the PLL output clock, otherwise spread is disabled The PLL factor is changed synchronously with clock monitor cycle to avoid a clock monitor alert when changing between 12 and 24MHz.

6.17.3 Rst_gen block

low signal on RESETB pin
the internal signal POResetB, generated by the VCC2P5 voltage regulator undervoltage flag
a global reset request received through the SPI, writing the reset code into the Global_reset Registers (0x1D0 and 0x1D1) This block generates the following reset signals:
Clock Monitor reset. This signal is activated asynchronously when either ResetB or POResetB are activated. It is deactivated synchronously with the backup clock reference when both ResetB and POResetB are inactive. This reset is supplied to the clock_manager block. This reset differs from the others, as it is synchronized to the backup clock reference.
Cipher Register reset. This signal is activated asynchronously when the POResetB is activated. It is deactivated synchronously with the cksys clock when the POResetB is inactive. This reset is supplied to the cipher configuration register. This reset puts the cipher configuration register in the same condition of the RAMs, which are reset only in case of a power loss.
SPI interface reset. This signal is activated asynchronously when either the ResetB, POResetB, global SPI reset, or cksys_missing is activated. This reset signal is deactivated synchronously with the cksys clock when all the signals ResetB, POResetB, global SPI reset, cksys_missing are inactive and the SPI chip select is inactive. If any SPI transfer is required while thecksys_missing signal is active, then the SPI transfer is aborted and a SPI error is stored in the SPI_error register (0x1D3).This condition avoids a transfer of dummy data, leading to a hieratic device operation.
Main reset (rst). This signal is activated asynchronously when the ResetB, POResetB, or global SPI reset is activated. It is deactivated synchronously with the cksys clock when ResetB, POResetB, and global SPI reset are inactive. This signal resets all the device, except the blocks using other resets.

Table 99. PLL_config Register (0x1C6)

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6.17.3.1 Global reset registers

lasts for eight cksys clock cycles, then the global reset registers are reset. The global reset code is ‘0xF473’ for Global reset register 1 and ‘0x57A1’ for Global reset register 2.

6.17.3.2 Reset source register

This 3-bit register identifies which resets were asserted since the last time this register was read. This register is reset at each access. SPI _reset is ‘1’ if the global SPI reset was asserted since the last time this register was read. POReseB is ‘1’ if the power on reset was asserted since the last time this register was read. ResetB is ‘1’ if the reset pin was asserted since the last time this register was read. After POResetB this bit is in an unknown state. Table 100. Global_reset register 1 (0x1D0) Table 101. Global_reset register 2 (0x1D1) Table 102. Reset_source register (0x01D6)

6.17.4 BIST_interface block

performed, the BIST check starts and can be monitored at any time, accessing the same BIST_register in read mode.

All 00, All 11
All 55, All AA
All 0F, All F0
All 00, All FF
All FF, All 00
BIST_result: set to ’00’ if the BIST has never been requested
BIST_result: set to ’01’ if the BIST operation is in progress
BIST_result: set to ’10’ if the BIST operation has been successfully completed
BIST_result: set to ’11’ if the BIST operation has failed

6.17.5 Channels_management block

combines all the signals issued from or feeding to the 2 act_channel blocks
provides all the main configuration registers
interfaces the 33816 with the MCU through the SPI connection. The channel_management block integrates the following blocks:
Device_lock
Identifier_and_revision
Flags_management
Irq_handle
Cipher_unit
SPI_slave
Communication_interface
Prescalers
Driver_enable
SPI_access_controller
Trace_unit

Table 103. BIST_interface register in write mode (0x1DC) Table 104. BIST_interface in read mode (0x1DC)

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Figure 28. Channel_management block diagram

6.17.5.1 Device_lock block

Some device registers can be protected against an unexpected write. In lock mode, these registers can only be accessed in read mode. time while writing an unlock password ‘0x1337’ into the Device_unlock register (0x1CF). Note that the last 16 addresses of each Data RAM can be independently locked.

6.17.5.1.1 Device_lock register

writing to the device lock register but only by writing the unlock password ‘0x1337’ into the Device_unlock register (0x1CF). Table 105. Device_lock register (0x1CD)

6.17.5.1.2 Reset behavior register

microcores using the SPI backdoor does not reset those registers.

Driver enable reset behavior (driver_enable_rb): if set to ‘1’ Driver_status register is reset on read.
Automatic diagnosis uc0 ch1 reset behavior (diag_uc0_ch1_rb): if set to ‘1’ diagnosis error registers (0x162 and 0x163) of microcore 0 of channel 1 is reset on read.
Automatic diagnosis uc1 ch1 reset behavior (diag_uc1_ch1_rb): if set to ‘1’ diagnosis error registers (0x164 and 0x165) of microcore 1 of channel 1 is reset on read.
Automatic diagnosis uc0 ch2 reset behavior (diag_uc0_ch2 _rb): if set to ‘1’ diagnosis error registers (0x166 and 0x167) of microcore 0 of channel 2 is reset on read.
Automatic diagnosis uc1 ch2 reset behavior (diag_uc1_ch2_rb): if set to ‘1’ diagnosis error registers (0x168 and 0x169) of microcore 1 of channel 2 is reset on read.
Status register uc0 ch1 reset behavior (sr_uc0_ch1_rb): if set to ‘1’ the Status register of microcore 0 of channel 1 is reset on read.
Status register uc1 ch1 reset behavior (sr_uc1_ch1_rb): if set to ‘1’ the Status register of microcore 1 of channel 1 is reset on read.
Status register uc0 ch2 reset behavior (sr_uc0_ch2_rb): if set to ‘1’ the Status register of microcore 0 of channel 2 is reset on read.
Status register uc1 ch2 reset behavior (sr_uc1_ch2_rb): if set to ‘1’ the status register of microcore 1 of channel 2 is reset on read. During a simultaneous register read SPI command and a register write access by any microcore, the refreshed bits status is available at the next external SPI and at the next register read SPI command.

6.17.5.1.3 Device_unlock register

Writing the password ‘0x1337’ in the unlock_password field resets the full Device_lock register (0x1CD).

6.17.5.2 Identifier_and_revision block

Table 106. Reset_behavior register (0x1CE) Table 107. Device_unlock register (0x1CF) Table 108. Identification_revision register (0x1D5)

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device_id is a constant that identifies the 33816. Its value is ‘0x9D’ for MC33816AE and '0x9C' for MC33816MAE.
mask_id is a version number of the mask set used for the device
sw_id is a version number related to the mask set. The value stored in the sw_id field determines the compatibility with the assembler instruction set.

6.17.5.3 Flags_management block

mode selection (Flags_direction register). busses are then combined to generate a single int_flags bus. connected to a fixed element of the flag bus.

if configured as an input, the pin signal overwrites the corresponding element of the flag_bus. In this configuration, an anti-glitch filter is applied to the flag. The filter time is three cksys clock cycles (125 ns at 24 MHz)
If configured as an output, the corresponding element of the flag_bus is taken from the int_flags bus. The flag_bus element is then directly connected to the external pin The three remaining internal flags int_flags are simply inputs to the two channels. In view of this feature, the channels can exchange data between them through these three signals, while the other 13 flags can be used either as internal flags or as general purpose I/Os that can be read and written by all the channels. Table 109 defines the I/Os of the device used as part of the flag_bus. The position of the external pin in the flag_bus cannot be reassigned The channel_flags_x busses are outputs of the two act_channel blocks, while the flags bus is the input to all the two act_channel blocks.

Table 109. Flag pin assignment

0 FLAG0

1 FLAG1

2 FLAG2

3 START1

4 START2

5 START3

6 START4

7 START5

8 START6

9 IRQ

10 OA_1

11 OA_2

12 DBG

6.17.5.3.1 Flags_source

flag, as shown in Table 110.

6.17.5.3.2 Flags_direction

for the flags that drive or can be driven by a device pin as specified in the Flags_source register. Table 110. Flags_source register (0x1C3) Table 111. Flags_direction register (0x1C1)

1 FLAG2 FLAG1 FLAG0

Table 112. flags_source and flags_direction registers OAx, etc). Flag_bus(x) is driven by int_flags(x). by int_flags(x). Flag_bus(x) is driven by int_flags(x).

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6.17.5.3.3 Flags_polarity

Some bits of this register are used to set the polarity of the start pins when they are not used as flag I/O.

6.17.5.4 Irq_handle block

This block combines all requests to issue an interrupt request on the external IRQB pin. the Interrupt_status register (0x1D4). By reading this register through the SPI, it is possible to ascertain the cause of the interrupt request. When none of the possible sources is requesting an interrupt, the IRQB pin is de-asserted and the Interrupt _reg register is cleared.

one of the four microcores of the microcode requests an interrupt. The interrupt source can be configured through the Sw_interrupt_routine_addr registers (0x10E and 0x12E). The related status is reported in the Uc0_irq_status registers (0x10F and 0x12F) and in the Uc1_irq_status registers (0x110 and 0x130)
the driver enable block disabling the output drivers. The interrupt source can be configured through the Driver_config register (0x1C5). The related status is reported in the Driver_status register (0x1D2)
an error that occurs on the SPI interface. The interrupt source can be configured through the SPI_config register (0x1C8). The related status is reported in the SPI_error register (0x1D3)

Table 113. Flags_polarity register (0x1C2) Table 114. Flags_polarity Table 115. Flag_polarity register for STARTx pins not used as I/Os (0x1C2) Table 116. Start_polarity

0 Start active high

1 Start active Low

the loss of the external clock. For more details, refer to the Clock_manager block section. The interrupt source can be configured through the Backup_clock_status_reg register (0x1C7). The related status is reported in the same register
the signature unit of one of the two channels, in case of a wrong signature. The interrupt source can be configured through the Flash_enable registers (0x100 and 0x120). The related status is reported in the same.

6.17.5.4.1 Interrupt register

the status of all the interrupt request towards the external microcontroller
the halt signal generated by the automatic diagnosis towards the four microcores The Figure 29 provides an overview of way configure and handle the interrupts according to the registers.

Table 117. Interrupt_status register (0x1D4) Table 118. Interrupt register bit description

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Figure 29. Interrupts sources configuration and handling overview

6.17.5.5 Backup_clock_status_handle block

This block contains an 8-bit register (Backup_clock_status_reg register) that handles the loss of its input clock reference.

timing_violation: this bit is set if a timing violation has been detected. Writing a ‘1’ value on this register bit, resets the timing violation information.
loss_of_clock: this read-only bit (loss_of_clock) latches the condition when the input reference is missing. These conditions are described in the PLL and Backup Clock section. The loss_of_clock bit can be reset by applying a valid clock frequency to the CLK device pin and setting the switch to clock pin bit high.
switch_to_clock_pin: this bit (active on rising edge) provides a way to reset the loss of clock condition. If this bit is set during a loss of clock condition, it is reset as soon as the clock manager switches the PLL input to the external reference. If this bit is set while there is no loss of clock, the bit is reset immediately without any effect.
mcu_irq_en: this bit generates an interrupt request to the microcontroller when cksys missing is detected. This interrupt is active until this register is read.
uc0_ch1_irq_en: this bit enables the generation of an interrupt request to microcore 0 channel 1 when cksys missing is detected.
uc1_ch1_irq_en: this bit enables the generation of an interrupt request to microcore 1 channel 1 when cksys missing is detected.
uc0_ch2_irq_en: this bit enables the generation of an interrupt request to microcore 0 channel 2 when cksys missing is detected.
uc1_ch2_irq_en: this bit enables the generation of an interrupt request to microcore 1 channel 2 when cksys missing is detected.
cksys_missing_disable_driver: if this bit is set, the output drivers are disabled via the signal cksys_drven, as long as the cksys_missing signal is ‘1’, for a typical duration of 25 s, as defined by tPLL_RELOCK. The interrupt to the external microcontroller and to the microcores is triggered as long as the cksys_missing signal is set. The microcore is able to process the interrupt as soon as there is a valid clock signal available on the CLK pin. The interrupt is triggered every time the Clock_manager switches to the internal clock reference, and when the clock manager tries to switch back to the external clock reference as this action is requested via the SPI.

6.17.5.6 Cipher_unit block

decoded microcode is then stored in the Code RAM. This feature cannot be disabled. The cipher algorithm is re-initialized every time the code memory is selected by a write operation to the Selection register (0x3FF).

6.17.5.7 Communication_interface block

The access to memories and register is managed, paging the addresses through a SPI accessible register, named Selection_reg. Table 119. Backup_clock_status_reg register (0x1C7)

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6.17.5.7.1 Selection_reg register

Code RAM is accessed, or to select all the other addresses, including the two Data RAMs and all the registers. Table 121 details the meaning of the three bits in this register. Some bit combinations are not allowed in this register and is ignored. can be written in parallel during Normal mode. Table 120. Selection_reg register (0x3FF) Table 121. Selection register 000 No page selected. Further SPI operation is ignored, except for the one concerning this register. 001 Channel 1 Code RAM selected. 010 Channel 2 Code RAM selected. 011 Write operation affects both channel’s Code RAM. Read operation is not possible in this case.

100 Common page selected

Table 122. Map areas selection

6.17.5.8 Prescalers block

This block contains all the clock dividers available in the 33816. The divider ratios can be set in the Ck_pre register via the SPI.

6.17.5.8.1 Clock prescaler

blocks registers, except those accessible with the SPI, which directly clocked by cksys. Note that the actual divider ratio is ck_per + 1. Setting ck_per to ’000100’ ck is cksys/5. The different device/channel operating mode available according to the Ck_per setting are described in Table 124.

6.17.5.8.2 Clock offset compensation prescaler

recovery counters of the current measure interface. Note that the actual divider ratio is ck_ofscmp_per + 1. Setting ck_ofscmp_per to ’00001000’ ck_ofscomp is cksys/9. Table 123. Ck_per register (0x1C0) Table 124. Ck_per and device modes Table 125. Ck_ofscomp_per register (0x1C4)

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6.17.5.9 Driver_enable block

the Backup_clock_status_reg (0x1C7) and the Driver_config (0x1C5) registers.

cksys_drven = 1 – The input clock signal is not missing (configurable)
drv_en = 1 – The DRVEN pin is high (mandatory)
uv_vccp = 0 – There is not undervoltage on VCCP (mandatory)
uv_vcc5 = 0 – There is not undervoltage on VCC5 (mandatory) The low-side seven output driver is enabled when:
cksys_drven = 1 – The input clock signal is not missing (configurable)
drv_en = 1 – The DRVEN pin is high (configurable)
uv_vccp = 0 – There is not undervoltage on VCCP (mandatory)
uv_vcc5 = 0 – There is not undervoltage on VCC5 (mandatory) The high-side output drivers are enabled when:
cksys_drven = 1 – The input clock signal is not missing (configurable)
drv_en = 1 – The DRVEN pin is high (mandatory)
uv_vccp = 0 – There is not undervoltage on VCCP (mandatory)
uv_vcc5 = 0 – There is not undervoltage on VCC5 (mandatory)
uv_vboost = 0 - There is not undervoltage on VBOOST (configurable)

6.17.5.9.1 Driver status

(0x1C7) and the Driver_config registers (0x1C5). configured in the Backup_clock_status_reg register (0x1C7). DrvEn_latch: this bit latches the condition when the DRVEN input pin is inactive.

1: DRVEN pin was NOT low since last reset of the driver_status register
0: DRVEN pin was low since the last reset of the driver_status register DrvEn_value: this bit is not an error condition but only a ’living copy’ of the DRVEN pin.
1: DRVEN pin is high
0: DRVEN pin is low over_temp: this bit latches the condition that an overtemperature is present. It is not used to disable the drivers. uv_vboost: this bit is set if the undervoltage on the vboost disables the high-side drivers. This condition can be configured through the Driver_config register (0x1C5). uv_vcc5: this bit latches the undervoltage condition on VCC5. uv_vccp: this bit latches the undervoltage condition on VCCP or the error issued from GND loss detection. Once an error bit has been set, it can only be reset by a SPI write operation in this register, considering that the corresponding error is no longer present. The same error bits are reset even upon SPI read operations, but only when a proper enable bit is set in the Reset_behavior register (0x1CE).

Table 126. Driver_status register (0x1D2)

6.17.5.9.2 Driver configuration

generation towards the microcontroller and the microcores can also be set.

drv_en_irq_en: if set, the drv_en generates the local interrupt.
vboost_irq_en: if set, an undervoltage on VBOOST generates the local interrupt.
vcc5_irq_en: if set, an undervoltage on VCC5 generates the local interrupt.
vccp_irq_en: if set, an undervoltage on VCCP generates the local interrupt.
over_temp_irq_en: if set, the overtemperature condition generates the local interrupt. If a local interrupt is generated, it is possible to propagate it to an external device (microcontroller) and to the four microcores. This is done when the following bits are set:
irq_mcu_en, for the external device through the IRQB pin
irq_uc0_ch1_en, for the microcore 0 of channel 1
irq_uc1_ch1_en, for the microcore 1 of channel 1
irq_uc0_ch2_en, for the microcore 0 of channel 2
irq_uc1 ch2 en, for the microcore 1 of channel 2 This register contains some other configuration bit related to the output drivers:
iret_en: the driver_enable block automatically generates a return from interrupt request towards all the microcores. This request can be filtered by microcode if not required. Two kind of return from interrupt is selectable. If iret_en is set to ‘0’, a return from interrupt request is sent to the microcores when the drivers are re-enabled after a disable condition. If iret en is set to ‘1’, a return from interrupt request is sent to the microcores when the Drivers_status register (0x1D2) is cleared. For the return from interrupt to happen the driver status register must be write or read while the reset on read configuration is activated in the Reset_behavior register (0x1CE)
vboost_disable_en: if set, an undervoltage of VBOOST disables the output drivers.
vboost_mon_en: this signal configures the divider on the VBOOST voltage. If vboost_mon_en is set to ‘0’, VBOOST is divided by 32 and then compared with a threshold. If vboost_mon_en is set to ‘1’, VBOOST is divided by 4 and then compared with a threshold.
ls7_ovr: if set to ‘1’, the low-side seven output driver is not influenced by the DrvEn signal.
hs5_ls36_ovr: if set to ‘1’, the high-side five and low-side three and six output driver is not influenced by the DrvEn signal.
vccp_ext_en: if set to ‘0’, the internal voltage regulator is enabled and the corresponding pin is used only to connect a bypass capacitor. If set to ‘1’, the internal voltage regulator is disabled and the VCCP voltage must be supplied externally through the corresponding pin. During bootstrap switch init (refer to Bootstrap switch control section) this setting is bypassed and the value of the vccp_ext_enable signal is set to the inverted value of the DBG pin sampled at reset (POResetB and ResetB) (see Table 128 for more details). In this case, the DBG pin, at reset, needs to be configured as an input, whose value is latched at the rising edge of the POResetB and ResetB signal, and used to set the configuration of the VCCP internal regulator during the init phase of the bootstrap switch. A SPI reset leaves the latched information unchanged. The DBG pin has an internal weak pull-up resistor so its value is ‘1’ when not connected (n. c.). The different device/channel operating mode available according to the Ck_per setting are described in Table 128.

Table 127. Driver_config register (0x1C5)

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6.17.5.10 SPI_access_controller block

and from all the enabled microcores. operation (register read/write) is immediately performed. SPI backdoor registers must not be changed until the backdoor operation is finished.

6.17.5.11 Trace_unit block

into microprogram counter values. The value is transmitted back, thanks to the tracer function through the DBG pin. prescaler > 3) or is not available (clock prescaler < 3). The MSB is always transmitted first on the DBG pin.

6.17.5.11.1 Full trace mode

Considering a point in the code execution, there are a very limited number of possibilities for the next values of the microprogram counter. Trace is then implemented, such as to transmit a code on four bits issued for the microprogram counter values. known by the tracer. From the starting point and knowing all the variations, it is possible to obtain the uPC path. The trace can be activated on one microcore at a time.

Calibrate: The communication between the 33816 and the tracer is asynchronous, since no clock line is shared. The first

frame transmitted through the DBG pin is a burst of eight clock cycles with a frequency half of the internal cksys. At the end of this phase the DBG pin stays low for at least one ck clock period.

Sync: The sync point is specified in Trace_start register (0x1CA). If the trace operation is enabled in the Trace_config

the 4 bits code ’1010’ (start sync) is transmitted on the DBG pin. Then the trace_unit goes to the next phase.

Trace: Each cycle is transmitted a four bit code value that identifies which path has been taken by the code execution

inside an interrupt service routine (ISR). Table 128. VCCP external enable setting

6.17.5.11.2 Normal execution trace

The codes used during normal execution are the following:

Code ’0101’, default path taken. It means that the path taken after the current instruction is the default one. For nearly all instructions, it means that the instruction has not altered the code flow, no interrupt has been received, so the following instruction is the next one. However their are some exceptions:
Unconditional jumps (jmpr, jmpf) and software interrupt requests (reqi) cannot produce this code.
This code is produced by the wait instruction if the wait is fulfilled and the wait entry 1 is selected as next destination.
Code ’1010’, forked path taken. It means that the instruction has altered the code execution path. It also means that no hardware interrupt has been received. The new uprogram counter value depends on the exact instruction that is currently under execution. For this reason, the tracer device must be provided with the microcode, to correctly select the new uPC value. Only some instruction can produce this code:
The wait instruction produces this code when the uprogram counter is unchanged (the code is waiting).
All the jump instructions produce this code when the jump is taken.
The jump to subroutine instructions (jtsr, jtsf) always produce this code.
The software interrupt request instruction (reqi) always produces this code.
Code ’0100’, automatic diagnosis interrupt. It means that the code execution has been interrupted for a fault detected by the automatic diagnosis. The new uprogram counter value is the start of the diagnosis interrupt routine. The tracer must be aware of the interrupt table to correctly select the new uPC value.
Code ’0010’, driver disabled interrupt. It means that the code execution has been interrupted for a fault that leads to disable the output drivers. The new uprogram counter value is the start of the driver disabled interrupt routine. The tracer must be aware of the interrupt table to correctly select the new uPC value.
Code ’0011’, start edge interrupt. It means that the code execution has been interrupted by a software interrupt caused by a start edge (Refer to Sw_interrupt_routine_addr (0x10E, 0x12E) for configuration). The new uprogram counter value is the start of the software interrupt routine. The tracer must be aware of the interrupt table to correctly select the new uPC value.
Code ’0110’, wait entry 2 selected. This code can be produced only by the wait instruction (wait) if the wait is fulfilled and the wait entry 2 is selected as next destination.
Code ’1011’, wait entry 3 selected. This code can be produced only by the wait instruction (wait) if the wait is fulfilled and the wait entry 3 is selected as next destination.
Code ’1101’, wait entry 4 selected. This code can be produced only by the wait instruction (wait) if the wait is fulfilled and the wait entry 4 is selected as next destination.
Code ’1001’, wait entry 5 selected. This code can be produced only by the wait instruction (wait) if the wait is fulfilled and the wait entry 5 is selected as next destination.

6.17.5.11.3 Interrupt execution trace

The most difficult concept is how to trace the flow of the uPC after the exit from an interrupt routine. If execution restarts, the next uPC value is the microcore entry point (refer to Uc0_entry_point (0x10A, 0x12A) and Uc1_entry_point (0x10B, 0x12B) sections for entry point configuration). If execution continues, the last code of the ISR point to which direction the flow continues, referring to the last instruction executed before the ISR was called. The tracing is ‘broken’ if the sync point is inside the ISR routine. If the execution restarts, after the ISR or the sync point is during normal code or inside another ISR, trace is not limited. Interrupt return (iret) instruction called with the ’restart’ parameter produces a fixed code (’1010’). Interrupt return (iret) instruction called with the ’continue’ parameter can produce any of the codes used during normal execution, except the codes referring to interrupt requests (’0010’, ’0011’ and ’0100’). Using the same rules, this code point to the path selected by the last instruction before the ISR. Automatic interrupt return request have the same possible destinations as the interrupt return (iret) instruction called with the ’continue’ parameter. However in this case, the codes are different from the ones used during normal execution.

Code ’0101’, default path taken. It means that the path taken after the current instruction is the default one. For nearly all instructions it means that the instruction has not altered the code flow, no interrupt has been received, so the following instruction is the next one. The are some exceptions:
Unconditional jumps (jmpr, jmpf) cannot produce this code.
Interrupt return (ret) instruction produces this code when they have the ’continue’ parameter and the path to be taken after the ISR is the default one (includes wait entry 1 selected).

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This code is produced by the wait instruction (wait) if the wait is fulfilled and the wait entry 1 is selected as next destination.

Code ’1010’, forked path taken. It means that the instruction has altered the code execution path. It also means that no hardware interrupt has been received. The new microprogram counter value depends on the exact instruction that is currently under execution. For this reason, the tracer device must be provided with the microcode to correctly select the new uPC value. Only some instruction can produce this code:
Interrupt return (iret) instruction produces this code when they have the ’restart’ parameter.
Interrupt return (iret) instruction produces this code when they have the ’continue’ parameter and the path to be taken after the ISR is the forked one.
The wait instruction produces this code when the uprogram counter is unchanged (the code is waiting).
All the jump instructions produce this code when the jump is taken.
The jump to subroutine instructions (jtsr, jtsf) always produce this code.
Code ’0110’, wait entry 2 selected. This code can be produced by the wait instruction (wait) if the wait is fulfilled and the wait entry 2 is selected as next destination. It is also produced by the interrupt return (iret) instruction when they have the ’continue’ parameter, a wait instruction was executing when ISR was called and the destination 2 was about to be selected.
Code ’1011’, wait entry 3 selected. This code can be produced by the wait instruction (wait) if the wait is fulfilled and the wait entry 3 is selected as next destination. It is also produced by the interrupt return (iret) instruction when they have the ’continue’ parameter, a wait instruction was executing when ISR was called and the destination 3 was about to be selected.
Code ’1101’, wait entry 4 selected. This code can be produced by the wait instruction (wait) if the wait is fulfilled and the wait entry 4 is selected as next destination. It is also produced by the interrupt return (iret) instruction when they have the ’continue’ parameter, a wait instruction was executing when ISR was called and the destination 4 was about to be selected.
Code ’1001’, wait entry 5 selected. This code can be produced by the wait instruction (wait) if the wait is fulfilled and the wait entry 5 is selected as next destination. It is also produced by the interrupt return (iret) instruction when they have the ’continue’ parameter, a wait instruction was executing when ISR was called and the destination 5 was about to be selected.
Code ’0001’, forked path after automatic interrupt return. This code can be produce only when an automatic interrupt return is received and the path to be taken after the ISR is the forked one.
Code ’0111’, default path after automatic interrupt return. This code can be produced when an automatic interrupt return is received and the path to be taken after the ISR is the default one (includes wait entry 1 selected).
Code ’0100’, wait entry 2 selected after automatic interrupt return. This code can be produce only when an automatic interrupt return is received, a wait instruction was executing when ISR was called and the destination 2 was about to be selected.
Code ’0010’, wait entry 3 selected after automatic interrupt return. This code can be produce only when an automatic interrupt return is received, a wait instruction was executing when ISR was called and the destination 3 was about to be selected.
Code ’1110’, wait entry 4 selected after automatic interrupt return. This code can be produce only when an automatic interrupt return is received, a wait instruction was executing when ISR was called and the destination 4 was about to be selected.
Code ’0011’, wait entry 5 selected after automatic interrupt return. This code can be produce only when an automatic interrupt return is received, a wait instruction was executing when ISR was called and the destination 5 was about to be selected. 1. Stop Sync: The trace operation is not meant to last indefinitely. It is possible to define a ’stop’ address (refer to the Trace_stop register (0x1CB) to define stop address). If during the precedent phase (trace) the uPC reaches the stop address, the code ’1100’ is sent on the DBG pin and the trace_unit goes to the following phase. 2. Post Trigger: The trace operation continues for a fixed number of ck clock cycles. After this time has elapsed, the trace_unit goes to idle state.

6.17.5.11.4 Trace_start

Table 129. Trace_start register (0x1CA)

6.17.5.11.5 Trace_stop

goes to the next phase (post trigger phase).

6.17.5.11.6 Trace_config

trace_enable. When this bit is set to ‘1’, the trace_unit start the first phase of the trace operation. This bit can be set to ‘0’ by the user, to immediately stop the device trace unit transmission. This bit is automatically reset after the trace operation is complete.
uc_select. Select which is the microcore target of the trace operation:
’00’: microcore 0, channel 1.
’01’: microcore 1, channel 1.
’10’: microcore 0, channel 2.
’11’: microcore 1, channel 2.
post_trigger_length. This field selects the duration of the post trigger phase, expressed as number of ck clock cycles. However, setting the post_trigger_length field to 255 generates a continuous stream after the stop point. The trace_unit can be simply deactivated by writing ’0’ in the trace_enable bit.

6.17.5.12 SPI_interface_slave block

spi_interface_slave
spi_config
spi_protocol
spi_error

Table 130. Trace_stop register (0x1CB) Table 131. Trace_config register (0x1CC)

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Figure 30. Spi_interface_slave block diagram

6.17.5.12.1 Spi_interface_slave block

This block is the module providing the SPI connection features. It only works as a slave SPI module, allowing only 1- bit data transactions. available on the MISO signal on the rising edge of the sclk clock. The cpol value of ‘1’ can be implemented by adding an external inverter.

6.17.5.12.2 Spi_config block

The spi_config register is an 8-bit register storing the SPI protocol configuration and SPI diagnosis.

miso_slewrate: selects one of the two possible values for the slew rate of the MISO pin.
protocol_mode: select the type of burst transmission accepted by the protocol, ‘0’ means mode A, ‘1’ means mode B.
irq_en: enable the SPI interface to request an interrupt towards the microcontroller, in case an incorrect SPI transmission is received.
watchdog: when using mode A, the maximum time the SPI chip select can be inactive during a burst is expressed as follows:
tWATCHDOG = tCKSYS ((watchdog +1) * 32768) where tCKSYS is the period of the cksys internal clock. The SPI protocol mode can be selected through the SPI. In this case, the SPI transmission must be compatible to mode A and B (see SPI read access and Mode B section for A and B compatible protocol description). The number of operations for the SPI transmission cannot be ‘0’ and the chip select must not be deassert during the transmission. The protocol mode can be changed at any time.

6.17.5.13 Spi_protocol block

Table 132. Spi_config register (0x1C8)

The field ‘r_w’ defines if the action is to read data (r_w = ‘1’) through the SPI or write (r_w = ‘0’) incoming data in registers. The field ‘offset’ defines where the read or write operation must start so what the first address in this burst of operations to be accessed. To detect corrupted burst of data, the protocol monitors the burst, according to the ‘protocol mode’ bit of the SPI_config Register (0x1C8).

6.17.5.13.1 SPI read access

is transmitted via the MISO line. The MSB is always transmitted first. Table 133. SPI control word description Table 134. SPI read access

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6.17.5.13.2 SPI write access

the SPI error status is transmitted via the MISO line. The MSB is always transmitted first. Table 135. SPI write access

6.17.5.14 Mode A

Figure 31. SPI protocol mode A the SPI interface goes into error state.

if the value of the select register is ’001’, the protocol transmits a frame allowing operations starting from the address 0; the number of operations is specified by the value of the Code_width register (0x107) of channel 1. This command is used to write the whole Code RAM of channel one with only one command word.
if the value of channel select register is ’010’, the protocol transmits a frame allowing operations starting from the address 0; the number of operations is specified by the value of the Code_width register (0x127) of channel 2. This command is used to write the whole Code RAM of channel two with only one command word.
if the value of channel select register is ’011’, the protocol transmits a frame allowing operations starting from the address 0; the number of operations is specified by the value of the Code_width register (0x0107) of channel 1. This command is used to fully write the Code RAMs of both channel (with exactly the same code) with only one command word.
if the value of channel select register is ’100’, the protocol transmits a frame allowing operations starting from the address 0; the maximum number of operations is 128. This command is used to fully write the Data RAMs of both channels with only one command word.
For all the other values of channel select register, the command is ignored. Transmission of control word with the parameter number set to zero and the parameter offset greater than zero is not allowed. It leads to data corruption in the registers or Data RAM. A SPI write access example is provided below. In this example, the used is setting the ADC conversion register 1 and 2 (0x194 and 0x195).
The first step consists in selecting the communication interface as target. The selection is done by writing the value 0x0004 at the Selection register address (0x3FF). The first 16-bit words to be sent is ‘0_1111111111_00001’ (0x07FE1). As the device is in idle conditions, the incoming data is a command word: write operation is selected (as the MSB is ‘0’) starting from address 0x03FF (the ten offset bits) and one data word is sent in the next frame (‘00001’ written in the 5 LSB). The next incoming frame (the data word) is 0x0004. As the number of word expected arrives, the SPI block returns to idle state;
The second step is writing the value of the two ADC conversion register one and two: the SPI block is expecting a command word. The correct data to send is ’0_0110010100_00010’. write operation is selected (as the MSB is ‘0’) starting form address 0x0194 (‘0110010100’ written in the offset field) and two data words sent in the next frame (‘00010’ written in the 5 LSB). The next incoming data is written in the ADC conversion register one (0x0194) then in following data into the ADC conversion register two (0x195).

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6.17.5.15 Mode B

Figure 32. SPI protocol mode B

The chip select is de-asserted and the number of words transferred is lower than the number specified in the command word,
The number of word transferred is equal to the number parameter + 1. If a write burst in mode B is longer than programmed in the number parameter one word more is written to the memory before the error is detected. If the number parameter is zero, the number of data word transmitted is only determined by the assertion of SPI chip select. Reading any register ’reset on read’ or any register located just before such a register using a mode B SPI communication with the number parameter set to zero is not recommended. It may lead to register reset even if no read out via the SPI. A such situation can be avoid by specifying the number data words transmitted in the command word.

6.17.5.15.1 Spi_error block

The Spi_error register is a 3-bit register split as described by the following.

cksys_missing: cksys missing error condition
frame_error: frame incomplete error condition
word_error: word incomplete error condition The block monitors the spi_protocol and the spi_interface, and reports any errors during the communication with the microcontroller. If an error is detected, the corresponding code is stored in the SPI_error register. To warn the microcontroller, during the write transfer (from microcontroller to device), the MISO signal transfers a diagnostic word:
the first 13 bits of this word are constant (’1010101010101’) and are used to detect short circuits on the MISO line,
the last three bits copy the three LSBs of the SPI_error register. After an error code is written in this register, the register becomes write-protected to latch the error condition. In this case, any other error is ignored to avoid error cumulation effect issued from error source side effect. In addition, an interrupt request can be generated towards the microcontroller, if the irq en bit is set to ‘1’ in the SPI_config register (0x1C8). When an error is reported during SPI connection, the SPI protocol inside the 33816 moves to the error state. In this state, only a read access to the SPI_error register is allowed using the command word (0xBA61). A single word then transmitted to the SPI master and the error is reset (along with the interrupt if enabled).

Table 136. Spi_error register (0x1D3)

If the value of the selection register was set to the value 0x04 (selecting the generic configuration registers) before the error, the word transmitted is the error code and the SPI_error register is immediately reset. Otherwise, a random word is sent and the error state of the SPI protocol is reset. In this second case, the error code register can be read (and thus reset) in a following frame. A detail of the error code is described by the following.

cksys missing: this errors is set if an SPI transfer is required (the chip select csb signal is low) while the cksys clock is missing.
frame error: this error is set if the number of data words in a burst is different from the one specified in the command word.
Mode A is selected, the slave_protocol block received a control word that specifies n word transfers, but the microcontroller performs less operations and then end the communication. In this case, this module provides a watchdog function: if during a programmed transfer, the communication with the microcontroller is inactive for a time longer than a prefixed limit, the transfer is considered aborted and an error is detected.
Mode B is selected, the number parameter is not zero in the command word and the number of transferred words is different from the one programmed in the command word. If a write burst in mode B is longer than programmed in the number parameter one word more is written to the memory before the error is detected.
word error: during the transfer of a long word data frame the device received or sent an incorrect number of bit. If multiple words are being transferred in a row with the chip select always active (the fastest way), the error is detected at the end of the sequence and it is not possible to identify the incorrect word. To identify the incorrect data, the chip select must be deactivated and reactivated between each word transfer. During normal operations, the SPI_error register value is 0x0000.

6.17.6 Act_channel block

This block named act_channel is defined to operate one or two microcores, depending on the dual microcore mode enablement. Two act_channel blocks are implemented in the device. Each microcore can be enable to all six start signals (refer to the Start_config_reg (0x104 and 0x124) section for more details). Each actuator can be controlled by a programmable number of output stages, normally including one high-side driver, one low-side driver and one optional freewheeling driver. The assignment of high-side and low-side output drivers to each actuator is flexible and can vary depending on the target application. Virtually each microcore is able to control all the output drivers (globally five high-side and seven low-side are available on the device). In the application, the drivers are assigned through the configuration registers. The Out_acc_ucX_chY (0x184, 0x185, 0x186, 0x187) configuration registers allow the access to any output driver by any microcore through microcode programming. This block includes two programmable microcores Uc0 and Uc1, sharing the same data memory Data RAM and the same code memory Code RAM. The second microcore of each channel can operate only if the following conditions are met:

The clock prescaler (refer to the Ck_per register (0x1C0) section for more details) is set to a value greater or equal to three. In this condition, the internal ck clock period is at least four times the cksys clock period.
The dual sequencing mode is enabled (refer to section Flash_enable (0x100 and 0x120)). Each microcore controls a dedicated set of outputs (output drivers commands, DAC commands, Vds_threshold control and diagnosis, and OPAMP gain selection) which is combined with the same set of outputs coming from the other microcores. The not-locked microcores are in a safe state because either they have still to be enabled, or they have been unlocked by the signature unit. DAC commands, Vds_threshold control and diagnosis, and operational amplifier gain selection are not affected, so they keep their former value (the reset value if all the microcores have still to be enabled), while the output drivers commands are all driven turned off. The turn off polarity can be specified in the output configuration registers (refer to LSx output register (0x140 to 0x151) and HSx output register (0x153 to 0x161) sections). This architecture has been selected in order to have two concurrent microcores able to control overlapped actuations on two different loads, without having to provide two different Code RAMs. This block integrates the following blocks:
Parameters
Dual_microcore_arbiter
Code_RAM
Signature_unit
Micro_interface
Ch_microcore (x2)

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Figure 33. Act_channels block diagram

6.17.6.1 Parameters block

Flash Enable (flash_enable)
Control Register Microcore 0 (ctrl_reg_uc0)
Control Register Microcore 1 (ctrl_reg_uc1)
Unlock Register (unlock_reg)
Start Config Register (start_config_reg)
Status Register Microcore 0 (status_reg_uc0)
Status Register Microcore 1 (status_reg_uc1)
Code Width Register (code_width)
Checksum Register 16 MSBs (checksum_h)
Checksum Register 16 LSBs (checksum_l)
Entry Point Microcore 0 (uc0_entry_point)
Entry Point Microcore 1 (uc1_entry_point)
Diagnosis routine address (diag_routine_addr)
Driver disabled routine address (driver_routine_addr)
Software interrupt routine address (sw_interrupt_routine_addr)
Interrupt status Microcore0 (uc0_irq_status)
Interrupt status Microcore1 (uc1_irq_status)
Counters prescaler (counters_prescaler)
Control register split (control_register_split)

6.17.6.1.1 Flash_enable

checksum_disable. If set, this bit disables the effects of a failed checksum, so microcore execution is not stopped.
pre_flash_enable. This bit ’freezes’ the Code RAM. When this bit is set to ‘1’, the microcontroller cannot further modify the configuration code unless the specific unlock code is written into Unlock_word registers (0x103 and 0x123). It also enables the signature_unit.
flash_enable. This bit enables the microcores. It can only be set by the signature_unit after a successful checksum calculation.
en_dual_microcore. This bit is used to enable the dual sequencing mode. Run dual sequencing requires to set the ck_per at least to three (refer to Ck_per register (0x1C0) section).
dual_uc_failure. This read-only bit is set to ‘1’ when the dual microcore mode is enabled, but the ck clock is not compatible (ck_per lower than three). The bit is also set if the ck_per value is reduced to a value lower than three while the two microcores on one channel are already running. The bit can only be cleared by unlocking and re-enabling the channel.
checksum_irq_en. If this bit is ‘1’, the signature unit can generate an interrupt on the IRQB pin of the device in case of Code RAM corruption detected.
checksum_failure. This read-only bit is set to ‘1’ when a mismatch is found between the calculated checksum and the checksum code stored in the appropriate registers (refer to the Checksum_h registers (0x108, 0x128) and the Checksum_l registers (0x109, 0x129) sections). This bit is set when a checksum calculation fail, even if the checksum is disabled. This bit is reset each time the pre_flash_enable bit is set to ‘1’ to lock the memory.

6.17.6.1.2 Ctrl_reg_uc0

control_register: these eight bits can be used to control the execution of the microprogram of microcore 0, providing control bits that can be read by the microprogram itself. For instance, one bit could be used to enable/disable recharge pulses on the channel, or to re-enable the actuation after error condition detected.
control_register_shared: according to a configuration bit stored in the Control_register_split register (0x112, 0x132), these eight bits can be used either as control or like status (similar to the Status_reg_uc0 (0x105, 0x125) registers). In this case, they can only be read through the SPI, while they can be set by the ‘set control register bit’ microcode instruction (stcrb).

Table 137. Flash_enable registers (0x100, 0x120) Table 138. Ctrl_reg_uc0 control registers for the microcores 0 (0x101, 0x121)

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6.17.6.1.3 Ctrl_reg_uc1

control_register: these eight bits can be used to control the execution of the microprogram of microcore 1, providing control bits that can be read by the microprogram itself. For instance, one bit could be used to enable/disable recharge pulses on the channel or to re-enable the actuation after an error condition detected.
control_register_shared: according to a configuration bit stored in the Control_register_split registers (0x112, 0x132), these eight bits can be used either as control or like status (similar to the Status_reg_uc1 (0x106, 0x126) registers). In this case, they can only be read through the SPI, while they can be set by the ‘set control register bit’ microcode instruction (stcrb).

6.17.6.1.4 Unlock_word

(hexadecimal). SPI read operations cannot be performed at this address.

6.17.6.1.5 Start_config_reg

for each microcore (refer to the Start_management Block section for more details).

start1_sens_uc0. This bit is ‘1’ if the uc0 is enabled by start1
start1_sens_uc0. This bit is ‘1’ if the uc0 is enabled by start2
start3_sens_uc0. This bit is ‘1’ if the uc0 is enabled by start3
start4_sens_uc0. This bit is ‘1’ if the uc0 is enabled by start4
start5_sens_uc0. This bit is ‘1’ if the uc0 is enabled by start5
start6_sens_uc0. This bit is ‘1’ if the uc0 is enabled by start6
start1_sens_uc1. This bit is ‘1’ if the uc1 is enabled by start1
start2_sens_uc1. This bit is ‘1’ if the uc1 is enabled by start2
start3_sens_uc1. This bit is ‘1’ if the uc1 is enabled by start3
start4_sens_uc1. This bit is ‘1’ if the uc1 is enabled by start4

Table 139. Ctrl_reg_uc1 control registers for the microcores 1(0x102, 0x122) Table 140. Unlock_word registers (0x103, 0x123) Table 141. Start_config_reg registers (0x104, 0x124)

start5_sens_uc1. This bit is ‘1’ if the uc1 is enabled by start5
start6_sens_uc1. This bit is ‘1’ if the uc1 is enabled by start6
smart_start_uc0. This bit is ‘1’ if the smart start mode is enabled for uc0 (refer to Start_management block section for more details)
smart_start_uc1. This bit is ‘1’ if the smart start mode is enabled for uc1 (refer to Start_management block section for more details)

6.17.6.1.6 Status_reg_uc0

microprogram) between the microcore and the main microcontroller according to the microprogram definition.

6.17.6.1.7 Status_reg_uc1

microprogram) between the microcore and the main microcontroller according to the microprogram definition.

6.17.6.1.8 Code_width

Determination of the length of the special frame transfer used for Code RAM initialization (refer to the Spi_protocol block section for more details). This information is used by the SPI interface.
Computing the checksum by the signature unit if only a part of the Code RAM is used. The signature unit only works for code width > 2. Specifying a value in the Code_with register allows the main MCU to partially write the Code RAM.

Table 142. Status_reg_uc0 registers (0x105, 0x125) Table 143. Status_reg_uc1 registers (0x106 and 0x126)

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6.17.6.1.9 Checksum_h

result of its computation to this register and checksum_l.

6.17.6.1.10 Checksum_l

of its computation to checksum_h and this register.

6.17.6.1.11 Uc0_entry_point

This 10-bit register contains the Code RAM address of the first instruction to be executed by the microcore 0 of the channels 1 and 2.

6.17.6.1.12 Uc1_entry_point

program in case the two entry points coincide. Table 144. Code_width registers (0x107, 0x127) Table 145. Checksum_h registers (0x108, 0x128) Table 146. Checksum_l registers (0x109, 0x129) Table 147. Uc0_entry_point registers (0x10A, 0x12A)

6.17.6.1.13 Diag_routine_addr

diagnosis_routine_address_uc0. The complete address is ’0000’ and ’diagnosis routine address uc0’: This is the Code RAM address of the first instruction of the interrupt routine to be executed by uc0 when an automatic diagnosis exception is raised.
diagnosis_routine_address uc1. The complete address is ’0000’ and ’diagnosis routine address uc1’: This is the Code RAM address of the first instruction of the interrupt routine to be executed by uc1 when an automatic diagnosis exception is raised.

6.17.6.1.14 Driver_disabled_routine_addr

driver_disable_routine_address_uc0. The complete address is ’0000’ & ’driver disable routine address uc0’: This is the Code RAM address of the first instruction of the interrupt routine to be executed by uc0 when a disabled driver or cksys missing exception is raised.
driver_disable_routine_address_uc1. The complete address is ’0000’ and ’driver disable routine address uc1’: This is the Code RAM address of the first instruction of the interrupt routine to be executed by uc1 when a disabled driver or cksys missing exception is raised. The following events can trigger this interrupt (all configurable):
DRVEN pin is low
uv_vccp is asserted
uv_vcc5 is asserted
uv_vboost is asserted
cksys is missing
overtemperature is asserted

Table 148. Uc1_entry_point registers (0x10B, 0x12B) Table 149. Diag_routine_addr registers (0x10C, 0x12C) Table 150. Driver_disabled_routine_addr registers (0x10D, 0x12D)

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6.17.6.1.15 Sw_interrupt_routine_addr

software_interrupt_routine_address_uc0: The complete address is ’0000’ & ’software interrupt routine address uc0’: This is the Code RAM address of the first instruction of the interrupt routine to be executed by uc0 when a software interrupt is requested.
software_interrupt_routine_address_uc1: The complete address is ’0000’ and ’software interrupt routine address uc1’: This is the Code RAM address of the first instruction of the interrupt routine to be executed by uc1 when a software interrupt is requested.
sw_irq_rising_edge_start_uc0: When this bit is set to ‘1’, the software interrupt 0 is generated towards microcore 0 if a rising edge is detected on the gen_start signal. When set to ‘0’, no software interrupt is required.
sw_irq_falling_edge start_uc0: When this bit is set to ‘1’, the software interrupt 0 is generated towards microcore 0 if a falling edge is detected on the gen_start signal. When set to ‘0’, no software interrupt is required.
sw_irq_rising_edge_start_uc1: When this bit is set to ‘1’, the software interrupt 1 is generated towards microcore 1 if a rising edge is detected on the gen_start signal. When set to ‘0’, no software interrupt is required.
sw_irq_falling_edge_start_uc1: When this bit is set to ‘1’, the software interrupt 1 is generated towards microcore 1 if a falling edge is detected on the gen_start signal. When set to ‘0’, no software interrupt is required.

6.17.6.1.16 Uc0_irq_status

cleared, except for the iret_address field which retains its value until overwritten by the next interrupt.

interrupt_routine_in_progress: ‘1’ when an interrupt is being served.
irq_source:
’000’: serving start rising edge interrupt
’001’: serving driver disable interrupt request
’010’: serving automatic diagnosis interrupt request
’011’: serving start falling edge interrupt
’100’: serving software interrupt request 0
’101’: serving software interrupt request 1
’110’: serving software interrupt request 2
’111’: serving software interrupt request 3
iret_address: the value of the return address after the interrupt is served The return address after an interrupt is always the address where the code execution would have had continued if no interrupt had occurred. For wait and conditional jump instructions, the address is defined taking into account the status of the feedbacks at the moment the interrupt request took place.

Table 151. Sw_interrupt_routine_addr registers (0x10E, 0x12E) Table 152. Uc0_irq_status registers (0x10F, 0x12F)

6.17.6.1.17 Uc1_irq_status

cleared, except for the iret_address field which retains its value until overwritten by the next interrupt.

interrupt_routine_in_progress: ‘1’ when an interrupt is being served.
irq_source:
’000’: serving start rising edge interrupt
’001’: serving driver disable interrupt request
’010’: serving automatic diagnosis interrupt request
’011’: serving start falling edge interrupt
’100’: serving software interrupt request 0
’101’: serving software interrupt request 1
’110’: serving software interrupt request 2
’111’: serving software interrupt request 3
iret_address: the value of the return address after the interrupt is served The return address after an interrupt is always the address where the code execution would have had continued if no interrupt had occurred. For wait and conditional jump instructions, the address is defined taking into account the status of the feedbacks at the moment the interrupt request took place.

6.17.6.1.18 Counter_34_prescaler

setting the counter_3_per_uc0 to ‘0100’ results in a time step of counter3 microcore0 of ck period * 5.

6.17.6.1.19 Control_register_split

Table 153. Uc1_irq_status registers (0x110, 0x130) Table 154. Counter_34_prescaler registers (0x111, 0x131) Table 155. Control_register_split registers (0x112, 0x132)

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cr_shared_uc0: if set to ‘0’, all the 16 bits of the control register uc0 are used as control bits. If set to ‘1’, the eight MSBs of the control register (control register shared) are used as status bits.
cr_shared_uc1: if set to ‘0’, all the 16 bits of the control register uc1 are used as control bits. If set to ‘1’, the eight MSBs of the control register (control register shared) are used as status bits.

6.17.6.2 Dual_microcore_arbiter block

the two microcores
the signature unit (Code RAM only)
the SPI interface.

6.17.6.2.1 Access sequence to code RAM

When the device is operating in single microcore mode, access slots to Code RAM are granted according to Table 156. even number id from T4 and following T4. T_odd represents all the time slots with an odd number id from T5 and following T5. When the device is operating in dual microcore mode, access slots to Code RAM are granted according to Table 157. Note that dual microcore mode is not operating if ‘ck_per < 3’ (refer to section Ck_per register (0x1C0)). Table 156. Code RAM access sequence (single microcore mode) Table 157. Code RAM access sequence (dual microcore mode)

6.17.6.2.2 Access sequence to data RAM

When the device is operating in single microcore mode, access slots to Data RAM are granted according to Table 158. Note that dual microcore mode is not operating if ‘ck_per < 3’ (refer to section Ck_per register (0x1C0)).

6.17.6.3 Code_RAM block

allowing both uc0 and uc1 to execute this code in parallel if dual microcore mode is enabled.

6.17.6.4 Signature_unit block

The task of the signature unit is to compute a checksum of the Code RAM to detect possible memory corruption. 0x109, 0x128, 0x129). These two registers contain the golden checksum provided during the initialization phase through the SPI. and both microcores accessing the same Code RAM are disabled. the flash_enable register) without disabling code execution. The signature unit works only for a code width 3. Otherwise, the signature unit must be disabled. In case a checksum calculation failure, the computation can be relaunched by writing again the pre_flash_enable bit to ‘1’. Table 158. Data RAM access sequence (single microcore mode) Table 159. Data RAM access sequence (dual microcore mode)

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6.17.6.5 Micro_interface block

microcontroller, but it can also be used by the microcores to store temporary data.

Start_management
dp_ram, actually instantiating the Data RAM block.

Figure 34. Micro_interface block diagram

6.17.6.5.1 Start_management block

the gen_start_uc0, gen_start_uc1, start_latch_uc0, and start_latch_uc1 signals. The main purpose of this block is to generate the internal gen_start signals feeding the microcores, starting from the STARTx pins. pin was active when the actuation currently ongoing had begun. actuation is ongoing, the level of the STARTx pins in two different modes that can be selected.

Transparent Mode. The gen_start_ucx is high, if at least one of the STARTx signals to which the corresponding microcore is enabled, is high (refer to the Start_config_reg register (0x104 and 0x124) section). The start_latch_ucx signal is a living copy of the six startx pins that can enable the channel.
Smart Latch Mode. When a STARTx pin (by which the microcore is enable) goes high and the start_latch_ucx is ’000000’, the gen_start_ucx is set and the current STARTx pin status is latched in the start_latch_ucx register. If a rising edge is detected on any other STARTx pin, this edge is ignored. The gen_start_ucx signal goes to 0 only when the STARTx pin initially latched goes low. The start_latch_ucx register is reset only by the microcode by means of the rstsl instruction (signal reset_start_latch). The gen_start_ucx signal does not go high, until the start_latch_ucx register has been reset.

Figure 35. Smart start latch diagram Latch mode is enabled, no start edge is latched before the channel is locked by the flash enable bit.

6.17.6.5.2 Dp_ram block

Data RAM memory locations can be accessed by the external microcontroller and both microcores of a Logic Channel. the dram1_ private_ area_lock and the dram2_ private_ area_lock bits of the device_lock register (0x1CD).

6.17.6.6 Ch_microcore block

to allow full flexibility and programmability of the control strategy.

Instruction_decoder
Internal_reg_mux
Counters
Uprogram_counter
ALU start_latch_ucx

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Figure 36. Microcore block diagram

6.17.6.6.1 Internal_reg_mux block

can be accessed by the instructions cp, load, and store. The memory map is shown in Table 160. Table 160. Microcore internal bus address map

transfer from one of the register of the internal bus.

6.17.6.6.2 Counters

asserted. These signals are fed to Instruction_decoder. than the counter value) until the new end of count value is reached. the Data RAM or into any the registers connected to the internal bus. this event has occurred. The load instructions don’t reset the counter after loading the eocx register. to measure longer times (refer to Conter_34_prescaler section (0x111 and 0x131)). Use these counters results in a lower resolution. Table 160. Microcore internal bus address map (continued)

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6.17.6.6.3 Uprogram_counter block

This block instances two registers: the microprogram counter (uPC) and the auxiliary register. uPC This is a 10-bit counter used to address the Code RAM containing the microprogram. After the Code RAM is locked, this counter is loaded with an entry point selected through a SPI register (refer to the Uc0_entry_point (0x10A and 0x12A) and the Uc1_entry_point (0x10B and 0x12B) sections), the address of the first ‘active’ instruction. If an interrupt is requested, the uPC counter is moved to the appropriate interrupt routine register, as programmed in the parameter registers (refer to Diag_routine_addr (0x10Cand 0x12C) and the Driver_disabled_routine_addr (0x10D and 0x12D) and the Sw_interrupt_routine_addr (0x10E and 0x12E) sections). Only one level of interrupt is supported. Before entering an interrupt routine, the interrupt status register is latched (refer to the Uc0_irq_status (0x10F and 0x12F) section). When an iret (interrupt return) instruction is executed, the interrupt status register is cleared and the uPC counter can be restored to the original address. The instruction_decoder block directly controls the uPC in order to allow an efficient management of:

direct jumps
conditional jumps
subroutines execution
wait states Auxiliary register (aux) This 10-bit register is used to manage the one-level subroutines returns or as an auxiliary memory element. Any time the system executes a ’jump to subroutine’ instruction, the uPC is automatically stored in the auxiliary register before jumping to the subroutine start address. When the subroutine execution ends, the incremented auxiliary register content is transferred back to the uPC.

6.17.6.6.4 ALU block

The microcore contains a simple Arithmetic Logic Unit (ALU). The ALU has an 8-word internal register file, connected to the internal bus. The ALU can perform the following operations:

Addition and subtraction. These operations are completed in a single ck clock cycle.
Multiplication. This operation is completed in 17 ck clock cycles. The result is available as a 32-bit number, always in the registers GPR6 (MSBs) and GPR7 (LSBs).
Shift operations. The operand is shifted of one position (left or right) each ck clock cycle, so it requires from 1 to 16 ck clock cycles to execute. The shift operations always consume the operand. It is also possible to shift an operand by eight positions (left or right) or to swap the eight MSBs with the eight LSBs in one ck clock cycle.
Logic operation. It is possible to operate a bitwise logical operation (and, or, xor) between an operand and a mask. It is also possible to bitwise invert an operand. All these operations are completed in a single ck clock cycle. These operations always consume the operand.
C2 conversions. It is possible to convert data from an unsigned representation to two’s complement and vice versa. This operation is completed in a single ck clock cycle.

Figure 37. ALU block diagram cases the request is ignored by the ALU.

Addition (add), addition with immediate (addi)
Subtraction (sub), subtraction with immediate (subi)
Multiplication (mul), multiplication with immediate (muli)
Logical operation (and, not, or, xor)
Conversion from positive to two’s complement (toc2) and from two’s complement to positive (toint)
Shift operation (sh32r, sh32l, shl, shr, shls, shrs), shift operation with immediate (sh32ri, sh32li, shli, shri, shlsi, shrsi), and byte manipulation shift (shl8, shr8, swap)
ALU configuration (stal) Some ALU instructions are multi-cycle (mul, muli and possibly sh32r, sh32l, shl, shr, shls, shrs, sh32ri, sh32li, shli, shri, shlsi, and shrsi, depending on how many shift positions are required). While a multi-cycle operation is in progress, all ALU instructions are ignored, except for the stal instruction. During this time, the operations who try to modify the ALU registers (GPR0-7, arith_reg) are ignored (ldirl, ldirh, and possibly cp, load if their destination address is one of the ALU registers). Instructions who try to read the ALU registers are successful (possibly cp and store). Transfer in the ALU register GPR5 constant values present in the microcode is possible by using the ldirl and ldirh instructions.

6.17.6.6.5 Instruction_decoder block

the Access sequence to Code RAM section for more details).

This block is enabled by the gen_start signal issue from the start_management block typically used to trigger an actuation
This block provides the output command, the dac values, the opamp_gain selection to perform the actuation
Timings is defined through four up-counters whose terminal count (tcx) signal is acquired by the Instruction_decoder block
This unit can write into the Data RAM data coming from any register connected to the internal bus (refer to the Internal_reg_mux block section)
The uPC and the auxiliary register change according to the decoded instruction
The 16-bit general purpose input-output flag bus is controlled by this unit
To grant a direct control on the actuation and diagnosis process, this unit can acquire all voltage feedbacks
In order to allow some control bits exchange, this unit can program a status register, usually used to transfer to the main microcontroller the faults detected on the actuation stage by the diagnosis block
To acquire a control register, this register allows the external microcontroller to control the microprogram execution flow through microprogram defined control bits
All the 33816 registers can normally be accessed from the SPI, using a SPI backdoor

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Some instructions can modify the configuration of the microcore or of the device, such as set the end of actuation mode or enable the automatic DCDC mode All the instructions managed by this block are detailed in the 33816 sections, beginning with CPU features and operation.

6.17.6.6.6 Internal registers addressing

The Instruction_decoder has access to the internal bus (refer to the Internal_reg_mux block section) and to a point to point data bus towards the Data RAM. The Instruction_decoder can manage the transfer of data between two internal registers or between one internal register and one element of the Data RAM. The Instruction_decoder cannot directly manage a transfer of data between two elements of the Data RAM. It is possible to use an offset while addressing the Data RAM. This feature is not available when addressing the internal registers. This offset is contained in the addr_base register and can be added (module 64) to the Data RAM address specified in the instruction. It is possible to modify the value of addr_base with the stab instruction. The three basic operations are:

Copy. This instruction copies the value of one of the internal registers to another. The value of addr_base is neglected
Load. This instruction copies the value of a Data RAM element into one of the internal registers. A boolean parameter specifies if addr_base must be considered while addressing the Data RAM only
Store. This instruction copies the value of one of the internal registers to a Data RAM element. A boolean parameter specifies if addr_base must be considered while addressing the Data RAM only
Load instructions can be operated byte wise copying parameters from Data RAM to registers using the following modes:
word_read_mode: load instruction transfers 16 bits to an internal register
lowbyte_read_mode: load instruction transfers the eight LSBs of the Data RAM value to eight LSBs of an internal register. The eight MSBs of internal register are set to 0x00
higbyte_read_mode: load instruction transfers the eight MSBs of the Data RAM value to eight LSBs of an internal register. The eight MSBs of internal register are set to 0x00
swapbyte_read_mode: load instruction transfers 16 bits to an internal register but swaps the 8MSBs with LSBs

6.17.6.6.7 Flow control

This function controls the microprogram counter, selecting the next executed instruction. Regarding the Flow Control, all events can be classified and described in the following categories:

Wait instruction. When this instruction is executed, the uPC is frozen (the code execution is stopped) until at least one of the conditions specified in a ’wait table’ becomes true. Then the uPC is set to the value corresponding to that condition
Jump instructions. When this instruction is executed, a condition is tested. If the condition is true, then next uPC value is the one specified by the instruction. Otherwise the uPC is incremented by 1
Other instructions. When all other instructions are executed, the uPC is incremented by 1
Interrupt requests and returns. When an interrupt request or return is received the uPC is set to a defined location as detailed by the following This block acquires all the possible conditions checked by the conditional instructions (wait and conditional jump) and checks whether the condition is being matched. Depending on the match of these conditions, the address of the next executed instruction can be:
uPC: the address doesn’t change. This happens when the instruction being executed is a wait, and none of the enabled conditions were met
uPC + 1: the address is incremented. This happens for all other instructions, or when the instruction being executed is a conditional jump and the condition was not met
Jump address: the address is set to the jump address. This happens for all unconditional jump instructions, or for conditional jump instructions when the condition was not met
Wait destination address: the address is set to the wait destination address (refer to the Wait Instruction section). This happens when the instruction being executed is a wait, and at least one of the enabled conditions has been met; the destination address is the one of the wait entry corresponding to the verified condition. When multiple conditions are satisfied at the same ck clock cycle, the entries with lower id have priority (N°1 is the top priority, N°5 is the lowest priority)
Automatic diagnosis interrupt routine address: this address (defined in the Diag_routine_addr (0x10C and 0x12C) section) is selected as the new uPC value if an automatic diagnosis interrupt request is received by the microcore. This condition has an higher priority than any instruction and any other interrupt
Driver disabled interrupt routine address: this address (defined in the Driver_disabled_routine_addr (0x10D and 0x12D) section) is selected as the new uPC value if an interrupt request, due to disabled drivers, is received by the microcore. This condition has an higher priority than any instruction and the software interrupt

Software interrupt routine address: this address (defined in the Sw_interrupt_routine_addr (0x10E and 0x12E) section) is selected as the new uPC value if a software interrupt request is received by the microcore. This condition has an higher priority than any instruction Wait instruction The wait instruction uses a ’wait table’ to configure its behavior. The wait table is composed of five entries. Each of the entries contains:
An enable flag (1-bit). This flag is set by the wait instruction to select if the condition code specified in the entry is enabled
A condition code. (6-bit) This code specifies the condition that has to be tested
A destination address (10-bit). This address specifies the address of the Code RAM to which the program execution should jump if the wait condition is met. Regardless of the addressing mode, the address stored in the wait table is always the physical address of the destination Before the wait instruction is issued, the wait table has to be filled to configure the wait entries to obtain the desired behavior. One instruction is required for each wait entry needing to be configured. The wait table is not reset after each wait, so if some of the entries are common between one wait instruction and the following one, the entry need not to be inserted in the table between the two waits.

Figure 38. Wait table management diagram

terminal_counts: any of the four terminal count (tc1, tc2, tc3, and tc4) signals can be checked to detect if any of the four counters (refer to document Micro Machine Description) has reached its end of count position
Flags: checks the value (both polarities) of one of the 16 flags signals available
Shortcut feedback: the voltage feedback (both polarities) related to the three shortcut outputs. For all the three shortcut, it is possible to test the VDS feedback; in addition for all three shortcuts, it is possible to test the Vsource feedback in negative polarity, if available (only if the shortcut is linked to an high-side driver)
gen_start: checks the value (both polarities) of the filtered chx_start input signal to define when to start and finish an actuation
current_feedback: the value (both polarities) of the six current feedbacks. Every time a DAC value is changed, the related current feedback is marked as invalid for a fixed time, to avoid using wrong feedback while the DAC is settling. While the feedback is invalid, all the checks related to that signal produce false result, whether the polarity requested by the check itself (jumps are not taken and waits are not quit). For further details refer to current filter registers (0x198, 0x199 and 0x19A) section
own_current_feedback: the value (both polarities) of the own current feedbacks. This feedback can be different for each microcore and can be changed with the microcode instruction dfcsct. Table 161 shows the configuration after reset. This can be useful when each microcore uses just one (and different) current feedback. This allows exactly the same code in Code RAM, even if each microcore uses a different current measure block

Table 161. Current feedback assignment

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vboost: the output (both polarities) of the comparator that measures the boost voltage. This checks if the boost voltage is above or below the threshold
op_done: check if a previously issued ALU operation is still in progress or it is completed Jump instructions Conditions to be checked by the jump instructions are the same of the wait instruction with the addition of the following inputs:
ctrl_reg: checks the value (both polarities) of one of the 16 control bits available in the ctrl_reg register. This is true both when the control register bits are 16 and when eight bits of the control register are used as status register bits (when operating in control_register_split mode the control bits is eight (refer to the Control_register_split (0x112 and 0x132) section)
status_bits: checks the value (both polarities) of one of the 16 control bits available in the Status_bits register
voltage feedback: the voltage feedback (both polarities) related to all the outputs
start_latch: checks the value of the six bit start_latch
arithmetic_register: checks the value (high polarity only) of one of the bit of the ALU arithmetic register (refer to Arithmetic Condition Register section)
microcore_id: check if the microcore currently executing is uc0 or uc1 Code RAM addressing modes All the jump instruction have two possible outcomes: if a specific condition (if any) is true, then the code flow continues at a destination specified by a parameter, otherwise it continues to the next code line. In the same way, when a wait entry is configured, a parameter specifies the destination. The destination is a 10-bit Code RAM address and cannot be directly expressed in the 16-bit instruction, as it is impossible to encode an instruction set with such large parameters. The instruction set of the 33816 allows only two addressing modes to express the destination parameter for the Code RAM:
Relative address. The relative address parameter is represented on the five bit only. The physical address of the destination is obtained by adding the relative address to the physical address of the instruction that uses the parameter. The relative address must be considered as 2s-complement, represented and must be extended on 10-bit before the addition By using relative addresses it is possible to range from ’current_address - 16’ to ’current_address +15’.
Indirect address. It is possible to jump to the Code RAM address contained into one of two jump_registers (jr1 and jr2): These registers can be loaded with a dedicated instruction and simply referred to in the wait or jump instructions Interrupt routines An interrupt routine is executed when an interrupt request is received by the microcore. The microcore must not already been executing another interrupt routine. The interrupt routine can’t be interrupted by any other interrupt, but only be terminated via an iret instruction or (if configured in this way by the iconf instruction) by reading the related diagnosis register through SPI (not through the SPI backdoor):
Err_ucXchY registers (0x162 to 0x169) for the automatic diagnosis interrupt
Driver_status register (0x1D2) for the disabled drivers interrupt The interrupts received are queued while another interrupt execution is on going. When exiting the ongoing interrupt routine with the iret instruction, the queue can be cleared and queued interrupt are ignored. Otherwise, the queued interrupts are executed per their priorities:
automatic diagnosis interrupt (higher priority)
driver disabled interrupt
software interrupt (lower priority) The interrupt return address is always calculated when the interrupt occurs, and is stored in the Ucx_irq_status registers (0x10F, 0x110, 0x12F, 0x130). The return address is the address where the code execution was interrupted. If a wait or a conditional jump instruction is interrupted, the return address is defined, restoring the status of the feedbacks at the moment the interrupt request occurred.

6.17.6.6.8 HS feedback selection

Two of the high-side outputs (HS2 and HS4) have two different VDS feedbacks. One compares the differential voltage between the VBOOST pin and the related high-side source against a threshold, the other one compares the differential voltage between the VBATT pin and the related high-side source against the same threshold. The two feedbacks can’t be used at the same time, but it is possible to selected the desired one by using the slfbk instruction. With the same instruction, it is possible to enable or disable automatic diagnosis on that high-side output. For instance, this can be used to disable automatic diagnosis, when switching to a comparator which is already known to produce an inconsistent feedback.

6.17.6.6.9 DAC control

contains the DAC_4h4neg register.

If the parameter is dac_access_mode, only the DAC field (the dac_value_4h field for the DAC_4h4neg register) can be read or written
If the parameter is offset_access_mode, only the offset field (the dac_value_4neg field for the DAC_4h4neg register) can be read or written
If the parameter is full_access_mode, all the fields can be read or written The current measure block can perform analog to digital conversion in ADC mode (refer to the ADC conversion registers (0x194, 0x195, 0x196, and 0x197) section). The result of the conversion can be accessed from the internal memory addresses normally used for the DACs (not DAC_4h4neg) if the parameter is set to dac_access_mode, until the ADC mode is disabled.

6.17.6.6.10 Microcore shared register

read the data using the same address, selecting the source microcore with the stcrt instruction.

6.17.6.6.11 Registers reset

Reset status bits
Reset control register
Reset status bits, automatic diagnosis register and re-enables the possibility to generate automatic diagnosis interrupts
Reset status bits, control register, automatic diagnosis register and re-enables the possibility to generate automatic diagnosis interrupts
Reset automatic diagnosis register and re-enables the possibility to generate automatic diagnosis interrupts
Reset status bits and control register
Reset status bits and re-enables the possibility to generate automatic diagnosis interrupts
Re-enables the possibility to generate automatic diagnosis interrupts

Table 162. DAC register x in DAC mode Table 163. DAC_4h4neg register Table 164. DAC register x in ADC mode

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6.17.6.6.12 Diagnosis configuration

According to the parameters of the endiag instruction being executed, this function selects the automatic protection to enable for every output. According to which the output is allowed to be driven by the microcore, the diagnosis enablement or disablement can be restricted.

6.17.6.6.13 Flags

This function sets the value of the 16-bit flag bus coming out of the act_channel block. All the flags controlled by the four microcores are combined according to flags_management setting (refer to the Flags_management block section). The flag are active low, so the reset value of the flags is ‘1’. When the microcore is unlocked, all the flags are fixed to the inactive state (‘1’) to avoid disturbing the communication of the other microcores.

6.17.6.6.14 Interrupt request

This function, according to the parameter of the stirq instruction, sets the value of the irq signal managed in the act_channel block and acts on the IRQB pin.

6.17.6.6.15 Subroutine

This function directs the auxiliary register to store the value of the uPC when a jump to subroutine instruction is being executed.

6.17.6.6.16 Current measure control

This function:

Enables and disables the offset compensation of the current measurement analog block when the stoc instruction is being executed (refer to the Offset Compensation (0x190, 0x192, 0x192, and 0x193) section). The offset compensation is performed only on the first four DACs. The offset measured on DAC4l is used also for offset recovery of DAC4h. No offset compensation is foreseen for DAC4neg
Changes the opamp gain used to measure the voltage across the shunt resistor when the stgn instruction is being executed (refer to the DAC Addressing section)
Request the current measure block to perform an ADC conversion of the current value by means of the stadc instruction. While in this mode, the current measure block cannot be used to perform threshold measures (refer to the ADC conversion section) The microcores are allowed to control the current measurement block using the suitable instructions (refer to the DAC addressing section).

6.17.6.6.17 Status bits

This functions sets either the value of the 16-bit status_bits or only one bit in this register when the stsrb, cp and load instructions are being executed.

6.17.6.6.18 SPI backdoor

Operation on registers included in the internal memory map and the Data RAM can be performed with most of the instructions. As these locations are often used, access to this location is optimized, in terms of the number of instructions required, the address register for SPI Accesses can either be the 'spi_add' register or the 'ir' register, as specified in the 'slsa' instruction. Read and write access to all the registers normally accessible through is possible except the Code RAM and Data RAM by using an SPI backdoor. To read an SPI register, first the eight LSBs of the address must be provided in the eight LSBs of the ‘SPI address’ at an internal memory map address to the load instruction. A read operation must be requested with the rdspi instruction. The result is available at the ‘SPI data’ address of the internal memory map. To write a SPI register, first the eight LSBs of the address must be provided in the eight LSBs of the ‘SPI address’ address, and the data to write must be provided at the ‘SPI data’ address to the load instruction. A write operation must be requested with the wrspi instruction. Both the SPI read and write operations are two cycle operations. The registers must not be changed while the operation is in progress. If the SPI backdoor is not used, the 8-bit register at the address ‘SPI address’ and the 16-bit register at the address ‘SPI data’ can be used as spare register. SPI backdoor access control There are some access limitations when requesting write access to SPI registers via the SPI backdoor. It is only possible to write to SPI registers that are not locked at the moment the write operation wrspi is requested. For some special registers, there are additional limitations dependant on the device configuration. Table 165 shows the different limitations. In some cases, the microcore is allowed to change some bits inside a register, but others are not accessible.

6.17.6.6.19 Microcore configuration

microcore, as long as the microcore has access to the ls7 output. output is set to zero. This condition can be automatically enabled and disabled together with the end of actuation mode.

6.17.7 Input_output_interface block

output signals as each microcore provides a complete signal set for all the output resources.

The automatic diagnosis, based on the combined output commands and the voltage feedbacks coming from the analog comparators.
The offset compensation. If requested by the microcores, this block runs the offset compensation algorithm, which uses a small DAC to compensate the input offset of the measurement amplifier. This block integrates the following blocks:
boost_dac
boost_filter
vds_regfile
slewrate_regfile
bias_regfile
bootstrap_switch_control
dac_settling_time
oa_out_config
dac_switch_box
output_switch_box

Table 165. SPI backdoor access limitations threshold. Changes to all other VDS and VSRC values are ignored. setting. Changes to all other slew rate settings are ignored. pre-driver are allowed to control the corresponding biasing source. Changes to all other biasing sources are ignored. other filter setups are ignored.

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Figure 39. Input_output_interface block diagram

6.17.7.1 Boost_dac block

possible to limit the microcore access to the boost_dac register by setting access rights. End of line offset compensation is provided for the boost monitoring, requiring no microcode operation.

Boost_threshold. This 8-bit parameter is the threshold used for boost voltage monitoring
ucX chY acc. This 1-bit parameter (active high) grants access to the dac_boost register

Table 166. Boost_dac register (0x19B) Table 167. Boost_dac_access register (0x19C)

6.17.7.2 Boost_filter block

This 13-bit register is used to configure the filter for the boost_fbk input signals.

filter_type: This 1-bit parameter selects the type of filter used:
if 0 – Any different sample resets the filter counter
if 1 – Any different sample decreases the filter counter
boost_fbk_filter. This 12-bit parameter sets the filtering time for the output of the vboost comparator The filtering time is: tFTN = tCK x (boost_fbk_filter + 1).

6.17.7.3 Vds_regfile block

they have the access right to control the related output (refer to the Out_acc_ucX_chY (0x184, 0x185, 0x186, 0x187) section). Bootstrap_switch_control block section). Table 168. Boost_filter register (0x19D) Table 169. Vds_threshold_hs register (0x18A) Table 170. Vsrc_threshold_hs register (0x18B) Table 171. Vds_threshold_ls_1 register (0x18C)

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6.17.7.4 Slewrate_regfile block

PMOS slew rate settings and Low-side seven pre-drivers NMOS slew rate settings tables).

6.17.7.5 Bias_regfile block

Bootstrap_switch_control block section). Table 172. Vds_threshold_ls_2 register (0x18D) Table 173. Hs_slewrate register (0x18E) Table 174. Ls_slewrate register (0x18F) Table 175. Bias_config register (0x1A4)

6.17.7.6 Bootstrap_switch_control block

configurations are affected.

Hsx_bs_lowcurrent: the low current limit (280 A), which is set only during initialization independently for each high-side pre-driver
Vsrc_threshold: the VSRC thresholds of each HSx, which init is set during the first to 0.5 V and after some time to 1.0 V. After the init phase is finished, the VSRC threshold goes back to the value defined in the appropriate register (refer to the Vds_regfile block section)
Ls_bias: all the ls_bias are set active for all LSx outputs, during init phase of any high-side pre-driver and then goes back to the configuration defined in the appropriate register (refer to the Bias_regfile section), when all high-side pre-drivers are out of the initialization phase
Hs_bias: the hs_bias is set inactive for the HSx outputs during initialization and then goes back to the configuration defined in the appropriate register (refer to the Bias_regfile block section) During the initialization phase of the bootstrap capacitors, the vccp_external_enable signal is also affected, according to what is defined in the VCCP External Enable Setting Table of the Driver_config register (0x1C5) section. In particular, as long as at least one high-side pre-driver is in bootstrap initialization mode, the vccp_external_enable setting is set to ‘0’ (internal regulator active) if the value of the DBG pin sampled at reset (POResetB and ResetB) was ‘1’. The charging of the bootstrap capacitors starts after reset is deactivated as soon as the VCCP voltage is ramping up. When the VCCP voltage is above the VCCP undervoltage threshold (uv_vccp=’0’), the state machine of the digital core changes to ‘init_low_thre’ state). As soon as the VCCP voltage is above the VCCP undervoltage threshold, a global timer is started for all high-side pre-drivers running on cksys with an end of count value of 36ms. As soon as the timer reaches the end of count value, the Vsrc_threshold is changed from 0.5 to 1.0 V for all the drivers which are still in initialization mode. The fsm for these pre-drivers goes to state ‘init_high_thre’. At the same moment the hsx_src_1V bit is set to ‘1’ for all these drivers. The bootstrap initialization for each HS pre-driver ends if one of the following conditions is met:
The bs ready comparator shows that the B_HSx voltage is close to the VCCP voltage, and at the same time the S_HSx voltage is below 0.5 or 1.0 V
The clamp is activated and at the same time the S_HSx voltage is below 0.5 or 1.0 V
An LS pre-driver connected to the same high-side pre-driver is switched on (hsx_ls_act signal = ‘1’)
The connection between low-side pre-drivers and high-side pre-driver is disabled (hsx_ls_act signal = ‘1’)
The same high-side pre-driver is switched on Care has to be taken in applications where two high-side pre-drivers are connected to the same node by their S_HSx pin directly or via a diode. It is not allowed in these configurations to turn on the hs_bias via the SPI register or the microcode command before all high-side pre-drivers finished their bootstrap initialization. Otherwise, an active hs_bias from one pre-driver may block the initialization of the other one. The initialization mode of each high-side pre-driver can be quit by setting the corresponding ‘hsx_ls_act_dis’ bit to ‘1’ (refer to the Hsx_ls_act registers (0x1A6, 0x1A7 and 0x1A8) section). This should be done for each high-side pre-driver not used in an application.

6.17.7.6.1 Bootstrap_charged

This register allows reading the charge status of the high-side bootstrap capacitors during initialization phase.

hsx_bs_charged: when ‘0’, the bootstrap capacitor for HSx is charged
hsx_src_1V: when ‘1’ it was necessary for this pre-driver to switch the VSRC threshold to 1.0 V in order to finish the bootstrap initialization
bootstrap_init_timer: this shows the current value of the six MSBs of the bootstrap initialization timer. The value is ‘111111’ when the timer is expired Table 177 details the exact meaning of the bits hsx_bs_charged and hsx_src_1V.

Table 176. Bootstrap_charged register (0x1A5)

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passed since VCCP voltage was stable, and which threshold is used to detect the charge of the bootstrap capacitor.

6.17.7.6.2 HS and LS coupling

This register is used to configure the ground reference of the high-side one and high-side two source pins.

hs1_ls1_act: must be set to ‘1’ if ls1 is connected to the same load as hs1
hs1_ls2_act: must be set to ‘1’ if ls2 is connected to the same load as hs1
hs1_ls3_act: must be set to ‘1’ if ls3 is connected to the same load as hs1
hs1_ls4_act: must be set to ‘1’ if ls4 is connected to the same load as hs1
hs1_ls5_act: must be set to ‘1’ if ls5 is connected to the same load as hs1
hs1_ls6_act: must be set to ‘1’ if ls6 is connected to the same load as hs1
hs1_ls7_act: must be set to ‘1’ if ls7 is connected to the same load as hs1
hs2_ls1_act: must be set to ‘1’ if ls1 is connected to the same load as hs2
hs2_ls2_act: must be set to ‘1’ if ls2 is connected to the same load as hs2
hs2_ls3_act: must be set to ‘1’ if ls3 is connected to the same load as hs2
hs2_ls4_act: must be set to ‘1’ if ls4 is connected to the same load as hs2

Table 177. Bootstrap_charged bits Table 178. Bootstrap initialization timer

000000 VCCP voltage is not stable (undervoltage)

Table 179. Hs12_ls_act register (0x1A6)

hs2_ls5_act: must be set to ‘1’ if ls5 is connected to the same load as hs2
hs2_ls6_act: must be set to ‘1’ if ls6 is connected to the same load as hs2
hs2_ls7_act: must be set to ‘1’ if ls7 is connected to the same load as hs2
hs1_ls_act_dis: set this bit to disable the link between high-side one and ls predrivers. If this bit is set, the hs1_ls_act signal is forced to ‘0’ regardless if a ls is active
hs2_ls_act_dis: set this bit to disable the link between high-side two and ls predrivers. If this bit is set, the hs2_ls_act signal is forced to ‘0’ regardless if a ls is active This register is used to configure the ground reference of the high-side three and high-side four source pins. The hs(3/4)_ls_act signal is high if any of the lsx pins connected to the hs(3/4) source pin is switched on or if the function is disabled by the hs(3/4)_ls_act_dis bit.
hs3_ls1_act: must be set to ‘1’ if ls1 is connected to the same load as hs3
hs3_ls2_act: must be set to ‘1’ if ls2 is connected to the same load as hs3
hs3_ls3_act: must be set to ‘1’ if ls3 is connected to the same load as hs3
hs3_ls4_act: must be set to ‘1’ if ls4 is connected to the same load as hs3
hs3_ls5_act: must be set to ‘1’ if ls5 is connected to the same load as hs3
hs3_ls6_act: must be set to ‘1’ if ls6 is connected to the same load as hs3
hs3_ls7_act: must be set to ‘1’ if ls7 is connected to the same load as hs3
hs4_ls1_act: must be set to ‘1’ if ls1 is connected to the same load as hs4
hs4_ls2_act: must be set to ‘1’ if ls2 is connected to the same load as hs4
hs4_ls3_act: must be set to ‘1’ if ls3 is connected to the same load as hs4
hs4_ls4_act: must be set to ‘1’ if ls4 is connected to the same load as hs4
hs4_ls5_act: must be set to ‘1’ if ls5 is connected to the same load as hs4
hs4_ls6_act: must be set to ‘1’ if ls6 is connected to the same load as hs4
hs4_ls7_act: must be set to ‘1’ if ls7 is connected to the same load as hs4
hs3_ls_act_dis: set this bit to disable the link between high-side three and ls predrivers. If this bit is set, the hs3_ls_act signal is forced to ‘1’ regardless if a ls is active
hs4_ls_act_dis: set this bit to disable the link between high-side four and ls predrivers. If this bit is set the hs4_ls_act signal is forced to ‘1’ regardless if a ls is active This register is used to configure the ground reference of the high-side five source pin. The hs5_ls_act signal is high if any of the lsx pins connected to the high-side five source pin is switched on or if the function is disabled by the hs5_ls_act_dis bit.
hs5_ls1_act: must be set to ‘1’ if ls1 is connected to the same load as hs5
hs5_ls2_act: must be set to ‘1’ if ls2 is connected to the same load as hs5
hs5_ls3_act: must be set to ‘1’ if ls3 is connected to the same load as hs5
hs5_ls4_act: must be set to ‘1’ if ls4 is connected to the same load as hs5
hs5_ls5_act: must be set to ‘1’ if ls5 is connected to the same load as hs5

Table 180. hs34_ls_ act register (0x1A7) Table 181. Hs5_ls_ act register (0x1A8)

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hs5_ls6_act: must be set to ‘1’ if ls6 is connected to the same load as hs5
hs5_ls7_act: must be set to ‘1’ if ls7 is connected to the same load as hs5
hs5_ls_act_dis: set this bit to disable the link between high-side four and ls predrivers. If this bit is set the hs5_ls_act signal is forced to ‘1’ regardless if a ls is active

6.17.7.7 Dac_settling_time block

is true as defined in the wait Instruction section. The filter_length value can be set in the current filter registers (0x198, 0x199, and 0x19A). also the resulting settling time can be different for each DAC.

6.17.7.8 Oa_out_config block

These two registers configures the function of the two OA_x pins.

oa1_en: when ‘1’ the selected source is sent to the OA_1 pin, otherwise it is put in high-impedance
oa1_gain: select the gain to apply to the signal.
’00’: gain 1.33
’01’: gain 2.0
’10’: gain 3.0
’11’: gain 5.33
oa1_source: select the signal to send to the OA_1 pin
’000’: output from current measurement block 1
’001’: output from current measurement block 3
’101’: 2.5 Volt

Table 182. Dac_settling_time register (0x1A9) Table 183. Oa_out1_config register (0x1AA) Table 184. Oa_out2_config register (0x1AB)

oa2_en: when ‘1’ the selected source is sent to the OA_2 pin, otherwise it is put in high-impedance
oa2_gain: select the gain to apply to the signal
’00’: gain 1.33
’01’: gain 2.0
’10’: gain 3.0
’11’: gain 5.33
oa2_source: select the signal to send to the OA_2 pin
’000’: output from current measurement block 2
’001’: output from current measurement block 4
’101’: 2.5 Volt

6.17.7.9 Dac_switch_box block

DAC value. The 8-bit value identifying the current threshold
Opamp gain. This 2-bit value identifies the gain of the operational amplifier
Ofscmp request. This bit identifies if the microcore is requesting to measure the offset
ADC conversion request. This bit identifies if the microcore is requesting the current measure block to perform an ADC conversion (refer to the ADC Conversion section) Each microcore produces four of these signals sets, one for each current measure block. This block combines the requests coming from the four microcores in one signal set for each current measure block: the multiple signals sets are managed according access right provided by the cur_access configuration register (refer to the DAC addressing section for further details). In addition, the dac_switch_box contains four offset compensation blocks, one for each current measure block. Refer to the Offset Compensation section for further details.

6.17.7.9.1 DAC addressing

Table 185 shows how the current measurement channels are addressed. This table is fixed and can not be changed.

6.17.7.9.2 Cur_access

measure block to the required microcores. microcore can drive those input signals, otherwise access is denied. are controlled by the acc_ucx_chy_curr_4h_4neg bit. Table 185. DAC addressing using sssc, ossc, …

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cycle, priorities are used as defined in the Table 188. the requested changes are applied in sequence.

6.17.7.9.3 Current filters

The six current feedbacks are filtered before feeding them to the microcores. The filters of all the current feedback are independent. Table 186. Cur_block_access_1 register (0x188) Table 187. Cur_block_access_2 register (0x189) Table 188. Cur_access collision handling Table 189. Current_filter12 Register (0x198)

filter_typex. This 1-bit parameter selects the type of filter used for the relative current feedback:
if 0 – Any different sample resets the filter counter
if 1 – Any different sample decreases the filter counter
filter_lenght_x. This 5-bit parameter set the filtering time for the current feedback signal The filtering time is tFTN = tCK x (Filter_lengthx + 1).

6.17.7.9.4 DAC values

Other than from microcores, it is possible to set the DAC for the current measure blocks by writing these registers. Table 190. Current_filter34l register (0x199) Table 191. Current_filter4h4neg register (0x19A) Table 192. Dac1_value register (0x19E) Table 193. Dac2_value register (0x19F)

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6.17.7.9.5 ADC conversion

(refer to the Current measure control section) with the correct access rights (refer to the DAC addressing section). The DAC4L is used when performing an ADC conversion using current measurement channel four. conversion at the same time at channel one and three, or on channel two and four. mode is on and available via the SPI register until the next ADC conversion is started. external microcontroller, or from every microcore via the internal register map (refer to the DAC control section). Table 194. Dac3_value register (0x1A0) Table 195. Dac4l_value register (0x1A1) Table 196. Dac4h_value register (0x1A2) Table 197. Dac4neg_value register (0x1A3)

6.17.7.9.6 Offset compensation

measurement block is null) through the combined ofs_comp signal. At the end of the measurement sequence, a new offset register value is stored until the next time this measurement sequence is executed. measure that is never worse than the precedent one. can be both positive and negative, all the values in these registers are represented as two’s complement. Table 198. Adc1_result register (0x194) Table 199. Adc2_result register (0x195) Table 200. Adc3_result register (0x196) Table 201. Adc4_result register (0x197)

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converted to sign-module notation before being transferred to the analog section.

6.17.7.10 Output_switch_box block

The 33816 can drive two types of outputs: high-side and low-side. Each type of output requires different control signals.

Output value. The value to be driven on the gate of the external MOSFET
VDS threshold. A 3-bit signal that selects the threshold for the comparator that measures the drain-source voltage of the external MOSFET
Automatic freewheeling (for low-side pre-drivers 4, 5, 6 and 7). Four low-sides pre-drivers can be configured to work as automatic freewheeling drivers
En_halt_vds. This signal enables (if set to 1) the automatic coherency check between the output and the VDS comparator
The high-side outputs require the following control signals
Output value. The value to be driven on the gate of the external MOSFET
VDS threshold. A 3-bit signal that selects the threshold for the comparator that measures the drain-source voltage of the external MOSFET

Table 202. Offset_compensation1 register (0x190) Table 203. Offset_compensation2 register (0x191) Table 204. Offset_compensation3 register (0x192) Table 205. Offset_compensation4 register (0x193)

VSRC threshold. A 3-bit signal that selects the threshold for the comparator that measures the source-ground voltage of the external MOSFET
Automatic freewheeling (for high-side pre-driver 5 only). One high-side pre-driver can be configured to work as an automatic freewheeling driver
En_halt_vds. This signal enables (if set to 1) the automatic coherency check between the output and the VDS comparator
En_halt_src. This signal enables (if set to 1) the automatic coherency check between the output and the VSRC comparator Each microcore produces seven signals sets for the low-sides and five signals sets for the high-sides. This block combines the requests coming from the four microcores in one signal set for each output: the multiple signals sets are managed according access right provided by the four Out_acc_ucX_chY configuration registers. This block integrates the following blocks:
output_access
dcdc_convert_control
automatic_diagnosis
output_routing
error_handler

Figure 40. Output_switch_box block diagram

6.17.7.10.1 Output_access block

Table 206. Out_acc_uc0_ch1 register (0x184)

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to change one of the control signals in the same ck cycle, priorities are used as defined in Table 210. microcore. This is a safety feature of the device. the requested changes are applied in sequence. Table 207. Out_acc_uc1_ch1 register (0x185) Table 208. Out_acc_uc0_ch2 register (0x186) Table 209. Out_acc_uc1_ch2 register (0x187) Table 210. Out_acc_ucX_chY collision handling

6.17.7.10.2 Dcdc_conver_control block

register (refer to the DAC values section). shunt resistor to the LS7 output is completely asynchronous to any clock (ck and cksys) of the device. is low), the output LS7 is driven low. (microcode instructions). As soon as a microcore which has access to the LS7 is unlocked, the automatic DC/DC control is switched off.

6.17.7.10.3 Automatic_diagnosis block

error_handler block (refer to the Error_handler block section).

Filter_input
Channel_check
Error_handler

Figure 41. Automatic_diagnosis block diagram

6.17.7.10.4 Automatic diagnosis reaction time

It takes four ck cycles (666 ns at 6.0 MHz) until the execution of the first microcode operation of the error routine is completed. and one ck cycle to execute the first instruction.

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Figure 42. Diagnosis reaction time diagram

6.17.7.10.5 LSx output registers

These registers define the automatic diagnosis parameter and output routing option from the low-side X output.

filter_type. This 1-bit parameter selects the type of filter used:
If 0 – Any different sample resets the filter counter
If 1 – Any different sample decreases the filter counter
filter_lenght: this 6-bit parameter set the filtering time for the input feedback signal. The filtering time is: tFTN = tCK x (filter_length + 1)
error_table: this 4-bit parameter defines the logical value of an error signal, issued from the output and the related VDS feedback signal. Basically, this table defines the output of the coherency check between the driven output and the acquired feedback; a logic one value means there is no coherency in the check, and then an error signal towards the microcore should be generated

Table 211. Lsx_diag_config1 registers (0x140, 0x143, 0x146, 0x149, 0x14C, 0x14F) Table 212. Lsx_diag_config2 registers (0x141, 0x144, 0x147, 0x14A, 0x14D, 0x150) Table 213. Lsx_output_config registers (0x142, 0x145, 0x148, 0x14B, 0x14E, 0x151) Table 214. LSx VDS error table selection true table

disable_window: this 7-bit parameter configures a time period during which any check on the LSx_Vds_feed signal is disabled after any change on the output_command signal. tDTL = tCK x (Disable_window + 4)
output_routing: this 4-bit parameter defines if the LSx output is controlled by the microcores or by an input flag pin. This function is not active if ck_per = 0.
inv: this parameter inverts the polarity of the LSx output signal, with respect to the polarity defined by the microcore. This affects the output command towards the pre-drivers, but the error_table of the associated feedback is not affected since diagnosis already takes into account the pre-driver status (even when the invert bit is set). This function is not available in case of direct gate drive by input flag pin.

6.17.7.10.6 LS7 output register

output_routing. This four bit parameter defines if the LSx output is controlled by the microcores or by an input flag pin. This function is not active if ck_per = 0.

Table 215. LSx output control table Table 216. Ls7_output_config register (0x152)

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Invert. This parameter inverts the polarity of the LSx output signal, with respect to the polarity defined by the microcore. This function is not available in case of direct gate drive by input flag pin.
fast_dcdc_en. This bit is set when the automatic DC-DC control feature for LS7 is enabled (Refer to the Dcdc_conver_control block section for the behavior of LS7 during this mode)

6.17.7.10.7 HSx output register

These registers define the automatic diagnosis parameter and output routing option for the high-side X output. Table 217. LSx output control table Table 218. Hsx_diag_config_1 Registers (0x153, 0x156, 0x159, 0x15C, 0x15F) Table 219. Hsx_diag_config_2 registers (0x154, 0x157, 0x115A, 0x15D, 0x160)

error_table_vds: This 4-bit parameter defines the logical value of an error signal, starting from the output and the related VDS feedback signal. Basically, this table defines the output of the coherency check between the driven output and the acquired feedback; a ‘logic one value’ means there is no coherency in the check and then an error signal towards the microcore should be generated
disable_window: This 7-bit parameter configures a time period during which any check on the HSx_Vds_feed and HSx_Vsrc_feed signals is disabled after any change on the output_command signal. tDTL = tCK x (disable_window + 4)
error_table_src: This 4-bit parameter defines the logical value of an error signal, starting from the output, and the related VSRC feedback signal. Basically this table defines the output of the coherency check between the driven output and the acquired feedback; a logic 1 value means there is no coherency in the check and then an error signal towards the microcore should be generated
filter_type: This 1-bit parameter selects the type of filter used: if 0 – Any different sample resets the filter counter if ‘1’ – Any different sample decreases the filter counter
dead_time: This 5-bit register is used to store the value of the dead_time end of count used in the generation of the freewheeling output (delay between the high-side output and the free wheeling output). The freewheeling command goes high after a programmable time (tFWDLY) with respect to the high-side falling edge. In this mode, the high-side command rising edge is always delayed of the same programmable time (tFWDLY) with respect to the rising edge requested by the microcores tFWDLY = tCK x (Dead_time + 1)
output_routing: This 4-bit parameter defines if the HSx output is controlled by the microcores or by an input flag pin. This function is not active if ck_per = 0.

Table 220. Hsx_output_config registers (0x155, 0x158, 0x15B, 0x15E, 0x161) Table 221. HSx VDS error table selection truth table Table 222. HSx Vsrc error table selection truth table Table 223. HSx output control table

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inv: This parameter inverts the polarity of the HSx output signal, with respect to the polarity defined by the microcore. This affects the output command towards the pre-drivers, but the error_table of the associated feedback is not affected since diagnosis already takes into account the pre-driver status (even when the invert bit is set). This function is not available in case of direct gate drive by input flag pin.
filter_lenght: This 6-bit parameter set the filtering time for the input feedback signal. The filtering time is: tFTN = tCK x (Filter_length + 1)

6.17.7.10.8 Filter_input block

This block is provided to filter the input feedback coming from each analog comparator. level is first detected on the input signal, at least N consecutive samples must be at that level before it is recognized as a valid transition. This filter operates the same way on the rising and the falling edge of the input signal. N is a programmable 6-bit value provided by signal filter_length, (refer to the LSx output registers and the HSx output registers sections).

6.17.7.10.9 Channel_check block

error_feed signal when a mismatch is detected. the delays introduced by the digital filter of the input feedback. the command and the feedback are equal or opposite, according to the way the application is designed.

6.17.7.10.10 Error_handler block

controlled by a specific instruction. order to allow the identification of the fault on the actuation stage. err_uc register through the SPI (configurable). with the rstreg instruction. Table 223. HSx output control table (continued)

6.17.7.10.11 Err_ucXchY registers

whenever an error condition is detected on any of the pairs (output/feedback) by which the microcore is enabled. The information stored in the register in regard to the output commands and the related voltage (VDS and VSOURCE) feedbacks. when the PLL output clock was not valid at the time the automatic diagnosis error occurred.

6.17.7.10.12 Fbk_sens_ucX_chY

Table 224. Err_ucXchY_1 registers (0x162, 0x164, 0x166, 0x168) Table 225. Err_ucXchY_2 registers (0x163, 0x165, 0x167, 0x169) Table 226. Fbk_sens_uc0ch1 register (0x180)

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6.17.7.10.13 Output_routing block

the combination of the microcores requests (refer to the output_switch_box section)
one device input flag (refer to the LSx output registers and HSx output registers sections)
a freewheeling command referred to one of the high-side outputs. This option can be selected, only on five outputs, by the control signal fw_auto. Refer to Table 230 for the possible combinations

Table 227. Fbk_sens_uc1ch1 register (0x181) Table 228. Fbk_sens_uc0ch2 register (0x182) Table 229. Fbk_sens_uc1ch2 register (0x183) Table 230. Automatic freewheeling pre-driver association

6.17.7.10.14 Freewheeling drive

This block controls the free wheeling output according to the high-side output command, and the fw_auto signals.

Automatic mode: (enabled when fw_auto is set to 1) the freewheeling output is always the opposite of the high-side output. The drive request by the microcore to the output used for the freewheeling function are neglected (refer to the above table). In this case, the freewheeling command goes high after a programmable time (programmed in HSx output registers) with respect to the HS command falling edge. It is also important to note that in this mode the HS command rising edge is always delayed of the same programmable time with respect to the rising edge requested by the microcore. This is done in order to always assure that high- side and freewheeling is never active at the same time.
Manual mode: (enabled when fw_auto is set to 0) the output that can be used as a freewheeling is not driven by this block. The output is instead driven by the combined microcores requests.Fw_external_request It is possible to activate automatic freewheeling even when the microcode is not running, by writing the corresponding bit of this register.
ls5_fw_en: if set, the low-side pre-driver 5 is driven as a freewheeling relative to high-side pre-diver 1, otherwise the status is defined by the microcore request (stfw instruction)
ls6_fw_en: if set, the low-side pre-driver 6 is driven as a freewheeling relative to high-side pre-diver 2, otherwise the status is defined by the microcore request (stfw instruction)
ls7_fw_en: if set, the low-side pre-driver 7 is driven as a freewheeling relative to high-side pre-diver 3, otherwise the status is defined by the microcore request (stfw instruction)
hs5_fw_en: if set, the high-side pre-diver 5 is driven as a freewheeling relative to high-side pre-diver 4, otherwise the status is defined by the microcore request (stfw instruction)
ls4_fw_en: if set, the low-side pre-driver 4 is driven as a freewheeling relative to high-side pre-diver 5, otherwise the status is defined by the microcore request (stfw instruction)

6.17.7.10.15 Diagnosis_option

Table 231. Fw_ext_req register (0x16A) Table 232. Diagnosis_option register (0x16B)

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7 CPU features and operation

7.1 Introduction

7.2 Features

The 33816 provides a set of two logic channels. A total of four similar microcores are implemented in the two logic channels of the 33816.

Two 16-bit processing units (microcores) that have a specific programming model
One code RAM - 1023 x 16-bit. This memory dedicated to microcode storage is shared between the two microcore of logic channel
One data RAM - 64 x 16-bit. This memory dedicated to variable storage is shared between the two microcore of a logic channel

Figure 43. Logic channels simplified block diagram

An instruction decode (Instruction_decoder) that manages all the instructions set
The instruction decode includes an internal register multiplexer (Internal_reg_mux) that manages interactions with the memories and the peripheral functions (ALU, counters…)
.A program counter (Uprogram_counter) that manages the code line to be executed by the instruction decoder. This program counter includes:
A program counter register (uPC)
An auxiliary register to store the program counter value when handling subroutine
An Interrupt return register to store the program counter value when handling interrupt.
One 16-bit ALU
Four counters

Figure 44. Microcore block diagram

7.3 Symbols and notation

The symbols and notation shown here are used throughout the manual.

7.3.1 Abbreviations for system resources

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eoc2 – End of count register 2 eoc3 – End of count register 3 eoc4 – End of count register 4 flag – Flag register ctrl_reg – Microcore control register status_bits – Microcore status register spi_data – SPI backdoor register dac_sssc – DAC register same microcore same channel dac_ossc – DAC register other microcore same channel dac_ssoc – DAC register same microcore other channel dac_osoc – DAC register other microcore other channel dac_4h4n – DAC register 4h and 4n spi_add – SPI backdoor address irq_status – Interrupt status bits register ch_rxtx – Other channel communication register uPC – Program counter register r0 – ALU general purpose register 0 r1 – ALU general purpose register 1 r2 – ALU general purpose register 2 r4 – ALU general purpose register 4 ir – ALU immediate register mh – ALU MSB multiplication result register ml – ALU LSB multiplication result register arith_reg – ALU condition register

7.3.2 Operators

+ - Addition – - Subtraction ? - Logical AND + - Logical XOR (inclusive) (+) - Logical OR (exclusive) × - Multiplication ÷ - Division \\ - Negation, logical NOT. One’s complement (invert each bit of a byte or a 16-bit word) => - Transfer <=> - Exchange >> n - Right shift of n bit(s) << n - Left shift of n bit(s)

7.3.3 Definitions

Logic level 1 is the voltage that corresponds to the true (1) state. Logic level 0 is the voltage that corresponds to the false (0) state. Set refers specifically to establishing logic level 1 on a bit or bits. Cleared refers specifically to establishing logic level 0 on a bit or bits. Asserted means that a signal is in active logic state. An active low signal changes from logic level 1 to logic level 0 when asserted, and an active high signal changes from logic level 0 to logic level 1. Negated means that an asserted signal changes logic state. An active low signal changes from logic level 0 to logic level 1 when negated, and an active high signal changes from logic level 1 to logic level 0. RAM is the acronym of random access memory Code RAM is a 1023 x 16-bit RAM area dedicated to the storage of the microcode. Two microcores share one 64 x 16-bit Data RAM area. Data RAM is a 64 x 16-bit RAM area dedicated to the storage of the variables. Two microcores share one 64 x 16-bit Data RAM area. LSB means least significant bit or bits.

MSB means most significant bit or bits. A range of bit locations is referred to by mnemonic and the numbers that define the range. For example, ctrl_reg[15:8] is the high byte of the microcore control register. Microcores are the CPUs integrated in the MC33816. ALU is the acronym of arithmetic logic unit. The ALU is a part of the microcore is charge of executing the mathematic and logic instructions. SPI is the acronym of serial peripheral interface. The SPI is the primary communication interface with the application MCU. MCU is the acronym of microcontroller unit. The main MCU is the main digital device of the electronic module.

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8 CPU features and operation overview

8.1 Introduction

Memory and signals management.
The ALU
Data RAM addressing modes

8.2 Memory and signals management programming model

Table 233. Microcore programming model

8.2.1 Interrupt return register (iret)

The interrupt return register (iret) is a 10-bit register that stores the address of the next instruction to be executed when an interrupt return is issued. The current uPC register value is automatically stored in the iret register each time a software interrupt request is called, by means of the reqi instruction or when an automatic interrupt is issued. The uPC register is loaded with the iret register contents when the iret instruction is called or an automatic software interrupt return is executed. However, according to the returned behavior set with the iconf instruction, the return from the instruction address loaded back into the uPC register can be the microcore Code RAM entry point. This register cannot be directly accessed by the instruction decoder.

8.2.2 Auxiliary register (aux)

The auxiliary register is a 10-bit register holding the address of the next instruction to be executed when a return from subroutine is issued. The return from subroutine address is automatically stored in this aux register each time a jump to a subroutine is called, by means of the jtsf and jtsr instructions. The uPC register is loaded back with the aux register contents when the rfs instruction is executed. Loading the auxiliary register value to register or DRAM is possible by means of the cp and store instructions.

8.2.3 Jump registers (jr1, jr2)

The jump registers 1 and 2 are two 10-bit registers are loaded with the instructions ldjr1, ldjr2, and load previously to execute jumps far or ‘wait table’ setting instructions (cwef, jarf, jcrf, jfbkf, jmpf, jocf, joidf, joslf, jsrf, jstf). This register contains the destination address when a jump far instruction (absolute jump) is executed.

8.2.4 Counter registers (cnt1, cnt2, cnt3, cnt4)

Each microcore has its own set of four independent counters. The four registers are 16-bit registers containing the four counter values. Each time the maximum counter value (0xFFFF) is encountered the counter value is reset (0x0000). The counter value is incremented by 1 independently for each counter at each ck cycle for the counter 1 and 2. A pre-scaling can be applied to the counter 3 and 4 according to the Counter_34_prescaler registers (0x111, 0x131). The counter registers can be loaded with the cp, ldca, ldcd and load instructions. Loading a counter value to register or DRAM is possible by means of cp and store instructions.

8.2.5 End of count registers (eoc1, eoc2, eoc3, eoc4)

Each counter is associated with a 16-bit end of count register. Each time the corresponding counter value reaches the end of count value, the corresponding tcx signal is set high and the counter incrementing is stopped. This tcx signal can be used as a wait table condition. The end of count registers can be loaded with the cp and load instructions. Loading the end of counter value to register or DRAM is also possible by means of cp and store instructions.

8.2.6 Flag register (flag)

The flag register controls the of reading of the 16 flags. Each flag bit issued from each microcore is combined (AND). The dominant level is the logic level 0. The flag states can be read and handled by each microcore with the cp and store instructions. The flag values can be set by using the stf instruction.

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8.2.7 Control register (ctrl_reg)

ctrl_reg[7:0], can only be read by the microcore while the MCU can read or write this slice. This slice can be used as an input communication channel from an external device.
ctrl_reg[15:8] have a configurable behavior by means of the control_register_split registers (0x112 and 0x132). This slice can be used like either the lower slice (ctrl_reg[7:0]) or as the status byte. The ctrl_reg[15:8] can be written bit-by-bit using the stcrl instructions in status mode

8.2.8 Status register (status_bits)

by means of cp and store instructions.

8.2.9 SPI backdoor data register (spi_data)

to the register or DRAM is also possible by means of cp and store instructions.

8.2.10 DAC registers (dac_sssc, dac_ossc, dac_ssoc, dac_osoc, dac_4h4n)

The DAC registers are used to setup the current measurement block DACs. These DACs are affected as shown below.

dac_XsYc[13:8] contains the offset compensation value of the related current measurement block (dac_offset_x).
dac_XsYc[7:0] contains the offset compensation value of the related current measurement block (dac_value_x). The dac_4h4n is unique and can be access by all the microcores. This register is split in two slices:
dac_4h4n[11:8] contains the DAC4neg register value (dac_value_4neg)
dac_4h4n[7:0] contains the DAC4h register value (dac_value_4h) These DACs can be set by using the stdm instruction to setup the access mode. The DAC registers can be loaded with the cp and load instructions. Loading DAC registers values to other registers or DRAM is also possible by means of cp and store instructions.

8.2.11 SPI backdoor address register (spi_add)

Table 234. Current measurement DACs affectation to microcores

8.2.12 Interrupt status register (irq_status)

of cp and store instructions.

8.2.13 Channel exchange data register (ch_rxtx)

8.2.14 Program counter register (uPC)

each time an instruction is fetched.

8.2.15 Data RAM address base register (add_base)

the Ofs operand in the instructions ldcd, load and store. The address base is set by means of the stab instruction.

44.3 ALU programming model

8.2.16 ALU general purpose registers (r0, r1, r2, r3, r4)

The 16-bit ALU general purpose registers are used in most of the logic and arithmetic operations as sources and/or destination registers.

8.2.17 ALU immediate register (ir)

8.2.18 ALU multiplication result registers (mh, ml – reg32)

the two multiplication results registers mh and ml. Table 235. ALU programming model

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The 16-bit ALU general purpose registers mh and ml can be used as ALU general purpose registers.

8.2.19 Condition register (arith_reg)

The 16-bit ALU condition register contains the ALU values condition and the flag issued from the ALU operations. SB - Shift out bit: the last bit shifted out (either left or right) from a shift operation. C – Carry over bit: the carry produced by the last addition or subtraction operation.

‘00’ or ‘10’: no limitation is imposed on addition or subtraction. In case of an overflow, the result should be represented on 17 bits, but only the 16 LSBs of this result are available in the target register. In case of an underflow, the result stored in the target register is ‘65536 - the correct result’, which can always be represented on 16 bits.
’01’: the result of addition or subtraction are saturated between the maximum possible value (if overflow) or the minimum possible value (if underflow). The numbers are considered to be twos-complement format, so saturated between 0x8000 (-32768) and 0x7FFF (+32767).
’11’: the result of addition or subtraction are saturated between the maximum possible value (if overflow) or the minimum possible value (if underflow). The numbers are considered to be unsigned so saturated between 0xFFFF (65535) and 0x0000 (0). MN - Mask result is 0x0000: set if the result of the last mask operation is 0x0000. MM - Mask result is 0xFFFF: set if the result of the last mask operation is 0xFFFF. MO - Multiplication or shift overflow: cleared if the 16 MSBs of the last multiplication or 32-bit shift result are all ‘0’, otherwise set to ‘1’. ML - Multiplication or shift precision loss: cleared if the 16 LSBs of the last multiplication or 32-bit shift result are all ‘0’, otherwise set to ‘1’. RZ - Addition or subtraction result is zero: the result of the last addition or subtraction is zero. RS - Addition or subtraction result is negative: the result of the last addition or subtraction is negative. UU - Unsigned underflow: set if the last addition or subtraction produced underflow, considering the operands as unsigned numbers. UO - Unsigned overflow: set if the last addition or subtraction produced overflow, considering the operands as unsigned numbers. SU - Signed underflow: is set if the last addition or subtraction produced underflow, considering the operands as two’s complement numbers. SO - Signed overflow: set if the last addition or subtraction produced overflow, considering the operands as two’s complement numbers. OD - Operation complete: set by the ALU. The Instruction_decoder can only read it. This bit is set to ‘0’ when a multi-cycle operation is in progress, otherwise is set to ‘1’. If an ALU operation is issued when another operation is in progress (in that case the OD bit is set to ‘0’), the request is neglected.

8.3 Addressing modes

8.3.1 Immediate addressing mode (IM)

no need to pre-load an address in any register as the address is an operand of the instruction. In this example, the data contained into the address 0 of the data RAM is loaded into the ALU register r0. Table 236. Reg32 register

31 Reg32 0

8.3.2 Direct addressing mode (DM)

mode are listed in the section Operand subsets. the corresponding binary value.

8.3.3 Extended addressing mode (EM)

In this example, the jump register jr1 is first loaded with the Code RAM address where the uPC counter is expected to go. The jmpf instruction is executed and the uPC counter is handled such as to jump to the expected Code RAM address.

8.3.4 Indexed addressing modes (XM)

mode, loading the offset value is required prior to use the indexed addressing mode. 1 (+7) is loaded into the ALU register r1. The Ofs operand is set to ofs to enable the indexed Data RAM addressing.

8.3.5 Relative addressing modes (RM)

in range of 16 to +15 lines referenced to the instruction line executed. Table 237. Complement format description

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9 Instruction set overview

9.1 Introduction

This section contains general information about the central processor unit instruction set. Its description is organized by function group.

9.2 Instruction set description

Table 238. 33816 instruction set overview

Table 238. 33816 instruction set overview (continued)

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9.3 Arithmetic logic unit (ALU) instructions

9.3.1 Addition and subtraction instructions

The addition (add, addi) and subtraction (sub, subi) operations allow handling of 16-bit numbers. the load and cp instructions.

C – Carry over bit
RZ - Addition or subtraction result is zero
RS - Addition or subtraction result is negative
UU - Unsigned underflow
UO - Unsigned overflow
SU - Signed underflow
SO - Signed overflow. The addition or subtraction result can be unsigned or signed according to the A1 and A0 bit of the ALU configuration register. arith_reg. The addition and subtraction instructions require one ck clock cycle to be executed. stcrt Set channel communication register stdcctl Set DC-DC control mode stdm Set DAC registers mode access stdrm Set Data RAM read mode steoa Set end of actuation mode stf Set flag stfw Set freewheeling mode stgn Set current measure operational amplifier gain stirq Set IRQB pin sto Set single pre-driver output stoc Set offset compensation store Store register data in Data RAM stos Set pre-driver output shortcuts stslew Set pre-driver output slew-rate mode stsrb Set status register bit sub Two ALU registers subtraction to ALU register subi ALU register subtraction with immediate value to ALU register swap Swap bytes inside ALU register toc2 Integer to two’s complement conversion in ALU register toint Two’s complement to integer conversion in ALU register wait Wait until condition satisfied wrspi SPI write request xor XOR-mask on ALU register with the immediate register to ALU register

9.3.2 Multiplication instructions

The multiplication instructions (mul, muli) operation allows handling of 16-bit numbers. The ALU registers called by the instruction operands must be previously loaded using the load and cp instructions. According to the instruction used one of the ALU register can be multiplied by another ALU register or by a 4-bit immediate value. The result is always stored in the ALU multiplication result register reg32. Overflow, loss of precision, operation complete are reported in the ALU Condition register arith_reg:

MO - Multiplication shift overflow
ML - Multiplication shift precision loss
OD – Operation complete The multiplication instructions require 17 ck clock cycles to be executed. The OD bit of the ALU condition register is low and the result is unavailable until the multiplication is completed. The ALU is not available and the ALU instructions are ignored until the shift operation is completed except for the stal instruction.

9.3.3 Mask instructions

The 33816 ALU offers the possibility to apply logic mask on the data stored into the ALU registers. The ALU register must be previously loaded with the 16–bit source value using the load and cp instructions. According to the instruction, the source value can be ANDed, NOTed (invert), ORed or XORed with the immediate register ir 16-bit value. The result is always available in the 16–bit source register. The mask instructions (and, not, or, xor) require one ck clock cycle to be executed.

9.3.4 Shift instructions

The shift instructions allow single or multiple left and right shifts. This instruction subset allows the following ALU registers shift:

Left shift of the multiplication result register reg32 with a 16-bit ALU register (sh32l)
Right shift of the multiplication result register reg32 with a 16-bit ALU register (sh32r)
Left shift of the multiplication result register reg32 with a 4-bit immediate value (sh32li)
Right shift of the multiplication result register reg32 with a 4-bit immediate value (sh32ri)
Left shift of a 16-bit ALU register with another a 16-bit ALU register (shl)
Right shift of a 16-bit ALU register with another a 16-bit ALU register (shr)
Left shift of a 16-bit ALU register of 8 positions (shl8)
Right shift of a 16-bit ALU register of 8 positions (shr8)
Left shift of a 16-bit ALU register with a 4-bit immediate value (shli)
Right shift of a 16-bit ALU register with a 4-bit immediate value (shri)
Left shift of a 16-bit ALU register containing a signed value with another a 16-bit ALU register (shls)
Right shift of a 16-bit ALU register containing a signed value with another a 16-bit ALU register (shrs)
Left shift of a 16-bit ALU register containing a signed value with a 4-bit immediate value (shlsi)
Right shift of a 16-bit ALU register
containing a signed value with a 4-bit immediate value (shrsi) The shift operation result is always the source register. Overflow, loss of precision, operation complete are reported in the ALU Condition register arith_reg:
SO – Shift out bit
MO - Multiplication shift overflow
ML - Multiplication shift precision loss
OD – Operation complete The number of ck clock cycle required to complete the operation is equal to the shift value. Example: Sh32i 4; In this example 4 ck clock cycles are required to complete the operation. The OC bit of the ALU condition register is high and the result is unavailable until the shift operation is completed. The ALU is not available and the ALU instructions are ignored until the shift operation is completed except for the stal instruction.

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9.3.5 Swap instruction

stored in the source register. The swap operation requires one ck clock cycle to be executed.

9.3.6 Format conversion

an unsigned value (integer) to a signed value (two’s complement) using the toc2 instruction
a signed value (two’s complement) to an unsigned value
(integer) using the toint instruction The Toc2 instruction sets the MSB according to the bit CS - Last conversion sign of the ALU condition register. The CS - Last conversion of the ALU condition register can be changed using the toint instruction. The CS bit is XORed with the existing operand MSB (the operand that contains the value to be handled) or replace by the operand MSB according to the Rst operand. The conversion operations require one ck clock cycle to be executed.

9.4 Configuration instructions

9.4.1 Pre-drivers

9.4.1.1 Pre-driver output shortcuts

lsx_command). The instruction dfsct requires one ck clock cycle to be executed.

9.4.1.2 Pre-driver outputs actuation

doesn’t require a shortcut definition. instruction required a preliminary definition of the shortcuts by means of the dfcsct instruction. The pre-drivers output actuation is possible only the microcore running the related instructions is allow to control the pre-drivers outputs. configuration registers. Both sto and stos instruction require one ck clock cycle to be executed. Table 239. Complement format description

9.4.1.3 Pre-drivers output slew rate

Each of the low-side and high-side pre-drivers output slew rates can be globally forced using the stslew instruction:

Either to their maximum slew rate
or to their normal slew rates individually defined in the Hs_slewrate (0x18E) and Ls_slewrate (0x18F) registers. The stslew instruction requires one ck clock cycle to be executed.

9.4.1.4 End of actuation

The steoa instruction allows to enable the End of Actuation mode. This instruction perform a selective disablement of the bootstrap such as the final decay current slew rate is not disturbed by a ‘parasitic’ bootstrap capacitor loading. The steoa instruction requires one ck clock cycle to be executed.

9.4.1.5 Bias structures

The 33816 provides biasing structures that are used for automatic diagnosis functions. Each high-side driver has an individual pull-up voltage source SRCpux connected to VCC5 voltage. The high-side drivers 2 and 4 have a specific option to increase the voltage source current capability. Each low-side drive, except the low-side pre-driver seven, has an individual pull-down voltage source SRCpdx connected to the device ground. The bias instruction allows switching on or off all the biasing structures of the low-side and high-side together. Note that some or all the bias structure of the low-side and high-side pre-drivers can be switched together at the same time either on or off. That means that, for example, switch on the bias structure for the low-side 1 and switch off the bias structure for the low-side 2 using a unique bias instruction is not possible. In such a case, the bias instruction must be called two times. The bias instruction has an effect in the load biasing structure only if the microcore is allowed to control the corresponding pre-driver. Pre-driver individual control is granted by the Out_acc_ucX_chY registers (0x184, 0x185, 0x186, 0x187).

9.4.1.6 DC-DC mode

Whatever the DC-DC converter regulation mode used (‘Variable frequency’ of ‘Fixed frequency’), the low-side pre-driver seven is periodically directly controlled by the device based on the current measured on the current measurement block four. This automatic mode allows maintaining the current going through the sense resistor between two threshold defined by the DAC4h_value register (0x1A2) and DAC4l_value register (0x1A1). This automatic current regulation mode (asynchronous mode) is activated by means of the stdcctl instruction. When this automatic mode is deactivated (synchronous mode), the low-side pre-driver seven is directly controlled by the microcore.

9.4.2 VDS and VSRC monitoring

9.4.2.1 Comparator voltage threshold

The 33816 provides integrated VDS and VSRC comparators used for driver diagnosis in idle mode. All five high-side drivers integrate individual VDS (differential voltage MOSFET drain to source) and VSRC (differential voltage MOSFET source to ground) comparators to an internal 3-bit DAC value defined in the Vds_threshold_hs register (0x18A) and the Vsrc_threshold_hs register (0x18B). Six of the seven low-side pre-driver drivers integrate individual VDS (differential voltage MOSFET drain to source) comparators to an internal 3-bit DAC value defined in the Vds_threshold_ls_1 and Vds_threshold_ls_2 registers (0x18C, and 0x18D). The VDS monitoring is not implemented into seventh low-side pre-diver. The DAC threshold can be individually set by each microcore using the chth instruction. This instruction requires one clock cycle to be executed.

9.4.2.2 High-side drain reference selection for VDS monitoring

The high-side driver drain for the High-side pre-drivers 2 and 4 can be selected among two voltages reference by means of the slfbk instruction:

The VBATT pin
The VBOOST pin This instruction requires one clock cycle to be executed.

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9.4.3 Freewheeling mode

The 33816 can manage MOSFET in freewheeling mode. High-side and low-side pre-drivers association is fixed.

Manual freewheeling
Automatic freewheeling The mode can be selected by means of the stfw instruction. This instruction requires one clock cycle to be executed.

9.4.4 Current measurement blocks configuration

9.4.4.1 Current comparator output shortcuts

The 33816 provides an enhanced way to manage the current comparator outputs by using shortcuts. The dfcsct instruction requires one clock cycle to be executed.

9.4.4.2 Current feedback

the Curr_block_access_2 (0x189). interrupt trig on the current threshold or any instruction (wait, jump) using the current feedback signals.

9.4.4.3 Operation amplifier gain setting

instruction requires one clock cycle to be executed.

9.4.4.4 Current offset compensation

instruction by any of the four microcores. The stoc instruction requires one clock cycle to be executed. Table 240. Automatic freewheeling pre-driver association Table 241. Correspondence between current comparator output signal and DAC name

9.4.4.5 DAC current feedback shortcut

The 33816 provides the possibility to each of the four microcores to access and modified the DAC value of each of the current measurement block comparator. Prior to change one of the 4 DAC value (dac1_value, dac2_value, dac3_value and dac4l_value) the DAC current shortcut must be set by the dfcsct instruction.

9.4.4.6 DAC register access control

The stdm instruction allows defining and limiting the control (read and write) of:

the DAC value and Offset compensation for each of the four current measurement blocks
the DAC4h value, DAC4neg value and the boost
DAC value The stdm instruction requires one clock cycle to be executed.

9.4.4.7 ADC mode

The current measurement blocks can be optionally configured as 8-bit analog to digital converters by means of the stadc instruction. Each microcore can set all four current measurement blocks. The stadc instruction requires one clock cycle to be executed.

9.5 Digital control

9.5.1 Start-latch registers reset

The rstsl instruction allows to reset the start_latch_ucx register assigned to the microcore executing the instruction. The rstsl instruction requires one clock cycle to be executed.

9.5.2 Data RAM access mode

The stdrm instruction offers the possibility to mask the read access to the data RAM and even to swap the high-byte and low-byte at read (does not affect the data RAM value, only the value in the destination register when reading data RAM). The stdrm instruction requires one clock cycle to be executed.

9.5.3 Data RAM address base

The 33816 offers the possibility to select the address base for the data RAM read or write access by means of the slab instruction. Either the value contained in the add_base register or in the ALU ir register can be used as address base when accessing the data RAM in XM mode. The add_base register value can be set using the stab instruction. This operand of this instruction Is the value to be loaded in the add_base register so no preliminary register loading is required. Both slab and stab instructions require one clock cycle to be executed.

9.5.4 Flags control

The bit of the 33816 internal flag bus can individual be set high or low using the stf instruction. The stf instruction requires one clock cycle to be executed.

9.5.5 Status and control registers

9.5.5.1 Registers reset

The control registers (Ctrl_reg_ucX (0x101, 0x102, 0x121, 0x122)), status registers (Status_reg_ucX (0x105, 0x106, 0x125, 0x126)) and automatic diagnosis registers (Err_ucXchY (0x162 to 0x169)) can be reset individually or in group by means of the rstreg instruction. The rstreg instruction requires one clock cycle to be executed.

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9.5.5.2 Control and status registers

The control and status registers bits can be individually set using the stcrb and stsrb instructions. Both stcrb and stsrb instructions require one clock cycle to be executed.

9.5.6 ALU configuration register

The ALU of each microcore can be set up individually to handle the saturation behavior when the ALU handles a number exceeding the destination register capacity. This configuration is possible using the stal instruction. The stal instruction requires one clock cycle to be executed.

9.5.7 Channel communication

Each microcore has access to a specific register ch_rxtx dedicated to information sharing between each microcore. The stcrt instruction set which microcore ch_rxtx register is being accessed. Example: The Uc0Ch1 executes the following code cp ir rxtx; The Uc0Ch1 executes the following code stcrt ossc; cp rxtx sr; In this example, the value contained in the ir register of the microcore Uc0Ch1 is copied in the ch_rxtx register of the same microcore. Then the microcore Uc1Ch1 accesses the ch_rxtx register of the microcore Uc0Ch1 and copies the value in its own status register. The stcrt instruction requires one clock cycle to be executed.

9.5.8 Interrupt configuration

Before calling, the microcode interruption routine must be configured using the iconf instruction. This instruction is required to determine the automatic return from interrupt behavior.:

The code execution continues where the main routine was stopped when the automatic return from interrupt conditions are satisfied.
The code restarts from the entry point defined in the Uc0_entry_point(0x10A, 0x12A) and Uc1_entry_point(0x10B, 0x12B) register when the automatic return from interrupt conditions are satisfied.
The microcore ignores any automatic return from interrupt. The automatic return from interrupt conditions are determined by the iret_en bit of the Driver_config register (0x1C5):
If iert_en is set to ‘0’, the automatic return from interrupt is generated when the pre-drivers are enabled after disable conditions.
If iret_en is set to ‘1’, the automatic return from interrupt is generated when the Driver_status register (0x1D2) is cleared. In this case, the Driver_status register must be reset on read by setting the driver_enable_rb bit in the Reset_behavior register (0x1CE). The iconf requires one clock cycle to be executed.

9.5.9 SPI handling instructions

The 33816 provides a way for each microcode to directly access the SPI registers through the SPI backdoor. Read and write access can be performed, but is limited by the lock function of each SPI register. Prior any SPI backdoor data transfer, the SPI address must be specified by means of the slsa instruction. This instruction sets the address in the spi_add register. The SPI write data must be loaded into the spi_data register using load or cp instructions. The SPI write can then be executed using the wrspi instruction. A SPI backdoor read action can be executed by means of the rdspi instruction. The result is available in the spi_data register. The slsa requires one clock cycle to be executed while the rdspi and wrspi instructions require two clock cycles.

9.5.10 External interrupt request

The 33816 IRQB pin has the primary function to report a hardware interrupt to the application MCU. The logic level of this pin can be directly managed by microcode using the stirq instruction. This function overwrites the current state of the IRQB pin. The stirq requires one clock cycle to be executed.

9.6 Diagnosis Instructions

The 33816 integrates an automatic diagnosis feature that can trigger a diagnosis interrupt. The interrupt is triggered according to:

the VDS feedback signal (hsx_vds_fbk) state, the VSrc feedback signal (hsx_src_fbk) state and pre-driver command (hsx_command) state for each of the high-side pre-driver.
the VDS feedback signal (lsx_vds_fbk) state and pre-driver command (hsx_command) state for each of the low-side pre-driver. The automatic diagnosis triggers an interrupt according to the combination of the above signals. This combination for the high-side pre- drivers can be set through the Hsx_diag_config_2 (0x154, 0x157, 0x115A, 0x15D, 0x160) registers. The combination for the low-side pre-drivers can be set through Lsx_diag_config2 (0x141, 0x144, 0x147, 0x14A, 0x14D, 0x150) registers. The automatic diagnosis can be enabled by two methods:
Either by direct enablement for a single (endiag instruction) or all (endiaga instruction) the VDS and VSRC monitoring.
Or by using the pre-driver shortcuts with the endiags instruction. In that case, the pre-driver shortcuts must be previously configured. The start address of the automatic diagnosis interrupt is set in the Diag_routine_address register (0x10C and 0x12C). The diagnosis enablement is effective for the pre-driver output configured to the driven by the related microcore. Pre-driver individual control is granted by the Out_acc_ucX_chY registers (0x184, 0x185, 0x186, 0x187). The biasing circuitry must be configured to make the S_HSx and D_LSx pin biased in idle phases. The diagnosis instructions (endiag, endiaga, endiags) require one clock cycle to be executed.

9.7 Flow control instructions

9.7.1 Subroutines

The 33816 instruction set offers the possibility to manage execution of subroutines. The subroutine is called using the jtsf and jtsr instructions and the current main routine uPC value is automatically stored in the aux register. Only one level of subroutine is supported inside or outside an interrupt.

9.7.1.1 Return from subroutine

Return from subroutine is generated by means of the rfs instruction. In this case, the address stored into the aux register is transferred back to the uPC register to allow continuing the main routine execution.

9.7.2 Interrupt

The 33816 instruction set offers the possibility to manage interrupts. Three kinds of interrupts are available:

automatic diagnosis interrupt (higher priority)
driver disabled interrupt
software interrupt (lower priority) The automatic diagnosis interrupt and driver disable interrupts are triggered according to the corresponding configuration registers:
Err_ucXchY registers (0x162 to 0x169) for the automatic diagnosis interrupt
Driver_status register (0x1D2) for the disabled drivers interrupt. The software interrupt is called by means of the reqi instruction. When an interrupt is requested, the uPC register value is automatically stored in the iret register. Only one level of interrupt is supported. The other interrupts requested during the initial interrupt execution are queued and are executed in series, or the queue can be cleared according to the Rst operand of the iret instruction.

9.7.2.1 Return from interrupt

The return from interrupt is atomically executed or requested by means of the iret instruction. Two return from interrupt behavior are possible when using iret instruction:

The address stored into the iret register is transferred back to the uPC register to allow continuing the main routine execution.
The execution restarts from the entry point address. If a wait or a conditional jump instruction was interrupted, the return address is defined, restoring the status of the feedbacks at the moment the interrupt. The iret instruction requires one clock cycle to be executed.

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9.7.3 Jumps

Branch instructions cause execution flow to change when specific pre-conditions exist. The 33816 instruction set includes:

Conditional jump relative
Conditional jump far
Unconditional jump relative
Unconditional jump far Conditional jump instructions have two execution cases:
The jump condition is satisfied, and a change of flow takes place.
The jump condition is not satisfied, and no change of flow occurs.

9.7.3.1 Conditional jump relative

The ’not-taken’ case for conditional jump relative is simple. Since the instructions consist of a single word containing the 6-bit relative destination address, the execution continues with the next instruction. The ’taken’ case for conditional jump relative instructions require that the uPC register be refilled so execution can continue at a new address. First, the effective address of the destination is calculated using the relative offset in the operand, then the address is loaded into the program counter (uPC). The conditional jump relative instructions (jarr, jcrr, jfbkr, jocr, joidr, joslr, jsrr, jtsr) require one ck clock cycle to be executed in both cases.

9.7.3.2 Conditional jump far

The execution of the conditional jump far instructions requires two steps. The first step consists of loading the destination address in the 10-bit jump register jr1 or jr2 with the load and cp instructions. The conditional jump far instruction can then be executed. The two instruction step can be consecutive. The jump instruction is not destructive for the jump register. The data that contains the jump registers can be reused by another instruction. The ’not-taken’ case for conditional jump relative is simple. Since the destination is preloaded into the jump registers and the jump register selection is an instruction operand, the execution continues with the next instruction. In the ’taken’ case, the effective address of jump is calculated using the10-bit absolute address previously loaded in the appropriate jump register. The suitable jump register is selected by an instruction operand among the two jump registers jr1 and jr2. The address is loaded into the program counter (uPC) and the execution can continue at a new address. The conditional jump far instructions themselves (jarf, jcrf, jfbkf, jocf, joidf, joslf, jsrf, jtsf) require one ck clock cycle to be executed in both cases.

9.7.3.3 Unconditional jump relative

The unconditional jump relative instructions require that the uPC register be refilled so execution can continue at a new address. First, the effective address of the destination is calculated using the relative offset in the instruction. The address is loaded into the program counter (uPC). The execution continues at the new address. The unconditional jump relative instruction jmpr requires one ck clock cycle to be executed.

9.7.3.4 Unconditional jump far

The execution of the unconditional jump far instructions require two steps. The first step consists of loading the destination address in the 10-bit jump register jr1 or jr2 with the load and cp instructions. The unconditional jump far instruction can then be executed. The two instruction steps can be consecutive. The jump instruction is not destructive for the jump register. The data that contain the jumps registers can be reused by another instruction. The effective address of jump is calculated using the 10-bit absolute address previously loaded in the appropriate jump register. The suitable jump register is selected by an instruction operand among the two jump registers jr1 and jr2. The address is loaded into the program counter (uPC) and the execution can continue at a new address. The unconditional jump far instruction jmpf requires one ck clock cycle to be executed.

9.7.3.5 Wait table

An enable flag (one bit). This flag is set by the wait instruction to select if the condition code specified in the entry is enabled.
A condition code. (6-bit) This code specifies the condition to be tested.
A destination address (10-bit). This address specifies the address of the Code RAM to which the program execution should jump if the wait condition is satisfied. Regardless of the addressing mode (DM or EM), the address stored in the wait table is always the physical address of the destination.

Figure 45. Wait table management diagram of the cwef and cwer instructions. reconfigured but can be modified, added, or removed. During the wait instruction execution the uPC register is not incremented until one of the condition defined in the wait table is satisfied. wait instruction is executed again.

9.8 Load instructions

The instruction load is used to load any registers (including ALU registers) from data RAM.
The instruction store is used to copy any registers (including ALU registers) to the data RAM.
The instruction cp is used to copy any registers (including ALU registers) to any registers (including ALU registers).
The instructions ldca and ldcd are dedicated to the counter registers loading (eoc1, eoc2, eoc3, eoc4). The ldca instruction also controls of the pre-driver outputs.
The instructions ldirh and ldirh are used for loading the ALU multiplication result register reg32.
The instructions ldjr1 and ldjr2 are dedicated for loading the jump registers jr1 and jr2. The load instructions (load, store, cp, ldca, ldcd, ldir, ldirh, ldjr1, ldjr2) require one ck clock cycle to be executed.

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10 Instruction glossary

10.1 Introduction

This section is a comprehensive reference to the MC33816 instruction set.

10.2 Glossary information

The glossary contains an entry for each assembler mnemonic, in alphabetic order. Figure 46 is a representation of a glossary page. Figure 46. Description of glossary page

10.3 Operand subsets

This section details the pre-defined microcore register subsets used by instruction operand in direct addressing mode (DM).

10.3.1 AluReg subset

10.3.2 AluGprIrReg subset

Table 242. Operand subset overview AluReg Register designator for registers r0, r1, r2, r3, r5, r5, ir, mh, and ml. AluGprIrReg Register designator for registers r0, r1, r2, r3, r5, r5, and ir. Table 243. AluReg subset description Table 244. AluGpsIrReg subset description

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10.3.3 UcReg subset

Table 245. UcReg subset description

ar is the ALU arithmetic register arith_reg
cr is the control register ctrl_reg
sr is the status bits register status_bits
irq is the interrupt status register irq_status
rxtx is the other channel communication register ch_rxtx

10.3.4 JpReg subset

10.4 Glossary

This subsection contains an entry for each assembler mnemonic, in alphabetic order. Sums the value contained in the op1 register with the value contained in op2 register and places the result in the res register.

C – Carry over bit
RZ - Addition or subtraction result is zero
RS - Addition or subtraction result is negative
UU - Unsigned underflow
UO - Unsigned overflow
SU - Signed underflow
SO - Signed overflow Instruction format:

Table 246. JrReg subset description

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Operation: (Source) + Immediate value => (Destination); Carry => C Assembler syntax: addi op1 Imm res; Description: Sums the value contained in the op1 register with the immediate value Imm and places the result in the res register. Operands: op1 – One of the register listed in the operand subset AluReg Imm –The Imm 4-bit immediate data register res – One of the register listed in the operand subset AluReg Condition register:

C – Carry over bit
RZ - Addition or subtraction result is zero
RS - Addition or subtraction result is negative
UU - Unsigned underflow
UO - Unsigned overflow
SU - Signed underflow
SO - Signed overflow Instruction format: addi ALU register addition with immediate value to ALU register addi 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 1 1 0 res Imm op1

Operation: (Source)? Immediate register => (Source) Assembler syntax: and op1; Description: Applies the AND-mask contained into the Ir register to the value contained in the op1 register and places the result in the op1 register. The initial data stored in the op1 register is loss. Operands: op1 – One of the register listed in the operand subset AluReg Ir –The ALU immediate register Condition register:

MN - Mask result is 0x0000
MM - Mask result is 0xFFFF Instruction format: and AND-mask on ALU register with the immediate register to ALU register and 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 0 1 1 1 0 1 1 0 0 1 op1

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Assembler syntax: bias BiasTarget Ctrl; Description: Enables/disables individually the high-side and low-side 33816 load bias structures. This operation is successful only if the microcore has the right to drive the output related to the selected bias structure. The drive right is granted by setting the related bits in the Out_acc_ucX_chY (0x184, 0x185, 0x186, 0x187) configuration registers. Operands: BiasTarget – Operand that defines the bias structure(s) to be selected Ctrl – Operand that define the bias structure(s) state to be applied Instruction format: bias Enable high-side and low-side bias bias Operand label Operand description Operand binary value hs1 Select HS1 bias structure 0000 hs2 Select HS2 bias structure 0001 hs3 Select HS3 bias structure 0010 hs4 Select HS4 bias structure 0011 hs5 Select HS5 bias structure 0100 ls1 Select LS1 bias structure 0101 ls2 Select LS2 bias structure 0110 ls3 Select LS3 bias structure 0111 ls4 Select LS4 bias structure 1000 ls5 Select LS5 bias structure 1001 ls6 Select LS6 bias structure 1100 hs2s Select HS2 strong bias structure 1010 hs4s Select HS4 strong bias structure 1011 all Select all high-side and low-side pre-driver bias structures including strong bias structures 1101 hs Select all high-side pre-driver bias structures including strong bias structures 1110 ls Select all low-side pre-driver bias structures 1111 Operand label Operand description Operand binary value off Bias structure disable 0 on Bias structure enable 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 1 0 1 1 0 0 0 1 Ctrl BiasTarget

Assembler syntax: chth SelFbk ThLevel; Description: Changes the thresholds for the selected VDS and VSRC feedback comparator. This operation is successful only if the microcore has the right to drive the output related to selected threshold. The configuration of the high-side pre-driver Vsrc thresholds is also impacted by the bootstrap initialization mode. Operands: SelFbk – Operand that defines the threshold comparator to be selected chth Change VDS and VSRC threshold chth Operand label Operand description Operand binary value hs1v High-side pre-driver 1 vds feedback 0000 hs1s High-side pre-driver 1 src feedback 0001 hs2v High-side pre-driver 2 vds feedback 0010 hs2s High-side pre-driver 2 src feedback 0011 hs3v High-side pre-driver 3 vds feedback 0100 hs3s High-side pre-driver 3 src feedback 0101 hs4v High-side pre-driver 4 vds feedback 0110 hs4s High-side pre-driver 4 src feedback 0111 hs5v High-side pre-driver 5 vds feedback 1000 hs5s High-side pre-driver 5 src feedback 1001 ls1v Low-side pre-driver 1 vds feedback 1010 ls2v Low-side pre-driver 2 vds feedback 1011 ls3v Low-side pre-driver 3 vds feedback 1100 ls4v Low-side pre-driver 4 vds feedback 1101 ls5v Low-side pre-driver 5 vds feedback 1110 ls6v Low-side pre-driver 6 vds feedback 1111

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ThLevel – Operand that defines threshold level to be applied Instruction format: Operand label Operand description Operand binary value lv1 First level 000 lv2 Second level 001 lv3 Third level 010 lv4 Fourth level 011 lv5 Fifth level 100 lv6 Sixth level 101 lv7 Seventh level 110 lv8 Height level 111 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 0 1 1 1 1 1 SelFbk ThLevel

Assembler syntax: cp op1 op2; Description: Copies the value from the source register op1 into the destination register op2. Operands: op1 – One of the register listed in the operand subset UcReg op2 – One of the register listed in the operand subset UcReg Instruction format: cp Copy source register data in destination register cp 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 1 op1 op2 0 0 0

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Assembler syntax: cwef op1 Cond Entry ; Description: Initializes or changes a row in the wait table used by the wait instruction The wait table is a five-row/two-column table:

The first column contains the wait conditions.
The second column contains the jump register name op1 that contains the absolute destination addresses. Up to 5 conditions may be checked at the same time. When the condition Cond is satisfied and the entry is enabled, the execution continues at the corresponding destination jump address. Operands: op1 – One of the register listed in the operand subset JpReg Cond – Operand that defines the condition to be satisfied to enable the jump far cwef Create wait table entry far cwef Operand label Operand description Operand binary value _f0 Flag 0 low 000000 _f1 Flag 1 low 000001 _f2 Flag 2 low 000010 _f3 Flag 3 low 000011 _f4 Flag 4 low 000100 _f5 Flag 5 low 000101 _f6 Flag 6 low 000110 _f7 Flag 7 low 000111 _f8 Flag 8 low 001000 _f9 Flag 9 low 001001 _f10 Flag 10 low 001010 _f11 Flag 11 low 001011 _f12 Flag 12 low 001100 _f13 Flag 13 low 001101 _f14 Flag 14 low 001110 _f15 Flag 15 low 001111 f0 Flag 0 high 010000 f1 Flag 1 high 010001 f2 Flag 2 high 010010 f3 Flag 3 high 010011 f4 Flag 4 high 010100 f5 Flag 5 high 010101

tc1 Terminal count 1 100000 tc2 Terminal count 2 100001 tc3 Terminal count 3 100010 tc4 Terminal count 4 100011 _start Start low 100100 start Start high 100101 _sc1v Shortcut1 VDS feedback low 100110 _sc2v Shortcut2 VDS feedback low 100111 _sc3v Shortcut3 VDS feedback low 101000 _sc1s Shortcut1 source feedback low 101001 _sc2s Shortcut2 source feedback low 101010 _sc3s Shortcut3 source feedback low 101011 sc1v Shortcut1 VDS feedback high 101100 sc2v Shortcut2 VDS feedback high 101101 sc3v Shortcut3 VDS feedback high 101110 opd Instruction request to ALU executed 101111 vb Boost voltage high 110000 _vb Boost voltage low 110001 cur1 Current feedback 1 high 110010 cur2 Current feedback 2 high 110011 cur3 Current feedback 3 high 110100 cur4l Current feedback 4l high 110101 cur4h Current feedback 4h high 110110 cur4n Current feedback 4n high 110111 _cur1 Current feedback 1 low 111000 _cur2 Current feedback 2 low 111001 _cur3 Current feedback 3 low 111010 _cur4l Current feedback 4l low 111011 _cur4h Current feedback 4h low 111100 _cur4n Current feedback 4n low 111101 Operand label Operand description Operand binary value

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Entry – Operand that defines the wait table row number Instruction format: ocur Own current feedback high 111110 _ocur Own current feedback low 111111 Operand label Operand description Operand binary value row1 Wait table row 1 000 row2 Wait table row 2 001 row3 Wait table row 3 010 row4 Wait table row 4 011 row5 Wait table row 5 100 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 1 0 0 op1 Entry Cond Operand label Operand description Operand binary value

Assembler syntax: cwer Dest Cond Entry ; Description: Initializes or changes a row in the wait table used by the wait instruction The wait table is a five-row/two-column table:

The first column contains the wait conditions
The second column contains the destination jump addresses Up to five conditions may be checked at the same time. When the condition Cond is satisfied and the entry is enabled, the execution continues at the correspondent destination jump address. The jump is relative to the instruction Code RAM location. The destination address is the actual instruction Code RAM location added to the Dest operand value. This 5-bit value is a two’s complemented number. The MSB is the sign. So Dest operand value is in the range of {-16, 15}. Operands: Dest – Operand that defines the 5-bit relative destination address in the range of {-16, 15} Cond – Operand that defines the condition to be satisfied to enable the jump far cwer Create wait table entry relative cwer Operand label Operand description Operand binary value _f0 Flag 0 low 000000 _f1 Flag 1 low 000001 _f2 Flag 2 low 000010 _f3 Flag 3 low 000011 _f4 Flag 4 low 000100 _f5 Flag 5 low 000101 _f6 Flag 6 low 000110 _f7 Flag 7 low 000111 _f8 Flag 8 low 001000 _f9 Flag 9 low 001001 _f10 Flag 10 low 001010 _f11 Flag 11 low 001011 _f12 Flag 12 low 001100 _f13 Flag 13 low 001101 _f14 Flag 14 low 001110 _f15 Flag 15 low 001111 f0 Flag 0 high 010000 f1 Flag 1 high 010001 f2 Flag 2 high 010010

207 NXP Semiconductors

tc1 Terminal count 1 100000 tc2 Terminal count 2 100001 tc3 Terminal count 3 100010 tc4 Terminal count 4 100011 _start Start low 100100 start Start high 100101 _sc1v Shortcut1 VDS feedback low 100110 _sc2v Shortcut2 VDS feedback low 100111 _sc3v Shortcut3 VDS feedback low 101000 _sc1s Shortcut1 source feedback low 101001 _sc2s Shortcut2 source feedback low 101010 _sc3s Shortcut3 source feedback low 101011 sc1v Shortcut1 VDS feedback high 101100 sc2v Shortcut2 VDS feedback high 101101 sc3v Shortcut3 VDS feedback high 101110 opd Instruction request to ALU executed 101111 vb Boost voltage high 110000 _vb Boost voltage low 110001 cur1 Current feedback 1 high 110010 cur2 Current feedback 2 high 110011 cur3 Current feedback 3 high 110100 cur4l Current feedback 4l high 110101 cur4h Current feedback 4h high 110110 cur4n Current feedback 4n high 110111 _cur1 Current feedback 1 low 111000 _cur2 Current feedback 2 low 111001 _cur3 Current feedback 3 low 111010 Operand label Operand description Operand binary value

Entry – Operand that defines the wait table row number Instruction format: _cur4l Current feedback 4l low 111011 _cur4h Current feedback 4h low 111100 _cur4n Current feedback 4n low 111101 ocur Own current feedback high 111110 _ocur Own current feedback low 111111 Operand label Operand description Operand binary value row1 Wait table row 1 000 row2 Wait table row 2 001 row3 Wait table row 3 010 row4 Wait table row 4 011 row5 Wait table row 5 100 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 Dest Entry Cond Operand label Operand description Operand binary value

209 NXP Semiconductors

Assembler syntax: dfcsct ShrtCur ; Description: Defines the shortcut for the current feedback. This shortcut defines the connection between the physical current feedback input of the microcore and the current measurement block. At reset the default shortcut setting is the following: Operands: ShrtCur – Operand that defines to which current measurement block is dedicated the shortcut. Instruction format: dfcsct Define current shortcut dfcsct Shortcut Uc0Ch1 Uc1Ch1 Uc0Ch2 Uc1Ch2 ShrtCur dac1 dac2 dac3 dac4l Operand label Operand description Operand binary value dac1 DAC1 is selected as current shortcut 00 dac2 DAC2 is selected as current shortcut 01 dac3 DAC3 is selected as current shortcut 10 dac4l DAC4l is selected as current shortcut 11 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 1 0 1 0 1 0 1 1 1 1 0 ShrtCur

Assembler syntax: dfsct Shrt1 Shrt2 Shrt3; Description: Defines three shortcuts applied to three pre-drivers output among the set of all the low-side and high-side pre-drivers. The shortcuts table defines the connection between the physical outputs of the microcore and the external outputs pin (G_HSx and G_LSx) driving the MOSFETs. At reset the default shortcut setting is the following: Operands: Shrt1, Shrt2, and Shrt3 – Operands that define to which pre-driver the shortcut is dedicated Instruction format: dfsct Define pre-driver output shortcuts dfsct Shortcut Channel 1 Channel 2 microcore 0 microcore 1 microcore 0 microcore 1 Shrt1 hs1 hs2 hs3 hs4 Shrt2 ls1 ls2 ls3 ls4 Shrt3 ls5 ls6 ls7 hs5 Operand label Operand description Operand binary value hs1 High-side pre-driver 1 0000 hs2 High-side pre-driver 2 0001 hs3 High-side pre-driver 3 0010 hs4 High-side pre-driver 4 0011 hs5 High-side pre-driver 5 0100 ls1 Low-side pre-driver 1 0101 ls2 Low-side pre-driver 2 0110 ls3 Low-side pre-driver 3 0111 ls4 Low-side pre-driver 4 1000 ls5 Low-side pre-driver 5 1001 ls6 Low-side pre-driver 6 1010 ls7 Low-side pre-driver 7 1011 undef Undefined shortcut 1100 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 Shrt1 Shrt2 Shrt3 1 1

211 NXP Semiconductors

Assembler syntax: endiag SelFbk Diag; Description: Enables or disables the automatic diagnosis for a single output and the related interrupt procedure for error handling. This operation is successful only if the microcore has the right to drive the related outputs. The drive right is granted by setting the related bits in the Out_acc_ucX_chY (0x184, 0x185, 0x186, 0x187) configuration registers. At reset the automatic diagnosis is disabled. Operands: SelFbk – Operand that defines the monitored pre-driver and VDS or VSRC feedback. Diag – Operand that defines the diagnosis status Instruction format: endiag Enable automatic diagnosis endiag Operand label Operand description Operand binary value hs1v High-side pre-driver 1 vds feedback 0000 hs1s High-side pre-driver 1 src feedback 0001 hs2v High-side pre-driver 2 vds feedback 0010 hs2s High-side pre-driver 2 src feedback 0011 hs3v High-side pre-driver 3 vds feedback 0100 hs3s High-side pre-driver 3 src feedback 0101 hs4v High-side pre-driver 4 vds feedback 0110 hs4s High-side pre-driver 4 src feedback 0111 hs5v High-side pre-driver 5 vds feedback 1000 hs5s High-side pre-driver 5 src feedback 1001 ls1v Low-side pre-driver 1 vds feedback 1010 ls2v Low-side pre-driver 2 vds feedback 1011 ls3v Low-side pre-driver 3 vds feedback 1100 ls4v Low-side pre-driver 4 vds feedback 1101 ls5v Low-side pre-driver 5 vds feedback 1110 ls6v Low-side pre-driver 6 vds feedback 1111 Operand label Operand description Operand binary value diagoff Automatic diagnosis disable 0 diagon Automatic diagnosis enable 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 1 0 1 0 0 1 1 0 SelFbk Diag

Assembler syntax: endiaga Diag; Description: Enables or disables the automatic diagnosis for all the pre-drivers output that the microcore is configured to drive. If automatic diagnosis condition is satisfied, the related interrupt procedure for error handling is triggered. The operation is successful only if the microcore has the right to drive the related outputs. The drive right is granted by setting the related bits in the Out_acc_ucX_chY (0x184, 0x185, 0x186, 0x187) configuration registers. At reset the automatic diagnosis is disabled. Operands: Diag – Operand that defines the diagnosis status Instruction format: endiaga Enable all automatic diagnosis endiaga Operand label Operand description Operand binary value diagoff Automatic diagnosis disable 0 diagon Automatic diagnosis enable 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 1 0 1 1 0 0 0 0 0 0 0 0 Diag

213 NXP Semiconductors

Assembler syntax: endiags Diag_sh1_vds Diag_sh1_src Diag_sh2_vds Diag_sh3_vds; Description: Enables or disables the automatic for the outputs selected via shortcuts Four events can be monitored in parallel:

the drain-source voltage on shortcut1 output (Diag_sh1_vds)
the source voltage on shortcut1 output (Diag_sh1_src)
the drain-source voltage on shortcut2 output (Diag_sh2_vds)
the drain-source voltage on shortcut3 output (Diag_sh3_vds) If automatic diagnosis condition is satisfied, the related interrupt procedure for error handling is triggered. The shortcuts are defined with the dfsct instruction. The operation is successful only if the microcore has the right to drive the related outputs. The drive right is granted by setting the related bits in the Out_acc_ucX_chY (0x184, 0x185, 0x186, 0x187) configuration registers. At reset the automatic diagnosis are disabled. Operands: Diag _sh1_vds, Diag_sh2_vds and Diag_sh3_vds – Operands corresponding to the shortcuts related to VDS to be monitored. Diag _sh1_src – Operand corresponding to the shortcuts related to VSRC to be monitored. Instruction format: endiags Enable automatic diagnosis shortcuts endiags Operand label Operand description Operand binary value keep No changes, maintains the previous setting 00 NA Not applicable 01 off Automatic diagnosis disabled 10 on Automatic diagnosis enabled 11 Operand label Operand description Operand binary value keep No changes, maintains the previous setting 00 NA Not applicable 01 off Automatic diagnosis disabled 10 on Automatic diagnosis enabled 11 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 0 0 1 1 0 Diag _sh1_vds Diag _sh1_src Diag_sh2_vds Diag_sh3_vds

Assembler syntax: iconf Conf; Description: Configures the microcore to be enabled by the interrupt return request. The automatic interrupt return request is issued from, according to the iret_en bit state of the Driver_config register (0x1C5):

Re-enabling the drivers in case the disabled drivers interrupt.
Reading or writing the Driver_status register (0x1D2) in case of automatic diagnosis interrupt. This register must be configured such as to be ‘reset at read’. The reset value is none. Operands: Conf – Operand that defines interrupt behaviors Instruction format: iconf Interrupt configuration iconf Operand label Operand description Operand binary value none The microcore ignores all automatic interrupt return request 00 NA Not applicable 01 continue When an interrupt return request is received, the code execution continues from where it was interrupted 10 restart When an interrupt return request is received, the code execution restarts from the entry point 11 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 1 0 1 1 0 0 0 0 0 0 1 Conf

215 NXP Semiconductors

Assembler syntax: iret Type Rst; Description: Ends the interrupt routine and clears the microcore Interrupt_status register (0x1D4). Operands: Type – Operand that defines how the program counter (uPC) is handled returning from the interrupt routine Rst – Operand that defines if the pending interrupts queue is clear when the iret instruction is executed Instruction format: iret Return from interrupt iret Operand label Operand description Operand binary value continue The execution is resumed at the address stored in the 10 LSBs of the Interrupt_status register (0x1D4) (iret microcore register) 0 restart The execution is resumed at the address stored in the Ucx_entry_point registers (0x10A, 0x10B, 0x12A, 0x12B) 1 Operand label Operand description Operand binary value _rst The pending interrupts queue is not cleared 0 rst The pending interrupts queue is cleared 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 1 0 1 0 1 1 0 0 1 1 0 Type Rst

Assembler syntax: jarf op1 BitSel; Description: Configures the jump to absolute location on arithmetic condition. If the condition defined by the BitSel operand is satisfied, the program counter (uPC) is handled such as the next executed instruction is located into the destination address contained in one of the jump registers. The destination address defined by the op1 register is any of the absolute Code RAM location. Operands: op1 – One of the register listed in the operand subset JpReg BitSel – Operand that defines the arithmetic condition that trigs the jump. The arithmetic conditions are stored into the ALU condition register Instruction format: jarf Jump far on arithmetic condition jarf Operand label Operand description Operand binary value opd OD -Operation complete 0000 ovs SO - Overflow with signed operands 0001 uns SU - Underflow with signed operands 0010 ovu UO - Overflow with unsigned operands 0011 unu UU - Underflow with unsigned operands 0100 sgn CS - Sign of result 0101 zero RZ - Result is zero 0110 mloss ML - Multiply precision loss 0111 mover MO - Multiply overflow 1000 all1 MM - Result of mask operation is 0xFFFF 1001 all0 MN - Result of mask operation is 0x0000 1010 aritl A0 1011 arith A1 1100 carry C - Carry 1101 conv CS - Conversion sign 1110 csh SB - Carry on shift operation 1111 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 1 1 0 1 BitSel op1 0 1 0 1

217 NXP Semiconductors

Assembler syntax: jarr Dest BitSel; Description: Configures jump to relative location on arithmetic condition. If the condition defined by the BitSel operand is satisfied, the program counter (uPC) is handled such as the next executed instruction is relative destination address. The jump is relative to the instruction Code RAM location. The destination address is the actual instruction Code RAM location added to the Dest operand value. This 5-bit value is a two’s complemented number. The MSB is the sign. So Dest operand value is in the range of {-16, 15}. Operands: Dest – Operand that defines the 5-bit relative destination address in the range of {-16, 15}. BitSel – Operand that defines the arithmetic condition that trigs the jump. The arithmetic conditions are stored into the ALU condition register Instruction format: jarr Jump relative on arithmetic condition jarr Operand label Operand description Operand binary value opd OD -Operation complete 0000 ovs SO - Overflow with signed operands 0001 uns SU - Underflow with signed operands 0010 ovu UO - Overflow with unsigned operands 0011 unu UU - Underflow with unsigned operands 0100 sgn CS - Sign of result 0101 zero RZ - Result is zero 0110 mloss ML - Multiply precision loss 0111 mover MO - Multiply overflow 1000 all1 MM - Result of mask operation is 0xFFFF 1001 all0 MN - Result of mask operation is 0x0000 1010 aritl A0 1011 arith A1 1100 carry C - Carry 1101 conv CS - Conversion sign 1110 csh SB - Carry on shift operation 1111 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 0 0 1 0 BitSel Dest

Assembler syntax: jcrf op1 CrSel Pol; Description: Configures the jump to absolute location on control register condition. If the condition defined by the CrSel operand is satisfied according to the polarity Pol, the program counter (uPC) is handled such as the next executed instruction is located into the destination address contained in one of the jump registers. The destination address defined by the op1 register is any of the absolute Code RAM location. Operands: op1 – One of the register listed in the operand subset JpReg CrSel – Operand that defines the control register condition (Ctrl_reg_uc0 and Ctrl_reg_uc1 registers (0x101, 0x102, 0x121, 0x122)) that trigs the jump Pol – Operand that defines the active polarity for the selected bit Instruction format: jcrf Jump far on control register condition jcrf Operand label Operand description Operand binary value b0 Control register bit 0 (LSB) 0000 b1 Control register bit 1 0001 b2 Control register bit 2 0010 b3 Control register bit 3 0011 b4 Control register bit 4 0100 b5 Control register bit 5 0101 b6 Control register bit 6 0110 b7 Control register bit 7 0111 b8 Control register bit 8 1000 b9 Control register bit 9 1001 b10 Control register bit 10 1010 b11 Control register bit 11 1011 b12 Control register bit 12 1100 b13 Control register bit 13 1101 b14 Control register bit 14 1110 b15 Control register bit 15 (MSB) 1111 Operand Label Operand description Operand binary value low Active condition if the selected bit is ‘0’ 0 high Active condition if the selected bit is ‘1’ 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 1 1 1 Pol CrSel op1 0 1 0 0

219 NXP Semiconductors

Assembler syntax: jcrr Dest CrSel Pol; Description: Configures the jump to relative location on control register condition. If the condition defined by the CrSel operand is satisfied according to the polarity Pol, the program counter (uPC) is handled such as the next executed instruction is relative destination address The jump is relative to the instruction Code RAM location. The destination address is the actual instruction Code RAM location added to the Dest operand value. This 5-bit value is a two’s complemented number. The MSB is the sign. So Dest operand value is in the range of {-16, 15}. Operands: Dest – Operand that defines the 5-bit relative destination address in the range of {-16, 15}. CrSel – Operand that defines the control register condition (Ctrl_reg_uc0 and Ctrl_reg_uc1 registers (0x101, 0x102, 0x121, 0x122) ) that trigs the jump. jcrr Jump relative on control register condition jcrr Operand label Operand description Operand binary value b0 Control register bit 0 (LSB) 0000 b1 Control register bit 1 0001 b2 Control register bit 2 0010 b3 Control register bit 3 0011 b4 Control register bit 4 0100 b5 Control register bit 5 0101 b6 Control register bit 6 0110 b7 Control register bit 7 0111 b8 Control register bit 8 1000 b9 Control register bit 9 1001 b10 Control register bit 10 1010 b11 Control register bit 11 1011 b12 Control register bit 12 1100 b13 Control register bit 13 1101 b14 Control register bit 14 1110 b15 Control register bit 15 (MSB) 1111

Pol – Operand that defines the active polarity for the selected bit Instruction format: Operand label Operand description Operand binary value low Active condition if the selected bit is ‘0’ 0 high Active condition if the selected bit is ‘1’ 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 0 0 0 Pol CrSel Dest

221 NXP Semiconductors

Assembler syntax: jfbkf op1 SelFbk Pol; Description: Configures the jump to absolute location on feedback condition. If the condition defined by the SelFbk operand is satisfied according to the polarity Pol, the program counter (uPC) is handled such as the next executed instruction is located into the destination address contained in one of the jump registers. The destination address defined by the op1 register is any of the absolute Code RAM location. Operands: op1 – One of the register listed in the operand subset JpReg SelFbk – Operand that defines the feedback signal condition Pol – Operand that defines the active polarity for the selected bit Instruction format: jfbkf Jump far on feedback condition jfbkf Operand label Operand description Operand binary value hs1v High-side pre-driver 1 VDS feedback 0000 hs1s High-side pre-driver 1 VSRC feedback 0001 hs2v High-side pre-driver 2 VDS feedback 0010 hs2s High-side pre-driver 2 VSRC feedback 0011 hs3v High-side pre-driver 3 VDS feedback 0100 hs3s High-side pre-driver 3 VSRC feedback 0101 hs4v High-side pre-driver 4 VDS feedback 0110 hs4s High-side pre-driver 4 VSRC feedback 0111 hs5v High-side pre-driver 5 VDS feedback 1000 hs5s High-side pre-driver 5 VSRC feedback 1001 ls1v Low-side pre-driver 1 VDS feedback 1010 ls2v Low-side pre-driver 2 VDS feedback 1011 ls3v Low-side pre-driver 3 VDS feedback 1100 ls4v Low-side pre-driver 4 VDS feedback 1101 ls5v Low-side pre-driver 5 VDS feedback 1110 ls6v Low-side pre-driver 6 VDS feedback 1111 Operand label Operand description Operand binary value low Active condition if the selected bit is ‘0’ 0 high Active condition if the selected bit is ‘1’ 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 1 1 0 SelFbk Pol op1 0 1 0 0

Assembler syntax: jfbkr Dest SelFbk Pol; Description: Configures the jump to relative location on feedback condition. If the condition defined by the SelFbk operand is satisfied according to the polarity Pol, the program counter (uPC) is handled such as the next executed instruction is relative destination address. The jump is relative to the instruction Code RAM location. The destination address is the actual instruction Code RAM location added to the Dest operand value. This 5-bit value is a two’s complemented number. The MSB is the sign. So Dest operand value is in the range of {-16, 15}. Operands: Dest – Operand that defines the 5-bit relative destination address in the range of {-16, 15}. SelFbk – Operand that defines the feedback signal condition jfbkr Jump relative on feedback condition jfbkr Operand label Operand description Operand binary value hs1v High-side pre-driver 1 VDS feedback 0000 hs1s High-side pre-driver 1 VSRC feedback 0001 hs2v High-side pre-driver 2 VDS feedback 0010 hs2s High-side pre-driver 2 VSRC feedback 0011 hs3v High-side pre-driver 3 VDS feedback 0100 hs3s High-side pre-driver 3 VSRC feedback 0101 hs4v High-side pre-driver 4 VDS feedback 0110 hs4s High-side pre-driver 4 VSRC feedback 0111 hs5v High-side pre-driver 5 VDS feedback 1000 hs5s High-side pre-driver 5 VSRC feedback 1001 ls1v Low-side pre-driver 1 VDS feedback 1010 ls2v Low-side pre-driver 2 VDS feedback 1011 ls3v Low-side pre-driver 3 VDS feedback 1100 ls4v Low-side pre-driver 4 VDS feedback 1101 ls5v Low-side pre-driver 5 VDS feedback 1110 ls6v Low-side pre-driver 6 VDS feedback 1111

223 NXP Semiconductors

Assembler syntax: jmpf op1; Description: Configures the unconditional jump. The destination address defined in one of the jump registers defined by the operand op1. The destination address is any of the absolute Code RAM location. Operands: op1 – One of the register listed in the operand subset JpReg Instruction format: jmpf Unconditional jump far jmpf 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 1 1 0 0 1 1 0 1 0 op1 1 0 1

225 NXP Semiconductors

Assembler syntax: jmpr Dest SelFbk Pol; Description: Configures the unconditional jump to relative location. The jump is relative to the instruction Code RAM location. The destination address is the actual instruction Code RAM location added to the Dest operand value. This 5-bit value is a two’s complemented number. The MSB is the sign. So Dest operand value is in the range of {-16, 15}. Operands: Dest – Operand that defines the 5-bit relative destination address in the range of {-16, 15}. Instruction format: jmpr Unconditional jump relative jmpr 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 0 1 1 1 1 0 0 0 Dest

Assembler syntax: jocf op1 Cond; Description: Configures the jump to absolute location on condition. If the condition defined by the Cond operand is satisfied, the program counter (uPC) is handled such as the next executed instruction is located into the destination address contained in one of the jump registers. The destination address defined by the op1 register is any of the absolute Code RAM location. Operands: op1 – One of the register listed in the operand subset JpReg Cond – Operand that defines the condition to be satisfied to enable the jump far jocf Jump far on condition jocf Operand label Operand description Operand binary value _f0 Flag 0 low 000000 _f1 Flag 1 low 000001 _f2 Flag 2 low 000010 _f3 Flag 3 low 000011 _f4 Flag 4 low 000100 _f5 Flag 5 low 000101 _f6 Flag 6 low 000110 _f7 Flag 7 low 000111 _f8 Flag 8 low 001000 _f9 Flag 9 low 001001 _f10 Flag 10 low 001010 _f11 Flag 11 low 001011 _f12 Flag 12 low 001100 _f13 Flag 13 low 001101 _f14 Flag 14 low 001110 _f15 Flag 15 low 001111 f0 Flag 0 high 010000 f1 Flag 1 high 010001 f2 Flag 2 high 010010 f3 Flag 3 high 010011 f4 Flag 4 high 010100 f5 Flag 5 high 010101 f6 Flag 6 high 010110 f7 Flag 7 high 010111 f8 Flag 8 high 011000

227 NXP Semiconductors

tc1 Terminal count 1 100000 tc2 Terminal count 2 100001 tc3 Terminal count 3 100010 tc4 Terminal count 4 100011 _start Start low 100100 start Start high 100101 _sc1v Shortcut1 VDS feedback low 100110 _sc2v Shortcut2 VDS feedback low 100111 _sc3v Shortcut3 VDS feedback low 101000 _sc1s Shortcut1 source feedback low 101001 _sc2s Shortcut2 source feedback low 101010 _sc3s Shortcut3 source feedback low 101011 sc1v Shortcut1 VDS feedback high 101100 sc2v Shortcut2 VDS feedback high 101101 sc3v Shortcut3 VDS feedback high 101110 opd Instruction request to ALU executed 101111 vb Boost voltage high 110000 _vb Boost voltage low 110001 cur1 Current feedback 1 high 110010 cur2 Current feedback 2 high 110011 cur3 Current feedback 3 high 110100 cur4l Current feedback 4l high 110101 cur4h Current feedback 4h high 110110 cur4n Current feedback 4n high 110111 _cur1 Current feedback 1 low 111000 _cur2 Current feedback 2 low 111001 _cur3 Current feedback 3 low 111010 _cur4l Current feedback 4l low 111011 _cur4h Current feedback 4h low 111100 _cur4n Current feedback 4n low 111101 ocur Own current feedback high 111110 _ocur Own current feedback low 111111 Operand label Operand description Operand binary value

Instruction format: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 1 1 Cond op1 0 0 0 0

229 NXP Semiconductors

Assembler syntax: jocr Dest Cond; Description: Configures the jump to relative location on condition. If the condition defined by the Cond operand is satisfied, the program counter (uPC) is handled such as the next executed instruction is relative destination address. The jump is relative to the instruction Code RAM location. The destination address is the actual instruction Code RAM location added to the Dest operand value. This 5-bit value is a two’s complemented number. The MSB is the sign. So Dest operand value is in the range of {-16, 15}. Operands: Dest – Operand that defines the 5-bit relative destination address in the range of {-16, 15}. Cond – Operand that defines the condition to be satisfied to enable the relative jump jocr Jump relative on condition jocr Operand label Operand description Operand binary value _f0 Flag 0 low 000000 _f1 Flag 1 low 000001 _f2 Flag 2 low 000010 _f3 Flag 3 low 000011 _f4 Flag 4 low 000100 _f5 Flag 5 low 000101 _f6 Flag 6 low 000110 _f7 Flag 7 low 000111 _f8 Flag 8 low 001000 _f9 Flag 9 low 001001 _f10 Flag 10 low 001010 _f11 Flag 11 low 001011 _f12 Flag 12 low 001100 _f13 Flag 13 low 001101 _f14 Flag 14 low 001110 _f15 Flag 15 low 001111 f0 Flag 0 high 010000 f1 Flag 1 high 010001 f2 Flag 2 high 010010 f3 Flag 3 high 010011 f4 Flag 4 high 010100 f5 Flag 5 high 010101 f6 Flag 6 high 010110

231 NXP Semiconductors

Instruction format: ocur Own current feedback high 111110 _ocur Own current feedback low 111111 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 Cond Dest Operand label Operand description Operand binary value

Assembler syntax: joidf op1 UcSel; Description: Configures the jump to absolute location on microcore identifier condition. If the condition defined by the UcSel operand is satisfied, the program counter (uPC) is handled such as the next executed instruction is located into the destination address contained in one of the jump registers. The destination address defined by the op1 register is any of the absolute Code RAM location. Operands: op1 – One of the register listed in the operand subset JpReg UcSel – Operand that defines the microcore identifier condition Instruction format: joidf Jump far on microcore condition joidf Operand label Operand description Operand binary value seq0 The microcore 0 is the current microcore 0 seq1 The microcore 1 is the current microcore 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 1 1 0 0 1 1 0 0 UcSel op1 1 0 1

233 NXP Semiconductors

Assembler syntax: joidr Dest UcSel; Description: Configures the jump to relative location on condition. If the condition defined by the UcSel operand is satisfied, the program counter (uPC) is handled such as the next executed instruction is relative destination address. The jump is relative to the instruction Code RAM location. The destination address is the actual instruction Code RAM location added to the Dest operand value. This 5-bit value is a two’s complemented number. The MSB is the sign. So Dest operand value is in the range of {-16, 15}. Operands: Dest – Operand that defines the 5-bit relative destination address in the range of {-16, 15}. UcSel – Operand that defines the microcore identifier condition Instruction format: joidr Jump relative on microcore condition joidr Operand label Operand description Operand binary value seq0 The microcore 0 is the current microcore 0 seq1 The microcore 1 is the current microcore 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 0 1 1 1 1 0 1 UcSel Dest

Assembler syntax: joslf op1 StSel; Description: Configures the jump to absolute location on condition. If the condition defined by the StSel operand is satisfied, the program counter (uPC) is handled such as the next executed instruction is located into the destination address contained in one of the jump registers. The destination address defined by the op1 register is any of the absolute Code RAM location. Operands: op1 – One of the register listed in the operand subset JpReg StSel – Operand that defines the start condition to be satisfied to enable the jump far joslf Jump far on start condition joslf Operand label Operand description Operand binary value none No start latched 000000 start1 Start 1 latched 000001 start2 Start 2 latched 000010 start12 Start 1,2 latched 000011 start3 Start 3 latched 000100 start13 Start 1,3 latched 000101 start23 Start 2,3 latched 000110 start123 Start 1,2,3 latched 000111 start4 Start 4 latched 001000 start14 Start 1,4 latched 001001 start24 Start 2,4 latched 001010 start124 Start 1,2,4 latched 001011 start34 Start 3,4 latched 001100 start134 Start 1,3,4 latched 001101 start234 Start 2,3,4 latched 001110 start1234 Start 1,2,3,4 latched 001111 start5 Start 5 latched 010000 start15 Start 1,5 latched 010001 start25 Start 2,5 latched 010010 start125 Start 1,2,5 latched 010011 start35 Start 3,5 latched 010100 start135 Start 1,3,5 latched 010101 start235 Start 2,3,5 latched 010110 start1235 Start 1,2,3,5 latched 010111 start45 Start 4,5 latched 011000

235 NXP Semiconductors

start145 Start 1,4,5 latched 011001 start245 Start 2,4,5 latched 011010 start1245 Start 1,2,4,5 latched 011011 start345 Start 3,4,5 latched 011100 start1345 Start 1,3,4,5 latched 011101 start2345 Start 2,3,4,5 latched 011110 start12345 Start 1,2,3,4,5 latched 011111 start6 Start 6 latched 100000 start16 Start 1,6 latched 100001 start26 Start 2,6 latched 100010 start126 Start 1,2,6 latched 100011 start36 Start 3,6 latched 100100 start136 Start 1,3,6 latched 100101 start236 Start 2,3,6 latched 100110 start1236 Start 1,2,3,6 latched 100111 start46 Start 4,6 latched 101000 start146 Start 1,4,6 latched 101001 start246 Start 2,4,6 latched 101010 start1246 Start 1,2,4,6 latched 101011 start346 Start 3,4,6 latched 101100 start1346 Start 1,3,4,6 latched 101101 start2346 Start 2,3,4,6 latched 101110 start12346 Start 1,2,3,4,6 latched 101111 start56 Start 5,6 latched 110000 start156 Start 1,5,6 latched 110001 start256 Start 2,5,6 latched 110010 start1256 Start 1,2,5,6 latched 110011 start356 Start 3,5,6 latched 110100 start1356 Start 1,3,5,6 latched 110101 start2356 Start 2,3,5,6 latched 110110 start12356 Start 1,2,3,5,6 latched 110111 start456 Start 4,5,6 latched 111000 start1456 Start 1,4,5,6 latched 111001 start2456 Start 2,4,5,6 latched 111010 start12456 Start 1,2,4,5,6 latched 111011 start3456 Start 3,4,5,6 latched 111100 start13456 Start 1,3,4,5,6 latched 111101 start23456 Start 2,3,4,5,6 latched 111110 start123456 Start 1,2,3,4,5,6 latched 111111 Operand label Operand description Operand binary value

Instruction format: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 1 1 StSel op1 0 0 0 1

237 NXP Semiconductors

Assembler syntax: joslr Dest StSel; Description: Configures the jump to relative location on condition. If the condition defined by the StSel operand is satisfied, the program counter (uPC) is handled such as the next executed instruction is relative destination address. The jump is relative to the instruction Code RAM location. The destination address is the actual instruction Code RAM location added to the Dest operand value. This 5-bit value is a two’s complemented number. The MSB is the sign. So Dest operand value is in the range of {-16, 15}. Operands: Dest – Operand that defines the 5-bit relative destination address in the range of {-16, 15}. StSel – Operand that defines the start condition to be satisfied to enable the jump far joslr Jump relative on start condition joslr Operand label Operand description Operand binary value none No start latched 000000 start1 Start 1 latched 000001 start2 Start 2 latched 000010 start12 Start 1,2 latched 000011 start3 Start 3 latched 000100 start13 Start 1,3 latched 000101 start23 Start 2,3 latched 000110 start123 Start 1,2,3 latched 000111 start4 Start 4 latched 001000 start14 Start 1,4 latched 001001 start24 Start 2,4 latched 001010 start124 Start 1,2,4 latched 001011 start34 Start 3,4 latched 001100 start134 Start 1,3,4 latched 001101 start234 Start 2,3,4 latched 001110 start1234 Start 1,2,3,4 latched 001111 start5 Start 5 latched 010000 start15 Start 1,5 latched 010001 start25 Start 2,5 latched 010010 start125 Start 1,2,5 latched 010011 start35 Start 3,5 latched 010100 start135 Start 1,3,5 latched 010101 start235 Start 2,3,5 latched 010110 start1235 Start 1,2,3,5 latched 010111

start45 Start 4,5 latched 011000 start145 Start 1,4,5 latched 011001 start245 Start 2,4,5 latched 011010 start1245 Start 1,2,4,5 latched 011011 start345 Start 3,4,5 latched 011100 start1345 Start 1,3,4,5 latched 011101 start2345 Start 2,3,4,5 latched 011110 start12345 Start 1,2,3,4,5 latched 011111 start6 Start 6 latched 100000 start16 Start 1,6 latched 100001 start26 Start 2,6 latched 100010 start126 Start 1,2,6 latched 100011 start36 Start 3,6 latched 100100 start136 Start 1,3,6 latched 100101 start236 Start 2,3,6 latched 100110 start1236 Start 1,2,3,6 latched 100111 start46 Start 4,6 latched 101000 start146 Start 1,4,6 latched 101001 start246 Start 2,4,6 latched 101010 start1246 Start 1,2,4,6 latched 101011 start346 Start 3,4,6 latched 101100 start1346 Start 1,3,4,6 latched 101101 start2346 Start 2,3,4,6 latched 101110 start12346 Start 1,2,3,4,6 latched 101111 start56 Start 5,6 latched 110000 start156 Start 1,5,6 latched 110001 start256 Start 2,5,6 latched 110010 start1256 Start 1,2,5,6 latched 110011 start356 Start 3,5,6 latched 110100 start1356 Start 1,3,5,6 latched 110101 start2356 Start 2,3,5,6 latched 110110 start12356 Start 1,2,3,5,6 latched 110111 start456 Start 4,5,6 latched 111000 start1456 Start 1,4,5,6 latched 111001 start2456 Start 2,4,5,6 latched 111010 start12456 Start 1,2,4,5,6 latched 111011 start3456 Start 3,4,5,6 latched 111100 start13456 Start 1,3,4,5,6 latched 111101 start23456 Start 2,3,4,5,6 latched 111110 start123456 Start 1,2,3,4,5,6 latched 111111 Operand label Operand description Operand binary value

239 NXP Semiconductors

Instruction format: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 1 StSel Dest

Assembler syntax: jsrf op1 SrSel Pol; Description: Configures the jump to absolute location on status register condition. If the condition defined by the SrSel operand is satisfied according to the polarity Pol, the program counter (uPC) is handled such as the next executed instruction is located into the destination address contained in one of the jump registers. The destination address defined by the op1 register is any of the absolute Code RAM location. Operands: op1 – One of the register listed in the operand subset JpReg SrSel – Operand that defines the status register condition (Ctrl_reg_uc0 and Ctrl_reg_uc1 registers (0x101, 0x102, 0x121, 0x122) ) that trigs the jump Pol – Operand that defines the active polarity for the selected bit jsrf Jump far on status register bit condition jsrf Operand label Operand description Operand binary value b0 Status register bit 0 (LSB) 0000 b1 Status register bit 1 0001 b2 Status register bit 2 0010 b3 Status register bit 3 0011 b4 Status register bit 4 0100 b5 Status register bit 5 0101 b6 Status register bit 6 0110 b7 Status register bit 7 0111 b8 Status register bit 8 1000 b9 Status register bit 9 1001 b10 Status register bit 10 1010 b11 Status register bit 11 1011 b12 Status register bit 12 1100 b13 Status register bit 13 1101 b14 Status register bit 14 1110 b15 Status register bit 15 (MSB) 1111 Operand label Operand description Operand binary value low Active condition if the selected bit is ‘0’ 0 high Active condition if the selected bit is ‘1’ 1

241 NXP Semiconductors

Instruction format: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 1 1 1 Pol SrSel op1 0 1 0 1

Assembler syntax: jsrr Dest SrSel Pol; Description: Configures the jump to the relative location of the status register condition. If the condition defined by the SrSel operand is satisfied according to the polarity Pol, the program counter (uPC) is handled such as the next executed instruction is relative destination address. The jump is relative to the instruction Code RAM location. The destination address is the actual instruction Code RAM location added to the Dest operand value. This 5-bit value is a two’s complemented number. The MSB is the sign. So Dest operand value is in the range of {-16, 15}. Operands: Dest – Operand that defines the 5-bit relative destination address in the range of {-16, 15}. SrSel – Operand that defines the status register condition (Ctrl_reg_uc0 and Ctrl_reg_uc1 registers (0x101, 0x102, 0x121, 0x122) ) that trigs the jump jsrr Jump relative on status register bit condition jsrr Operand label Operand description Operand binary value b0 Status register bit 0 (LSB) 0000 b1 Status register bit 1 0001 b2 Status register bit 2 0010 b3 Status register bit 3 0011 b4 Status register bit 4 0100 b5 Status register bit 5 0101 b6 Status register bit 6 0110 b7 Status register bit 7 0111 b8 Status register bit 8 1000 b9 Status register bit 9 1001 b10 Status register bit 10 1010 b11 Status register bit 11 1011 b12 Status register bit 12 1100 b13 Status register bit 13 1101 b14 Status register bit 14 1110 b15 Status register bit 15 (MSB) 1111

243 NXP Semiconductors

Assembler syntax: jtsf op1; Description: Configures the jump on subroutine to absolute location The program counter (uPC) is handled such as the next executed instruction is located into the destination address contained in one of the jump registers. When jump to subroutine is called, the current program counter value (uPC) is stored into the auxiliary register (aux) to handle end of subroutine return. The destination address defined by the op1 register is any of the absolute Code RAM location. Operands: op1 – One of the register listed in the operand subset JpReg Instruction format: jtsf Jump far to subroutine jtsf 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 1 1 0 0 1 1 0 1 1 op1 1 0 1

245 NXP Semiconductors

Assembler syntax: jtsr Dest ; Description: Configures the jump to subroutine to relative location on condition. When jump to subroutine is called, the current program counter value (uPC) is stored into the auxiliary register (aux) to handle end of subroutine return. The jump is relative to the instruction Code RAM location. The destination address is the actual instruction Code RAM location added to the Dest operand value. This 5-bit value is a two’s complemented number. The MSB is the sign. So Dest operand value is in the range of {-16, 15}. Operands: Dest – Operand that defines the 5-bit relative destination address in the range of {-16, 15}. Instruction format: jtsr Jump relative to subroutine jtsr 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 0 1 1 1 1 0 0 1 Dest

Assembler syntax: ldca Rst Sh1 Sh2 op1 Eoc; Description: Loads one of the four end of count register (eoc1, eoc2, eoc3, eoc4) defined by the operand Eoc with a value stored in a ALU register op1 and sets the outputs defined by the shortcut Sh1 and Sh2. Operands: Rst – Operand (Boolean) that defines if the selected counter value must be reset to zero or must be unchanged. Sh1, Sh2– Operands that set the first and second shortcuts related to the corresponding outputs. The output shortcuts are defined using the dfsct instruction. 1 – One of the register listed in the operand subset AluReg. Eoc– Operand that defines the end of count targeted among the four counters available. Instruction format: ldca Load counter from ALU register and set outputs ldca Operand label Operand description Operand binary value _rst The counter value is maintained, only the end of counter is modified 0 rst The counter value is reset to zero and start to count from zero 1 Operand label Operand description Operand binary value keep No changes, maintains the previous setting 00 off Disable the output 01 on Enable the output 10 toggle Reverse the previous setting 11 Operand label Operand description Operand binary value c1 Register eoc1 00 c2 Register eoc2 01 c3 Register eoc3 10 c4 Register eoc4 11 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 1 Rst Sh1 Sh2 Eoc op1 1 0 0

247 NXP Semiconductors

Assembler syntax: ldcd Rst Ofs Sh1 Sh2 Dram Eoc; Description: Loads one of the four end of count register (eoc1, eoc2, eoc3, eoc4) Eoc with a value stored in the 6-bit Data RAM address Dram and sets the outputs defined by the shortcut Sh1 and Sh2. The operand Dram can be identified with a univocal label. The compiler automatically substitutes the ‘define’ label (if used) with the suitable Data RAM address. The Data RAM address is accessed according to the Boolean operand Ofs using the: Immediate addressing mode (IM). Indexed addressing mode (XM). In that case address base is added the address Dram. The address base is set using the stab instructions. Operands: Rst – Operand (Boolean) that defines if the selected counter value must be reset to zero or must be unchanged. Ofs– Operands that set Data RAM addressing mode Sh1, Sh2– Operands that set the first and second shortcuts related to the corresponding outputs. The output shortcuts are defined using the dfsct instruction. Dram– Operand that defines the 6-bit DRAM address Eoc– Operand that defines the end of count targeted among the four counters available. ldcd Load counter from Data RAM and set outputs ldcd Operand label Operand description Operand binary value _rst The counter value is maintained, only the end of counter is modified 0 rst The counter value is reset to zero and start to count from zero 1 Operand label Operand description Operand binary value _ofs Data RAM immediate addressing mode (IM) 0 ofs Data RAM indexed addressing mode (XM) 1 Operand label Operand Description Operand binary value keep No changes, maintains the previous setting 00 off Disable the output 01 on Enable the output 10 toggle Reverse the previous setting 11

Instruction format: Operand Label Operand Description Operand Binary Value c1 Register eoc1 00 c2 Register eoc2 01 c3 Register eoc3 10 c4 Register eoc4 11 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 Ofs Rst Sh1 Sh2 Eoc Dram

249 NXP Semiconductors

Assembler syntax: ldirh Value8 RstH; Description: Loads the Value8 data in the 8-MSB of the immediate register (ir). Operands: Value8 – Operand that defines the 8-bit value to be loading into the 8-MSB of the immediate register RstH– Operand (Boolean) that defines if set to zero the 8-MSB of the immediate register Instruction format: ldirh Load 8-MSB ir register ldirh Operand label Operand description Operand binary value _rst No change on the ir[15:8] 0 rst Set the Zero the ir[15:8] 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 1 1 RstH Value8 1 1

Assembler syntax: ldirl Value8 RstL; Description: Loads the Value8 data in the 8-LSB of the immediate register (ir). Operands: Value8 – Operand that defines the 8-bit value to be loading into the 8-MSB of the immediate register RstL– Operand (Boolean) that defines if set to zero the 8-LSB of the immediate register Instruction format: ldirl Load 8-LSB ir register ldirl Operand label Operand description Operand binary value _rst No change on the ir[7:0] 0 rst Set the Zero the ir[7/0] 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 1 1 RstL Value8 1 0

251 NXP Semiconductors

Assembler syntax: ldjr1 Value10; Description: Loads the Value10 data in the 16-bit jump register 1 (jr1). The operand Value10 can be replaced by a label. The compiler automatically substitutes the label (if used) with the defined value. Operands: Value10 – Operand that defines the 10-bit value to be loading into the jump register 1 Instruction format: ldjr1 Load jump register 1 ldjr1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 0 0 Value10 0 0

Assembler syntax: ldjr2 Value10; Description: Loads the Value10 data in the 16-bit jump register 2 (jr2). The operand Value10 can be replaced by a label. The compiler automatically substitutes the label (if used) with the defined value. Operands: Value10 – Operand that defines the 10-bit value to be loading into the jump register 2 Instruction format: ldjr2 Load jump register 2 ldjr2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 0 1 Value10 0 0

253 NXP Semiconductors

Assembler syntax: load Dram op1 Ofs; Description: Loads the data from the Data RAM at the address defined by the Dram operand to the op1 register. The operand Dram can be identified with a univocal label. The compiler automatically substitutes the ‘define’ label (if used) with the suitable Data RAM address. The Data RAM address is accessed according to the Boolean operand Ofs using the: Immediate addressing mode (IM). Indexed addressing mode (XM). In that case, address base is added the address Dram. The address base is set using the stab instructions. Operands: Dram– Operand that defines the 6-bit Data RAM address op1 – One of the register listed in the operand subset UcReg Ofs– Operands that set data RAM addressing mode Instruction format: load Load data from Data RAM to register load Operand label Operand description Operand binary value _ofs Data RAM immediate addressing mode (IM) 0 ofs Data RAM indexed addressing mode (XM) 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 Dram op1 Ofs 1 0

Operation: (Source1) x (Source2) => (Destination) Assembler syntax: mul op1 op2; Description: Multiplies the value contained in the op1 register with the value contained in op2 register and places the result in the reg32 register. The reg32 register is the concatenation of the multiplication result registers mh and ml: mh contains the 16-MSB ml contains the 16-MSB The multiplication requires 17 ck clock cycles to be completed. Operands: op1 – One of the register listed in the operand subset AluGprIrReg op2 – One of the register listed in the operand subset AluGprIrReg Condition register: MO - Multiplication shift overflow ML - Multiplication shift precision loss OD –Operation complete Instruction format: mul Two ALU registers multiplication to reg32 mul 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 0 1 1 0 1 1 0 op2 op1

255 NXP Semiconductors

Operation: (Source) x Immediate value => (Destination) Assembler syntax: muli op1 Imm; Description: Multiplies the value contained in the op1 register with the immediate value Imm and places the result in the reg32 register. The reg32 register is the concatenation of the multiplication result registers mh and ml: mh contains the 16-MSB ml contains the 16-LSB The multiplication requires 17 ck clock cycles to be completed. Operands: op1 – One of the register listed in the operand subset AluGprIrReg Imm –The Imm 4-bit immediate data register Condition register: MO - Multiplication shift overflow ML - Multiplication shift precision loss OD –Operation complete Instruction format: muli ALU register multiplication with immediate value to reg32 muli 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 0 0 1 1 1 0 Imm op1

Operation: (Source) \\ => (Source) Assembler syntax: not op1; Description: Inverts each bit of the op1 register and places the result in the op1 register. Operands: op1 – One of the register listed in the operand subset AluReg Condition register: MN – Mask result is 0x0000 MM - Mask result is 0xFFFF Instruction format: not Invert ALU register bits not 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 0 1 1 1 0 1 1 0 1 1 op1

257 NXP Semiconductors

Operation: (Source) (+) Immediate register => (Source) Assembler syntax: or op1 ir; Description: Applies the OR-mask stored in the Immediate Register (ir) to the op1 register and places the result in the op1 register. Operands: op1 – One of the register listed in the operand subset AluReg Condition register: MN – Mask result is 0x0000 MM - Mask result is 0xFFFF Instruction format: or OR mask on ALU register with immediate register to ALU register or 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 0 1 1 1 0 1 1 0 0 0 op1

Assembler syntax: rdspi; Description: Requests an SPI backdoor read. The address must previously be defined in the SPI address register spi_add. The rdspi instruction requires 2 ck cycle to complete operation. The SPI address register must not be changed on the following instruction, otherwise the operation fails and the read data is dummy. Instruction format: rdspi SPI read request rdspi 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 1 0 1 0 1 0 1 0 0 0 0 0 0

259 NXP Semiconductors

Assembler syntax: reqi id; Description: Requests a software interrupt At the reqi instruction execution, the Code RAM address currently executed is stored in the interrupt return register corresponding to the

10 LSB of the Ucx_irq_status register (0x10F and 0x12F)

By default, the return address of an interrupt is the line where the code was interrupted. In the case of a software interrupt, the return address is the address where the code was interrupted + 1. A software interrupt must not be interrupted. Operands: Id – Operand that defines the 2-bit software interrupt request identifier. Instruction format: reqi Software interrupt request reqi 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 1 0 1 0 1 1 0 0 0 1 0 Id

Assembler syntax: rfs; Description: Ends a subroutine. To continue the code execution, the program counter (uPC) is loaded with the content of the auxiliary register (aux) that was automatically updated when the subroutine was called with the instructions jtsf and jtsr. Instruction format: rfs Return from subroutine rfs 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 1 0 1 0 1 1 0 0 1 1 1 0 0

261 NXP Semiconductors

Assembler syntax: rstreg TgtBit; Description: Resets single or multiple registers defined by the TgtBit operand. The instruction reset bits issued from SPI registers including:

control register Ctrl_reg_ucX (0x101, 0x102, 0x121, 0x122)
status register Status_reg_ucX registers (0x105, 0x106, 0x125, 0x126)
automatic diagnosis register Err_ucXchY (0x162 to 0x169) Operands: TgtBit– Operands that defines the registers to be reset. Instruction format: rstreg Registers reset rstreg Operand label Operand description Operand binary value sr Reset status bits of the status registers 000 cr Reset control register 001 sr_diag_halt Reset status bits, automatic diagnosis register and re-enables the possibility to generate automatic diagnosis interrupts 010 all Reset status bits, control register, automatic diagnosis register and re- enables the possibility to generate automatic diagnosis interrupts 011 diag_halt Reset automatic diagnosis register and re-enables the possibility to generate automatic diagnosis interrupts 100 sr_cr Reset status bits and control register 101 sr_halt Reset status bits and re-enables the possibility to generate automatic diagnosis interrupts 110 halt Re-enables the possibility to generate automatic diagnosis interrupts 111 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 1 0 1 0 1 0 1 0 0 1 TgtBit

Assembler syntax: rstsl; Description: Resets the Start_latch_ucx register. This instruction is active only if the Smart Latch Mode is enabled. The smart mode register can be activated by setting the bits smart_start_uc0 and smart_start_uc1 of the Start_config_reg registers (0x104, 0x124). Instruction format: rstsl Start-latch registers reset rstsl 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 1 0 1 0 1 1 0 0 1 1 1 0 1

263 NXP Semiconductors

Operation: (Source) << factor => (Source) Assembler syntax: sh32l op1; Description: Shifts the reg32 register left. The shift is single or multiple according to the op1 register value (factor). The reg32 register is the concatenation of the multiplication result registers mh and ml:

mh contains the 16-MSB
ml contains the 16-LSB To be completed, the shift operation requires a number of ck clock cycles corresponding to the op1 register value. Operands: op1 – One of the register listed in the operand subset AluReg Condition register: SB – Shift out bit MO - Multiplication shift overflow Instruction format: sh32l Shift left multiplication result register sh32l 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 1 1 0 0 1 0 1 op1 1 0 1

Operation: (Source) << Immediate value => (Source) Assembler syntax: sh32li Imm; Description: Shifts the reg32 register left. The shift is single or multiple according to the immediate value (factor). The reg32 register is the concatenation of the multiplication result registers mh and ml:

mh contains the 16-MSB
ml contains the 16-LSB To be completed, the shift operation requires a number of ck clock cycles corresponding to the immediate value. Operands: Imm –The Imm 4-bit immediate data register Condition register: SB – Shift out bit MO - Multiplication shift overflow Instruction format: sh32li Shift left multiplication result register of immediate value sh32li 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 1 1 0 0 0 1 Imm 1 0 1

265 NXP Semiconductors

Operation: (Source) >> factor => (Source) Assembler syntax: sh32r op1; Description: Shifts the reg32 register right. The right shift is single or multiple according to the op1 register value (factor). The reg32 register is the concatenation of the multiplication result registers mh and ml:

mh contains the 16-MSB
ml contains the 16-LSB To be completed, the shift operation requires a number of ck clock cycles corresponding to the op1 register value. Operands: op1 – One of the register listed in the operand subset AluReg Condition register: SB – Shift out bit ML - Multiplication shift precision loss Instruction format: sh32r Shift right multiplication result register sh32r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 1 1 0 0 1 0 0 op1 1 0 1

Operation: (Source) >> Immediate value => (Source) Assembler syntax: sh32ri Imm; Description: Shifts the reg32 register right. The right shift is single or multiple according to the immediate value. The reg32 register is the concatenation of the multiplication result registers mh and ml:

mh contains the 16-MSB
ml contains the 16-LSB To be completed, the shift operation requires a number of ck clock cycles corresponding to the immediate value. Operands: Imm –The Imm 4-bit immediate data register Condition register: SB – Shift out bit ML - Multiplication shift precision loss Instruction format: sh32ri Shift right multiplication result register of immediate value sh32ri 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 1 1 0 0 0 0 Imm 1 0 1

267 NXP Semiconductors

Operation: (Source) << factor => (Source) Assembler syntax: shl op1 op2; Description: Shifts the op1 register left. The shift is single or multiple according to the op2 register value (factor). To be completed, the shift operation requires a number of ck clock cycles corresponding to the op2 register value. Operands: op1 – One of the register listed in the operand subset AluReg op2– One of the register listed in the operand subset AluReg Condition register: SB – Shift out bit MO - Multiplication shift overflow Instruction format: shl Shift left ALU register shl 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 0 1 1 1 0 1 0 op2 op1

Operation: (Source) << 8 => (Source) Assembler syntax: shl8 op1; Description: Shifts the op1 register of 8 positions left. To be completed, the shift operation requires one ck clock cycles. Operands: op1 – One of the register listed in the operand subset AluReg Condition register: SB – Shift out bit MO - Multiplication shift overflow Instruction format: shl8 Shift left ALU register of 8 bits shl8 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 0 1 1 1 0 1 1 1 1 1 op1

269 NXP Semiconductors

Operation: (Source) << immediate value => (Source) Assembler syntax: shl op1 Imm; Description: Shift the op1 register left. The shift is single or multiple according to the immediate value Imm. To be completed, the shift operation requires a number of ck clock cycles corresponding to the immediate value Imm. Operands: op1 – One of the register listed in the operand subset AluReg Imm –The Imm 4-bit immediate data register Condition register: SB – Shift out bit MO - Multiplication shift overflow Instruction format: shli Shift left the ALU register of immediate value shli 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 0 1 1 0 1 0 Imm op1

Operation: (Source) << factor => (Source) Assembler syntax: shls op1 op2; Description: Shift the op1 register left. The shift is single or multiple according to the op2 register value (factor). The op1 register is handled as a two’s complement number. Its MBS (sign bit) is unchanged during the shift operation. To be completed, the shift operation requires a number of ck clock cycles corresponding to the op2 register value. Operands: op1 – One of the register listed in the operand subset AluReg op1 – One of the register listed in the operand subset AluReg Condition register: SB – Shift out bit MO - Multiplication shift overflow Instruction format: shls Shift left signed ALU register shls 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 0 1 1 1 0 0 0 op2 op1

271 NXP Semiconductors

Operation: (Source) << immediate value => (Source) Assembler syntax: shls op1 Imm; Description: Shifts the op1 register left. The shift is single or multiple according to the immediate value Imm. The op1 register is handled as a two’s complement number. Its MBS (sign bit) is unchanged during the shift operation. To be completed, the shift operation requires a number of ck clock cycles corresponding to the immediate value Imm. Operands: op1 – One of the register listed in the operand subset AluReg Imm –The Imm 4-bit immediate data register Condition register: SB – Shift out bit MO - Multiplication shift overflow Instruction format: shlsi Shift left signed ALU register of immediate value shlsi 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 0 1 1 0 0 0 Imm op1

Operation: (Source) >> factor => (Source) Assembler syntax: shr op1 op2; Description: Shift the op1 register right. The shift is single or multiple according to the op2 register value (factor). To be completed, the shift operation requires a number of ck clock cycles corresponding to the op2 register value. Operands: op1 – One of the register listed in the operand subset AluReg op2– One of the register listed in the operand subset AluReg Condition register: SB – Shift out bit ML - Multiplication shift precision loss Instruction format: shr Shift right ALU register shr 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 0 1 1 1 0 0 1 op2 op1

273 NXP Semiconductors

Operation: (Source) >> 8 => (Source) Assembler syntax: shr8 op1; Description: Shift the op1 register of 8 positions right. To be completed, the shift operation requires one ck clock cycle. Operands: op1 – One of the register listed in the operand subset AluReg Condition register: SB – Shift out bit ML - Multiplication shift precision loss Instruction format: shr8 Shift right ALU register of 8 bits shr8 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 0 1 1 1 0 1 1 1 1 0 op1

Operation: (Source) >> immediate value => (Source) Assembler syntax: shr op1 Imm; Description: Shifts the op1 register right. The shift is single or multiple according to the immediate value Imm. To be completed, the shift operation requires a number of ck clock cycles corresponding to the immediate value Imm. Operands: op1 – One of the register listed in the operand subset AluReg Imm –The Imm 4-bit immediate data register Condition register: SB – Shift out bit ML - Multiplication shift precision loss Instruction format: shri Shift right the ALU register of immediate value shri 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 0 1 1 0 0 1 Imm op1

275 NXP Semiconductors

Operation: (Source) >> factor => (Source) Assembler syntax: shrs op1 op2; Description: Shift the op1 register right. The shift is single or multiple according to the op2 register value (factor). The op1 register is handled as a two’s complement number. Its MBS (sign bit) is unchanged during the shift operation. To be completed, the shift operation requires a number of ck clock cycles corresponding to the op2 register value. Operands: op1 – One of the register listed in the operand subset AluReg op2 – One of the register listed in the operand subset AluReg Condition register: SB – Shift out bit ML - Multiplication shift precision loss Instruction format: shrs Shift right signed ALU register shrs 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 0 1 1 0 1 1 1 op2 op1

Operation: (Source) >> immediate value => (Source) Assembler syntax: shrsi op1 Imm; Description: Shifts the op1 register right. The shift is single or multiple according to the immediate value Imm. The op1 register is handled as a two’s complement number. Its MBS (sign bit) is unchanged during the shift operation. To be completed, the shift operation requires a number of ck clock cycles corresponding to the immediate value Imm. Operands: op1 – One of the register listed in the operand subset AluReg Imm –The Imm 4-bit immediate data register Condition register: SB – Shift out bit MO - Multiplication shift overflow Instruction format: shrsi Shift right signed ALU register of immediate value shrsi 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 0 0 1 1 1 1 Imm op1

277 NXP Semiconductors

Assembler syntax: slab SelBase; Description: Selects the register that contains the address base used in the data RAM Indexed Addressing Mode (XM). The reset value of SelBase is reg. Operands: SelBase – Operand that defines the register to be used to determine the data RAM address base Instruction format: slab Select Data RAM address base slab Operand label Operand description Operand binary value reg Use the dedicated address base add_base register. In this case the address base is defined with the stab instruction. 0 ir Use the ALU ir register as address base 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 1 0 1 1 0 0 0 0 0 1 0 1 SelBase

Assembler syntax: slfbk Ref Diag; Description: Selects the feedback reference for both VDS of the high-side pre-drivers 2 and 4, only if the microcore has access to this high-side. In addition, this instruction enables the automatic diagnosis. This operation is successful only if the microcore has the right to drive the related outputs. The drive right is granted by setting the related bits in the Out_acc_ucX_chY (0x184, 0x185, 0x186, 0x187) configuration registers. The reset of Ref value is boost. Operands: Ref – Operand that defines the feedback reference for both VDS of the high-side pre-drivers 2 and 4. Diag – Operand that defines the diagnosis status for both VDS of the high-side pre-drivers 2 and 4. Instruction format: slfbk Select HS2/4 feedback reference slfbk Operand label Operand description Operand binary value boost The both VDS of the high-side pre-drivers 2 and 4 are referred to boost voltage (VBOOST pin) 0 bat The both VDS of the high-side pre-drivers 2 and 4 are referred to bat voltage (VBATT pin) 1 Operand label Operand description Operand binary value keep No changes, maintains the previous setting 00 NA Not Applicable 01 off Automatic diagnosis disabled 10 on Automatic diagnosis enabled 11 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 1 0 1 1 0 0 1 0 0 0 Ref Diag

279 NXP Semiconductors

Assembler syntax: slsa SelSpi; Description: Selects the register that contains the address used on SPI read and write instructions (drspi and wrspi) The reset values of SelSpi is reg. Operands: SelSpi – Operand that defines the register containing the SPI address Instruction format: slsa Select SPI address slsa Operand label Operand description Operand binary value reg Use the dedicated address register spi_add. 0 ir Use the ALU ir register as SPI address 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 1 0 1 1 0 0 0 0 0 1 0 0 SelSpi

Assembler syntax: stab AddBase; Description: Loads the address value in the address base register add_base. The address base register is a 6-bit register that contains the address base used in the Data RAM Indexed Addressing Mode (XM). The operand AddBase can be identified with a univocal label. The compiler automatically substitutes the ‘define’ label (if used) with the suitable address. Operands: AddBase – Operand that defines the 6-bit register containing the Address Base. Instruction format: stab Set Data RAM address base stab 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 1 0 1 0 0 0 0 AddBase

281 NXP Semiconductors

Assembler syntax: stadc AdcMode DacTarget; Description: Enables or disables the ADC conversion mode on the specified current measurement block. The operation is successful only if the microcore has the right to access the related current measurement block. The access right is granted by setting the related bits in the Cur_block_access_1 register (0x188) and Cur_block_access_2 Register (0x189). The reset value of AdcMode is off. Operands: AdcMode – Operand that activate the ADC mode on the selected current measurement block DacTarget – Operand that defines the current measurement block DAC to be set in ADC mode Instruction format: stadc Set ADC mode stadc Operand label Operand description Operand binary value off The current measurement block compares the current flowing in the actuator with a threshold (nominal behavior). 0 on The current measurement block performs an analog to digital conversion of the current flowing in the actuator 1 Operand label Operand description Operand binary value sssc DAC of the same microcore same channel 00 ossc DAC of the other microcore same channel 01 ssoc DAC of the same microcore other channel 10 osoc DAC of the other microcore other channel 11 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 1 0 1 0 1 0 1 1 0 1 Adc Mode DacTarget

Assembler syntax: stal ModeAL; Description: Sets the arithmetic logic mode. This mode is the set according to the bits A1 and A0 of the ALU condition register (arith_reg). ALU operations behavior is affected by the arithmetic logic mode ModeAL as described below: The ALU instruction operands are handled as C-complement number (signed number). If the resulting value exceeds the result register capacity, leads to overflow detection but no saturation. The ALU instruction operands are handled as C-complement number (signed number). If the resulting value exceeds the result register capacity, it leads to overflow detection and saturation (arith_logic_c2_sat). The ALU instruction operands are handled as positive number (unsigned number). If the resulting value exceeds the result register capacity it leads to overflow detection but no saturation. The ALU instruction operands are handled as positive number (unsigned number). If the resulting value exceeds the result register capacity it leads to overflow detection and saturation. The ModeAL reset value is al3. Operands: ModeAL – Operand that defines the ALU behavior selected Instruction format: stal Set arithmetic logic mode stal Operand label Operand description Operand Binary Value al1 two’s complement number without overflow saturation 00 al2 two’s complement number with overflow saturation 01 al3 Positive number without overflow saturation 10 al4 Positive number with overflow saturation 11 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 1 0 1 0 1 0 1 1 1 1 1 ModeAL

283 NXP Semiconductors

Assembler syntax: stcrb Logic CrbSel; Description: Sets the logic level value individually with the Logic operand of each selected bit CrbSel of the control register. Operands: Logic – Operand that defines the logic level value CrbSel – Operand that defines the control register bit to be selected Instruction format: stcrb Set control register bit stcrb Operand label Operand description Operand binary value low Low level 0 high High level 1 Operand label Operand description Operand binary value b8 Control register bit 8 000 b9 Control register bit 9 001 b10 Control register bit 10 010 b11 Control register bit 11 011 b12 Control register bit 12 100 b13 Control register bit 13 101 b14 Control register bit 14 110 b15 Control register bit 15 (MSB) 111 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 1 0 1 1 1 0 1 0 Logic 0 CrbSel

Assembler syntax: stcrt UcId; Description: Each microcore: shares the ch_rxtx register with the other microcores can read the shared register of another microcore. This instruction selects the microcore's shared register that is accessed by the microcore executing the stcrt instruction. The UcId reset value is sssc. Operands: UcId – Operand that defines the microcore shared register to be access. Instruction format: stcrt Set channel communication register stcrt Operand label Operand description Operand binary value sssc The microcore that is executing the code 00 ossc The other microcore in the same channel 01 ssoc The same microcore in the other channel 10 osoc The other microcore in the other channel 11 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 1 0 1 0 1 1 0 0 0 1 1 UcId

285 NXP Semiconductors

Assembler syntax: stdcctl ModeDC; Description: Selects if the DCDC must be controlled by the microcore (sync) or perform the automatic current regulation (async) by managing controlling the low-side pre-driver 7. If automatic mode is selected, the current is regulated between threshold 4l and 4h The ModeDC reset value is sync. Operands: ModeDC – Operand that defines the DC-DC control mode Instruction format: stdcctl Set DC-DC control mode stdcctl Operand label Operand description Operand binary value sync DCDC is controlled by the microcore 0 async DCDC perform an automatic current control between threshold 4l and 4h 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 1 0 1 0 1 0 1 0 0 0 0 1 ModeDC

Assembler syntax: stdm ModeDAC; Description: The DAC registers address (DAC Register x in DAC Mode and DAC_4h4neg Register) in the internal data memory map are split in two slices:

dac_value_x and dac_value_x for the DAC Register x in DAC Mode
dac_value_4neg, dac_value_4h for the DAC_4h4neg Register. This instruction selects which slice(s) is accessed. The dac4h4n_boost address in the internal data memory map can refer to three registers (dac4h value, dac4neg value, dac boost value); this same instruction selects which of the three register is accessed, according to the ModeDAC operand.
dac_boost_access_mode: nothing (for the dac address) or the value of the dac boost (for the dac4h4n_boost address) is accessed
dac_access_mode/dac4h_access_mode: the dac value (for the dac address) or the dac4h value (for the dac4h4n_boost address) is accessed. the result is available in the 8 lower bits
offset_access_mode/dac4neg_access_mode: the offset register (for the dac address) or the dac4neg value (for the dac4h4n_boost address) is accessed. the result is available in the 13-8 bits if reading an offset, in the 11-8 bits if reading dac4neg
full_access_mode/dac4h4n_access_mode: both the dac value and the offset register (for the dac address) or both the dac4h and the dac4n value (for the dac4h4n_boost address) is accessed The ModeDAC reset value is dac. Operands: ModeDAC – Operand that defines the DAC access mode Instruction format: stdm Set DAC register mode access stdm Operand label Operand description Operand binary value null dac_bst_access_mde 00 dac dac_access_mde/dac4h_access_mde 01 offset offset_access_mde/dac4n_access_mode 10 full full_access_mode/ dac4h4n_access_mode 11 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 1 0 1 0 1 1 0 0 0 0 1 ModeDC

287 NXP Semiconductors

Assembler syntax: stdrm ModeDRM; Description: Sets the Data RAM read mode. The possible read modes according to the ModeDRM operand are:

dram_word_mode: all 16 bits are accessed
dram_lowbyte _mode: only the 8 LSBs of the source Data RAM are accessed. The result is available in the 8 lower bits of the destination register. The upper 8 bits of the destination register is set to 0x00.
dram_highbyte_mode: only the 8 MSBs of the source Data RAM are accessed. The result is available in the 8 lower bits of the destination register. The upper 8 bits of the destination register is set to 0x00.
dram_swapbyte_mode: the 8 LSBs and 8 MSBs of the source dram are accessed swapped and is available at the destination register. This read mode is valid after the load and ldcd instructions following this stdrm instruction. The ModeDRM reset value is word. Operands: ModeDRM – Operand that defines the Data RAM read access Instruction format: stdrm Set Data RAM read mode stdrm Operand label Operand description Operand binary value word dram_word_mode 00 low dram_lowbyte _mode: 01 high dram_highbyte_mode 10 swap dram_swapbyte_mode 11 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 1 0 1 0 1 1 0 0 0 0 0 ModeDRM

Assembler syntax: steoa Mask Switch; Description: Enables or disables the end of actuation mode for all the high-side pre-drivers that the microcore is enabled to drive by means of the Switch operand. The VSRC threshold monitoring of the related pre-drivers can be disabled by setting the operand Mask The Mask default value is nomask. The Switch default value is bsoff. Operands: Mask – Operand that set the VDS threshold mask Switch – Operand that set the end of actuation mode Instruction format: steoa Set end of actuation mode steoa Operand label Operand description Operand binary value nomask VSRC threshold monitoring (hsx_vsrc_threshold (2:0)) of the selected HS is as defined per the Vds_threshold_hs register (0x18B) 0 mask VSRC threshold monitoring (hsx_vsrc_threshold (2:0)) of the selected HS is masked with the binary value '000’ 1 Operand label Operand description Operand binary value keep Maintain the previous values 00 bsoff Bootstrap switch is forced off 11 bson Bootstrap switch can be enabled even if no low-side pre-driver is switched on 01 bsneutral Bootstrap control is not affected 10 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 1 0 1 0 1 0 0 1 0 0 Mask Switch

289 NXP Semiconductors

Assembler syntax: stf Logic FlgSel; Description: Sets the logic level value with the Boolean Logic of the selected flag. The flag is selected according the FlgSel operand. Operands: Logic – Operand that defines the logic level value FlgSel – Operand that defines the flag bit to be selected Instruction format: stf Set flag stf Operand label Operand description Operand binary value low Low level 0 high High level 1 Operand label Operand description Operand binary value b0 Flag bit 0 0000 b1 Flag bit 1 0001 b2 Flag bit 2 0010 b3 Flag bit 3 0011 b4 Flag bit 4 0100 b5 Flag bit 5 0101 b6 Flag bit 6 0110 b7 Flag bit 7 0111 b8 Flag bit 8 1000 b9 Flag bit 9 1001 b10 Flag bit 10 1010 b11 Flag bit 11 1011 b12 Flag bit 12 1100 b13 Flag bit 13 1101 b14 Flag bit 14 1110 b15 Flag bit 15 1111 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 1 0 1 0 0 1 1 1 Logic FlgSel

Assembler syntax: stfw FwMode; Description: Defines the freewheeling output modes. Freewheeling control is automatic or manual according to the FwMode operand. The FwMode operand is a Boolean that defines the control mode:

if Shortcut1 is HS1, then LS5 is set as freewheeling pre-driver
if Shortcut1 is HS2, then LS6 is set as freewheeling pre-driver
if Shortcut1 is HS3, then LS7 is set as freewheeling pre-driver
if Shortcut1 is HS4, then HS5 is set as freewheeling pre-driver
if Shortcut1 is HS5, then LS4 is set as freewheeling pre-driver. The shortcuts are set using the dfsct instruction. This operation is successful only if the microcore has the right to drive the output related to freewheeling. The drive right is granted by setting the related bits in the Out_acc_ucX_chY (0x184, 0x185, 0x186, 0x187) configuration registers. The FwMode reset value is manual. Operands: FwMode – Operand that defines the freewheeling mode Instruction format: stfw Set freewheeling mode stfw Operand label Operand description Operand binary value manual Freewheeling manual control 0 auto Freewheeling automatic control 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 1 0 1 0 1 1 0 0 1 0 0 0 FwMode

291 NXP Semiconductors

Assembler syntax: stgn Gain OpAmp; Description: Sets the gain of an operational amplifier with the Gain operand used to measure the current flowing through the actuator sense resistor. The operational amplifier is selected according to the OpAmp operand. The operation is successful only if the microcore has the right to access the related current measurement block. The access right is granted by setting the related bits in the Cur_block_access_1 register (0x188) and Cur_block_access_2 Register (0x189). The Gain reset value is gain 5.8. Operands: Gain – Operand that defines the current measure operational amplifier gain OpAmp – Operand that defines the current measure operational amplifier gain to be set Instruction format: stgn Set current measure operational amplifier gain stgn Operand label Operand description Operand binary value gain5.8 Operational amplifier gain set to 5.8 00 gain8.7 Operational amplifier gain set to 8.7 01 gain12.6 Operational amplifier gain set to 12.6 10 gain19.3 Operational amplifier gain set to 19.3 11 Operand label Operand description Operand binary value sssc Current measure operational amplifier of the same microcore same channel 00 ossc Current measure operational amplifier of the other microcore same channel 01 ssoc Current measure operational amplifier of the same microcore other channel 10 osoc Current measure operational amplifier of the other microcore other channel 11 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 1 0 1 0 1 0 0 1 1 Gain OpAmp

Assembler syntax: stirq Logic; Description: Set the IRQB output pin The Logic reset value is high. Operands: Logic – Operand that defines the logic level of the IRQB pin Instruction format: stirq Set IRQB pin stirq Operand label Operand description Operand binary value low Low level 0 high High level 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 1 0 1 0 1 1 0 0 1 0 0 1 Logic

293 NXP Semiconductors

Assembler syntax: sto OutSel Out; Description: Sets the state with the Out operand for the selected output according to the OutSel operand. The operation is successful only if the microcore has the right to drive the related outputs. The drive right is granted by setting the related bits in the Out_acc_ucX_chY (0x184, 0x185, 0x186, 0x187) configuration registers. Operands: OutSel – Operand that defines the handled output Out – Operand that set output state Instruction format: sto Set single pre-driver output sto Operand label Operand description Operand binary value hs1 High-side pre-driver 1 0000 hs2 High-side pre-driver 2 0001 hs3 High-side pre-driver 3 0010 hs4 High-side pre-driver 4 0011 hs5 High-side pre-driver 5 0100 ls1 Low-side pre-driver 1 0101 ls2 Low-side pre-driver 2 0110 ls3 Low-side pre-driver 3 0111 ls4 Low-side pre-driver 4 1000 ls5 Low-side pre-driver 5 1001 ls6 Low-side pre-driver 6 1010 ls7 Low-side pre-driver 7 1011 undef Undefined 1100 Operand label Operand description Operand binary value keep No changes, maintains the previous setting 00 off Output disabled 01 on Output enabled 10 toggle Reverse the previous setting 11 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 1 0 1 0 0 1 0 OutSel Out

Assembler syntax: stoc Ctrl DacTraget; Description: Enables or disables the offset compensation with the operand Ctrl on the current measurement block specified according to the DacTarget operand. The operation is successful only if the microcore has the right to access the related current measurement block. The access right is granted by setting the related bits in the Cur_block_access_1 register (0x188) and Cur_block_access_2 Register (0x189). The Ctrl reset value is off for all current measurement blocks. Operands: Ctrl – Operands that set offset compensation state DacTarget – Operand that defines the current measurement block Instruction format: stoc Set offset compensation stoc Operand label Operand description Operand binary value off Disable the offset compensation 0 on Enable the offset compensation 1 Operand label Operand description Operand binary value sssc DAC of the same microcore same channel 00 ossc DAC of the other microcore same channel 01 ssoc DAC of the same microcore other channel 10 osoc DAC of the other microcore other channel 11 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 1 0 1 0 1 0 1 0 1 0 Ctrl DacTarget

295 NXP Semiconductors

Assembler syntax: store op1 Dram Ofs; Description: Copies the content of the op1 source register in a Data RAM line defined by the 6-bit Data RAM address Dram. The operand Dram can be identified with a univocal label. The compiler automatically substitutes the ‘define’ label (if used) with the suitable Data RAM address. The Data RAM address is accessed according to the Boolean operand Ofs using the:

Immediate addressing mode (IM).
Indexed addressing mode (XM). In that case,
the address base is added to the address Dram. The address base is set using the stab instructions. Operands: op1 – One of the register listed in the operand subset UcReg Dram– Operand that defines the 6-bit DRAM address Ofs– Operands that set data RAM addressing mode Instruction format: store Store register data in Data RAM store Operand label Operand description Operand binary value _ofs Data RAM immediate addressing mode (IM) 0 ofs Data RAM indexed addressing mode (XM) 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 Ofs op1 Dram 0 1

Assembler syntax: stos Out1 Out2 Out3; Description: Sets the state of three outputs Out1, Out2 and Out3 previously defined as shortcuts with the dfsct instruction. The operation is successful only if the microcore has the right to drive the related outputs. The drive right is granted by setting the related bits in the Out_acc_ucX_chY (0x184, 0x185, 0x186, 0x187) configuration registers. Operands: Out1, Out2, and Out3 – Operands that set output state Instruction format: stos Set pre-driver output shortcuts stos Operand label Operand description Operand binary value keep No changes, maintains the previous setting 00 off Output disabled 01 on Output enabled 10 toggle Reverse the previous setting 11 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 1 0 1 0 0 0 1 Out1 Out2 Out3

297 NXP Semiconductors

Assembler syntax: stslew SlMode; Description: Defines the outputs slew rate mode with the Boolean SlMode. The operation is successful only if the microcore has the right to drive the related outputs. The drive right is granted by setting the related bits in the Out_acc_ucX_chY (0x184, 0x185, 0x186, 0x187) configuration registers. The SlMode reset value is normal. When switching the slew-rate from slow to fast, the new slew-rate is valid after typically 1ck cycle (166 ns considering fck = 6.0 MHz). When switching from fast to slow, it takes typically four ck cycles (666 ns considering fck = 6.0 MHz) until the new slew-rate is effective. Operands: SlMode – Operands that set outputs slew rate mode Instruction format: stslew Set pre-driver output slew rate mode stslew Operand label Operand description Operand binary value normal The outputs slew rate is set by an SPI register 0 fast The outputs slew rate is the highest one 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 1 0 1 0 1 1 0 0 1 0 1 1 SlMod e

Assembler syntax: stsrb Logic SrbSel; Description: Sets individually the logic level value with the Logic operand of each selected bit SrbSel of the status register. Operands: Logic – Operand that defines the logic level value SrbSel – Operand that defines the status register bit to be selected Instruction format: stsrb Set status register bit stsrb Operand label Operand description Operand binary value low Low level 0 high High level 1 Operand label Operand description Operand binary value b0 Status register bit 0 (LSB) 0000 b1 Status register bit 1 0001 b2 Status register bit 2 0010 b3 Status register bit 3 0011 b4 Status register bit 4 0100 b5 Status register bit 5 0101 b6 Status register bit 6 0110 b7 Status register bit 7 0111 b8 Status register bit 8 1000 b9 Status register bit 9 1001 b10 Status register bit 10 1010 b11 Status register bit 11 1011 b12 Status register bit 12 1100 b13 Status register bit 13 1101 b14 Status register bit 14 1110 b15 Status register bit 15 (MSB) 1111 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 1 0 1 1 1 0 0 0 Logic SrbSel

299 NXP Semiconductors

Operation: (Source1) - (Source2) => (Destination) Assembler syntax: sub op1 op2 res; Description: Subtracts the value contained in the op1 register to the value contained in op2 register and places the result in the res register. Operands: op1 – One of the register listed in the operand subset AluReg op2 – One of the register listed in the operand subset AluReg res – One of the register listed in the operand subset AluReg Condition register: RZ - Addition or subtraction result is zero RS - Addition or subtraction result is negative UU - Unsigned underflow UO - Unsigned overflow SU - Signed underflow SO - Signed overflow Instruction format: sub Two ALU registers subtraction to ALU register sub 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 0 1 0 res 1 op2 op1

Operation: (Source) - Immediate value => (Destination) Assembler syntax: subi op1 Imm res; Description: Subtracts the value contained in the Imm register to the value contained in the op1 register and places the result in the res register. Operands: op1 – One of the register listed in the operand subset AluReg Imm –The Imm 4-bit immediate data register res – One of the register listed in the operand subset AluReg Condition register: RZ - Addition or subtraction result is zero RS - Addition or subtraction result is negative UU - Unsigned underflow UO - Unsigned overflow SU - Signed underflow SO - Signed overflow Instruction format: subi ALU register subtraction with immediate value to ALU register subi 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 1 1 1 res Imm op1

301 NXP Semiconductors

Operation: (Source)[0:7] < => (Source)[8:15] Assembler syntax: swap op1; Description: Swaps the high byte and the low byte of the register op1. Operands: op1 – One of the register listed in the operand subset AluReg Instruction format: swap Swap bytes inside ALU register swap 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 1 0 1 0 1 0 1 1 0 0 op1

Assembler syntax: toc2 op1; Description: Converts the integer value contained in op1 register to two’s complement format. If the conversion bit CS in the arithmetic condition register arith_reg is zero, the toc2 instruction set the operand register MSB to zero. If the conversion bit is one, then it returns the 2's complement of the operand (bits[14:0] only) register op1 and set the MSB to one. Operands: op1 – One of the register listed in the operand subset AluReg Instruction format: toc2 Integer to two’s complement conversion in ALU register toc2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 1 0 1 1 1 0 0 1 1 0 op1

303 NXP Semiconductors

Assembler syntax: toint op1 Rst; Description: Convert the two’s complement value contained in op1 register to integer format. The toint instruction retains the original value in the operand register op1 when its MSB bit is zero. If the MSB is 1, then it returns the 2's complement of the operand register (op1[14:0]). The toint instruction also saves the MSB of the operand op1 in the conversion bit CS of the arithmetic condition register arith_reg. The MSB of the operand is either XORed with the existing conversion bit CS of the ALU condition register (if the instruction is called with the _rst parameter) or replaces it (if the instruction is called with the rst parameter). Operands: op1 – One of the register listed in the operand subset AluReg Rst – Operand that defines if the conversion bit CS of the ALU condition register is reset Condition register: CS - Last conversion sign Instruction format: toint two’s complement to integer conversion in ALU register toint Operand label Operand description Operand binary value _rst The existing conversion bit CS is XORed with the op1 MSB 0 rst The existing conversion bit CS is set according to the op1 MSB 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 1 0 1 1 1 0 0 1 0 Rst op1

Assembler syntax: wait WaitMask ; Description: Stops the program counter (uPC) incrementing and waits until at least one of the enabled wait conditions is satisfied. When one of the conditions is satisfied, the program counter is moved to the corresponding destination. The possible wait conditions, along with the corresponding destinations, are stored in the wait table by means of the cwer and cwef instructions. The active wait table rows are enabled according to the WaitMask 5-bit operand. Operands: WaitMask – Operand that defines the active wait table rows wait Wait until condition satisfied wait Operand label Operand description Operand binary value always No wait table row enabled. Infinite loop 00000 row1 Wait table row 1 enabled 00001 row2 Wait table row 2 enabled 00010 row12 Wait table row 1,2 enabled 00011 row3 Wait table row 3 enabled 00100 row13 Wait table row 1,3 enabled 00101 row23 Wait table row 2,3 enabled 00110 row123 Wait table row 1,2,3 enabled 00111 row4 Wait table row 4 enabled 01000 row14 Wait table row 1,4 enabled 01001 row24 Wait table row 2,4 enabled 01010 row124 Wait table row 1,2,4 enabled 01011 row34 Wait table row 3,4 enabled 01100 row134 Wait table row 1,3,4 enabled 01101 row234 Wait table row 2,3,4 enabled 01110 row1234 Wait table row 1,2,3,4 enabled 01111 row5 Wait table row 5 enabled 10000 row15 Wait table row 1,5 enabled 10001 row25 Wait table row 2,5 enabled 10010 row125 Wait table row 1,2,5 enabled 10011 row35 Wait table row 3,5 enabled 10100 row135 Wait table row 1,3,5 enabled 10101 row235 Wait table row 2,3,5 enabled 10110 row1235 Wait table row 1,2,3,5 enabled 10111 row45 Wait table row 4,5 enabled 11000 row145 Wait table row 1,4,5 enabled 11001

305 NXP Semiconductors

Instruction format: row245 Wait table row 2,4,5 enabled 11010 row1245 Wait table row 1,2,4,5 enabled 11011 row345 Wait table row 3,4,5 enabled 11100 row1345 Wait table row 1,3,4,5 enabled 11101 row2345 Wait table row 2,3,4,5 enabled 11110 row12345 Wait table row 1,2,3,4,5 enabled 11111 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 1 0 1 0 1 0 0 0 WaitMask Operand label Operand description Operand binary value

Assembler syntax: wrspi; Description: Requests an SPI backdoor write. The address must previously be defined in the SPI address register spi_add. The data must previously be defined in the SPI address register spi_data register. The wrspi instruction requires 2 ck cycles to complete operation. The SPI address register and SPI data register must not be changed on the following instruction, otherwise the operation fails and the written data is dummy. Instruction format: wrspi SPI write request wrspi 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 1 0 1 0 1 0 1 0 0 0 0 0 1

307 NXP Semiconductors

Operation: (Source) + Immediate register => (Source) Assembler syntax: xor op1; Description: Applies the XOR-mask contained into the Ir register to the value contained in the op1 register and places the result in the op1 register. The initial data stored in the op1 register is loss. Operands: op1 – One of the register listed in the operand subset AluReg Ir –The ALU immediate register Condition register: MM - Mask result is 0x0000 MN - Mask result is 0xFFFF Instruction format: xor XOR-mask on ALU register with the immediate register to ALU register xor 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 0 1 1 1 0 1 1 0 1 0 op1

11 Packaging

11.1 Package mechanical dimensions

perform a keyword search for the drawing’s document number. Table 247. Packaging information

309 NXP Semiconductors

311 NXP Semiconductors

Revision Date Description of changes 1.0 7/2012 • Initial release 2.0 11/2012 • Wording and part definitions changes were made.

No electrical content was altered. 3.0
Corrected errors, typos, and formatting
Added HSX leakage current when pre-driver on (biasing switched off) and S_HSX leakage current delta between pre-drivers off and on parameters
Changed min for VB_HSX_VCCP__TH_R and VB_HSX_VCCP__TH_F
Added missing sentence for Cipher_unit block 1/2014 • Updated Data Sheet title 4.0 4/2014 • Redefined the minimum for tCSBF_SCLKR and tSCLKF_CSBR in Table 91.
Removed associated table and graphic for tCSBF_SCLKR and tSCLKF_CSBR. 5.0 9/2014
Updated Note (9)
Updated Table 4 (added min. and max. value for RJA)
Updated Figure 7 (added DGND to ground symbol)
Added Table 11 for VCC5 Slew Rate
Updated Figure 10 (added PGND to the ground symbol)
Updated Table 16 (changed cksys_drven to 1 for the last two cases)
Updated Table 22 (added total DAC error)
Updated Table 38 (changed cksys_drven to 1 for the last case)
Updated (63) (changed 330 nF to 330 pF)
Updated Section 6.15.2 Clock_manager block on page 99
Updated timing in Table 179
Updated reset values in Table 208, Table 209, and Table 210
Updated operand description for Sh1 and Sh2 on page 247
Updated mask values for steoa instruction 6.0 4/2015
Updated Table 3 (replaced high-side with low-side)
Updated Table 38 (set Drven to 1)
Table 39, clarified the maximum PWM frequency
Table 93, changed flag 11 from OA1 to OA2
Replaced IRQ by IRQB
Updated reset value in Table 152 for boost feedback filter
Updated hs1 and hs2 ls act disable description
Updated dac_4neg from 8 bits to 4 bits in Table 181
Updated Table 204 (dead time from 4 bits to 5 bits)
Corrected typo error in Table 221 (decimal replaced with hexadecimal)
Updated operand label in Bias instruction 7.0 8/2016
Updated to NXP document form and style
Added 69 V parameter to VCP_SRC in Table 37
Added tSPI_RESETB_T0 and tSPI_RESETB parameters to Table 91 8.0 4/2018
Updated conditions for parameter IVBOOST_QUIESC in Table 6
Deleted Figure 24
Updated text in Section 6.15.5.15 Mode B
Updated text in Section 6.15.5.15.1 Spi_error block 8.1 11/2018
Changed reset for bit 0 from “0” to “1” in Table 126
Changed reset for bits 9 to 0 from “0000000000” to “11 1111 1111” in Table 152
Changed reset for bits 9 to 0 from “0000000000” to “11 1111 1111” in Table 153
Changed R/W for bits 7 to 0 from “r/w” to “r” in Table 198
Changed R/W for bits 7 to 0 from “r/w” to “r” in Table 199
Changed R/W for bits 7 to 0 from “r/w” to “r” in Table 200
Changed R/W for bits 7 to 0 from “r/w” to “r” in Table 201 9.0 1/2019 • Changed document status from Advance information to Technical data

313 NXP Semiconductors

10.0 2/2023

CIN: 202301020I
Part Number MC33816MAE added with additional Measurement Function feature
Added Measurement function electrical characteristics (MC33816MAE only)
Table 76:, “Measurement function output noise": Changed unit for Out_OAx_noise to “µV” from “mV” Revision Date Description of changes

Information in this document is provided solely to enable system and software implementers to use NXP products. There are no expressed or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. NXP reserves the right to make changes without further notice to any products herein. NXP makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does NXP assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation, consequential or incidental damages. "Typical" parameters that may be provided in NXP data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including "typicals," must be validated for each customer application by the customer's technical experts. NXP does not convey any license under its patent rights nor the rights of others. NXP sells products pursuant to standard terms and conditions of sale, which can be found at the following address: http://www.nxp.com/terms-of-use.html. How to Reach Us: Home Page: NXP.com Web Support: http://www.nxp.com/support NXP, the NXP logo, Freescale, the Freescale logo, and SMARTMOS are trademarks of NXP B.V. All other product or service names are the property of their respective owners. All rights reserved. © NXP B.V. 2023 Document Number: MC33816 Rev. 10.0

Product Information

33816 specifications and overview.

Summary

SD6 programmable solenoid controller for precision solenoid control applications Rev. 10.0, 2/2023

Description

SD6 programmable solenoid controller for precision solenoid control applications Rev. 10.0, 2/2023

Source title 33816 Datasheet(PDF) - NXP Semiconductors

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