33810

33810_10 FREESCALE | Alldatasheet

Document overview

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Technical content

Features

• Designed to operate over the range of 4.5V ≤ VPWR ≤ 36V
• Quad ignition IGBT or MOSFET gate pre-driver with Parallel/SPI and /or PWM control
• Quad injector driver with Parallel/SPI control
• Interfaces directly to MCU using 3.3V / 5.0V SPI protocol
• Injector driver current limit - 4.5A max.
• Independent fault protection and diagnostics
• VPWR standby current 10 μA max.
• Pb-free packaging designated by suffix code EK VPWR VDD SI SCLK CS SO DIN0 DIN3 GIN0 OUT EN SPKDUR NOMI MAXI OUT0 OUT1 OUT2 OUT3 GND FB0 GD0 FB1 GD1 FB2 GD2 FB3 GD3 RSP RSN MOSI SCLK MISO ETPU ETPU GPIO ETPU ETPU ETPU MCU 33810 VBAT VBAT VBAT VBAT VBAT VBAT VBAT VBAT CS ETPU GIN3 ETPU VDD VBAT

Figure 1. MC33810 Simplified Application Diagram

32 PIN SOICW EP

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Figure 2. 33810 Simplified Internal Block Diagram

Figure 3. 33810 Pin Connections Table 1. 33810 Pin Definitions A functional description of each pin can be found in the Functional Pin Description section beginning on page 13.

8 VDD Input Digital Logic Supply

source for the Chip Select (CS). 6 SI Input Serial Input Data The SI input pin is used to receive serial data from the MCU. d SO pins, while being addressed by the CS.

4 CS Input Chip Select The Chip Select input pin is an active low signal sent by the MCU to

logic levels and has an internal active pull-up current source. 25 VPWR Input Analog Supply Voltage VPWR is the main voltage input for all interna l analog bias circuitry. impedance ground plane for both electrical and thermal considerations.

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29 MAXI Output Maximum Ignition Coil

resistor connected to pins RSP and RSN.

28 NOMI Output Nominal Ignition Coil

IGBT's collector voltage to provide the spark duration timer control signal.

26 RSP Input Resistor Sense

This pin is the Positive input of a current sense amplifier.

27 RSN Input Resistor Sense

This pin is the Negative input of a current sense amplifier. These pin are the Open drain low side injector driver outputs. Table 1. 33810 Pin Definitions (continued) A functional description of each pin can be found in the Functional Pin Description section beginning on page 13.

Analog Integrated Circuit Device Data Freescale Semiconductor 5 33810

ELECTRICAL CHARACTERISTICS

Table 2. Maximum Ratings All voltages are with respect to ground unless otherwise noted.

1. Exceeding these limits may cause malf unction or permanent damage to the device.
2. ESD data available upon request.
3. ESD testing is performed in accordance with the Human Body Mo del (HBM) (AEC-Q100-002), the Machine Model (MM) (AEC-Q100-

003), and the Charge Device Model (CDM), Robotic (AEC-Q100-011).

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STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics

1. These parameters are guaranteed by design, but not production te sted. Fully operational means driver outputs will toggle as expected
2. Over-voltage thresholds minimu m and maximum include hysteresis.
3. Under-voltage thresholds minimu m and maximum include hysteresis.
4. Device is functional provided T J is less than 150°C. Some table parameters may be out of specification.
5. Device in Sleep State, returns from sleep state with power on reset.
6. Output fault detection thresholds with outputs programmed OFF. Output fault detect thresholds are the same for output open and shorts.

Analog Integrated Circuit Device Data Freescale Semiconductor 7 33810 STATIC ELECTRICAL CHARACTERISTICS INJECTOR DRIVER OUTPUTS (OUT 0:3) (Continued) Output Clamp Voltage 1 ID = 20 mA VOC1 48 53 58 V Output Leakage Current VDD = 5.0 V, VDRAIN = 24 V, Open Load Detection Current Disabled VDD = 5.0 V, VDRAIN = VOC - 1.0 V, Open Load Detection Current Disabled VDD = 0 V, VDRAIN = 24 V, Sleep State IOUT (LKG) 3000 μA Over-temperature Shutdown(10) TLIM 155 – 185 °C Over-temperature Shutdown Hysteresis(10) TLIM (HYS) 5.0 10 15 °C IGNITION (IGBT) GATE DRIVER PARAMETERS (GD 0:3 FB0:3) Gate Driver Output Voltage IGD = 500 μA IGD = -500 μA V GS (ON) V GS (OFF) 4.8 7.0 0.375 9.0 0.5 V Sleep Mode Gate to Source Resistor R GS (PULLDOW 100 200 300 KΩ Sleep Mode FBx pin Leakage Current VDD = 0 V, VFBx = 24 V, IFBX (LKG) – – 1.0 μA Feedback Sense Current (FBx Input Current) FBx = 18 V, Outputs Programmed OFF IFBX(FLT-SNS) 1.0 μA Gate Drive Source Current (1 ≤ VGD ≤ 3) I GATEDRIVE 650 780 950 μA Gate Drive Turn Off Resistance RDS(ON) 500 – 1000 Ω SOFT SHUTDOWN FUNCTION (VOLTAGES REFERENCED TO IGBT COLLECTOR) Low Voltage Flyback Clamp Driver Command Off, Soft Shutdown Enabled, GDx = 2.0 V VLVC VPWR +9.0 VPWR +11 VPWR + 13 V Spark Duration Comparator Threshold (referenced to IC Ground Tab) Rising Edge Relative to VPWR VTH-RISE 18 21 24 V Spark Duration Comparator Threshold (referenced to IC Ground Tab)(11) Falling Edge Relative to VPWR, Default = 5.5 V Assuming ideal external 10:1 voltage divider. Voltage measured at high end of divider, not at pin. Tolerance of divider not included VTH-FALL 1.2 4.9 7.4 9.9 2.75 8.2 11.00 3.6 6.1 9.1 12.1 V Open Secondary Comparator Threshold (referenced from primary to Rising Edge Relative to GND. No hyster esis with 10:1 voltage divider. VTH-RISE 11.5 – 15.5 V CURRENT SENSE COMPARATOR (RSP, RSN) NOMI Trip Threshold Accuracy - Steady State Condition 3.0 A across 0.02 Ω (RSP - R SN = 60 mV) 10.75 A across 0.04 Ω (RSP - RSN = 430 mV) NOMITRIPTA -10 – 10 Notes 10. This parameter is guaranteed by design, however is not production tested. 11. Assuming Ideal external 10:1 Voltage Divider. T olerance of 10:1 Voltage Divider is not included. Voltage is measured on the High End of Divider - not at the pin. 10:1 N.3.A 10:1 Voltage Divider is produced using two resistors with a 9:1 resistance ratio by the basic formula: Where R2 = 9XR1VOUT

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STATIC ELECTRICAL CHARACTERISTICS CURRENT SENSE COMPARATOR (RSP, RSN) (CONTINUED) MAXI Trip Threshold Accuracy Steady State Condition 6.0 A across 0.02 Ω (RSP - RSN = 120 mV) 21 A across 0.04 Ω (RSP - RSN = 840 mV) MAXITRIPTA -7.5 7.5 % MAXI Trip Point During Overlapping Dwell MAXITRIPOD -35 – +35 % Input Bias Current RSP and RSN IBIASRSX -50 – 50 µA Comparator Hysteresis Voltage NOMI MAXI NOMIHYS MAXIIHYS % of VT Input Voltage Range (Maximum voltage between RSN and RSP)(12) VCMVRCMVR 0.0 – 2.0 V Ground Offset Voltage Range(12) Maximum offset between RSN pin and IC Ground (Exposed Pad) VGNDOVR -0.3 – 0.3 V GENERAL PURPOSE GATE DRIVER PARAMETERS (GD 0:3) Gate Drive Sink and Source Current IGD 1.0 2.0 5 mA Gate Drive Output Voltage IGD = 1.0 mA IGD = -1.0 mA V GS (ON) V GS (OFF) 4.8 0.0 7.0 0.2 9.0 0.5 V V Short to Battery Fault Detection Voltage Threshold VDD = 5.0 V, Outputs Programmed ON Programmable from 0.5 to 3.0 V in 0.5 V increments. (Table 14) VDS(FLT-TH) -35% +35% V Open Fault Detection Voltage Threshold (referenced to IC ground tab) VDD = 5.0 V, Outputs Programmed OFF VDS(FLT-TH) 2.0 2.5 3.0 V Output OFF Open Load Detection Current FBx = 18 V, Outputs Programmed OFF IFBX(FLT-SNS) 50 75 120 μA Output Clamp Voltage Driver Command Off, Clamp Enabled, VGATE = 2.0 V VOC 48 53 58 V DIGITAL INTERFACE Input Logic High-voltage Thresholds VIH 0.7 x VDD – VDD + 0.3 V Input Logic Low-voltage Thresholds VIL GND - 0.3 – 0.2 x VDD V Input Logic-voltage Hysteresis VHYS 100 – 400 mV Input Logic Capacitance CIN – – 20 pF Sleep Mode Input Logic Current VDD = 0 V I LOGIC_SS -10 – 10 μA Input Logic Pull-down Current 0.8 to 5.0 V (DINX and GINX) ILOGIC_PD 30 50 100 μA Notes 12. This parameter is guaranteed by desi gn, however it is not production tested.

Analog Integrated Circuit Device Data Freescale Semiconductor 9 33810 STATIC ELECTRICAL CHARACTERISTICS DIGITAL INTERFACE (CONTINUED) Input Logic Pull-down Current 0.8 to 5.0 V (SI) ISI_PD 5.0 15 25 μA Input Logic Pull-up Current on OUT_EN OUT_EN = 0.0 V, VDD = 5.0 V IOUT_EN_PU -30 -50 -100 μA OUT_EN Leakage Current to VDD OUT_EN = 5.0 V, VDD = 0 V IOUT_EN(LKG) – – 50 μA SCLK Pull-down Current VSCLK = VDD I SCLK 5 15 25 μA Tri-state SO Output 0 to 5.0 V I TRISO -10 – 10 μA CS Input Current CS = VDD ICS -50 – 50 μA CS Pull-up Current CS = 0 V ICS_PU -30 -50 -100 μA CS Leakage Current to VDD CS = 5.0 V, VDD = 0 V ICS(LKG) – – 50 μA SO Input Capacitance in Tri-state Mode CSO – 20 – pF SO High State Output Voltage ISO-HIGH = -1.0 mA VSO_HIGH VDD - 0.4 – – V SO Low State Output Voltage ISO-LOW = 1.0 mA VSO_LOW – – 0.4 V NOMI, MAXI in V10 Mode Pull-down Current NOMI, MAXI = 0.8 V, VDD = 5.0 V IPD 30 70 100 μA SPKDUR Output Voltage ISPKDUR = 1.0 mA VSPKDUR_LO – – 0.4 V Output Pull-up Current for SPKDUR ISPKDUR_PV 30 50 100 μA NOMI, MAXI High State Output Voltage INOMI-HIGH = -1.0 mA IMAXI-HIGH = -1.0 mA VI_HIGH VDD - 0.4 – – V NOMI, MAXI Low State Output Voltage INOMI-LOW = 250 µA IMAXI-LOW = 250 µA VI_LOW – – 0.4 V

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DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 4. Dynamic Electrical Characteristics

1. This parameter is guaranteed by desi gn, however it is not production tested.

Analog Integrated Circuit Device Data Freescale Semiconductor 11 33810 DYNAMIC ELECTRICAL CHARACTERISTICS GENERAL PURPOSE GATE DRIVER PARAMETERS Short to Battery Fault Detection Filter Timer Accuracy VDD = High, Outputs Programmed ON Programmable from 30 µs to 960 µs in replicating increments Tolerance of timer after using calibration command Tolerance of timer before using calibration command VDS(flt-th) -10 -35 +10 +35 Output OFF Open Circuit Fault Filter Timer VDD = 5.0 V, Outputs Off Tolerance of timer before using calibration command t(OFF)OC 100 400 µs PWM Frequency 10 Hz to 1.28 kHz Tolerance after using calibration command PWM Frequency 10 Hz to 1.28 kHz Tolerance before using calibration command PWMFREQ PWMFREQ -10% -35% 10% 35% Gate Driver Short Fault Duty Cycle GDSHRT_DC 1.0 3.0 % SPI DIGITAL INTERFACE TIMING(14) Falling Edge of CS to Rising Edge of SCLK Required Setup Time t LEAD 100 – – ns Falling Edge of SCLK to Rising Edge of CS Required Setup Time t LAG 50 – – ns SI to Rising Edge of SCLK Required Setup Time t SI (SU) 16 – – ns Rising Edge of SCLK to SI Required Hold Time t SI (HOLD) 20 – – ns SI, CS, SCLK Signal Rise Time(15) t R (SI) – 5.0 – ns SI, CS, SCLK Signal Fall Time(16) t F (SI) – 5.0 – ns Time from Falling Edge of CS Low-impedance(17) t SO (EN) – – 55 ns Time from Rising Edge off CS to SO High-impedance(18) t SO (DIS) – – 55 ns Time from Falling Edge of SCLK to SO Data Valid(19) t VALID – 25 55 ns Sequential Transfer Rate Time required between data transfers tSTR 1.0 – – µs DIGITAL INTERFACE Calibrated Timer Accuracy t TIMER – – 10 % Un-calibrated Timer Accuracy t TIMER – – 35 % Notes 15. This parameter is guaranteed by desi gn, however it is not production tested. 16. Rise and Fall time of incoming SI, CS and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing. 17. Time required for valid output status data to be available on SO pin. 18. Time required for output states data to be terminated at SO pin. 19. Time required to obtain valid data out from SO following the fall of SCLK with 200 pF load. Table 4. Dynamic Electrical Characteristics (continued)

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tSO(EN) CS SCLK SI SO MSB OUT LSB OUT MSB IN

0.7 VDD

0.2 VDD

tVALID tSO(DIS) tSI(SU) tSI(HOLD)

Analog Integrated Circuit Device Data Freescale Semiconductor 13 33810 FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION ANALOG SUPPLY VOLTAGE (VPWR) The VPWR pin is the battery input to the 33810 IC. The VPWR pin requires external reverse battery and transient protection. All IC analog current and internal logic current is provided from the VPWR pin. With VDD applied to the IC, the application of VPWR will perform a POR. DIGITAL LOGIC SUPPLY VOLTAGE (VDD) The VDD input pin is used to determine communication logic levels between the microprocessor and the 33810 IC. Current from VDD is used to drive SO output and the pull-up current for CS. VDD must be applied for normal mode operation. Removing VDD from the IC will place the device in sleep mode. With VPWR applied to the IC, the application of VDD will perform a POR. GROUND (GND) The bottom pad or FLAG provides the only ground connection for the IC. The VPWR and VDD supplies are both referenced to the GND pad. The GND pad is used for both de-coupling the power supplies as well as power ground for the output drivers. Although the silicon die is epoxy attached to the top side of the pad, the pad must be grounded for proper electrical operation. SERIAL CLOCK INPUT (SCLK) The system clock (SCLK) pin clocks the internal shift register of the 33810. The SI data is latched into the input shift register on the rising edge of SCLK signal. The SO pin shifts status bits out on the falling edge of SCLK. The SO data is available for the MCU to read on the rising edge of SCLK. With CS in a logic high state, signals on the SCLK and SI pins will be ignored and the SO pin is tri-state CHIP SELECT (CS) The system MCU selects the 33810 to receive communication using the chip select (CS) pin. With the CS in a logic low state, command words may be sent to the 33810 via the serial input (SI) pin, and status information is received by the MCU via the serial output (SO) pin. The falling edge of CS enables the SO output and transfers status information into the SO buffer. Rising edge of the CS initiates the following operation: Disables the SO driver (high-impedance) Activates the received command word, allowing the 33810 to activate/deactivate output drivers. To avoid any spurious data, it is essential that the high-to- low and low-to-high transitions of the CS signal occur only when SCLK is in a logic low state. Internal to the 33810 device is an active pull-up to VDD on CS. SERIAL INPUT DATA (SI) The SI pin is used for serial instruction data input. SI information is latched into the input register on the rising edge of SCLK. A logic high state present on SI will program a one in the command word on the rising edge of the CS signal. To program a complete word, 16 bits of information or multiples of 8 there of must be entered into the device. SERIAL OUTPUT DATA (SO) The SO pin is the output from the shift register. The SO pin remains tri-stated until the CS pin transitions to a logic low state. All normal operating drivers are reported as zero, all faulted drivers are reported as one. The negative transition of CS enables the SO driver. The SI / SO shifting of the data follows a first-in-first-out protocol, with both input and output words transferring the most significant bit (MSB) first. OUTPUT ENABLE (OUTEN) The OUTEN pin is an active low input. When the OUTEN pin is low, all the device outputs are active. The outputs are all disabled when OUTEN pin is high. SPI and parallel communications are still active in either state of OUTEN. FEEDBACK VOLTAGE SENSOR (FB0-FB3) The FBx pin has multiple functions for control and diagnostics of the external MOSFET/IGBT Ignition gate driver. In Ignition (IGBT) Gate Driver Mode, the feedback inputs monitor the IGBT's collector voltage to provide the spark duration timer control signal. The spark duration timer monitors this input to determine if the secondary clamp function should be activated. In secondary clamp mode, the IGBT's collector voltage is internally clamped to V PWR+11V. In the General Purpose Gate Driver mode, this input monitors the drain of an external MOSFET to provide short- circuit and open circuit detection by monitoring the MOSFET's drain to source voltage. The filter timer and threshold voltage are easily programmed through SPI (See tables 18 and 19 for SPI messages). In General Purpose Gate Driver mode the FBx pin also provides a drain to gate clamp for fast turn off of inductive loads and external MOSFET protection. GATE DRIVER OUTPUT (GD0-GD3) The GDX pins are the gate drive outputs for an external MOSFET or IGBT. Internal to the device is a Gate to Source resistor designed to hold the external device in the OFF state while the device is in the POR or SLEEP state.

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FUNCTIONAL PIN DESCRIPTION LOW SIDE INJECTOR DRIVER OUTPUT (OUT0 - OUT3) OUT0 - OUT3 are the Open drain low side (Injector) driver outputs. The drain voltage is actively clamped during turn off of inductive loads. These outputs can be connected in parallel for higher current loads provided the turn off energy rating is not exceeded. RESISTOR SENSE POSITIVE (RSP) Resistor Sense Positive - Positive input of a current sense amplifier. The ignition coil current is monitored by sensing the voltage across an external resistor connected between RSP and RSN. The output of the current sense amplifier feeds the inputs of the NOMI and MAXI comparators. Note: RSN and RSP must be grounded in V10 mode. RESISTOR SENSE NEGATIVE (RSN) Resistor Sense Negative - Negative input of a current sense amplifier. The ignition coil current is monitored by sensing the voltage across an external resistor connected to RSP and RSN. The output of the current sense amplifier feeds the inputs of the NOMI and MAXI comparators. Note: RSN and RSP must be grounded in V10 mode. NOMINAL IGNITION COIL CURRENT (NOMI) Nominal ignition coil current output flag. This output is asserted when the output current exceeds the level selected by the DAC. NOMI can be configured as an input pin for V10 mode applications where the gate drive needs to be latched off by another device’s MAXI current sense amplifier output. The NOMI input will latch off gate drivers 5 and 6 when configured as a V10 mode ignition gate driver See Figure 10. SPARK DURATION OUTPUT (SPKDUR) SPKDUR is the Spark Duration output. This open drain output is low while feedback inputs FB0 through FB3 are above the programmed spark detection threshold. This output indicates an ignition flyback event. Each feedback input (FB0 - FB3) is logically OR'd to drive the SPKDUR output. There is a 50μA pull up current source connected internally to the SPKDUR pin. MAXIMUM IGNITION COIL CURRENT (MAXI) Maximum ignition coil current output flag. This output is asserted when the output ignition coil current exceeds the selected level of the DAC. This signal also latches off the gate drive outputs when configured as an ignition gate driver. The MAXI current level is determined by the voltage drop across an external sense resistor connected to pins RSP and RSN. MAXI can be configured as an input pin for V10 applications where the gate drive needs to be latched off by another devices MAXI current sense amplifier output. The MAXI input will latch off gate drivers 7 and 8 when configured as ignition gate drive outputs See Figure 10. DRIVER INPUT (DIN0-DIN3), GATE DRIVER INPUT (GIN0-GIN3) Parallel input pins for OUT0-OUT3 low side drivers and GD0-GD3 gate drivers. Each parallel input control pin is active high and has an internal pull-down current sink. The parallel input data is logically OR’d with the corresponding SPI input data register contents, except for the ignition mode IGBT drivers. They are only controlled by the parallel inputs GIN0-GIN3. In GPGD mode, GIN0-GIN3 are logically OR’d with SPI input data. All outputs are disabled when the OUTEN pin is HIGH, regardless of the state of the command inputs.

Figure 4. Functional Internal Block Diagram frequency transients from causing a POR. regardless of the state of the command inputs. while the device is in the POR or Sleep State.

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quiescent current sleep mode. prevent high frequency transients from causing a POR. based on the state of the command register or parallel input. Table 5. Operational States removed from the VDD pin. In Sleep State all outputs are off.

• All outputs off
• IGNITION gate driver mode enabled (IGBT Ignition Mode).
• PWM frequency and duty cycle control disabled.
• Off State open load detection enabled (LSD)
• MAXI dac set to 14 A, NOMI DAC set to 5.5A
• Spark detect level VIL DAC set to V PWR +5.5V
• Open secondary timer set to 100 μs
• Dwell timer set 32ms
• Soft shutdown disabled
• Low-voltage flyback clamp disabled
• Dwell overlap MAXI offset disabled MODES OF OPERATION In Normal State, the 33810 gate driver has three modes of operation, ignition Mode, GPGD (General Purpose Gate Driver) Mode and V10 mode.The operating mode of each gate driver may be set individually and is programmed using the Mode Select Command. MODE SELECT COMMAND The MODE Select Command is used to set the operating mode for the GDx gate driver outputs, over/under-voltage operation and to enable V10 Mode and the PWM generators. The Mode Select Command programmable features are listed below.
• Ignition/GPGD Mode select (gate drivers)
• V10 Mode enable
• Over/Under-voltage operation for all drivers
• GPGD PWM controller enable IGNITION/GPGD MODE SELECT The Ignition/General Purpose Gate Driver Mode select bits determine independently, the operating mode of each of the GDx gate driver outputs. Bits 8,9,10,11 correspond to GD0, GD1, GD2, GD3 respectively. Setting the bit to a logic 0 sets the GDx driver to the Ignition Mode. Setting the bit to a logic 1 commands the GDX driver to the General Purpose Mode and disables the ignition features for that particular gate driver (except the MAXI current shutdown feature). Further information on GDx gate driver in Ignition Mode and General Purpose Mode is provided later in this section of the data sheet. V10 MODE ENABLE BIT The V10 Enable bit allows the user to configure the device for 10 cylinder applications. When the V10 Mode is enabled, the device configures the NOMI pin and MAXI pin as digital inputs rather than outputs. The new MAXI input pin receives

Analog Integrated Circuit Device Data Freescale Semiconductor 17 33810 FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES the MAXI shutdown signal for GD0 and GD2 and the new NOMI input pin receives the MAXI shutdown signal for GD1 and GD3. Further information on V10 Mode is provided in the Note: RSN and RSP must be grounded in V10 Mode. OVER/UNDER-VOLTAGE SHUTDOWN/RETRY BIT The Over/Under-voltage Shutdown/Retry bit allows the user to select the global over and under-voltage fault strategy for all the outputs. In an over-voltage or under-voltage condition on the VPWR pin, all outputs are commanded off. The Over/Under-voltage control bit sets the operation of the outputs when returning from over/under- voltage. Setting the Over/Under-voltage bit to logic [1] will force all outputs to remain OFF when VPWR returns to normal level. To turn the output on again, the corresponding input pin or SPI bit must be reactivated. Setting the Over/Under-voltage bit to logic [0] will command all outputs to resume their previous state when VPWR returns to normal level. Table 6 below provides the output state when returning from over or under-voltage. Table 6. GINx DINx Input Pin SPI Bit Over/ Under- voltage Control Bit OUTEN Input pin State When Returning From Over/Under-voltage X X X 1 OFF X X 1 0 OFF 0 0 0* 0 OFF X 1 0* 0 ON

1 X 0* 0 ON

• Default Setting Over-voltage/Under-voltage Truth Table Note: The SPI bit does not control the Gate Driver outputs in th e Ignition Mode, only in the GPGD Mode. An under-voltage condition on VDD results in the global shutdow n of all outputs and reset of all internal control registers. The VDD under-voltage threshold is between 0.8V and 2.8V PWMX ENABLE BIT Gate Driver outputs programmed as General Purpose Gate Drivers may be used as low frequency PWM outputs. The PWM generators are enabled via bits 0 through 3 in the Mode Select Command. Bits 0 through 3 correspond to outputs GD0 through GD3 respectively. Once the frequency and duty cycle are programmed through the PWM Frequency & DC command, the PWM output may be turned ON and OFF through the PWM enable bit. Further information on PWM control is provided in the General Purpose Gate Driver Mode section of this data sheet. IGNITION (IGBT) GATE DRIVER MODE The MC33810 contains dedicated circuitry necessary for automotive ignition control systems. Each gate driver may be individually configured as an Ignition Gate Driver with the following features:
• Spark duration signal
• Open secondary timer
• Soft shutdown control
• Low-voltage flyback clamp
• Ignition ignition coil current measurement
• MAXI output and control
• NOMI output
• Maximum dwell timer In the Ignition Mode, several control strategi es are in place to control the IGBT for enhanced system performance. Information acquired from the FBx pin allows the device to produce a spark duration signal output (SPKDUR) and detect open secondary ignition coils. Based on the FBx signal and Spark Command register settings, the device performs the appropriate gate control (Low-voltage Flyback Clamp, Soft Shutdown) and produces the SPKDUR output. The FBx pin is connected to the collector of the IGBT throug h an external 9:1 resistor divider network. The recommended values for the resistor divider network is 36K and 4.02K, with the 36K resistor connected from the IGBT collector to the FBx pin and the 4.02K resistor connected from the FBx pin to ground. Additional controls to the gate driver are achieved by sensi ng the current through the external IGBT. The Resistor Sense Positive (RSP) and Resistor Sense Negative (RSN) inputs are use to measure the voltage across an external 20 mΩ or 40 mΩ current sense resistor. A gain select bit in the Spark Command SPI Command messages should be set to 1 (gain of 2) when using a 20 mΩ current sense resistor. Wh en using a 40 mΩ current sense resistor, the gain select bit should be set to 0 (gain of 1 is the default value). The ignition coil current is compare d with the output of the DACs which have been programmed via the SPI Commands. The comparison generates the Nominal Current signal (NOMI) and the Maximum Current signal (MAXI). Both signals have a low output when the ignition coil current is below the programmed DAC value and a high output when the current is above the programmed DAC value. When the GDx output is shutdown b ecause of the control strategy, the output may be activated again by toggling the input control. SPARK COMMAND The Spark Command is an ignition mode command used to program the parameters for the ignition mode features listed below:
• End spark threshold (EndSpa rkTh bits)
• Open secondary fault timer (OSFLT bits)

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• Secondary clamp (secondary clamp bit)
• Soft shutdown enable (SoftShutDn bit)
• Ignition ignition coil current amplifier gain (Gain Sel bit)
• Overlapping dwell disable (Overlap Dwell Disable bit)
• Maximum dwell enable (MaxDwellEn bit)
• Maximum dwell timer (MaxDwellTimer bits)
• End of spark filter timer value Spark Command address and data bits are listed in Table NOTE: Gate driver outputs programmed to be General Purpose Gate Drivers are not affected by the Spark Commands. SPARK DURATION SIGNAL The Spark Duration is defined as the beginning of current flow to the end of current flow across the spark plug gap. Because the extremely high-voltage ignition coil secondary output is difficult to monitor, corresponding lower voltage signals generated on the ignition coil primary are often used. The FBx pins monitor the ignition coil primary voltage (IGBT Collector) through a 10 to 1 voltage divider. When the IGBT is disabled, the rise in the FBx signal indicates a sparkout condition is occurring at the spark plug gap. The device considers the initial thresholds for spark dura tion to be VIH = VPWR + 21 V for rising edge as measured on the col lector of the IGBT. The spark duration falling edge reference is programmable via SPI through the End Spark Threshold bits 0 and 1 (See Table 7). Figure 5 illustrates a typical ignition event with dwell time and spark duration indicated. Figure 5. SPKDUR~3.0ms DWELL Time Ignition Coil Current, Channel 1: GINx IGBT Gate Drive Channel 2: IGBT Collector Voltage Channel 3: IGBT Current @ 5.0A/Div 5.0A/div Ignition Coil Charge and Spark Event VPWR = 16.0V Default settings Begin spark threshold VIH = VPWR + 21V End spark threshold VIL = VPWR +5.5V The pulse width of the SPKDUR signal is measured by the MCU timer/input capture port to determine the actual spark duration. Spark duration information is then used by the MCU spark control algorithm to optimize the dwell time.

Table 7. End Spark Threshold dary fault condition signature.

ary threshold is VIL = 135V. Table 8. Open Secondary Timer period of time than if the internal IGBT clamp were used. clamp. The internal clamp only provides the bias to the IGBT.

13 V 53 V

asserting control bit 5 in the Spark Command message. wn control of the gate driver.

• OUTEN = High (Outputs Disabled)
• Over-voltage on VPWR pin

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• Max dwell time Soft Shutdown is designed to prevent an ignition spark whil e turning off the external IGBT. The Low-voltage Clamp is activated to provide the mechanism for a soft shutdown. GAIN SELECT BIT The ignition coil current comparators are used to compare the programmed NOMI and MAXI DAC value with voltage across the external current sense resistor. When selecting a gain of two, the ignition coil current sense resistor must be reduced from 40mΩ to 20mΩ. OVERLAPPING DWELL ENABLE BIT Overlapping dwell occurs when two or more ignition mode drivers are commanded ON at the same time. In this condition, with the Overlapping Dwell Bit enabled the MAXI DAC threshold value is increased as a percentage of the nominal programmed value. The percent increase is determined by bit 5 through bit 7 of the DAC Command.

Table 9. Overlapping Dwell Compensation

1. The Max Dwell Timer feature pertains to Ignition Mode only

Table 10. Maximum Dwell Timer bit 6 =0. This is also the default value. V10 Mode application section of this data sheet.

Table 11. Nominal Current DAC Select ition drivers when the DAC MAXI setting is exceeded. register is set and the MAXI pin is asserted (High). bit 6 =0. This is also the default value. status register has been read by the MCU.

Table 12. Maximum Current DAC Select

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ringing at the end of spark.

1. End of Spark Filter Time Select

and duty cycle output (PWM).

• Gate driver for discrete external MOSFET
• Off state open load detect
• On state short circuit protection
• Programmable drain threshold and duration timer for short fault detection
• PWM frequency/duty cycle controller In GPGD Mode the GDx output is a current controlled ou tput driver with slew rate control, gate to source clamp, passive pull-down resistor and a drain to gate clamp for switching inductive loads. Driver ON /OFF Command The Driver ON/OFF Command, bits 4 through 7 control ga te drivers that have been Mode Select Command programmed as GPGD. A logic 1 in bits 4 through 7 will command the specific output ON. A logic 0 in the appropriate bit location commands the specific output Off. Also contained in the Driver ON/OFF Command are SPI control bits for the integrated LSD output drivers. Further information on LSD control is provided in the Low Side Injector Driver section of the data sheet. NOTE: Gate drivers programmed to IGNITION mode have pa rallel input control only, and cannot be turned off and on via SPI commands. GPGD Short Threshold Voltage Command Each GPGD driver is capable of detecting an open load in the off state and shorted load in the on state. All faults are reported through the SPI communication. For open load detection, a current source is placed between the FBx pin and ground of the IC. An open load fault is reported when the FBx voltage is less than the 2.5 V threshold. Open load fault de tect threshold is set internally to 2.5 V and may not be prog rammed. A shorted load fault is reported when the FBx pin voltage is greater than the programmed short threshold voltage. The short to battery fault thresho ld voltage of the external MOSFET is programmed via the GPGD Short Threshold Voltage Command. Table 14 illustrates the bit pattern to select a particular threshold. Drain voltages less than the se lected threshold are considered normal operation. Drain voltages greater than the selected threshold voltage are considered faulted.

Table 14. FBx Fault Threshold Select

110 No Change

111 No Change

Table 15. FBx Short Fault Timer a programmed “inhibit time”. than 120μs), the GDx output driver will be forced off for 12ms. result in another 12ms shutdown period. shutdown and remain off when the short fault is declared. force the output to try and turn on again. and commanded ON again at the next PWM cycle. the minimum duty cycle ON time of the PWM controller. the next PWM rising edge time. set GD1, PWM output to 10Hz and 12% duty cycle.

24 Freescale Semiconductor

Table 16. Frequency Select

1 X 1 1 Freq/DC

two driver(s) from the V10 device.

• NOMI/MAXI configured as input pins
• MAXI shutdown for GPGD disabled
• NOMI/MAXI comparators disabled In V10 Mode, Spark Command bits 7 and 8 (Gain Select, Ove rlapping Dwell) are disabled. These two features are achieved through the Normal Mode devices. RSN and RSP must be grounded in V10 Mode.

4 GIN (0-3)

4 GIN

Figure 10. V10 Mode (Ignition Mode, General Purpose Mode, V10 mode). Command turn ON or OFF the specific output driver. bits 0 through 7 set the open load strategy.

Analog Integrated Circuit Device Data

26 Freescale Semiconductor

FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES protection circuit uses the junction temperature of the output driver to determine the fault. Both methods may be used together or individually. TIMER PROTECTION The first protection scheme uses a low ON to OFF duty cycle to protect the output driver. The low duty cycle allows the device to cool so that the maximum junction temperatures are not exceeded. During a short condition, the device enters current limit. The driver will shutdown for short conditions lasting longer than the current limit timer (~60μs) TEMPERATURE LIMIT (TLIM) The second scheme senses the temperature of the individual output driver. During a short event the device enters current limit and will remain in current limit until the output driver temperature limit is exceeded (TLIM). At this point, the device will shutdown until the junction temperature falls below the hysteresis temperature value. The TLIM hysteresis value is listed in the previous specification tables. The third method combines both protection schemes into one . During a short event the device will enter current limit. The output driver will shutdown for short conditions lasting longer than the current limit timer. In the event that the output driver temperature is higher than maximum specified temperature the output will shutdown. The Shutdown/Retry bit allows the user to determine how th e drivers will respond to each short circuit strategy. Table 18 provides fault operation for all three strategies. Outputs may be used in parallel to drive higher current loa ds provided the turn-off energy of the load does not exceed the energy rating of a single output driver (100mJ maximum). Table 18. Shutdn Retry Bit 11 TLIM Bit 10 Fault Timer Bit 9 Operation During Short Fault 1 0 X Timer only, Outputs will retry on period OUT0-OUT3 = 60μs ON, ~10ms OFF 1 1 0 TLIM only, Outputs will retry on TLIM hysteresis. 1 1 1 Timer and TLIM, Outputs will retry on period and driver temperature below threshold. OUT0-OUT3= 60μs ON, ~10ms OFF 0 0 X Timer only, Outputs will not retry on period OUT0-OUT3 = 60μs ON, OFF 0 1 0 TLIM only, Outputs will not retry on TLim hysteresis. 0 1 1 Timer and TLIM, Outputs will not retry on period or TLIM. OUT0-OUT3 = 60μs ON, OFF Injector Driver (OUTx) Fault Operation OUTPUT DRIVER DIAGNOSTICS. Short to battery, Temperature Limit (TLIM) and open load faults are reported through the All Status Response message Table 21. OFF OPEN LOAD PULL-DOWN CURRENT ENABLE BITS An open load on the output driver is detected by the voltage level on the drain of the MOSFET in the off state. Internal to the device is a 75μA pull-down current sink. In the event of an open load the drain voltage is pulled low. When the voltage crosses the threshold, and open load is detected. The pull-down current source may be disabled by bit 0 through bit 3 in the LSD Fault Command. With the driver off and the Off Open Load bit disabled, the Off Open Load fault status bit will be logic 0. ON OPEN LOAD ENABLE BITS The On State Open Load enable bit allows the user to determine an On State Open Load. When the On State Open Load bit disabled, the On State Fault bit is always logic 0. On Open Load is determined by monitoring the current through the OUTx MOSFET. In the ON state, currents less than 20 to 200mA are considered open.

0 X Off STB 0 0 0 No Fault

0 X Off STG 0 0 0 No Fault

0 X Off OPEN 0 0 0 No Fault

1 X Off STB 0 0 0 No Fault

1 X Off STG 0 1 0 Open Load

1 X Off OPEN 0 1 0 Open Load

device at any time in NORMAL STATE. Table 20. SPI Command Message Set and Default State

28 Freescale Semiconductor

Fault reporting is accomplished through the SPI interface. Table 21. SPI Response Messages

1. These bits refer to command On or Off state in the command re gisters, not the state of the respective output lines. These bits are not to be

confused with the ignition mode state which is controlled only by the parallel inputs and their state is not reflected in these bits.

30 Freescale Semiconductor

NMF = Set When Faults Occur on V10 Mode MAXI and NOMI Inputs and V10 Mode Ignition Driver are OFF.

Analog Integrated Circuit Device Data Freescale Semiconductor 31 33810 PACKAGING PACKAGE DIMENSIONS PACKAGING PACKAGE DIMENSIONS For the most current package revision, visit www.freescale.com and perform a keyword search using the “98A” listed below. EK (Pb-FREE) SUFFIX 32-PIN 98ASA10556D ISSUE D

Analog Integrated Circuit Device Data

32 Freescale Semiconductor

EK (Pb-FREE) SUFFIX 32-PIN 98ASA10556D ISSUE D

EK (Pb-FREE) SUFFIX 32-PIN 98ASA10556D ISSUE D Analog Integrated Circuit Device Data Freescale Semiconductor 33 33810 PACKAGING PACKAGE DIMENSIONS

Analog Integrated Circuit Device Data

34 Freescale Semiconductor

REVISION HISTORY

REVISION DATE DESCRIPTION OF CHANGES 3.0 10/2007 • Initial Release 4.0 2/2008 • Fixed several typos throughout document

• Changed Static Electrical Characteri sti cs, Table 3, Digital Interface, OUT_EN Leakage Current to VDD, maximum from 10 to 50μA.
• Reworded Table 15.
• Added Table 16 back (it was inadvertently deleted.
• Added “Ignition &” to tile in Table 4. 5.0 8/2008 • Updated package drawing. 6.0 12/2008 • Parameter changes to Gate Drive Source Current, Spark Duration Comparator Threshold, NOMI Trip Threshold Accuracy, MAXI Trip Point During Overlapping Dwell, Comparator Hysteresis Voltage, Short to Battery Fault Detection Voltage Threshold, Output OFF Open Load Detection Current, and Input Logic-voltage Hysteresis.
• Made change to End of Spark Filter Time Select
• Changed orderable Part Number from PCZ 33810EK/R2 to MCZ33810EK/R2 on Page 1.
• Revised Exposed Pad pin definition in Table 1, page 3.
• Changed Package outline drawing to 98ASA10556D. 7.0 7/2010 • Changed introduction paragraph to Tables 3 and 4 from “9.0 V ≤ VPWR ≤ 18 V” to “6.0 V ≤ VPWR ≤ 32 V”
• Changed Gate Driver Parameters of V GS (ON) from 5.0 to 4.8.

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