33800

33800 FREESCALE | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 39

Technical content

Features

• Wide operating voltage range, 5 < VPWR < 36V
• Interfaces to 3.3V and 5V microprocessors via SPI protocol
• Low, Sleep Mode, standby current, typically 10uA.
• Internal or external voltage reference
• Internal oscillator with calibrate capability
• Measures resistance to monitor HEGO sensors
• CCDs have programmable current, dither frequency and amplitude
• OSSs can be paralleled to increase current capability
• GDs have programmable fr equency and duty cycle PWM
• All outputs controllable via serial and/or parallel inputs
• Pb-free packaging designated by suffix code EK

Figure 1. MC33800 Simplified Application Diagram

ORDERING INFORMATION

Range (TA) Package MCZ33800EK/R2 -40°C to 125°C 54 SOICW EP VDD VPWR DEFAULT VDD SI SO SCLK CS MOSI MISO AN0 OUT1 33800 SCLK CS GND VBAT OUT8 CCD1_OUT CCD2_OUT VPWR VBAT VBAT VDSNS1 GD1 GD6 PWM1 PWM6 CCD1_REC CCD2_REC MCU VCAL REXT RI_REF LRFDBK P1,P3,P5,P7 2.5V VDSNS6 EN VSSNS456 VSSNS123 VPWR

2 Freescale Semiconductor

Figure 2. 33800 Simplified Internal Block Diagram

Figure 3. 33800 Pin Connections Table 1. 33800 Pin Definitions A functional description of each pin can be found in the Functional Pin Description section beginning on page 16.

8 LRFDBK Output Load Resistance

The LRFDBK pin is an operational amplifier output. transitions on the falling edge of SCLK. and SO Pins while being addressed by the CS.

11 CS Input Chip Select The Chip Select input pin is an active low signal sent by the MCU to

logic levels and has an internal active pull up current source. be used to control OSS output 1 and output 2 in parallel. be used to control OSS output 3 and output 4 in parallel. be used to control OSS output 5 and output 6 in parallel.

4 Freescale Semiconductor

be used to control OSS output 7 and output 8 in parallel. controller. Control strategy is programmed via the SPI.

22 CCD2_GND Ground CCD2 Ground The CCD2_GND pin provides a dedicated ground for the CCD2 constant

23 CCD2_OUT Output Current Controlled

current source and is used for fault threshold monitoring.

24 CCD2_REC Input Current Controlled

The CCD2_REC pin provides a recirculation path for the load current. 25 EN Input ENABLE The EN pin is an active high input.

26 RI_REF Output Resistor for Current

1075mA and the CCD2 to be 232mA.

27 CCD1_OUT Output Current Controlled

current source and is used for fault threshold monitoring.

28 CCD1_REC Input Current Controlled

The CCD1_REC pin provides a recirculation path for the load current.

29 CCD1_GND Ground CCD1 Ground The CCD1_GND pin provides a dedicated ground for the CCD1 constant

and other internal functions such as the oscillator and SPI circuits. should be used for decoupling of VDD and VPWR supply.

32 VCAL Input Voltage Calibrated

decoupling capacitor is required on the VCAL input pin to ground.

34 SO Output Serial Output Data The SO output pin is used to transmit serial data from the device to the

MCU. The SO pin remains tri-stated until selected by the active low CS. edge of SCLK. The SO data transitions on falling edge of the SCLK. 35 DEFAULT Input Default Mode Enable The DEFAULT pin is an active high input. OUT1-OUT8 Output OSS Output 1-8 Octal Serial Switch (OSS) low side driver output 1-8. Table 1. 33800 Pin Definitions(continued) A functional description of each pin can be found in the Functional Pin Description section beginning on page 16.

39 PGND3 Ground OSS 3-8 Ground This PGND pins provide a dedicated ground for the Octal Serial Switch

(OSS) low side driver outputs 3 - 8.

44 PGND2 Ground OSS 2 Ground This PGND pin provides a dedicated ground for the Octal Serial Switch

(OSS) low side driver output 2.

46 PGND1 Ground OSS 1 Ground This PGND pin provides a dedicated ground for the Octal Serial Switch

(OSS) low side driver output 1.

47 REXT Output Resistor External

The REXT pin is used to generate a reference current. should be grounded to system ground. A functional description of each pin can be found in the Functional Pin Description section beginning on page 16.

Analog Integrated Circuit Device Data

6 Freescale Semiconductor

ELECTRICAL CHARACTERISTICS

Table 2. Maximum Ratings permanent damage to the device.

1. ESD data available upon request. All pins te sted individually. ESD1 testing is performed in accordance with the Human Body Model

(AEC-Q100-002). and the Machine Model (AEC-Q100-003).

1. Maximum power dissipation at T J =150°C junction temperature with no heat sink used.
2. This parameter is guaranteed by design but is not production tested.

Analog Integrated Circuit Device Data Freescale Semiconductor 7 33800 STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics

1. Over-voltage thresholds minimu m and maximum include hysteresis.
2. Under-voltage thresholds minimu m and maximum include hysteresis.
3. Using the internally generated V CAL increases all applicable parametric tables by +- 10%

Analog Integrated Circuit Device Data

8 Freescale Semiconductor

STATIC ELECTRICAL CHARACTERISTICS CONSTANT CURRENT SOLENOID DRIVER OUTPUT (CDD1_OUT) (CONTINUED) Programmable Dither Amplitude Peak to Peak Programmable from 0.0mA to 350mA in 50mA increments IDITHER -10 10 CCD1 Fault Detection Voltage Threshold Outputs Programmed OFF VOUT(FLTTH) 2.0 2.5 3.0 V CCD1 Output Clamp Voltage Outputs Programmed OFF VOC 50 55 60 V CCD1 Output Self Limiting Current IOUT (LIM) 1.5 – 2.8 A CCD1 Output Leakage Current Pull-up enabled, Dither Off, CCD1OUT = VOC - 1.0V Pull-up enabled, Dither Off, CCD1OUT = VPWR = 24V ICCD1 (LKG) – – 8000 µA CCD1 Pull Up Current Pull-up enabled, DAC = 000, CCD1OUT = CCD1REC = 2.0V ICCD1(PULLUP) -60 -40 -20 µA CCD1 Pull Down Current Pull-up disabled, DAC = 000, CCD1OUT = CCD1REC = 2.0V ICCD1(PULLDOWN) 20 40 60 µA CONSTANT CURRENT SOLENOID DRIVER OUTPUT (CCD2_OUT) Drain-to-Source ON Resistance TJ = 125°C, VPWR = 13V TJ = 25°C, VPWR = 13V TJ = -40°C, VPWR = 13V RDSON 1.0 2.0 Ω Internal Current Sense Resistor DAC Value = 000, VCCD2REC = 0V, ICCD2OUT = 100mA RSENSE = VCCD2OUT / ICCD2OUT RSENSE 3.5 5.0 Ω Current Regulation DAC Value = 17C HEX +/- (4%) DAC Value = 05F HEX +/- (10%) Load Resistance = 32Ω, Load Inductance = 130mH, Dither Off ICCD2 166 38.9 173 43.2 180 47.5 mA Programmable Dither Frequency Programmable from 50Hz to 500Hz in 50Hz Increments after Calibration fDITHER -10 10 Programmable Dither Amplitude Peak to Peak Programmable from 0.0mA to 90mA in 10.9mA increments IDITHER -10 10 CCD2 Fault Detection Voltage Threshold Outputs Programmed OFF VOUT(FLTTH) 2.0 2.5 3.0 V CCD2 Output Clamp Voltage Outputs Programmed OFF VOC 50 55 60 V CCD2 Output Leakage Current Pull-up enabled, Dither Off, CCD2OUT = VOC - 1.0V Pull-up enabled, Dither Off, CCD2OUT = VPWR = 24V ICCD2 (LKG) – – 8000 µA CCD2 Output Self Limiting Current IOUT (LIM) 0.5 – 1.0 A

Analog Integrated Circuit Device Data Freescale Semiconductor 9 33800 STATIC ELECTRICAL CHARACTERISTICS CONSTANT CURRENT SOLENOID DRIVER OUTPUT (CCD2_OUT) (CONTINUED) CCD2 Pull Up Current Pull-up enabled, DAC = 000, CCD1OUT = CCD1REC = 2.0V ICCD2(PULLUP) -60 -40 -20 µA CCD2 Pull Down Current Pull-up disabled, DAC = 000, CCD2OUT = CCD2REC = 2.0V ICCD2(PULLDOWN) 20 40 60 µA OCTAL SERIAL DRIVERS (OUT1 - 8) Drain-to-Source ON Resistance (OUT1 - 2) IOUT = 0.350A, TJ = 125°C, VPWR = 13V IOUT = 0.350A, TJ = 25°C, VPWR = 13V IOUT = 0.350A, TJ = -40°C, VPWR = 13V RDS (ON) 0.7 1.4 Ω Drain-to-Source ON Resistance (OUT3 - 8) IOUT = 0.350A, TJ = 125°C, VPWR = 13V IOUT = 0.350A, TJ = 25°C, VPWR = 13V IOUT = 0.350A, TJ = -40°C, VPWR = 13V RDS (ON) 1.0 1.7 Ω Output Self Limiting Current Output 3 to Output 8 Output 1, Output 2 IOUT (LIM) 1.0 4.0 2.0 6.0 A Output Fault Detection Voltage Threshold.(7) Outputs Programmed OFF VOUT(FLTTH) 2.0 2.5 3.0 V Output OFF Open Load Detection Current VDrain = 18V, Outputs Programmed OFF IOCO 40 75 100 µA Output Clamp Voltage Low Side Drive ID = 20mA VOC 50 55 60 V Output Leakage Current VDD = 5.0V, VDrain = 24V, Open Load Detection Current Disabled VDD = 5.0V, VDrain = VOC - 1.0V, Open Load Detection Current Disabled VDD = 0V, VDrain = 24V, Device Disabled IOUT (LKG) 3000 µA Over-temperature Shutdown(8) TLim 155 – 185 °C Over-temperature Shutdown Hysteresis(8) TLim (HYS) 5.0 10 15 °C SPI DIGITAL INTERFACE (SO, SI, CS, SCLK) Input Logic High-voltage Thresholds(8) VIH 0.7 x VDD – VDD + 0.3 V Input Logic Low-voltage Thresholds(8) VIL GND - 0.3 – 0.2 x VDD V Input Logic Voltage Hysteresis(8) VHYS 100 – 300 mV Input Logic Capacitance(8) CIN – – 20 pF Sleep Mode Input Logic Current(8) VDD = 0.0V I LOGICSS -10 – 10 µA Notes 7. Output fault detection thresholds with outputs programmed OFF. Output fault detect thresholds are the same for output open and shorts. 8. This parameter is guaranteed by design, however is not production tested.

Analog Integrated Circuit Device Data

10 Freescale Semiconductor

STATIC ELECTRICAL CHARACTERISTICS SPI DIGITAL INTERFACE (SO, SI, CS, SCLK) (CONTINUED) Sleep Mode EN and DEFAULT Input Current VD D = 0.0V, VEN = 5.0V, VD E FA U LT = 5.0V I LOGICSS -10 – 10 µA Normal Mode Input Logic Pull-down Current(9) 0.8V to 5.0V ILOGICPD 5.0 15 25 µA Normal Mode DEFAULT Pull-up Current IDEFAULTPU -5.0 – -25 µA SCLK, Tri-state SO Output 0.0V to 5.0V I SCLK, I TRISO -10 – 10 µA CS Input Current CS = VDD ICS -10 – 10 µA CS Pull-up Current CS = 0.0V ICSPU -5.0 – -30 µA CS Leakage Current to VDD CS = 5.0V, VDD = 0.0V ICS(LKG) – – 10 µA SO High-state Output Voltage ISOHIGH = -1.0mA VSOHIGH VDD - 0.4 – – V SO Low-state Output Voltage ISOLOW = 1.0mA VSOLOW – – 0.4 V EN Input Pull-down Current EN = VDD IENPD 10 50 100 µA PREDRIVER OUTPUT FUNCTION (GD1 - GD6) Gate Drive Output Voltage IGATEDRIVE = 100µA IGATEDRIVE = - 100µA V GS (ON) V GS (OFF) 5.0 7.0 0.2 9.0 0.5 V Gate Drive Sink and Source Current I GATEDRIVE – 2.0 5.0 mA Sleep Mode Gate to Source Resistor R GS (PULLDOWN) 65 200 300 KΩ Short Fault Detection Voltage Threshold VDD = High, Outputs Programmed ON Programmable from 0.5V to 3.0V in 0.5V increments. VDS(FLTTH) -20% +20% V Open Fault Detection Voltage Threshold VDD = High, Outputs Programmed OFF VDS(FLTTH) 2.0 2.5 3.0 V Notes 9. Parameter applies to P1, P3, P5, P7, PWM1 to PWM6, SI and VCAL, and are guaranteed by design.

Analog Integrated Circuit Device Data Freescale Semiconductor 11 33800 STATIC ELECTRICAL CHARACTERISTICS PREDRIVER OUTPUT FUNCTION (GD1 - GD6) (CONTINUED) Drain Sense Fault Detection Current Gate Drive Off, VDS = 18V IDSNS(flt-sns) 40 180 400 µA Output Clamp Voltage Driver Command Off, VGATE = 2.0V VOC 50 55 60 V Sleep Mode Drain Sense Leakage Current VDD = 0.0V, VDSNS = 24V, IDSNS (LKG) – – 25 µA Load Resistance Feedback Accuracy Sample and Hold After 150ms REXT = 24ohm, RLOAD = 10ohm, LRFDBK = VCAL*2.5*(RLOAD/REXT) LRFBCKACC -10% 2.6 +10% V Load Resistance Feedback Output Voltage (VDSNS1 - VDSNS2) ≥ 10V, PWM Diagnostics Select = 0001 LRFBCKMax 6.0 V

Analog Integrated Circuit Device Data

12 Freescale Semiconductor

DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 4. Dynamic Electrical Characteristics than threshold for specified time. Fault is detected with driver off and voltage threshold is not achieved. than threshold for specified time.

1. Assumes oscillator has been cali brated using SPI Calibrate Command.

Analog Integrated Circuit Device Data Freescale Semiconductor 13 33800 DYNAMIC ELECTRICAL CHARACTERISTICS OCTAL SERIAL DRIVERS (OUT1 - OUT8) (CONTINUED) Output Off Open Circuit Fault Filter Timer(11) tOC 400 500 650 µs Output Slew Rate RLOAD = 51Ω RLOAD = 51Ω t SR(RISE) t SR(FALL) 1.0 1.0 5.0 5.0 V/µs P1 Input Propagation Delay Input @ 50% VDD to Output voltage 10% of final value Input @ 50% VDD to Output voltage 90% of initial value t(RISEDELAY) t(FALLDELAY) 6.0 6.0 µs P3, P5, P7 Input Propagation Delay Input @ 50% VDD to Output voltage 10% of final value Input @ 50% VDD to Output voltage 90% of initial value t(RISEDELAY) t(FALLDELAY) 5.0 5.0 µs OSCILLATOR AND TIMER ACCURACY Calibrated Timer Accuracy(11) t TIMER – – ±10 % Un-calibrated Timer Accuracy t TIMER – – ±80 % SPI DIGITAL INTERFACE TIMING (SO, SI, CS, SCLK)(12) Required Low State Duration on VPWR for Reset(13) VPWR ≤ 0.2V t RESET 1.0 – – µs Falling Edge of CS to Rising Edge of SCLK Required Setup Time t LEAD 100 – – ns Falling Edge of SCLK to Rising Edge of CS Required Setup Time t LAG 50 – – ns SI to Rising Edge of SCLK Required Setup Time t SI (SU) 16 – – ns Rising Edge of SCLK to SI Required Hold Time t SI (HOLD) 20 – – ns SI, CS, SCLK Signal Rise Time(14) t R (SI) – 5.0 – ns SI, CS, SCLK Signal Fall Time(14) t F (SI) – 5.0 – ns Time from Falling Edge of CS to SO Low-impedance(15) t SO (EN) – – 150 ns Time from Rising Edge of CS to SO High-impedance(16) t SO (DIS) – – 150 ns Time from Falling Edge of SCLK to SO Data Valid(17) t VALID – 25 150 ns Sequential Transfer Rate Time required between data transfers tSTR 1.0 µs Notes 11. Assumes oscillator has been cali brated using SPI Calibrate Command 12. These parameters are guaranteed by design. Production test equipment uses 1MHz, 5.0V SPI interface. 13. This parameter is guaranteed by desi gn, however it is not production tested. 14. Rise and Fall time of incoming SI, CS, and SCLK signals for design consideration to prevent the occurrence of double pulsing. 15. Time required for valid output status data to be available on SO pin. 16. Time required for output states data to be terminated at SO pin. 17. Time required to obtain valid data out from SO following the fall of SCLK with 200pF load.

Analog Integrated Circuit Device Data

14 Freescale Semiconductor

DYNAMIC ELECTRICAL CHARACTERISTICS PREDRIVER OUTPUT FUNCTION (GD1 - GD6) Open Fault Detection Filter Timer(18) VDD = High, Outputs Programmed OFF VDS(FLTTH) 100 128 400 µs Short Fault Detection Filter Timer(18) VDD = High, Outputs Programmed ON Programmable from 30µs to 960µs in replicating increments. tDS(FLTTMR) -10% +10% µs Gate Drive Rise Slew Rate Cload = 1.0nF, VGS from 0.5 to 5.0V t GDSR(RISE) – 1.7 – V/µs Gate Drive Fall Slew Rate Cload = 1.0nF, VGS from 5.0 to 0.5V t GDSR(FALL) – 1.7 – V/µs PWM1 to PWM6 Input Propagation Delay Measured from PWM input at 4.5V and GDx output at 0.5V. tPWMDELAY 20 300 ns Load Resistance Feedback Output Rise Slew Rate CLOAD = 40pF t LRSR(RISE) 0.5 – 2.0 V/µs Load Resistance Feedback Output Fall Slew Rate CLOAD = 40pF t LRSR(FALL) 0.5 – 2.0 V/µs Load Resistance Sample Duration(18) tLOADSAMPLE 200 µs Load Resistance Feedback Valid (18) Time from rising edge of CS to Load Resistance measurement valid tFDBKVALID 400 us Notes 18. Assumes oscillator has been cali brated using SPI Calibrate Command.

Analog Integrated Circuit Device Data Freescale Semiconductor 15 33800 Figure 4. SPI Timing Characteristics

0.7 VDD

0.2 VDD

Analog Integrated Circuit Device Data

16 Freescale Semiconductor

FUNCTIONAL PIN DESCRIPTION FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION ANALOG VOLTAGE SUPPLY (VPWR) The VPWR pin is battery input to the 33800 IC. The VPWR pin requires external reverse battery and transient protection. Maximum input voltage on VPWR is 45V. All IC analog current and internal logic current is provided from the VPWR pin. With V DD and EN applied to the IC, the application of VPWR will perform a Power-ON Reset (POR). DIGITAL VOLTAGE SUPPLY (VDD) The VDD input pin is used to determine communication logic levels between the microprocessor and the 33800 device. Current from VDD is used to drive SO output and pull- up current for CS. VDD must be applied for Normal Mode operation. Removing VDD from the IC will place the device in Sleep Mode. Power-ON Reset will be performed with the application of VDD supply. GROUND (GND) The GND pin provides a low current analog ground for the IC. The VPWR and VDD supplies are both referenced to the GND pin. GND pin should be used for decoupling both supplies. CONSTANT CURRENT DRIVER GROUND (CCDX_GND) The Constant Current Driver Ground (CCDX_GND) pins provide dedicated grounds for the Constant Current output drivers. Both CCDX_GND1 and CCDX_GND2 grounds are isolated from the other grounds of the IC. GROUND (PGND1 - 3, CCD1_GND, CCD2_GND) There are three PGND pins associated with the OSS drivers. OUT1 driver and OUT2 driver have dedicated PGND1 & PGND2 pins. Drivers OUT3 through Driver OUT8 share one PGND3 pin. In general all ground pins must be connected together and terminated to ground on the circuit board. SOURCE VOLTAGE SENSE (VSSNS123, VSSNS456) The Source Sense Ground pins (VSSNS123, VSSNS456) provide dedicated grounds for the hex MOSFET pre-drivers. The pins are used by the IC to monitor the drain to source voltage of the external MOSFET. This pin must be connected to the source of the external MOSFET and system ground. VSSNS123 and VSSNS456 ground pins are isolated from other internal IC grounds. SERIAL CLOCK INPUT (SCLK) The system clock (SCLK) pin clocks the internal shift register of the 33800. The SI data is latched into the input shift register on the rising edge of SCLK signal. The SO pin shifts status bits out on the falling edge of SCLK. The SO data is available for the MCU to read on the rising edge of SCLK. With CS in a logic high state, signals on the SCLK and SI pins will be ignored and the SO pin is tri-state. CHIP SELECT (CS) The system MCU selects the 33800 to receive communication using the chip select (CS) pin. With the CS in a logic low state, command words may be sent to the 33800 via the serial input (SI) pin, and status information is received by the MCU via the serial output (SO) pin. The falling edge of CS enables the SO output and transfers status information into the SO buffer. Rising edge of the CS initiates the following operation: 1. Disables the SO driver (high-impedance) 2. Activates the received command word, allowing the 33800 to activate/deactivate output drivers. To avoid any spurious data, it is essential the high-to-low and low-to-high transitions of the CS signal occur only when SCLK is in a logic low state. Internal to the 33800 device is an active pull-up to VDD on CS. In cases were voltage exists on CS without the application of VDD, no current will flow from CS to the VDD pin. SERIAL INPUT DATA (SI) The SI pin is used for serial instruction data input. SI information is latched into the input register on the rising edge of SCLK. A logic high state present on SI will program a one in the command word on the rising edge of the CS signal. To program a complete word, 16-bits of information must be entered into the device. SERIAL OUTPUT DATA (SO) The SO pin is the output from the shift register. The SO pin remains tri-stated until the CS pin transitions to a logic low state. All normal operating drivers are reported as zero, all faulted drivers are reported as one. The negative transition of CS enables the SO driver. The SI / SO shifting of the data follows a first-in-first-out protocol, with both input and output words transferring the most significant bit (MSB) first. ENABLE (EN) The ENABLE pin is an active high digital input pin used to enable the device. With the EN pin low the device is in Sleep Mode. With the EN pin high, the device is in Normal Mode DD and VPWR applied). Exit from Sleep Mode initiates a

Analog Integrated Circuit Device Data Freescale Semiconductor 17 33800 FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION Power On Reset (POR). All internal registers will be placed in the reset state. The device has an Internal 100 kΩ resistor pull down on the ENABLE pin. PULSE WIDTH MODULATION (PWM) The PWM pins are control input pins for the MOSFET pre- drivers. The PWM pins provide parallel control and can be programmed for an OR function with the SPI bit or an AND function with the SPI bit (See Table 12, on page 25 for SPI message detail). Each PWM input pin has an internal 15µA pull down current source. The current sources are active when the device is in Normal Mode. DRAIN VOLTAGE SENSE (VDSNSX) The VDSNSx pin has multiple functions for control and diagnostics of the external MOSFET: 1. By monitoring the drain voltage of the external device, short circuits and open circuits are detected. The filter timer and threshold voltage are easily programmed through SPI (see Table 10, on page 23 and Table 11, on page 24 for SPI messages). 2. The VDSNSx pins are use to determine the external load resistance. Further information is provided in the Device Operation section of this specification. 3. The VDSNSx pins provide a drain to gate clamp for fast turn off of inductive loads and MOSFET protection. GATE DRIVER OUTPUTS (GDX) The GDX pins are the gate drive outputs for an external MOSFETS. Internal to the device is a Gate to Source resistor designed to hold the external MOSFET in the OFF state while the device is in POR. INPUTS (P1, P3, P5, P7) The input pins for octal serial switch outputs 1,3,5,7. Each input control pin has an internal pull down current source. Two outputs may be controlled in parallel using the PX pins See Functional Device Operation on page 25). VOLTAGE CALIBRATED INPUT (VCAL) The Voltage calibrated input (VCAL) provides the IC with a reference voltage for analog circuits. VCAL (EXT or INT) must be applied for the CCD1 and CCD2 constant current controllers and Load Resistance measurement function to operate. For applications where measurements are not critical, the VCAL pin may grounded and an internally generated reference will be used. Using the internally generated reference will add ±10% to all tolerances in the parametric table. LOAD RESISTANCE FEEDBACK (LRFDBK) The LRFDBK pin is an operational amplifier output. The amplifier output voltage is proportional to the load resistance for the selected channel. The channel is selected via the SPI. DEFAULT The DEFAULT input controls the operation of each driver to a Default Mode. The DEFAULT input must be logic 0 for full function of all output drivers. For more information on the DEFAULT operation (See Functional Device Operation on page 19). With the DEFAULT pin HIGH, the device is placed in Default Mode. The DEFAULT pin is pulled up to the VDD supply through an active pull up current source. In Default Mode the device operates in the following manner: 1. OSS outputs are disabled. 2. CCD1 and CCD2 outputs are disabled. 3. SPI ON/OFF control of GATE DRIVE (GD1 to GD6) outputs and on board PWM controllers are disabled. PWMx input control is enabled. In the Default Mode the device retains all register information and output status information. Normal operation will resume when the DEFAULT pin transitions low again and the device will operate as programmed prior to Default Mode. RESISTOR EXTERNAL REFERENCE (REXT) The reference current is used in the equation to calculate the load resistance of the PWM outputs. The load resistance measurement current is inversely proportional to REXT current. The resistor value may be changed to adjust the load measurement current. A 24 Ω resistor to ground sets the LRFDBK output to 260mV/Ω. EXPOSED PAD The silicon die is epoxy attached to the top side of the pad. Although the device does not use the pad for electrical conduction, the bottom side exposed pad of the package should be grounded.

18 Freescale Semiconductor

Figure 5. Functional Block Diagram supply the required voltages to the internal circuitry. through the use of several input command words. programmable constant current through a solenoid valve. MOSFET in the OFF state while the device is in POR.

quiescent current Sleep Modes.

• All Outputs Off
• Inputs Enabled and OR’d with SPI Bit.
• PWM Frequency and Duty Cycle Control Disabled.
• OSS Open Load Detect Current Enabled.
• OSS Outputs with Individual Control.
• Control Inputs P1,P3,P5,P 7 Enabled and OR’d with the SPI Bit.
• CCD1 Output Off, Diagnostic Pull-up Enabled, DAC = 0.
• CCD2 Output Off, Diagnostic Pull-up Enabled, DAC = 0. Power On Reset circuit incorporates a 0.5µs timer to prevent high frequency transients from causing a POR. During the low-voltage condition, internal logic states are maintained. To guarantee a POR from V PWR, the VPWR pin must be less than 0.2V for greater than 1.0µs. MODES OF OPERATION The 33800 has three operating modes, Normal, Sleep and Default Mode. A discussion on Normal Mode follows. NORMAL MODE Normal Mode allows full functional control of the device. Transferring from Sleep Mode to Normal Mode performs a POR and resets all internal registers to the POR state. When entering Normal Mode from Default Mode, no POR is performed and register states are maintained. Features programmed in Normal Mode are listed below. Further explanation of each feature is provided in subsequent paragraphs.
• Programmable PWM Frequency & Duty Cycle
• Programmable PWM Drain Fault Threshold
• CCD2 Constant Current Dit her Frequency and Amplitude
• CCD2 DAC Programming
• CCD1 Constant Current Dit her Frequency and Amplitude
• CCD1 DAC Programming
• On/Off OSS Open Load Detect Current
• Calibration of Timers ( Calibration Command )
• R e s e t (Reset Command )
• No Operation ( NO_OP Command) DEFAULT MODE The Default Mode allows the user to disable all outputs except the PWM pre-driver. In Default Mode the PWM pre- driver outputs may only be controlled via the PWM input pins. All register control bits and fault bits are maintained in Default Mode, however control for the pre-driver is accomplished through the PWM pins only. With the DEFAULT pin HIGH, the device is placed in Default Mode. When exiting Default Mode, output control reverts to the internal register settings. In Default Mode the device operates with the following parameters. 1. OSS outputs are disabled. 2. CCD1 and CCD2 outputs are disabled. 3. SPI ON/OFF control of GATE DRIVE (GD1 to GD6) outputs is disabled. PWMx input control is enabled. The device will operate as programmed prior to Default Mode. In Default Mode the device retains all register information and output status information. Normal operation will resume when the DEFAULT pin transitions low again. SLEEP MODE Sleep Mode is entered by placing a logic [0] on the ENABLE or VDD pins. All outputs are commanded off and the device enters a low quiescent current state.

Table 5. Modes of Operation

20 Freescale Semiconductor

status information (production tested at 1MHz). between an MCU and one 33800. initial power-up of the VDD and EN pins is recommended. second 16-bits will be the same bit pattern sent by the MCU. Figure 6. SPI Interface with Microprocessor transfer data in / out of the ICs. Figure 7. SPI Parallel Interface with Microprocessor Figure 8. SPI Serial Interface with Microprocessor

• Off State Open Load Detect
• On State Short Circuit Detect
• Programmable Drain Threshold and Timer for Short Fault Detection
• Load Resistance Measurement Each pre-driver is capable of detecting an open load in the off state and shorted load in the on state. All faults are reported through SPI communication. For open load detection, a resistor is placed between the drain sense pin and source sense pin of the IC. An open load fault is reported when the drain voltage is less than the 2.5V threshold. A shorted load fault is reported when the drain voltage is greater than the programmed threshold voltage. Programming of the drain short fault threshold voltage is done through SPI commands provided in Table 7. Bits 6 through 9 are used to perform the load resistance measurement function as described in the Gate Drive On/Off Command section below. GATE DRIVE ON/OFF COMMAND The GD ON/OFF Command provides control bits for two functions:
• On/Off control of the GDx outputs.
• Load Resistance measurement function. On/Off control bit 0 through bit 5 control gate drive outputs GD1 through GD6 respectively. Setting the bit to logic1 will enable the gate drive to the external MOSFET. Setting the bit to logic 0 will actively pull the gate to ground. GD ON/OFF Command bits 6 through 9 control the load measurement feature. The gate drive pre-drivers are selected in matched pairs. Selecting a load resistance measurement disables a specified output pair and performs the resistance measurement using the defined pair. All other outputs will operate as programmed. Resistance is measured by passing a known current through the load and by measuring the voltage across it. The resistor placed on the REXT pin determines the current through the load during measurement. The voltage output on the LRFDBK pin is the differential load voltage with the defined current through it. From the two parameters, the load resistance may be calculated. Table 6 illustrates the load diagnostic multiplex function. PWM PIN ENABLE COMMAND The PWM Pin Enable Command provides control bits for two functions:
• Enable or Disable of PWM input pins.
• Enable or Disable of the internal PWM controller for GD1 through GD6. PWM pin Enable bit 0 through bit 5 enable or disable the PWM1 through PWM6 input pins respectively. A logic 0 in the SPI word will enable the PWM input pin, while logic 1 in the SPI word will disable the PWM input pin. Default state is with the PWM input pin enabled. With the PWM input pin disabled, the AND/OR function is also disabled and control is achieved through the Gate Drive ON/OFF command or the internal PWM controller. AND /OR COMMAND The AND/OR Command provides control bits for two functions:
• Determines AND/OR relation between ON/OFF SPI bit and PWM input pin.
• Enable or Disable of the internal PWM controller for G1 through GD6. The AND /OR command describes the condition by which the PWM input pin controls the output driver. A logic[0] in the AND / OR register will OR the PWM input pin with the respective bit in the ON/OFF register. Likewise, a logic[1] in

Table 6. Load Resistance Measurement Select

0000 Normal Operation

0001 VDSNS1 to REXT, VDSNS2 to Diff-Amp +

0010 VDSNS2 to REXT, VDSNS1 to Diff-Amp +

0011 VDSNS3 to REXT, VDSNS4 to Diff-Amp +

0100 VDSNS4 to REXT, VDSNS3 to Diff-Amp +

0101 VDSNS5 to REXT, VDSNS6 to Diff-Amp +

0110 VDSNS6 to REXT, VDSNS5 to Diff-Amp +

0111 Normal Operation

1000 Normal Operation

1001 Normal Operation

1010 VDSNS2 to REXT, VDSNS1 to Diff-Amp +

1011 VDSNS3 to REXT, VDSNS1 to Diff-Amp +

1100 VDSNS4 to REXT, VDSNS1 to Diff-Amp +

1101 VDSNS5 to REXT, VDSNS1 to Diff-Amp +

1110 VDSNS6 to REXT, VDSNS1 to Diff-Amp +

1111 Normal Operation

22 Freescale Semiconductor

is disabled when the PWM input pin is disabled. Table 7. PWM Command

Table 8. And/Or/SPI/Parallel Control output control bits supersede the internal PWM controller. Table 9. Frequency Select detected if t_off_open > 1/fpwm * (1-duty_cycle) * 0.75. Table 10. VDSNSx Fault Threshold Select

110 No Change

111 No Change

24 Freescale Semiconductor

Serial Output Response Register. differential load voltage and forces a known load current. Figure 9. Example of Channel 1 Measurement logic operation and commands for the octal driver. eight commands, and one response as shown in Table 12. 0 through 10 determine how a specific output will operate. Table 11. PWM Short Fault Timer Notes: Tolerance on fault timer setting is ±10% with calibrated part.

which corresponds to output 1. PWR returns to normal level. Table 12. OSS SPI Control Commands and Response

26 Freescale Semiconductor

limit fault timer (typically 50µs). detection (~500µs) of the off-state open load fault. Table 13. TLim/Timer Control 1 on SPI bit 0 or SPI bit 1 will command both outputs on. 3&4, 5&6, 7&8 is increased to a range of 2.0 to 4.0A. Open Load Detect is programmed. Table 14. And/Or/SPI/Parallel Control temperature below threshold.

Analog Integrated Circuit Device Data Freescale Semiconductor 27 33800 FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS AND /OR COMMAND The AND/OR Command provides control bits for the following function:

• Determines AND/OR relation between ON/OFF SPI bit and PX input pin. The AND /OR command describes the condition by which the PX input pin controls the output driver. A logic[0] in the AND / OR register will OR the PX input pin with the respective bit in the ON/OFF register. Likewise, a logic[1] in the AND / OR register will AND the PX input pin with the respective bit in the ON/OFF register. The AND/OR function is disabled when the PX input pin is disabled. SERIAL OUTPUT (SO) RESPONSE REGISTER Fault reporting is accomplished through the SPI interface. All logic[1]s received by the MCU via the SO pin indicate fault. All logic[0]s received by the MCU via the SO pin indicate no fault. All fault bits are cleared on the positive edge of CS. SO bits 15 to 0 represent the fault status of outputs 15 to 0. The timing between two write words must be greater than 450µs to allow adequate time to sense and report the proper fault status. CCD1 CONSTANT CURRENT CONTROLLER The CCD1 constant current controller is a switching hysteretic current controller with a superimposed dither. The controller is designed to provide a programmable constant current through a solenoid valve. Fluid flow is controlled by the amount of current run through the solenoid valve. The master SPI device sends 16 bit command words to the 33800 device (see Table 15). The master device sets up the output current based on the CCD1 Control command. The IC is capable of sinking an average output current from 0mA to 1075mA (without dither). If operating the device with dither, the DAC + Dither value must be less than 1075mA or greater than 0.0mA. Commands outside of this command range will automatically lock out dither. Programming the solenoid current begins by sending the CCD1 Control command. The command consists of an control address, Diagnostic Pull Up Enable bit (Diag_pu_EN), Dither Disable bit (DTHR_DIS), and a 9-bits of data for digital to analog conversion (DAC). The data is received and the DAC provides bias for a comparator to produce a threshold level. The comparator drives a switch control circuit which generates a frequency modulated signal for the output drive. The differential voltage across the sense resistor provides the feedback necessary to maintain the desired output current. The output current is continuously monitored as a differential voltage across the internal sense resistor. When the current is in recirculation and the driver is in the off state, the current will decay to the lower limit switch point. When the current reaches the lower limit, the driver will turn on to increase the current until the upper limit switch point is reached. The output current will continue to switch between the switch points, resulting in the desired average current. The switch points are set to a fixed ±5% of the commanded current. The switching frequency and accuracy are dependent upon the load inductance and resistance, battery voltage, dither amplitude and frequency, switch points and the commanded current. Current dither is a method by which the average current is increased and decreased through the solenoid valve. The 33800 allows the user to program the frequency and amplitude of the dither control. Dither amplitude is implemented by increasing and decreasing the DAC by the programmed dither value. The rate at which the value changes is set by the programmed dither frequency. When reprogramming the dither amplitude or dither frequency, the update will occur on the start of a positive cycle. The maximum value of the output (DAC + Dither) must be less than 1075mA. When a greater value is programmed the device will disable the dither on the output. Similarly, the minimum value of the output (DAC - Dither) must be greater than 0.0mA. Requesting a lower value will disable the dither on the output. ON/OFF CONTROL BIT The CCD1 output may be used as a standard 1.0A low side driver. For on/off control, the CCD1_DIS bit int the CCD1Frequency & Amplitude command must be set to logic 1. This disables the constant current driver and enables the on/off control. To turn the driver ON a logic 1 is placed in the ON/OFF control bit. A logic 0 placed in the ON/OFF control bit will turn the driver OFF. The protection scheme in low side driver mode operates the same as constant current mode.

28 Freescale Semiconductor

through the solenoid valve, fluid flow control is achieved. the output current based on the CCD2 Control command. Table 15. CCD1 Constant Current Controller Commands

9 BIT DAC Command Data

1. Trim Set bit indicates (0=untrimmed, 1= trimmed)
2. VCAL Status bit indicates when internal or external supply is used. VCAL Bit = 0 indicates external, VCAL Bit = 1indicates internal.
3. Reset Bit indicates the device has performed a POR.
4. CCD1 DISable bit allows the CCD1 driver to operate as a st andard 1.0A low side driver. With CCD1_DIS bit = 1 the CCD1 function is

Table 16. CCD1 Dither Frequency Select

0000 Dither Off

1111 No change

Table 17. CCD1 Dither Amplitude Select

000 Dither Off

range will automatically lock out dither. generates a frequency modulated signal for the output drive. the switch points, resulting in the desired average current. update will occur on the start of a positive cycle. Table 18. CCD2 Constant Current Controller Commands

1. Trim Set bit indicates (0 = untrimmed, 1 = trimmed)
2. VCAL Status bit indicates when internal or external supply is used. VCAL Bit = 0 indicates external, VCAL Bit = 1indicates internal.
3. Reset Bit indicates the device has performed a POR.

30 Freescale Semiconductor

Table 19. CCD2 Dither Frequency Select Table 20. CCD2 Dither Amplitude Select Table 21. Calibration Command Table 22. Reset Command

Sending these two commands perform no operation. The device outputs will remain in previous state. The Most Significant Bit (MSB) is sent and received first. Table 23. No Operation Command Table 24. Fault Operation Over-current SO Pin reports short-to-battery/supply or over-current condition. Output OFF Open Load Fault SO Pin reports output “OFF” open load condition. CCDX outputs will remain in current limit until TLim is reached. Table 25. SPI Commands

32 Freescale Semiconductor

34 Freescale Semiconductor

1. 1 = VPWR Over-Voltage and 0 = Ok

Table 26. Serial Output (SO) Response Register

1. Trim Set bit indicates (0 = untrimmed, 1 = trimmed)

dedicated comparator for this purpose. Mode or when disabled via the SPI. under-voltage threshold is between 0.8 and 2.8V. curve (IA) times the clamp voltage (VCL) (see Figure 10). energy to be 50mJ at 150°C junction temperature per output. Figure 10. Output Voltage Clamping placed in series with the load.

Analog Integrated Circuit Device Data

36 Freescale Semiconductor

For the most current package revision, visit www.freescale.com and perform a keyword search using the “98A” listed below. EK (Pb-FREE) SUFFIX 54-PIN SOICW EXPOSED PAD 98ASA99334D ISSUE C

Analog Integrated Circuit Device Data Freescale Semiconductor 37 33800 PACKAGING PACKAGE DIMENSIONS EK (Pb-FREE) SUFFIX 54-PIN SOIC EXPOSED PAD 98ASA99334D ISSUE C

Analog Integrated Circuit Device Data

38 Freescale Semiconductor

REVISION HISTORY

REVISION DATE DESCRIPTION OF CHANGES 1.0 7/2006 • Initial Release 2.0 8/2006 • Updated format and style 3.0 7/2007 • Changed Part Number PC33800EK/R2 to MCZ33800EK/R2 in Ordering Information.

• Changed Category from Product Preview to Advance Information. 4.0 8/2007 • Changed Octal Serial Driver, Output Refresh Timer, minimum value from “-” to 2.0ms on page 12 5.0 10/2007 • Added paragraph for PWM Frequency/Duty Cycle Command on page 23
• Revised Table 12, OSS SPI Commands and Response on page 25
• Revised Table 26, SPI Commands on page 31

Rev. 5.0 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”, must be validated for each customer application by customer’s technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc., 2007. All rights reserved. How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. Technical Information Center, EL516

2100 East Elliot Road

Tempe, Arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.com/support Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7

81829 Muenchen, Germany

+44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) www.freescale.com/support Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo 153-0064 Japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com Asia/Pacific: Freescale Semiconductor Hong Kong Ltd. Technical Information Center

2 Dai King Street

Tai Po, N.T., Hong Kong +800 2666 8080 support.asia@freescale.com For Literature Requests Only: Freescale Semiconductor Literature Distribution Center P .O. Box 5405 Denver, Colorado 80217 1-800-441-2447 or 303-675-2140 Fax: 303-675-2150 LDCForFreescaleSemiconductor@hibbertgroup.com