33797

33797 FREESCALE | Alldatasheet

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Technical content

2 Freescale Semiconductor

Figure 3. 33797 Simplified Internal Block Diagram

Figure 4. Pin Function Description Table 1. Pin Function Description

1 SQB_LO_1A Output Squib Lo 1A Drain of the low-side switch that connects to the low pin of

2 SENSE_1A Input Squib Sense 1A Used during standard applications involving a four-channel

3 MOSI Input Data Input 1 Serial data input for SPI interface. 4 CLK Input Serial Clock Serial clock input for SPI interface.

5 SQB_HI_1A Output Squib Hi 1A Drain of the high-side switch that connects to the low pin of

6 VFIRE_1A Supply Squib Firing Supply

Firing supply pin for Squib_1A.

7 VDIAG_1 Input Squib Diagnostic 1A

and the VFIRE supply voltage. 8 GND Ground Device Ground Device ground pin for internal logic and diagnostic circuitry. 9 MISO Output Data Output 0 Serial data output for SPI interface. 10 VDD Input Logic Power Device power pin for internal logic and diagnostic circuitry.

11 VFIRE_1B Supply Squib Firing Supply

Firing supply pin for Squib_1B.

12 SQB_HI_1B Output Squib Hi 1B Drain of the high-side switch that connects to the low pin of

13 FEN_1 Input FET Driver 1A and

14 R_LIMIT_1 Output Limit Resistor - 1A

Squib_1A and squib_1B FET drivers.

4 Freescale Semiconductor

15 SENSE_1B Input Squib Sense 1B Used during standard applications involving a four-channel

16 SQB_LO_1B Output Squib Lo 1B Drain of the low-side switch that connects to the low pin of

17 SQB_LO_2B Output Squib Lo 2B Drain of the low-side switch that connects to the low pin of

18 SENSE_2B Input Squib Sense 2B Used during standard applications involving a four-channel

19 R_LIMIT_2 Output Limit Resistor - 2A

Squib_2A and squib_2B FET drivers.

20 FEN_2 Input FET Driver 2A

21 SQB_HI_2B Output Squib Hi 2B Drain of the high-side switch that connects to the low pin of

22 VFIRE_2B Supply Squib Firing Supply

Firing supply pin for squib_2B.

23 R_DIAG Input Limit Resistor -

24 VFIRE_RTN Ground Squib Fire Power

25 VFIRE_RTN Ground Squib Fire Power

26 VDIAG_2 Supply Squib Diagnostic 2A

and the VFIRE supply voltage.

27 VFIRE_2A Supply Squib Firing Supply

28 SQB_HI_2A Output Squib Hi 2A Drain of the high-side switch that connects to the low pin of

29 RST Input Reset Reset, Active Low

30 CS Input Chip Select Chip Select for SPI interface, Active Low

31 SENSE_2A Input Squib Sense 2A Used during standard applications involving a four-channel

32 SQB_LO_2A Output Squib Lo 2A Drain of the low-side switch that connects to the low pin of

Table 1. Pin Function Description (continued)

Analog Integrated Circuit Device Data Freescale Semiconductor 5 33797

ELECTRICAL CHARACTERISTICS

Table 2. Maximum Ratings permanent damage to the device. accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 Ω). 2 With a nominal squib load, the FET squib driver will not enter thermal shutdown until the driver has been active for a minimum of 2.1 ms. arm / fire command when the TEMPRENABLE (MIN) is reached (thermal shutdown status “0”). Nominal squib load is 2.15 Ω ± 0.15 Ω. Shorted squib load is 0.1 Ω. VVDIAG_X = VVFIRE_XX = 35 V. cause malfunction or permanent damage to the device.

1. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow

MC33xxxD enter 33xxx), and review parametrics.

Analog Integrated Circuit Device Data

6 Freescale Semiconductor

OPERATING RATINGS (6) Low-Side FET Fire Conditions RSQUIBtONISQUIBVSQUIBHI 2.0 Ω2.6 ms3.0 A16 V 1.2 Ω2.6 ms3.0 A16 V 0.1 Ω2.6 ms3.0 A16 V Notes 6 Operating ratings indicate conditions fo r which the device is intended to be functional. For guaranteed specifications and test conditions, refer to the static and dynamic electrical characteristics tables on the following pages. permanent damage to the device.

Analog Integrated Circuit Device Data Freescale Semiconductor 7 33797 STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.

7.0 V = SQLO < 16 V

7.0 V ≤ VVFIRE ≤ 35 V

7 Guaranteed by design

8 VFIRE quiescent current includes any leakage current through squib.

Analog Integrated Circuit Device Data

8 Freescale Semiconductor

STATIC ELECTRICAL CHARACTERISTICS VFIRE1A / VFIRE2A Current During High Side Safing Sensor Diagnostics (Command $CO) Per VFIREXA pin, with High Side Safing Sensor Diagnostic active IRRE 260 350 400 µA VFIRE1B / VFIRE2B Current During High Side Safing Sensor Diagnostics (Command $CO) Per VFIREXB pin, with High Side Safing Sensor Diagnostic active IRRE 22 32 55 µA VFIRE1B / VFIRE2B Current During VFIRE Diagnostics (Command $C5) Either VFIRE!B or VFIRE2B Diagnostic active IRRE 0.3 2.0 3.8 mA VFIRE Quiescent Current - Total All VFIRE pins measured together, with Diagnostics Off IQVFIRETOTAL 90 135 180 µA Maximum Allowable External Capacitance to Ground (9) Per Squib pin SQB_LO and SQB_HI CSMAX – – 0.12 µF Maximum Allowable External Resistance to Ground During Firing (9) VFIRE_RTN pin to Ground RSMAX – – 0.15 Ω Individual FET Driver Thermal Shutdown (9), (10) TSD 160 – 190 C FET Driver Thermal Shutdown Re-Enable Threshold After Drive Cool-down (9), (10) TREN 90 – 110 C FET DRIVERS HIGH- AND LOW-SIDE DRIVER TRANSISTOR STATUS /DIAGNOSTICS ($82, $83 COMMANDS) Voltage Transistor Test Threshold for High-Side Driver Transistor VTRANTST1 5.5 6.0 6.5 V High-Side Driver Current Limit During High-Side Driver Transistor Diagnostics

15 V ≤ VVFIRE_XX ≤ 35 V

2.0 10 50 mA Voltage Transistor Test Threshold for Low-Side Driver Transistor VTRANTST2 1.0 1.4 2.0 V Low-Side Driver Current Limit During Low-Side Driver Transistor Diagnostics 2.0 10 50 mA FEN INPUT PIN (FEN_1 AND FEN_2) Internal Current Pull-Down IFEN -25 -40 -50 µA Logic Low Level VFEN(LO) 0.0 2.5 0.35 x VDD V Fire Enable Pin Logic High Level VFEN(HI) 0.65 x VDD 2.5 1.0 x VDD V Notes 9 Guaranteed by design. 10 With a nominal squib load, the FET squib driver will not enter thermal shutdown until the driver has been active for a minimum of 2.1 ms. The individual squib driver thermal shutdown will not affect other squib driver firing ON times. With a shorted squib load, the FET squib driver will not enter thermal shutdown until the driver has been active for a minimum of 2.1 ms. When the thermal shutdown limit is exceeded, the FET driver will turn OFF and the thermal status bit will be set to 1. The FET squib driver can be activated through the arm / fire command when the TEMPRENABLE (MIN) is reached (thermal shutdown status “0”). Nominal squib load: 2.15 Ω ± 0.15 Ω. Shorted squib load: 0.1 Ω. Table 3. Static Electrical Characteristics (continued) noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.

Analog Integrated Circuit Device Data Freescale Semiconductor 9 33797 STATIC ELECTRICAL CHARACTERISTICS RST INPUT PIN (ACTIVE LOW) (11) System Reset Threshold VDDRST – – 4.1 V Internal Current Pull-Down IRST -6 -10 -15 µA RST Logic Low Level VRST(LO) 0.0 2.5 0.35 x VDD V RST Logic High Level VRST(HI) 0.65 x VDD 2.5 1.0 x VDD V SQUIB DIAGNOSTICS ($D0–$D3 COMMANDS) (12) Diagnostic Current Through Squib (13) IDIAG 30 34 40.5 mA Resistance Threshold 1 (13) RTH1 1.2 1.4 1.6 Ω Resistance Threshold 2 (13) RTH2 1.6 1.8 2.1 Ω Resistance Threshold 3 (13) RTH3 2.1 2.4 2.6 Ω Resistance Threshold 4 (13) RTH4 2.6 2.9 3.2 Ω Resistance Threshold 5 (13) RTH5 3.3 3.7 4.4 Ω Resistance Threshold 6 (13) RTH6 4.6 5.4 6.0 Ω Resistance Threshold 7 (13) RTH7 5.7 6.5 7.1 Ω Resistance Threshold 8 (13) RTH8 6.7 7.8 8.5 Ω SQUIB SHORT-TO-BATTERY / GROUND DIAGNOSTICS AND SQUIB HARNESS SHORT-TO-BATTERY / GROUND DIAGNOSTICS WITH AN OPEN SQUIB ($C1, $C3 COMMANDS) Voltage Threshold for SQB_LO and SQB_HI Shorted to VPWR

7.0 V ≤ VVDIAG_X ≤ 35 V

5.7 6.0 6.4 V Voltage Threshold for SQB_LO and SQB_HI Shorted to Ground 1.3 1.4 1.6 V Current Sink Shorts Measurements I_SQB_LO_XX (14)

1.0 V ≤ SENSE_XX ≤ 16 V, Typical = 800 µA

-500 -800 -900 µA Current Source Shorts Measurements I_SQB_HI_XX (14) 1.0 V ≤ SENSE_XX ≤ 16 V, 7.0 V ≤ VVDIAG_X ≤ 35 V ISOURSHRTS 1.7 3.5 3.7 mA Voltage Threshold for SQB_LO or SQB_HI Shorted to VPWR with an Open Squib using $C3 Command RSQUIB = Open VTHSB_SO 5.75 – 6.75 V Notes 11 Reset Bar range of operation: The minimum system reset ba r threshold/active will be set to “0” for a value of VDD ≤ 4.1 V. 12 By changing the R _DIAG resistor value, the resistance thresholds can be varied in a linear relationship.The R_DIAG resistance can be changed by ±10% to shift the thresholds by ±10%. Design goal for resistance threshold change is ±15%. R_DIAG threshold limit may have to be changed to accommodate ±15% change. Example: Shifting the R_DIAG resistance value ±10%, the resistance threshold will change by ±10%. Refer to Table 4, page 12. 13 R R_DIAG = 10 kΩ ±1.0% 14 XX = 1A, 1B, 2A, or 2B. noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.

Analog Integrated Circuit Device Data

10 Freescale Semiconductor

STATIC ELECTRICAL CHARACTERISTICS Voltage Threshold for SQB_LO or SQB_HI Shorted to Ground with an Open Squib using $C3 Command RSQUIB = Open VTHSG_SO 1.3 1.8 2.0 V DIAGNOSTICS FOR SQUIB CONTINUITY BETWEEN SENSE_XX AND SQB_LO_XX ($C2 COMMAND) Current Threshold for SQUIB_LO_1A, 1B, 2A, and 2B Continuity Check for Standard and Cross-coupled Conditions ($C2) SQUIB_LO_XXCONT (15) ITHSQB CON 150 – 350 mA DIAGNOSTICS FOR SQUIB SHORT BETWEEN FIRING LOOPS ($E0–$E3, $E8 COMMANDS) Voltage Threshold for Standard Squib Connection 1.0 1.4 2.0 V Voltage Threshold for SQUIB_X Shorted to SQUIB_Y (1 or More Shorted Conditions) Short Between Squib Lines (Loops) (SQUIB_XX_SSQB_YY) (16) VTHSSQB 1.0 1.4 2.0 V VDIAG SUPPLY DIAGNOSTICS ($C0 COMMAND) VDIAG Supply Voltage High Threshold VDHI 15 17 18.3 V VDIAG Supply Voltage Low Threshold VDLO 5.7 6.5 7.0 V VFIRE SUPPLY DIAGNOSTICS VFIRE_1B AND VFIRE_2B ($C5 COMMAND) VFIRE Supply Voltage High Threshold VFDHI 15 17 18.3 V VFIRE Supply Voltage Low Threshold VFLO 5.7 6.5 7.0 V VDIAG SUPPLY DIAGNOSTICS VDIAG_1 AND VDIAG_2 (ADDITIONAL VOLTAGE THRESHOLDS) ($C5 COMMAND) VDIAG Supply Voltage Threshold 4 VVDIAG_X V4 30.2 32.8 36.2 V VDIAG Supply Voltage Threshold 3 VVDIAG_X V3 25.5 27.7 30.2 V VDIAG Supply Voltage Threshold 2 VVDIAG_X V2 20.5 22.6 25.5 V VDIAG Supply Voltage Threshold 1 VVDIAG_X V1 16 18.4 20.5 V VFIRE_RTN DIAGNOSTICS ($C9 COMMAND) R_RTN1 Short-to-Ground Threshold (Open Ground Connection) RRTN1 0.15 – 0.6 Ω R_RTN2 Short-to-Ground Threshold (Open Ground Connection) RRTN2 0.15 – 0.6 Ω HIGH-SIDE SAFING SENSOR DIAGNOSTICS ($C0 COMMAND) R_HS Valid Resistor Range

15 V ≤ VVDIAG_X ≤ 35 V

4.1 5.1 6.1 kΩ R_HS Open Threshold 6.1 7.2 9.0 kΩ Notes

15 XX = 1A, 1B, 2A, or 2B

16 XX and YY = 1A, 1B, 2A, or 2B

noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.

Analog Integrated Circuit Device Data Freescale Semiconductor 11 33797 STATIC ELECTRICAL CHARACTERISTICS R_HS Short Threshold RHSS 2.8 – 4.1 κΩ VFIRE_XA & VFIRE_XB Current during High Side Safing Test at Open Threshold VFIRE_1A & VFIRE_1B or VFIRE_2A & VFIRE_2B I1HSO 270 360 410 µA VFIRE_XA & VFIRE_XB Current during High Side Safing Test at Short Threshold VFIRE_1A & VFIRE_1B or VFIRE_2A & VFIRE_2B I1HSS 287 385 436 µA HIGH-SIDE SAFING SENSOR DIAGNOSTICS WITH 1 SAFING SENSOR IN FIRING PATH CONNECTED TO VFIRE_1A AND VFIRE_2A PINS (GUARANTEED BY DESIGN) ($C0 COMMAND) Total VFIRE_XX Current during High Side Safing Test at Open Threshold VFIRE_1A, VFIRE_1B, VFIRE_2A & VFIRE_2B pins I2HSO 574 705 835 µA Total VFIRE_XX Current during High Side Safing Test at Short Threshold VFIRE_1A, VFIRE_1B, VFIRE_2A & VFIRE_2B pins I2HSS 605 748 892 µA R_HS Valid Resistor Range 1.99 – 2.93 kΩ R_HS Open Threshold 2.93 3.35 4.43 kΩ R_HS Short Threshold 1.41 1.61 1.99 kΩ R_LIMIT RESISTOR DIAGNOSTICS ($C8 COMMAND) R_LIMIT Valid Resistor Range RRL 4.32 – 45.3 kΩ R_LIMIT Open Threshold (“Out of Range Threshold”) RRLO 60 76 105 kΩ R_LIMIT Short-to-Ground Threshold (“Out of Range Threshold”) RRLS 3.0 3.5 4.31 kΩ Maximum External Capacitance to Ground CRL – – 20 pF R_DIAG RESISTOR DIAGNOSTICS ($C8 COMMAND) (17) R_DIAG Valid Resistor Range RRD 8.0 – 13 kΩ R_DIAG Open Threshold (“Out of Range Threshold”) RRDO 13 23 60 kΩ R_DIAG Short-to-Ground Threshold (“Out of Range Threshold”) RRDS 3.0 5.4 8.0 kΩ Maximum External Capacitance to Ground CRD – – 20 pF Notes 17 By changing the R _DIAG resistor value, the resistance thresholds can be varied by a linear relationship.The R_DIAG resistance could be changed by ±10% to shift the thresholds by ±10%. Design goal for resistance threshold change is ±15%. R_DIAG threshold limit may have to be changed to accommodate ±15% change. Example: Shifting the R_DIAG resistance value ±10%, the resistance threshold will change by ±10%. Refer to Table 4. noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.

Analog Integrated Circuit Device Data

12 Freescale Semiconductor

STATIC ELECTRICAL CHARACTERISTICS Table 4. Resistance Range vs. R_DIAG noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.

Analog Integrated Circuit Device Data Freescale Semiconductor 13 33797 DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 5. Dynamic Electrical Characteristics noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.

18 Determined by Design

19 Guaranteed by Characterization

Analog Integrated Circuit Device Data

14 Freescale Semiconductor

DYNAMIC ELECTRICAL CHARACTERISTICS FET DRIVERS Turn-On Delay Time CS ↑ to 80% IHS tON – – 72 µs Turn-Off Delay Time CS ↑ to 20% IHS tOFF – – 10 µs Diagnostic Timing / Resolution 5.0 V ≤ VVDIAG_X ≤ 35 V, IHS ≥ IMEAS, 0 s ≤ tMEASURE_TIME ≤ 6.375 ms, CSQUIB_HI = 0.12 µF, CSQUIB_LO = 0.12 µF tRESOLUTION 21.25 25 28.75 µs DIAGNOSTIC DELAY TIME Squib Resistance Diagnostic Delay Time (20) From CSB ↑ Until Transistor Test Results Are Valid, CSQUIB_HI = 0.12 µF, CSQUIB_LO = 0.12 µF tDIAG1 – – 300 µs Squib Open / Short Diagnostic Delay Time (20) From CSB ↑ Until Squib Open / Short Diagnostic Results Are Valid, CSQUIB_HI = 0.12 µF, CSQUIB_LO = 0.12 µF tDIAG2 – – 3000 µs VDIAG Supply Diagnostic Delay Time From CSB ↑ until VDIAG Diagnostic Results Are Valid (20) tDIAG4 – – 3000 µs VFIRE Supply Diagnostic Delay Time (20)

15 V ≤ VVDIAG_X ≤ 35 V, From CSB ↑ Until High-Side Safing Sensor

Diagnostic Results Are Valid, CVDIAG < 0.015 µF tDIAG6 – – 1000 µs High-Side Safing Sensor Diagnostic Delay Time (20) Diagnostic Results Are Valid, CVDIAG < 0.015 µF tDIAG7 – – 1000 µs FET Drivers High- and Low-Side Driver Transistor Diagnostic Delay Time (20)

15 V ≤ VVDIAG_X ≤ 35 V, From CSB ↑ Until Transistor Test Results Are

Valid, CSQUIB_HI = 0.12 µF, CSQUIB_LO = 0.12 µF, CVDIAG < 0.015 µF tDIAG9 – – 1000 µs VFIRE_RTN Diagnostic Delay Time (20) From CSB ↑ Until VFIRE_RTN Diagnostic Results Are Valid tDIAG10 – – 300 µs Squib Continuity Diagnostic Delay Time (20) From CSB ↑ Until VTHSQBCON Diagnostic Results Are Valid tDIAG11 – – 3000 µs Squib Short Between Firing Loops Diagnostic Delay Time From CSB ↑ Until VTHSSQB Diagnostic Results Are Valid (20) tDIAG12 – – 3000 µs FEN INPUT PIN Minimum Pulse Width FENFILTER 12 14 16 µs Notes

20 Guaranteed by Characterization

Table 5. Dynamic Electrical Characteristics (continued) noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.

Analog Integrated Circuit Device Data

16 Freescale Semiconductor

The Four-Channel Squib Driver IC is a complete squib diagnostic and deployment interface for use in automotive air bag modules. Extensive diagnostics and system control features are incorporated to provide fail-safe operation. The device contains a serial peripheral interface- (SPI) compatible 8-bit interface for microprocessor control. This interface allows the microprocessor to set up and read back the results of all internal diagnostic functions. Squib resistance level, along with possible shorts-to-battery or ground, open ground connections, or shorts between squib firing loops, are included in the diagnostic set. Additionally, the squib supply voltage levels can be checked and the low- side fire return can be checked for an open condition (open ground connection). The SPI interface, along with the additional FEN pin, is used to arm and fire a selected squib. The device has the capability to be used in a standard four- channel squib driver IC or in a cross-coupled state with the high- and low-side squib drivers located on separate squib driver ICs. Both the high-side and low-side output drivers are protected against temporary shorts to battery or ground. The current limit threshold is set by an external resistor. FUNCTIONAL PIN DESCRIPTION INTRODUCTION In this section references are made to XX; e.g., in SENSE_XX, SQB_LO_XX, and SQB_LO_XX_CONT. In these and similar instances, XX denotes 1A, 1B, 2A, and 2B. SERIAL CLOCK (SCLK) Serial clock input for SPI interface. Data on the D1 pin is clocked into the device on the rising edge. Data is clocked out of the device via the D0 pin on the falling edge. Default state is low with no connection. CHIP SELECT (CS) Chip select for SPI interface. Active low. On rising edge, data shifted into the shift register is internally latched. On falling edge, diagnostic results are latched into shift register. Default state is high with no connection. MASTEROUT/SLAVE IN (MOSI) Serial data input to 33797 SPI interface. Default state is low with no connection. MASTER IN/SLAVE OUT (MISO) Serial data output from 33797 SPI interface. FET DRIVER 1A AND 1B (FEN_1) Active high input signal to enable operation of squibs 1A and 1B FET drivers. All diagnostic functions are available while pin is low. Default state is low with no connection. FET DRIVER 2A AND 2B (FEN_2) Active high input signal to enable operation of squibs 2A and 2B FET drivers. All diagnostic functions are available while pin is low. Default state is low with no connection. DEVICE GROUND (GND) Device ground pin for internal logic and diagnostic circuitry. DEVICE POWER (VDD) Device power pin for internal logic and diagnostic circuitry. RESET (RST) Reset Bar. Active low. With low input signal the internal functions of the squib driver IC are disabled and all data in the serial interface shift registers is cleared. Default state is low with no connection. LIMIT RESISTOR - DIAGNOSTIC (R_DIAG) External resistor to ground is used to set the diagnostic current for squib resistance. LIMIT RESISTOR 1A AND 1B (R_LIMIT_1) External resistor to ground is used to set current limit for squibs 1A and 1B FET drivers. LIMIT RESISTOR 2A AND 2B (R_LIMIT_2) External resistor to ground is used to set current limit for squibs 2A and 2B FET drivers. SQUIB DIAGNOSTIC 1A AND 1B (VDIAG_1) Diagnostic pins for the high-side safing sensors for squibs 1A and 1B, as well as the VFIRE supply voltage. SQUIB DIAGNOSTIC 2A AND 2B (VDIAG_2) Diagnostic pins for the high-side safing sensors for squibs 2A and 2B, as well as the VFIRE supply voltage.

Analog Integrated Circuit Device Data Freescale Semiconductor 17 33797 FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION SQUIB SENSE XX (SENSE_XX) The Sense pins are used exclusively for diagnostics related to the squib, driver FETs, or harness. Commands using the Sense pins include:

• C1, C2, C3, C9
• D < 3 : 0 >
• E < 3 : 0 >
• E 9
• 82/1x
• 83/2x Independent of the system configuration, normal or cross coupled, the Sense pin, xx and SquibHi, xx of a single IC are always connected to the same squib with the SquibHi pin connected to the high pin of the squib and the Sense pin connected to the low pin of the squib. A cross coupled configuration is achieved by only cross coupling the squib low pins. See Figure 8 and Figure 9. STANDARD APPLICATIONS In the standard mode, the $C2 (SQUIB_LO_XX_CONT) command will be used to check continuity of the low-side driver from the SQB_LO_XX pin to the high-side driver FET (see Figure 6). CROSS-COUPLED APPLICATIONS Used during cross-coupling applications involving two four-channel squib driver ICs (squib driver IC #1 and squib driver IC #2). SENSE_XX pins from squib driver IC #1 are connected to their respective squib minus pins (Squib Low / SQB_LO_XX) from squib driver IC #2 (Figure 9). SENSE_XX pins are used to feed diagnostic signals back to squib driver IC #1 for determining squib resistance, short-to- battery/ground, and squib loop-to-loop short conditions. During a fire event, the fire current passes from squib driver IC #1 high-side driver though the squib to squib driver IC #2 low-side driver (Figure 9). In the cross-coupled mode, the squib driver IC #2 $C2 (SQUIB_LO_XX_CONT) command will be used to check continuity of the low-side driver from the SQB_LO_XX pin to the low-side driver FET. DESIGN NOTES Diagnostics always have the form of a forcing function and a measurement or sense function. In a cross couple configuration, most diagnostics are unaffected and are single commands except for $C2 Low Side FET Continuity and $E<3:0> Harness Shorts, and 83/2x Low- Side FET test. This command must be sent to each IC to be executed. For these three diagnostics, two commands are required because the forcing function and sensing function are on separate ICs. Harness Shorts Diagnostics: Force using $E<3:0> on IC#1, Sense $E8 on IC2 Low-Side FET Continuity: Force using $C1 on IC#1, Sense using $C2 on IC#2 Low-Side FET Test: Force using $C1 on IC#1, Sense using $C2 on IC#2 An active 600 µA current sink is located in the SENSE_XX pin. The sink current is used to pull the charge off of the external EMC / filter caps after a diagnostic measurement has been made. SQUIB HI XX (SQB_HI_XX) Squib high pins for squibs 1A, 1B, 2A, and 2B. These pins are connected to the sources of the high-side FET drivers, as well as the diagnostic circuitry. SQUIB LOW XX (SQB_LO_XX) Squib low pins for squibs 1A, 1B, 2A, and 2B. These pins are connected to the drains of the low-side FET drivers, as well as the diagnostic circuitry. SQUIB FIRING SUPPLY XX (VFIRE_XX) Firing supply pins for squibs 1A, 1B, 2A, and 2B. These pins are connected to the drains of the high-side FET drivers. Feedback for high-side safing for squibs 1A and 1B will be referenced from VFIRE_1A and squibs 2A and 2B from VFIRE_2A. For high-side safing, VFIRE_1B should be connected to VFIRE_1A pin and VFIRE_2B to VFIRE_2A pin. SQUIB FIRE POWER GROUND (VFIRE_RTN) Return for squibs 1A, 1B, 2A AND 2B. The pins are tied to the source pins of both low-side FET drivers, as well as the diagnostic circuitry. The RTN pins are tied internally.

18 Freescale Semiconductor

Figure 8. Standard Squib Firing Figure 9. Cross-Coupled Squib Firing

Analog Integrated Circuit Device Data

20 Freescale Semiconductor

FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES TX: Request loop-to-loop short command ($E0–$E3) RX: Previous executed command information. TX: Request another command sequence. RX: Receive loop-to-loop results from test. CROSS-COUPLED SQUIB IC FUNCTION The cross-coupled application utilizes the high- and low- side squib drivers from two different squib driver ICs (see Figure 9, Cross-Coupled Squib Firing, page 18.) Through the SPI interface, the squib IC will maintain the capability to conduct standard diagnostics (short-to-battery, short-to- ground, short between squibs, and squib diagnostics) between two different squib ICs. The squib IC must maintain the capability to fire the squib drivers with the ARM and FIRE command in either cross-coupled or single IC applications. When the firing squib driver IC is used in cross-coupled applications, the low-side squib driver must be activated prior to activating the high-side squib driver. Cross-coupling the high- and low-side squib driver from two different squib driver ICs must be done without interfering with standard squib operations when the squib IC is used in an application where the high- and low-side squib drivers are located on the same IC. All remaining diagnostic functions will operate standard in either a cross-coupled or single IC applications. These functions include RR_DIAG, RR_LIMIT_X, High side, VVFIRE_XX, VVFIRE_RTN, VTRANSTX, squib current timing measurement, and FEN_1 and FEN_2 diagnostics. The SENSE_1A (1B, 2A, or 2B) pin squib IC #1 is connected to SQB_LO_1A (1B, 2A, or 2B) pin squib driver IC #2 and is used to feed the diagnostic signal for determining squib resistance and short-to-battery / ground conditions (see Figure 9, page 18). During a fire event, the fire current passes from squib driver IC #1 high-side driver though the squib to squib driver IC #2 low-side driver. In the cross-coupled mode, the squib driver IC #2 $C2 (SQUIB_LO_1A_CONT, [1B, 2A, or 2B]) command will be used to check continuity of the low-side driver from the SQB_LO_1A (1B, 2A, or 2B) pin to the low-side driver FET. The low-side driver continuity is checked during the continuity test. The driver continuity information will be cleared after the information is transmitted on the next valid SPI command. EXAMPLE—CROSS-COUPLED SQUIB COMMAND SPI SEQUENCE FROM MICROCONTROLLER TX: Squib IC #1 request squib 1A resistance measurement ($D0). RX: Previous executed command information. TX: Run another command on the same squib IC #1. RX: Receive measured squib 1A resistance information. TX: Squib IC #1 request continuity command ($C2). RX: Previous executed command information. TX: Squib IC #2 request continuity command ($C2). RX: Previous executed command information. TX: Squib IC #2 request continuity command ($C2). RX: Receive low-side driver continuity information for low- side drivers which reside on IC #2. TX: Squib IC #1 request another command sequence. RX: Receive low-side driver continuity information for low- side drivers that reside on IC #1. TX: Squib IC #1 request loop-to-loop short command ($E0–$E3) RX: Previous executed command information. TX: Squib IC #2 request loop to loop short command for other ICs ($E8). RX: Previous executed command information. TX: Squib IC #2 request loop-to-loop short command for other ICs ($E8). RX: Receive loop-to-loop results from test run on IC #1. TX: Squib IC #1 request another command sequence. RX: Receive loop-to-loop results from test run on IC #1. FIRING A SQUIB The firing of a squib driver requires the FEN_1 and FEN_2 pins to be high and two separate 8-bit writes be made to the shift register. With FEN_1 pin high, squibs 1A and 1B can be armed and fired. With FEN_2 pin high, squibs 2A and 2B can be armed and fired. The first write is to ARM squib drivers in preparation of receiving the fire command. Squib 1A and squib 1B can be armed separately from squib 2A and squib 2B (refer to Table 6) or all squibs can be fired at once (refer to Table 7). All ARM and 5X (Fire) commands will be echoed back on the SPI Data output.

armed, all diagnostic functions are cleared.

• Sending a valid 2-byte write sequence through the shift register.
• Having the reset pin pulled low.
• Having the thermal shutdown limit exceeded (once minimum firing duration requirement has been met; refer to Note 4 in the Maximum Ratings table, page 5).
• Having the FEN pin pulled low. Note that the code sequences allow any combination of drivers to be turned on or off. Once fired, the current limit measurement register increments when the squib current is measured and is above the I MEAS threshold during the timer activation. The FEN_1 or FEN_2 pin must be high to enable firing of the drivers. If fire command is active and the FEN (1 or 2) pin is pulled low, the FET drivers will turn off (assuming the latch and hold function is not in effect; refer to paragraph entitled FEN_1 and FEN_2, page 29). If fire command is active and the FEN (1 or 2) pin is pulled high, the FET driver will turn on. During the firing of a squib, significant I•R losses may occur, which could cause a voltage shift across a circuit board trace. It is recommended that current paths for discharging the firing supply storage capacitors through the squib be kept as short as possible and isolated from logic and diagnostic grounds.

Table 6. Squib Firing Commands

50 OFF OFF OFF OFF OFF OFF OFF OFF

51 OFF OFF OFF ON OFF OFF OFF ON

52 OFF OFF ON OFF OFF OFF ON OFF

53 OFF OFF ON ON OFF OFF ON ON

54 OFF ON OFF OFF OFF ON OFF OFF

55 OFF ON OFF ON OFF ON OFF ON

56 OFF ON ON OFF OFF ON ON OFF

57 OFF ON ON ON OFF ON ON ON

58 ON OFF OFF OFF ON OFF OFF OFF

59 ON OFF OFF ON ON OFF OFF ON

Analog Integrated Circuit Device Data

22 Freescale Semiconductor

FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES Table 7. Diagnostic Bit Definitions

Description

Diagnostic Data Out (Available on Next Command) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

00 NOP 0 0 0 0 0 0 0 0

70 Squib 1A Current

SQB_1A BIT 7 MS SQB_1A BIT 6 SQB_1A BIT 5 SQB_1A BIT 4 SQB_1A BIT 3 SQB_1A BIT 2 SQB_1A BIT 1 SQB_1A BIT 0 LS

71 Squib 1B Current

SQB_1B BIT 7 MS SQB_1B BIT SQB_1B BIT SQB_1B BIT 4 SQB_1B BIT 3 SQB_1B BIT 2 SQB_1B BIT 1 SQB_1B BIT 0 LS

72 Squib 2A Current

SQB_2A BIT 7 MS SQB_2A BIT 6 SQB_2A BIT 5 SQB_2A BIT 4 SQB_2A BIT 3 SQB_2A BIT 2 SQB_2A BIT 1 SQB_2A BIT 0 LS

73 Squib 2B Current

SQB_2B BIT 7 MS SQB_2B BIT 6 SQB_2B BIT 5 SQB_2B BIT 4 SQB_2B BIT 3 SQB_2B BIT 2 SQB_2B BIT 1 SQB_2B BIT 0 LS

79 Squib X Current

0 0 0 0 SQB_2B Current Limit Status SQB_2A Current Limit Status SQB_1B Current Limit Status SQB_1A Current Limit Status 7F Thermal Shutdown Status ThermalSD Thermal LSDSTAT _2B Thermal HSDSTAT _2B Thermal LSDSTAT _2A Thermal HSDSTAT _2A Thermal LSDSTAT _1B Thermal HSDSTAT _1B Thermal LSDSTAT _1A Thermal HSDSTAT _1A C0 VDIAG and High- Side Safing Sensor Diagnostics RSSLO RSSHI VDIAG_2 VDHI VDIAG_2 VDLO RSSLO RSSHI VDIAG_1 VDHI VDIAG_1 VDLO C1 Squib Short-to- Ground / Short-to- Battery Diagnostics SQB_2B NO_SH_ GND SQB_2B NO_SH_ BATT SQB_2A NO_SH_ GND SQB_2A NO_SH_ BATT SQB_1B NO_SH_ GND SQB_1B NO_SH_ BATT SQB_1A NO_SH_ GND SQB_1A NO_SH_ BATT C2 Low-Side Driver Continuity Status 0 0 0 0 SQB_LO_2B_ CONT SQB_LO_2A CONT SQB_LO_1B CONT SQB_LO_1A CONT C3 Harness Short-to- Ground / Short-to- Battery with Squib Open (No Squib Present) SQB_2B OPEN NO_SH_ GND SQB_2B OPEN NO_SH_ BATT SQB_2A OPEN NO_SH_ GND SQB_2A OPEN NO_SH_ BATT SQB_1B OPEN NO_SH_ GND SQB_1B OPEN NO_SH_ BATT SQB_1A OPEN NO_SH_ GND SQB_1A OPEN NO_SH_ BATT Hex Code Command Diagnostic Data Out (Available on Next Command) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 C5 VFIRE_1B and VFIRE_2B Voltage 0 0 0 VFIRE_B Tested X X VHI VLO C6 VDIAG_1 and VDIAG_2 Diagnostics VDIAG_2 VDIAG_2 VDIAG_2 VDIAG_2 VDIAG_1 VDIAG_1 VDIAG_1 VDIAG_1

1 R_LIMIT_2

Table 7. Diagnostic Bit Definitions (continued)

Analog Integrated Circuit Device Data

24 Freescale Semiconductor

FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES Table 8. Command Programming and Diagnostic Bit Definitions Command Programming Input and Diagnostic Data Out (Available on Next Command) (21) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 3X Current Measurement Register Reset Command for Squib X Current 1 = ON 0 0 1 1 SQB_2B Data / Timer Reset SQB_2A Data / Timer Reset SQB_1B Data / Timer Reset SQB_1A Data / Timer Reset DATA OUT Squib X Current Register Reset Status 0 0 1 1 SQB_2B Data / Timer Reset SQB_2A Data / Timer Reset SQB_1B Data / Timer Reset SQB_1A Data / Timer Reset

80 Unlock for FEN 1

Programming. 1 0 0 0 0 0 0 0 Response DATA Output: Command Echoed 1 0 0 0 0 0 0 0 XX Programming Command for FEN

1 Counter

1 = ON FEN1 CNT BIT 7 MSB FEN1 CNT BIT 6 FEN1 CNT BIT 5 FEN1 CNT BIT 4 FEN1 CNT BIT 3 FEN1 CNT BIT 2 FEN1 CNT BIT 1 FEN1 CNT BIT 0 LSB Response DATA OUT FEN 1 Counter Programming Status FEN1 CNT BIT 7 MSB FEN1 CNT BIT 6 FEN1 CNT BIT 5 FEN1 CNT BIT 4 FEN1 CNT BIT 3 FEN1 CNT BIT 2 FEN1 CNT BIT 1 FEN1 CNT BIT 0 LSB

81 Unlock for FEN 2

Output: Command Echoed 1 0 0 0 0 0 0 1 Notes 21 The second byte for command programming will be treated as a NOP if any FET is firing. The programming commands have to be sequential or they will be treated as a NOP.

Analog Integrated Circuit Device Data Freescale Semiconductor 25 33797 FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES Hex Code Command Command Programming Input and Diagnostic Data Out (Available on Next Command) (22) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 XX Programming Command for FEN

2 Counter

1 = ON FEN2 CNT BIT 7 MS FEN2 CNT BIT 6 FEN2 CNT BIT 5 FEN2 CNT BIT 4 FEN2 CNT BIT 3 FEN2 CNT BIT 2 FEN2 CNT BIT 1 FEN2 CNT BIT 0 LS Response DATA OUT FEN 2 Counter Programming Status FEN2 CNT BIT 7 MS FEN2 CNT BIT 6 FEN2 CNT BIT 5 FEN2 CNT BIT 4 FEN2 CNT BIT 3 FEN2 CNT BIT 2 FEN2 CNT BIT 1 FEN2 CNT BIT 0 LS

82 Unlock to Test

1A, 1B, 2A, 2B 1 0 0 0 0 0 1 0 Response DATA Output: Command Echoed 1 0 0 0 0 0 1 0 1X High-Side Driver Transistor Test Command 0 0 0 1 SQB_ 2B High-Side Driver “ON” SQB_ 2A High-Side Driver “ON” SQB_1B High-Side Driver “ON” SQB_1A High-Side Driver “ON” Response DATA OUT High-Side Driver Transistor Status V TRANTST1 0 0 0 0 SQB_2B HSDSTAT_2B SQB_2A HSDSTAT_2A SQB_1B HSDSTAT_1B SQB_1A HSDSTAT_1A

83 Unlock to Test Low

Squib Drivers 1A, 1B, 2A, and 2B 1 0 0 0 0 0 1 1 Response Data Output: Command Echoed 1 0 0 0 0 0 1 1 2X Low-Side Driver Transistor Test Command 0 0 1 0 SQB_ 2B Low-Side Driver “ON” SQB_2A Low-Side Driver “ON” SQB_1B Low-Side Driver “ON” SQB_1A Low-Side Driver “ON” Response DATA OUT Low-Side Driver Transistor Status V TRANTST2 0 0 0 0 SQB_2B LSDSTAT_ 2B SQB_2A LSDSTAT_ 2A SQB_1B LSDSTAT_1B SQB_1A LSDSTAT_1A Notes 22 The second byte for command programming will be treated as a NOP if any FET is firing. The programming commands have to be sequential or they will be treated as a NOP. Table 8. Command Programming and Diagnostic Bit Definitions (continued)

Analog Integrated Circuit Device Data

26 Freescale Semiconductor

FUNCTIONAL DEVICE OPERATION PROTECTION AND DIAGNOSIS FEATURES PROTECTION AND DIAGNOSIS FEATURES The diagnostic circuit’s internal references are provided by a bandgap voltage reference, and by scaled currents determined by the resistor value of R_DIAG and the value of the bandgap voltage. Refer to Table 7, Diagnostic Bit Definitions, and Table 8, Command Programming and Diagnostic Bit Definitions, as necessary throughout this section. R_DIAG and R_LIMIT_X RESISTOR DIAGNOSTICS ($C8 COMMAND) This function monitors reference currents derived by the R_LIMIT_1, R_LIMIT_2, and R_DIAG resistors. An open pin or short to ground will cause the comparator to give an “out of range resistor value” indication. A short to VDD will have the same effect as an open pin and will cause an “out of range resistor value” indication. R_LIMIT_X and R_DIAG DATA RESULTS If R_LIMIT_X is open, shorted to ground, or shorted to VDD, the bit R_LIMIT_NO_FAULT will be set to “0”. Standard operation will have this bit set to “1”. If R_DIAG is open, shorted to ground, or shorted to VDD, the bit R_DIAG_NO_FAULT will be set to “0”. Standard operation will have this bit set to “1”. The FEN 1 and FEN 2 status bits are a reflection of the FEN_1 and FEN_2 pins. HIGH-SIDE SAFING SENSOR DIAGNOSTICS ($C0 COMMAND) This function monitors the VFIRE_XX pin connection to the VDIAG_X pin. The high-side safing function is attached to the VFIRE _1A and VFIRE_2A pins. The high-side safing function is not available on the VFIRE _1B and VFIRE_2B pins. When enabled, this diagnostic circuit will typically draw less than 500 µA from the VFIRE supply voltage source. Hex Code Command Command Programming Input and Diagnostic Data Out (Available on Next Command) (23) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

90 Reserved for

91 Reserved for

92 Reserved for

93 Reserved for

96 SPI Integrity Check 1 0 0 1 0 1 1 0

OUT: $69 Echo to Diagnose the SPI Integrity 0 1 1 0 1 0 0 1 Notes 23 The second byte for command programming will be treated as a NOP if any FET is firing. The programming commands have to be sequential or they will be treated as a NOP.

Analog Integrated Circuit Device Data Freescale Semiconductor 27 33797 FUNCTIONAL DEVICE OPERATION PROTECTION AND DIAGNOSIS FEATURES Internal window comparators will monitor the voltage difference between the VDIAG_X pin and the VFIRE_XX pin, and will provide two bits of data to indicate if the pin voltage is either above (open) or below (shorted) the threshold levels. When using a high-side safing sensor, typical 5.1 kΩ reference resistor must be placed across the sensor to provide a current path for the diagnostic circuit. As long as there is a current path and the safing sensor switch is open, the resulting differential voltage will fall between the comparator thresholds so that neither an open fault nor a shorted fault condition will be indicated. A closed safing sensor will be indicated as a short, and a loss of the connection between the VDIAG_X pin and the VFIRE_XX pin will be indicated as an open. Any external capacitance on the VFIRE_XX pin will affect the time needed to settle to an accurate value. HIGH-SIDE SAFING SENSOR DIAGNOSTIC DATA RESULTS If the VFIRE_XX pin is shorted to the VDIAG_X pin, the RSSLO bit will be set to “1” and the RSSHI bit will be set to “1”. If the VFIRE_XX pin has no connection to the VDIAG_X pin, the RSSLO bit will be set to “0” and the RSSHI bit will be set to “0”. Standard operation with a safing sensor resistor will have the RSSHI bit set to “1” and the RSSLO bit set to “0”. FIRING SUPPLY VOLTAGE (VDIAG_X) DIAGNOSTICS ($C0 COMMAND) This function monitors the voltage on the VDIAG_X pin. The supply voltage is compared to two thresholds (nominal and minimum) and will provide two bits of data to indicate if the pin voltage is above, below, or in between the predetermined threshold levels. There is one diagnostic circuit for each VDIAG_X pin. VDIAG_X SUPPLY VOLTAGE DIAGNOSTIC DATA RESULTS If the VDIAG_X voltage is above the high limit, bits VDHI and VDLO will both be set to “1”. If the VDIAG_X voltage is between the high limit and the low limit, bit VDHI will be set to “0” and VDLO will be set to “1”. If the VDIAG_X voltage is below the low limit, bits VDHI and VDLO will both be set to “0”. FIRING SUPPLY VOLTAGE (VFIRE_XX) DIAGNOSTICS ($C5 COMMAND) This function monitors the voltage on the VFIRE_XX pin. The supply voltage is compared to two thresholds (nominal and minimum) and will provide two bits of data to indicate if the pin voltage is above, below, or in between the predetermined threshold levels. There is one diagnostic circuit for each VFIRE_XX pin. VFIRE_XX SUPPLY VOLTAGE DIAGNOSTIC DATA RESULTS If the VFIRE_XX voltage is above the high limit, bits VFHI and VFLO will both be set to “1”. If the VFIRE_XX voltage is between the high limit and the low limit, bit VFHI will be set to “0” and VFLO will be set to “1”. If the VFIRE_XX voltage is below the low limit, bits VFHI and VFLO will both be set to “0”. FIRING SUPPLY VOLTAGE DIAGNOSTICS, VDIAG_X V1, V2, V3, V4 ($C6 COMMAND) The VDIAG_X V1, V2, V3, V4 function monitors voltage on the VDIAG pins. The voltage being measured is then compared to four thresholds and will provide four bits of data to indicate if the pin voltage is above, below, or between the predetermined threshold levels. There is one diagnostic circuit for each VDIAG_X pin. VDIAG_X VOLTAGE DIAGNOSTIC DATA RESULTS If the VDIAG_X voltage is above the threshold limit, the VDIAG_X VX bit will be set to “1”. If the VDIAG_X voltage is below the threshold limit, the VDIAG_X VX bit will be set to “0”. VFIRE_RTN DIAGNOSTICS ($C9 COMMAND) This function monitors the resistance on the VFIRE_RTN pin for open pin connections. The VFIRE_RTN voltage is compared to a threshold to determine if the VFIRE_RTN pin connection between the pin and the printed circuit board is shorted or open. VFIRE_RTN DIAGNOSTIC DATA RESULTS If the VFIRE_RTN pin is above the threshold limit (open), the VFIRE_RTN X VFXLOW will be set to “1”. If the VFIRE_RTN pin is below the threshold limit (shorted), the VFIRE_RTN X VFXLOW will be set to “0”. VFIRE return tests are disabled during firing. DESIGN NOTES For all standard or cross-coupled squib IC configurations, the SQB_LO_XX pin must be tied to a SENSE_XX pin for either squib IC #1 or squib IC #2 (see Figure 6 and Figure 9). An active 600 µA current sink is located in the SENSE_XX pin. The sink current is used to pull the charge off the external EMC / filter caps after a diagnostic measurement has been made. SQUIB SHORT-TO-BATTERY / GROUND DIAGNOSTICS ($C1 COMMAND) This function monitors the voltage on the SENSE_XX pins. The voltage is compared to two thresholds (minimum and maximum) and will provide two bits of data to indicate if the pin voltage is above, below, or in between the predetermined threshold levels. When enabled, a 2.7 mA current source located in the SQB_HI_XX pin is activated, sourcing current from the

Analog Integrated Circuit Device Data

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FUNCTIONAL DEVICE OPERATION PROTECTION AND DIAGNOSIS FEATURES SQB_HI_XX to the SENSE_XX pin. When resistive measurement legs to comparators located in the SENSE_XX pin are activated, a fault on either side of the squib can be easily detected. An external current path that causes the SQB_LO_XX, SQB_HI_XX, or SENSE_XX pin to be pulled below the minimum threshold, will be indicated as a “Short to Ground”. If the SQB_LO_XX, SQB_HI_XX, or SENSE_XX pin has an external current path that causes the pin to be pulled above the maximum threshold, a “Short to Battery” will be indicated. SQUIB SHORT-TO-BATTERY/GROUND DIAGNOSTIC DATA RESULTS If SQB_LO_XX, SQB_HI_XX, or SENSE_XX pin is shorted to battery, the bit NO_SH_BATT will be set to “0”. If a SQB_LO_XX, SQB_HI_XX, or SENSE_XX pin is shorted to ground, the bit NO_SH_GND will be set to “0”. During standard operation, both NO_SH_BATT and NO_SH_GND will be set to “1”. Note This diagnostic circuit uses an internal 2.7 mA current source connected to the SQB_HI_XX pin as a bias. If the SQB_LO_XX and SQB_HI_XX pins have any capacitance (due to discrete capacitors or parasitic loading), the diagnostic condition will require a settling time based on the RC time constant. SQUIB HARNESS SHORT-TO-BATTERY / GROUND DIAGNOSTICS WITH AN OPEN SQUIB ($C3 COMMAND) This diagnostic function is to be used with no squib present (open squib condition) in the wiring harness. For an open squib condition, the function must monitor the voltage on the SQB_HI_XX and SQB_LO_XX pins for “Short to Ground” and “Short to Battery” conditions. This function monitors the voltage on the SENSE_XX pins. The voltage is compared to two thresholds (minimum and maximum) and will provide two bits of data to indicate if the pin voltage is above, below, or in between the predetermined threshold levels. When enabled, a pair of opposing N-channel CMOS transistors are activated, creating roughly a 500Ω resistance between the SQB_HI_XX and SQB_LO_XX pins together. A 2.7 mA current source located in the SQB_HI_XX pin is activated, sourcing current from the SQB_HI_XX to the SQB_LO_XX pin to the SENSE_XX pin. When resistive measurement legs to comparators located in the SENSE_XX pin are activated, a short to BAT / GND fault can easily be detected. An external current path that causes the SQB_LO_XX, SQB_HI_XX, or SENSE_XX pin to be pulled below the minimum threshold, will be indicated as a “Short- to-Ground”. If the SQB_LO_XX, SQB_HI_XX, or SENSE_XX pin has an external current path that causes the pin to be pulled above the maximum threshold, a “Short-to-Battery” will be indicated. SQUIB SHORT-TO-BATTERY/GROUND DIAGNOSTIC DATA RESULTS If SQB_LO_XX, SQB_HI_XX, or SENSE_XX pin is shorted to battery, the bit OPEN NO_SH_BATT will be set to “0”. If a SQB_LO_XX, SQB_HI_XX, or SENSE_XX pin is shorted to Ground, the bit OPEN NO_SH_GND will be set to “0”. During standard operation, both OPEN NO_SH_BATT and OPEN NO_SH_GND will be set to “1”. Notes 1. This diagnostic circuit uses an internal 2.7 mA current source connected to the SQB_HI_XX pin as a bias. If the SQB_LO_XX and SQB_HI_XX pins have any capacitance (due to discrete capacitors or parasitic loading) the diagnostic condition will require a settling time based on the RC time constant. 2. With an OPEN NO_SH_GND or OPEN_NO_SH_BATT indicated, the SQB_HI_XX or SQB_LO_XX line contains the fault condition. The standard squib short- to-battery / ground diagnostics ($C1) can be executed to determine if the fault condition is on the SQB_HI_XX pin or the SQB_LO_XX pin. CONTINUITY TEST for the LOW-SIDE DRIVER SQB_LO_XX CONNECTION ($C2 COMMAND) (LOW-SIDE DRIVER CONTINUITY STATUS) Low-side driver continuity is checked during the continuity test diagnostics. This function is used to check continuity at the SQB_LO_XX pin connection. When enabled, a 2.0 mA current source located in the SQB_HI_XX pin is activated sourcing current from the SQB_HI_XX to the SQB_LO_XX pin. For a standard connection, the SQUIB_LO_XX_CON bit will be set to “1”. With an open circuit connection, the SQUIB_LO_XX bit will be set to “0”. The driver continuity information will be cleared after the information is transmitted on the next valid SPI command. SQUIB RESISTANCE DIAGNOSTICS ($D0–$D3 COMMAND) This function monitors squib resistance. When enabled, a diagnostic current derived from R_DIAG is passed through the selected squib. The resulting voltage across the squib is amplified and passed to an 8-bit voltage level detector. The eight bits of data will indicate if the selected squib has a resistance value above or below predetermined thresholds. The value of R_DIAG can be varied to allow the detection range to be altered. Increasing the value of R_DIAG will reduce the diagnostic current; thus, a higher squib resistance will be needed to reach the same RTH points. In the case that R_DIAG is a short-to-ground, the diagnostic current through the squib resistance will typically be less than 50 mA.

Analog Integrated Circuit Device Data Freescale Semiconductor 29 33797 FUNCTIONAL DEVICE OPERATION PROTECTION AND DIAGNOSIS FEATURES SQUIB RESISTANCE DIAGNOSTIC DATA RESULTS A comparator result bit set to “1” indicates that the input voltage is above the threshold resistance for that bit. Thus an open squib would cause all bits to be set to “1”; likewise, a shorted squib will cause all bits to be set to “0”. Squib resistance tests are disabled during firing. SQUIB DIAGNOSTICS SHORTS BETWEEN SQUIB LINES (FIRING LOOPS) ($EX COMMAND) This function monitors conditions that have shorts between squib lines (firing loops). When enabled, a 2.7 mA current source located in the SQB_HI_XX pin is activated sourcing current from the selected SQB_HI_XX to the SENSE_XX pin. The resulting voltage is checked on all other squib lines to determine if the squib lines are shorted. In applications using more than one squib driver IC, a separate command can also be issued to check all squibs for shorted squib lines. SQUIB DIAGNOSTICS SHORTS BETWEEN SQUIB LINES DIAGNOSTIC DATA RESULTS (SHORTS BETWEEN FIRING LOOPS) A comparator result bit set to “1” for SQUIB_XX indicates standard test current detected in squib line under test. A comparator result bit set to “0” for SQUIB_XX indicates faulty diagnostic current detected in squib line under test. A comparator result bit set to “1” for SQUIB_XX_SSQB_ YY indicates that the squib line is shorted to the squib under test. A comparator result bit set to “0” for SQUIB_XX_SSQB_YY indicates no shorted squib line detected (standard conditions). If more than two squibs are shorted together, the response will consist of all “0”s. RESET (RST) The Reset pin has an internal current pull-down of typically 40 µA. While this pin is low, the internal functions of the squib driver IC are disabled and all data in the serial interface shift registers is cleared. This includes all FEN 1 and 2 counter programming, squib driver activation, and squib driver FET tests. With a minimum system V DD ≤ 4.1 V, the system reset bar threshold will be set to “0”. FEN_1 and FEN_2 (FEN) ($C8 COMMAND) FEN_1 and FEN_2 have an internal current pull-down of typically 40 µA. While the FEN pin is low, firing of the FET drivers is disabled. All internal diagnostic functions and results will be available through the serial interface. The FEN pin must be pulled high to enable firing of the FET drivers. Also, the pin state can be used to turn the FET driver “ON” and “OFF” after the arm and fire command has been issued. (That is, once the FET drivers are turned on, pulling FEN_1 or FEN_2 low can turn the drivers off if the latch and hold function is not active, and pulling FEN_1 or FEN_2 high will activate the drivers if the fire command is still active). Status of FEN 1 and FEN 2 is contained in the C8 diagnostic byte, as shown in Table 7, Diagnostic Bit Definitions, page 23.) The FEN_1 and FEN_2 function should be capable of latching and holding the enable function for electronic safing function input. This function is required for dual-stage air bag applications. FEN_1 or FEN_2 will be considered active when either pin is active (“1”) for more than 12 ms. Tolerance range for the filter to be used will be 12 to 16 µs. When FEN_1 or FEN_2 input is active high, the FEN_1 or FEN_2 function will be active high. When the FEN_1 or FEN_2 input state transitions from high to low, a programmable latching function will hold the FEN function active until the timeout of the FEN timer. The programmable latch and hold function will be capable of delays from 1.0 ms to 255 ms, in 1.0 ms increments. The timer is reset to programmed time when FEN_1 or FEN_2 pin transitions from “0” to “1”. The programmable counter delay will be set through an SPI command during module power-up / prove- out. The default for the counter will be 0 ms. The bits FEN 1 and FEN 2 STATUS are a reflection of their respective pins. The counter will be reset to 0-Sec time during a reset condition. Notes 1. Status information will be required to read counter- programmed value. 2. Precautions need to be taken in the design to prevent the latching function from becoming a glitch catching function. FEN 1 and FEN 2 COUNTER PROGRAMMING ($80 and $81 COMMAND) The FEN 1 and FEN 2 counters require two separate 8-bit writes be made to the shift register. The first write is to unlock ($80 or $81) and reset the FEN counter registers in preparation of receiving a command. The second byte contains the programming information to set the required counter delay time (0 ms to 255 ms with 1.0 ms interval). Squib IC Power-Up default and $80 or $81 followed by $00 command will set the counter to 0 ms timer delay (refer to Table 8, page 24.) The FEN 1 and FEN 2 Counter programming status bits are a reflection of the counters programming. The programming status information can be compared to the data sent to ensure the squib driver was programmed properly. Counter programming status will be shifted from the shift register during the next read / write operation (Table 8). All unlock commands will be echoed back on the SPI Data output.

30 Freescale Semiconductor

current limit is never less than the high-side current limit. The high-side driver controls the current through the squib. status bit will be set to “0”. shutdown will not affect other squib drivers firing “ON” times. with an “ON” time of 2.09 ms ≤ tON ≤ 2.82 ms. This function checks the squib driver FET transistor status. $83) will be echoed back on the SPI Data output. if firing from any FET is enabled. other diagnostic functions are made available again. pin is required for the high-side squib driver to be tested. followed by $2X diagnostic command (Table 8). automated and is controlled through SPI. Table 9. RR_LIMIT_X Current Limit

Analog Integrated Circuit Device Data Freescale Semiconductor 31 33797 FUNCTIONAL DEVICE OPERATION PROTECTION AND DIAGNOSIS FEATURES When either a $82 or a $83 command is issued, the previous transistor test will stop to prevent coinciding high- and low-side FET drive transistors from turning “ON”. This prevents high- and low-side drivers from being activated simultaneously. Note The high- or low-side squib driver test is capable of checking a code sequence, allowing any combination of high- or low-side drivers to be tested. The diagnostic squib driver bit (HSDSTAT_X or LSDSTAT_X) will be set to “1” if the squib driver did not activate (turn “ON”) during the diagnostic test. The diagnostic squib driver bit (HSDSTAT_X or LSDSTAT_X) will be set to “0” if the squib driver did activate (turn “ON”) during the diagnostic test. Diagnostic data will be shifted from the shift register during the next read/write operation. The diagnostic squib driver register will be set / cleared to “0” when the unlock command is loaded ($82 or $83 loaded with rising edge of CS). A diagnostic bit set to “0” indicates standard squib driver transistor operation.

Analog Integrated Circuit Device Data

32 Freescale Semiconductor

Important For the most current revision of the package, visit www.freescale.com and do a keyword search on the 98A drawing number below. NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETERS. 2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 3. DATUMS B AND C TO BE DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. 4. THIS DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSION OR GATE BURRS. MOLD FLASH, PROTRUSION OR GATE BURRS SHALL NOT EXCEED 0.15 MM PER SIDE. THIS DIMENSION IS DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. 5. THIS DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH AND PROTRUSIONS SHALL NOT EXCEED 0.25 MM PER SIDE. THIS DIMENSION IS DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. 6. THIS DIMENSION DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.4 MM PER SIDE. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD SHALL NOT LESS THAN 0.07 MM. 7. EXACT SHAPE OF EACH CORNER IS OPTIONAL. 8. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10 MM AND 0.3 MM FROM THE LEAD TIP. 9. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM. THIS DIMENSION IS DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTER-LEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. CL10.9 7.4 16 17 0.10 A 2.35 SEATING PLANE 0.9 SECTION B-B 0.65 R0.08 MIN B A PIN 1 ID (0.29) 0.38 0.25 (0.203) PLATING BASE METAL SECTION A-A ROTATED 90 CLOCKWISE° 0.19 0.22

0.13 M CA M B

A C7.6 11.1 10.3 5.15 A 32X 30X 2.65 0.3 A 2X 16 TIPS B C B 0.29 0.13 0.50° 0°0.25 GAUGE PLANE MIN EK SUFFIX (32-LEAD SOIC) PLASTIC PACKAGE 98ARH99137A

Analog Integrated Circuit Device Data Freescale Semiconductor 33 33797

REVISION HISTORY

REVISION DATE DESCRIPTION OF CHANGES 3.0 11/2006 • Updated to the current Freescale format and style

• Implemented Revision History page
• Added MCZ33797EK/R2
• Removed Peak Package Reflow Temperature During Reflow (solder reflow) parameter from Maximum Ratings on page 5. Added note with instructions from www.freescale.com.

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