33781 FREESCALE | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 44
Technical content
Features
- Four independent differential DSI (DBUS) channels
- Dual SPI interface
- Enhanced bus fault performance
- Automatic message cyclical redundancy checking (CRC) generation and checking for each channel
- Enhanced register set with addressa ble buffer allows queuing of 4 independent slave commands at one time for each channel
- 8- to 16-Bit messages with 0- to 8-Bit CRC
- Independent frequency spreading for each channel
- Pseudo bus switch feature on channel 0
- Pb-free packaging designated by suffix code EK
Figure 1. 33781 Simplified Application Diagram
ORDERING INFORMATION
Range (TA) Package PCZ33781EK/R2 -40°C to 90°C 32 SOICW EP EK SUFFIX (PB-FREE) 98ASA10556D 32-PIN SOICW EP VCC SCLK0 CS0 MOSI0 MISO0 RST CLK SCLK1 MISO1 CS1 VSUP1 DPH DPL D0H D0L D1H D1L D2H D2L VCC SCLK CS MOSI MISO RST CLK MCU1 33781 MCU2 SCLK1 MISO1 CS1 GND +5.0V GND D3H D3L GND 2.2nF capacitors from DOH, D0L, D1H, D1L, D2H, D2L, D3H and D3L to circuit ground are required for proper operation DBUS SLAVE DBUS SLAVE DBUS SLAVE DBUS SLAVE DBUS SLAVE +25V VDD VSS_IDDQ AGND VSS 1.0μF 0.1μF
2 Freescale Semiconductor
Figure 2. 33781 Internal Block Diagram
2.5 V RegulatorVDD
Figure 3. 33781 Pin Connections Table 1. 33781 Pin Definitions A functional description of each Pin can be found in the Functional Pin Descriptions section beginning on page 15.
1 RST Reset IC Reset A low level on this pin returns all registers to a known state as indicated
transition of SCLK0. MOSI0 is sampled on the positive edge of SCLK0.
3 MOSI0 Input SPI0 Master Out Slave
4 MISO0 Output SPI0 Master In Slave
6 MISO1 Output SPI1 Master In Slave
completed when this signal returns high. completed when this signal returns high. current draw is allowed from this pin.
4 Freescale Semiconductor
12 VPP Input Test Mode A high-voltage on this pin puts the device in test mode for IC
manufacturing test. It must be grounded in the application.
13 VCC Input Logic Supply Regulated 5V input
15 TESTIN Test Test Input Input pin for device test. This pin must be tied to ground in the application. 16 TESTOUT Test Test Output Output pin for device test. This pin is left floating in the application.
17 VSS_IDDQ Ground Digital Ground and
18 GND Ground Power Ground Bus power return
19 D3L Output Driver Low Side Bus 3 Bus 3 low side
20 D3H Output Driver High Side Bus 3 Bus 3 high side
21 VSUP2 Power Positive Supply for
22 D2H Output Driver High Side Bus 2 Bus 2 high side
23 D2L Output Driver Low Side Bus 2 Bus 2 low side
24 GND Ground Power Ground Bus power return
25 D1L Output Driver Low Side Bus 1 Bus 1 low side
26 D1H Output Driver High Side Bus 1 Bus 1 high side
27 VSUP1 Power Positive Supply for
28 D0H Output Driver High Side Bus 0 Bus 0 high side
29 DPH Output Driver High Side Pseudo Bus Pseudo Bus high side
30 D0L Output Driver Low Side Bus 0 Bus 0 low side
31 DPL Output Driver Low Side Pseudo Bus Pseudo Bus low side
32 GND Ground Power Ground Bus power return
A functional description of each Pin can be found in the Functional Pin Descriptions section beginning on page 15.
Analog Integrated Circuit Device Data Freescale Semiconductor 5 33781
ELECTRICAL CHARACTERISTICS
Table 2. Maximum Ratings
- ESD1 testing is performed in accordance with the Human Body Model (HBM) (CZAP = 100pF, RZAP = 1500Ω); ESD2 testing is performed
in accordance with the Machine Model (MM) (CZAP = 200pF, RZAP = 0Ω); and Charge Body Model (CBM).
- Pin soldering temperature limit is for 10 seconds maximum dura tion. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
- Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow
and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.
Analog Integrated Circuit Device Data
6 Freescale Semiconductor
STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics parameter at TA = 25°C under nominal conditions, unless otherwise noted.
- Not measured in production.
Analog Integrated Circuit Device Data Freescale Semiconductor 7 33781 STATIC ELECTRICAL CHARACTERISTICS BUS TRANSMITTER (DnH, DnL) Output Bus Idle Voltage (Drop) InH = -200mA, InL = 200mA(6) VDnD(Drop) (7)(8) – – 1.6 V Output Signal High Voltage (Differential) -12.5mA ≤ InH ≤ 1.0mA, -1.0mA ≤ InL ≤ 12.5mA (6) VDnD(HIGH) (7) 4.175 4.5 4.825 V Output Signal Low Voltage (Differential) -12.5mA ≤ InH ≤ 1.0mA, -1.0mA ≤ InL ≤ 12.5mA(6) VDnD(LOW) (7) 1.175 1.5 1.825 V Vmid, (DnH + DnL)/2 (Voltage Halfway Between Bus High Side and Bus Low Side VMID (8) VSUPn/ 2-0 . 8 VSUPn/2 VSUPn/ 2+ 0 . 8 V VCM Peak to Peak (Maximum Vmid-Minimum Vmid) For Vmid (Idle), Vmid (Signal_H), Vmid (Signal_L)(5) VCMP 0 – 30 mV Bus Driver Vmid Peak to Peak, (DnH+DnL)/2(5) For Signal to Idle, Idle, Idle to Signal, VmidPP(Idle)=Vmid(Max)- Vmid (Min) VMIDPP(IDLE) – – 300 mV Bus Driver Vmid Peak to Peak (Dnh+DnL)/2(5) For Signal_H to Signal_L, Signal_L, Signal_L to Signal_H, Signal_H VmidPP(Signal)=Vmid(Max)-Vmid(Min) VMIDPP(SIGNAL) – – 80 mV Output High Side (DnH) Driver Current Limit Fault Condition: DnH = 0V Normal Operation Fault Condition: DnH = VSUPn ICL(HIGH) -600 -400 150 -200 -200 350 mA Output Low Side (DnL) Driver Current Limit Fault Condition: DnL = 0V Fault Condition: DnL = VSUPn ICL(LOW) -350 200 -150 400 mA Signal mode Over-current Shutdown l ISSD l DnH, DnL ISSD 20 60 mA Disabled High Side (DnH) Bus Leakage (DnL open) DnH = 0V DnH = VSUPn ILK(HIGH) -1.0 -1.0 1.0 1.0 mA Disabled Low Side (DnL) Bus Leakage (DnH open)(9) DnL = 0V DnL = VSUPn ILK(LOW) -1.0 -1.0 1.0 1.0 mA Notes 5. Not measured in production. 6. InH=bus current at DnH, InL=bus current at DnL 7. V DnD=VDnH-VDnL 8. Max V DnD = VSUPn - 2 * VMID_OFFSET - VDnD(Drop), VMID_OFFSET = |VMID - VSUPn / 2| 9. Worst Case Disabled Low Side Bus Leakage for DnL occurs with DnL = V SUP and DnH = 0V. In this configuration, the DnL leakage current can exceed 1mA. This is not measured in production. Table 3. Static Electrical Characteristics (continued) parameter at TA = 25°C under nominal conditions, unless otherwise noted.
Analog Integrated Circuit Device Data
8 Freescale Semiconductor
STATIC ELECTRICAL CHARACTERISTICS BUS TRANSMITTER (DnH, DnL) (CONTINUED) High Side Pseudo Bus Switch Resistance ISWH=160mA RSWH – 8.0 16.0 Ω Low Side Pseudo Bus Switch Resistance ISWL=160mA RSWL – 8.0 16.0 Ω Pseudo Bus Switch Matching RPSMATCH – – 1.0 Ω High Side Pseudo Bus Switch Leakage Current DPH = Open: CH0 drivers in Idle, DPH = 0V or CH0 drivers in Signal_H, DPH = 25V IDPHLK -20 – 20 μA Low Side Pseudo Bus Switch Leakage Current DPL = Open: CH0 drivers in Idle, DPL = 25V,or CH0 drivers in Signal_H, DPL = 0V IDPLLK -20 – 20 μA BUS RECEIVER (DnH, DnL) Comparator Trip Point for High Side COMPHIGH 5.0 6.0 7.0 mA Comparator Trip Point for Low Side COMPLOW 5.0 6.0 7.0 mA Comparator Trip Point for Adder COMPADD 6.0 12 18 mA parameter at TA = 25°C under nominal conditions, unless otherwise noted.
Analog Integrated Circuit Device Data Freescale Semiconductor 9 33781 DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 4. Dynamic Electrical Characteristics parameter at TA = 25°C under nominal conditions, unless otherwise noted.
- Not measured in production.
- SPI signal timing from the production test equipment is programmed to ensure compliance.
- Conditions are verified indirectly during test.
Analog Integrated Circuit Device Data
10 Freescale Semiconductor
DYNAMIC ELECTRICAL CHARACTERISTICS BUS TRANSMITTER Idle-to-Signal and Signal-to-Idle Slew Rate(13) tSLEW(IDLE) 3.0 6.0 8.0 V/μs Signal High-to-Low and Signal Low-to-High Slew Rate(13),(14) (See Data Valid DSIS to DnD Timing) tSLEW(SIGNAL) 3.0 6.0 8.0 V/μs Communication Data Rate Capability(14) (Ensured by Transmitter Data Valid and Receiver Delay Measurements) Data Rate(before frequency spreading) DRATE 77.1 – 200 kbps Signal Bit Time (1 / DRATE)(14) The Max value depends on the settings in the FSEL bits tBIT 5.0 – – μs DBUS Start Delay, CS0 Rising Edge to DBUS(14) note: DLY is the inter-message delay selected in the DnCTRL register tDBUSSTART2 2/3tBIT + (DLY-2) * tBIT – 5/3tBIT + (DLY-2) * tBIT μs Data Valid(13) DSIF = 0.5 * VCC to DnD Fall = 5.5 V (9V < VSUPn < 40V) DSIS = 0.5 * VCC to DnD Fall = 2.8V (9V < VSUPn < 40V) DSIS = 0.5 * VCC to DnD Rise = 3.2V (9V < VSUPn < 40V) DSIF = 0.5 * VCC to DnD Rise = 6.5 V (9V < VSUPn < 40V) tDVLD1 tDVLD2 tDVLD3 tDVLD4 5.3 1.0 1.0 1.0 μs Signal mode Over-current Shutdown Delay(14) tOC 3.0 5.0 7.0 μs Signal Low Time for Logic Zero 33.3% Duty Cycle (2/3*tBIT) + 10% for threshold delta t0LO 0.6 * tBIT 2/3 * tBIT 0.73 * tBIT μs Signal Low Time for Logic One 66.7% Duty Cycle (1/3*t BIT) + 10% for threshold delta t1LO 0.3 * tBIT 1/3 * tBIT 0.37 * tBIT μs Notes 13. C = 2.8nF from DnH to DnL and 2.2nF from DnH and DnL to GND, capacitor tolerance = ±10%. 14. Not measured in production. Table 4. Dynamic Electrical Characteristics (continued) parameter at TA = 25°C under nominal conditions, unless otherwise noted.
Analog Integrated Circuit Device Data Freescale Semiconductor 11 33781 DYNAMIC ELECTRICAL CHARACTERISTICS BUS RECEIVER Receiver Delay Time (IRSP = 0mA / 11mA step)(15) IRSP = -6.0mA to DSIR = 0.5 * VCC IRSP = -6.0mA to DSIR = 0.5 * VCC tDRH tDRL 500 500 ns Common Mode Current Noise Rejection (2.5ms max.) ICMNR -50 – +50 mA SPREAD SPECTRUM Base Frequency Range fCEN 77.1 - 2% – 200 + 2% kHz PSEUDO BUS Pseudo Bus On Delay Time tPBD1 – 5 10 μs Pseudo Bus Off Delay Time tPBD2 – 5 10 μs Notes 15. Not measured in production. parameter at TA = 25°C under nominal conditions, unless otherwise noted.
12 Freescale Semiconductor
Figure 4. DBUS Timing Characteristics
14 Freescale Semiconductor
Figure 7. SPI0 Interface Timing Figure 8. SPI1 Interface Timing
the same in order to achieve the lowest radiated EMI energy. the bus as seen by either bus wire. the bus waveforms in normal operation. and Bit Descriptions on page 29. MOSI pin or function for SPI1. Ground source for DSI/DBUS return. Used for IDDQ testing during IC manufacturing test. Ground source for analog circuits. Nominal +5.0V Regulated Input. Table 5. High Side and Low Side Typical Voltages (Voltage Relative to Ground)
16 Freescale Semiconductor
Figure 5. The output of DnH should have a bypass capacitor devices on DBUS2 and DBUS3. See Figure 9. voltage to supply the output NMOS devices. Figure 9. VSUP Block Diagram
Figure 10. Block Illustration wave-shaped voltage and current signals. Refer to Figure 1.
- SPI0 interface and registers to a main MCU
- SPI1 interface and registers to a second MCU
- Four channels of DSI 2.02 protocol state logic
- CRC block for each channel
- Control and status registers
- Four addressable register sets per channel for queuing up to four commands and data per bus. The addressable buffer acts as a circular buffer for command writes and data reads.
- Pseudo Bus Switch from D0H/L to DPH/L SPI0 AND REGISTERS This block contains the SPI0 interface logic and the control and response registers that are written to and read from the SPI interface. The IC is an SPI slave-type device, so MOSI0 (Master- Out-Slave-In) is an input and MISO0 (Master-In-Slave-Out) is an output. CS0 and SCLK0 are also inputs. The SPI0 port can handle 2-byte and 4-byte transfers. It addresses 87 registers. The organization of the registers is described in the section entitled SPI0 Register and Bit Descriptions on page 29. SPI1 AND REGISTERS The 33781 has a second SPI port (called SPI1) that allows valid response data from Bus Channel 2 and 3, along with the slave address, to be read independently by a second MCU. This block contains the SPI1 interface logic and the response registers that are read from the SPI1 interface. The IC is an SPI slave-type device, so MISO1 (Master-In- Slave-Out) is an output, and CS1 and SCLK1 are inputs. SPI1 does not use the MOSI (Master-Out-Slave-In) pin or function as it does not receive commands. The SPI1 port handles only 16-bit transfers. It addresses eight registers which are read only. PROTOCOL ENGINE This block converts the data to be transmitted from the registers into the DBUS sequences, and converts DBUS response sequences to data in the registers. The DBUS transmit protocol uses a return to 1 type data with a duty cycle determined by the logic state. The protocol includes Cyclical Redundancy Check (CRC) generation and validation. MC33781 - Functional Block Diagram Supply Voltage Power Stage Supply Voltage 2.5V Regulator Power Stage CRC Generation and Checking Clock Generation and Frequency Spreading Logic and Control Over-temperature Sensing SPI0 Registers and State Machine Over-current Sensing DBUS Drivers and Receivers Pseudo-bus Logic and Control VSUP Voltage Monitor HCAP Charging Circuitry SPI1 Registers and State Machine Switches
18 Freescale Semiconductor
Figure 11. Driver/Receiver Block Diagram Figure 11. The circuit uses a common driver for both the Idle drivers are disabled in HiZ. Register and Bit Descriptions sections. the logic. This is shown in Table 6. DSIS signal to the DBUS differential signal voltage levels. Table 6. Internal Signal Truth Table
Analog Integrated Circuit Device Data Freescale Semiconductor 19 33781 FUNCTIONAL DESCRIPTIONS FUNCTIONAL INTERNAL BLOCK DESCRIPTION the driver. The over-voltage input causes the driver characteristics to be modified under over-voltage conditions. This is described in more detail in the Load Dump Operation section. A special requirement of the differential bus is to maintain a low common mode voltage. This is accomplished by monitoring the common mode voltage and modifying the driver slew rates. This is the function of the Common Mode Correction block. Current signals sent by the slave are detected on both the high side and the low side of the bus using a differential current sense architecture. Sense resistors between the Signal driver and the DnH and DnL outputs detect the slave device response current. Sensing the current on both bus lines improves the fault diagnostics of the bus. Also included is an adder circuit which is used to improve the reception of sensor data in the presence of common mode noise. The comparators in the blocks output a high or low value depending on if the input is above or below the signal threshold. The Receiver High, Receiver Low, and Receiver Sum outputs are sent to the device logic block which is shown in Figure 23 . The data is sampled at the falling edge of DSIS. In the presence of faults or common mode noise it is possible that all three receiver circuits will not produce the same bit pattern. To check for this, each of the three receiver filter outputs is passed to a CRC generation and checking block. A logic block determines which (if any) of the receiver filter blocks has produced the correct result, by comparing the CRC results along with the bit-by-bit XOR of the high side and low side bit pattern. Table 7 shows how the logic determines which (if any) receiver outputs contain a valid response. The data is selected from either the Receiver High, Receiver Low or Receiver Sum circuit and the ER bit is set accordingly in the DnRnSTAT register. If either Receiver High or Receiver Low has all 1’s for data, including the CRC bits, then the ER bit will be set. For either of these two conditions, the ER bit will be set regardless of the Receiver Sum data value and regardless of whether or not all the 1’s caused a CRC error on the High or Low side. Note that SPI0 and SPI1 do not use the same sources for their respective output data streams. SPI0 chooses between Receiver High or Receiver Sum0; SPI1 chooses between Receiver Low and Receiver Sum1. In order to provide the maximum protection against a single-point failure causing a disruption in communication, the decision paths for the two SPI channels are internally independent . For example, Receiver Sum0 and Receiver Sum1 use different holding registers in the Receiver logic. These registers are duplicates, although they will always hold the same data unless there is a fault in one of the data paths.
20 Freescale Semiconductor
Pseudo Bus Switches are provided on the Channel 0 bus. the devices on DPH/DPL to be initialized. can also open the switch at any time. that can be strong enough to interfere with a desired signal. a much smaller percentage of time at any specific frequency. Table 7. Receiver Decision Logic
0 Receiver
Figure 12. Spread Spectrum Block Diagram
22 Freescale Semiconductor
registers, and to queue up transfers over the DBUS. new command will be ignored. Figure 13. SPI016-Bit Burst Transfer Example. Figure 14. SPI0 32-Bit Burst Transfer Example Words or Enhanced Short words.
00000000 DATA FROM D0R0H DATA FROM D0R0L DATA FROM D0R0STAT
24 Freescale Semiconductor
Figure 17. SPI0 Communications, 32-Bit Burst Transfer Enhanced Short Word DBUS Bit Definitions overwriting data if necessary. location is read it is cleared by the SPI1 logic. Figure 18. SPI1 16-Bit Burst Transfer Example
26 Freescale Semiconductor
CRCPOLY[7:0], and CRCSEED[7:0] control register fields. the peripheral device considers the message invalid. Figure 21. CRC Algorithm Figure 22. Default CRC Block Diagram 16-bit message is expected to be another 16-bit message. transition from one message size to a different message size. others can be short words (8 to 15 bits of data). DSI formatted short word (8 bits of data and 4 bits of CRC). -- Calculates the 4-bit CRC (x^4 + 1) serially for 8 to 16 bits of data.
28 Freescale Semiconductor
An eight position circular buffer made up of 16-bit words. section SPI1 Communications. contains the high byte and low byte of a DBUS command. response from the slaves to be received. GENERATION /CHECKING on page 26. Table 9. This bit is read back using the
registers containing check pattern data. Table 9. Register List
0000000 D0R0H DBUS 0 Reg 0 Upper Byte D15 D14 D13 D12 D11 D10 D9 D8
0000001 D0R0L DBUS 0 Reg 0 Lower Byte D7 D6 D5 D4 D3 D2 D1 D0
0000010 D0R0STAT DBUS 0 Reg 0 Status ER TE SDS RNE ICL 0 FIX0 FIX1
0000011 D0R1H DBUS 0 Reg 1 Upper Byte D15 D14 D13 D12 D11 D10 D9 D8
0000100 D0R1L DBUS 0 Reg 1 Lower Byte D7 D6 D5 D4 D3 D2 D1 D0
0000101 D0R1STAT DBUS 0 Reg 1 Status ER TE SDS RNE ICL 0 FIX0 FIX1
0000110 D0R2H DBUS 0 Reg 2 Upper Byte D15 D14 D13 D12 D11 D10 D9 D8
0000111 D0R2L DBUS 0 Reg 2 Lower Byte D7 D6 D5 D4 D3 D2 D1 D0
0001000 D0R2STAT DBUS 0 Reg 2 Status ER TE SDS RNE ICL 0 FIX0 FIX1
0001001 D0R3H DBUS 0 Reg 3 Upper Byte D15 D14 D13 D12 D11 D10 D9 D8
0001010 D0R3L DBUS 0 Reg 3 Lower Byte D7 D6 D5 D4 D3 D2 D1 D0
0001011 D0R3STAT DBUS 0 Reg 3 Status ER TE SDS RNE ICL 0 FIX0 FIX1
0001100 D0CTRL DBUS 0 Control Register - - DLYB DLYA - LOOP1 LOOP0 MS
0001101 D0EN DBUS 0 Enable Register TS ISDD - - - BSWH BSWL EN
0001110 D0POLY DBUS 0 Polynomial CRC
0001111 D0SEED DBUS 0 CRC Seed CRC
0010000 D0LENGTH DBUS 0 Short Word and
0010001 D0SSCTRL DBUS 0 Spread Spectrum
0010010 D0FSEL DBUS 0 Frequency Select FSEL7 FSEL6 FSEL5 FSEL4 FSEL3 FSEL2 FSEL1 FSEL0
0010011 RESERVED Writes/reads of this address
0010100 RESERVED Writes/reads of this address
0010101 D1R0H DBUS 1 Reg 0 Upper Byte D15 D14 D13 D12 D11 D10 D9 D8
0010110 D1R0L DBUS 1 Reg 0 Lower Byte D7 D6 D5 D4 D3 D2 D1 D0
0010111 D1R0STAT DBUS 1 Reg 0 Status ER TE SDS RNE ICL 0 FIX0 FIX1
0011000 D1R1H DBUS 1 Reg 1 Upper Byte D15 D14 D13 D12 D11 D10 D9 D8
0011001 D1R1L DBUS 1 Reg 1 Lower Byte D7 D6 D5 D4 D3 D2 D1 D0
0011010 D1R1STAT DBUS 1 Reg 1 Status ER TE SDS RNE ICL 0 FIX0 FIX1
0011011 D1R2H DBUS 1 Reg 2 Upper Byte D15 D14 D13 D12 D11 D10 D9 D8
0011100 D1R2L DBUS 1 Reg 2 Lower Byte D7 D6 D5 D4 D3 D2 D1 D0
0011101 D1R2STAT DBUS 1 Reg 2 Status ER TE SDS RNE ICL 0 FIX0 FIX1
0011110 D1R3H DBUS 1 Reg 3 Upper Byte D15 D14 D13 D12 D11 D10 D9 D8
0011111 D1R3L DBUS 1 Reg 3 Lower Byte D7 D6 D5 D4 D3 D2 D1 D0
30 Freescale Semiconductor
0100000 D1R3STAT DBUS 1 Reg 3 Status ER TE SDS RNE ICL 0 FIX0 FIX1
0100001 D1CTRL DBUS 1 Control Register - - DLYB DLYA - LOOP1 LOOP0 MS
0100010 D1EN DBUS 1 Enable Register TS ISDD - - - - - EN
0100011 D1POLY DBUS 1 Polynomial CRC
0100100 D1SEED DBUS 1 CRC Seed CRC
0100101 D1LENGTH DBUS 1 Short Word and
0100110 D1SSCTRL DBUS 1 Spread Spectrum
0100111 D1FSEL DBUS 1 Frequency Select FSEL7 FSEL6 FSEL5 FSEL4 FSEL3 FSEL2 FSEL1 FSEL0
0101000 RESERVED Writes/reads of this address
0101001 RESERVED Writes/reads of this address
0101010 D2R0H DBUS 2 Reg 0 Upper Byte D15 D14 D13 D12 D11 D10 D9 D8
0101011 D2R0L DBUS 2 Reg 0 Lower Byte D7 D6 D5 D4 D3 D2 D1 D0
0101100 D2R0STAT DBUS 2 Reg 0 Status ER TE SDS RNE ICL 0 FIX0 FIX1
0101101 D2R1H DBUS 2 Reg 1 Upper Byte D15 D14 D13 D12 D11 D10 D9 D8
0101110 D2R1L DBUS 2 Reg 1 Lower Byte D7 D6 D5 D4 D3 D2 D1 D0
0101111 D2R1STAT DBUS 2 Reg 1 Status ER TE SDS RNE ICL 0 FIX0 FIX1
0110000 D2R2H DBUS 2 Reg 2 Upper Byte D15 D14 D13 D12 D11 D10 D9 D8
0110001 D2R2L DBUS 2 Reg 2 Lower Byte D7 D6 D5 D4 D3 D2 D1 D0
0110010 D2R2STAT DBUS 2 Reg 2 Status ER TE SDS RNE ICL 0 FIX0 FIX1
0110011 D2R3H DBUS 2 Reg 3 Upper Byte D15 D14 D13 D12 D11 D10 D9 D8
0110100 D2R3L DBUS 2 Reg 3 Lower Byte D7 D6 D5 D4 D3 D2 D1 D0
0110101 D2R3STAT DBUS 2 Reg 3 Status ER TE SDS RNE ICL 0 FIX0 FIX1
0110110 D2CTRL DBUS 2 Control Register - - DLYB DLYA - LOOP1 LOOP0 MS
0110111 D2EN DBUS 2 Enable Register TS ISDD - - - - - EN
0111000 D2POLY DBUS 2 Polynomial CRC
0111001 D2SEED DBUS 2 CRC Seed CRC
0111010 D2LENGTH DBUS 2 Short Word and
0111011 D2SSCTRL DBUS 2 Spread Spectrum
0111100 D2FSEL DBUS 2 Frequency Select FSEL7 FSEL6 FSEL5 FSEL4 FSEL3 FSEL2 FSEL1 FSEL0
0111101 RESERVED Writes/reads of this address
0111110 RESERVED Writes/reads of this address
Table 9. Register List (continued)
0111111 D3R0H DBUS 3 Reg 0 Upper Byte D15 D14 D13 D12 D11 D10 D9 D8
1000000 D3R0L DBUS 3 Reg 0 Lower Byte D7 D6 D5 D4 D3 D2 D1 D0
1000001 D3R0STAT DBUS 3 Reg 0 Status ER TE SDS RNE ICL 0 FIX0 FIX1
1000010 D3R1H DBUS 3 Reg 1 Upper Byte D15 D14 D13 D12 D11 D10 D9 D8
1000011 D3R1L DBUS 3 Reg 1 Lower Byte D7 D6 D5 D4 D3 D2 D1 D0
1000100 D3R1STAT DBUS 3 Reg 1 Status ER TE SDS RNE ICL 0 FIX0 FIX1
1000101 D3R2H DBUS 3 Reg 2 Upper Byte D15 D14 D13 D12 D11 D10 D9 D8
1000110 D3R2L DBUS 3 Reg 2 Lower Byte D7 D6 D5 D4 D3 D2 D1 D0
1000111 D3R2STAT DBUS 3 Reg 2 Status ER TE SDS RNE ICL 0 FIX0 FIX1
1001000 D3R3H DBUS 3 Reg 3 Upper Byte D15 D14 D13 D12 D11 D10 D9 D8
1001001 D3R3L DBUS 3 Reg 3 Lower Byte D7 D6 D5 D4 D3 D2 D1 D0
1001010 D3R3STAT DBUS 3 Reg 3 Status ER TE SDS RNE ICL 0 FIX0 FIX1
1001011 D3CTRL DBUS 3 Control Register - - DLYB DLYA - LOOP1 LOOP0 MS
1001100 D3EN DBUS 3 Enable Register TS ISDD - - - - - EN
1001101 D3POLY DBUS 3 Polynomial CRC
1001110 D3SEED DBUS 3 CRC Seed CRC
1001111 D3LENGTH DBUS 3 Short Word and
1010000 D3SSCTRL DBUS 3 Spread Spectrum
1010001 D3FSEL DBUS 3 Frequency Select FSEL7 FSEL6 FSEL5 FSEL4 FSEL3 FSEL2 FSEL1 FSEL0
1010010 MASKID Mask Version ID Code FPAR ID6 ID5 ID4 ID3 ID2 ID1 ID0
1010011 CHKCD0 Check Pattern 0 CKPTN2
1010100 CHKCD1 Check Pattern 1 CKPTN1
1010101 CHKCD2 Check Pattern 2 CKPTN7 CKPTN6 CKPTN5 CKPTN4 CKPTN3 CKPTN2 CKPTN1 CKPTN0
1010110 NCKCD0 Negative Check Pattern 0 NCKPTN
1010111 NCKCD1 Negative Check Pattern 1 NCKPTN
1011000 NCKCD2 Negative Check Pattern 2 NCKPTN
1011001 RESERVED Writes/reads of this address
1011010 RESERVED Writes/reads of this address
32 Freescale Semiconductor
registers, four for each of the buses, as shown in Table 8. Figure 24. DnRnH Data Register Bit Assignments burst transaction, that transaction is ignored. Figure 25. DnRnL Data Register Bit Assignments Figure 26. DnRnSTAT Register Bit Assignments
- 0 = CRC value for the data in the read buffer was correct.
- 1 = CRC value for the data in the read buffer was not correct (data not valid). CRC errors are associated with each receive buffer, so that each buffer has a bit to indicate whether the data in that buffer was received correctly. Whenever a received data value is available in the DnRnH and DnRnL registers, the associated CRC error status is available at ERn in the associated DnRnSTAT register. The ER bit is set or cleared whenever data is written from the DBUS into the DnRnH/L receive registers. If Channel Thermal Shutdown or Idle and SIgnal Mode Disable occur, these bits will be reset along with the other channel register bits. TE–Transmit Register Empty Bit
- 0 = Transmit buffer not empty.
- 1 = Transmit buffer empty. This bit indicates that data has been written to the associated channel register high and/or low, but has not been read for sending on the DBUS. The bit is set to 0 on the rising SPI Data Bit Bit 7 6 5 4 3 2 1 0 Read/Write Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Reset 0 0 0 0 0 0 0 0 SPI Data Bit Bit 7 6 5 4 3 2 1 0 Read/Write Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset 0 0 0 0 0 0 0 0 SPI Data Bit Bit 7 6 5 4 3 2 1 0 Read ER TE SDS RNE ICL 0 FIX0 FIX1 Reset 0 1 0 0 0 0 0 1
34 Freescale Semiconductor
- 00, 01, 10 = Loop Mode disabled.
- 11 = Loop Mode enabled When loop mode is enabled, the transmitter and receiver circuits are connected within the IC. This allows data to be passed directly through the transmit and receive circuits without going out on the DBUS channel. When LOOP mode is enabled, the DBUS channel is disconnected from the transmitter and receiver circuits, so that any bus fault conditions do not interfere with this test. Setting this bit also disables the bus channel and clears the EN bit in the DnEN register. MS–Message Size for Channel n
- 0 = Long Word.
- 1 = Short Word The Long Word will contain 16 bits of data and 0 to 8 bits of CRC. The Short Word can be made to have between 8 and 15 bits of data and 0 to 8 bits of CRC. Long words are generally used for configuration and setup messages. Short words are generally used for DBUS data transactions. DnEN REGISTER This read/write register is used to enable or disable each of the buses. It also allows the channel thermal shutdown and bus driver shutdown bits to be read. The bit assignments are shown in Figure 29
Figure 29. DnEN Register Bits
- 0 = No thermal shutdown occurring on the Channel.
- 1 = Thermal shutdown has occurred on the Channel. If the channel bus thermal limit is reached for either of the channel bus drivers, the channel drivers are disabled and the TS bit is set. There is a 4 μsec filter on Tlim to prevent false triggering. When this bit is set, the channel registers are all reset along with the buffer pointers. Any DBUS transfer that was in progress is stopped. If the shutdown occurs on channel zero, the pseudo bus switches are also opened and the BSWH and BSWL bits are cleared. If the thermal limit is reached on either of the pseudo bus switches (but not on the channel zero drivers), the bus switches are opened, only the BSWH and BSWL bits are cleared, and no other register bits are changed. The TS bit is cleared after a zero has been written to the TS bit. ISDD - Idle and Signal Mode Disable on Channel n
- 0 = Idle and signal mode are active on the Channel.
- 1 = During signaling mode, the bus driver has shut down for sequential transactions on the Channel and the bus drivers are now disabled (high-impedance). If a channel high side or low side bus driver over-current limit is reached during signaling mode in 2 consecutive frames, the bus drivers are disabled and the ISDD bit is set. If the condition occurs on channel zero, the pseudo bus switches are also opened and the BSWH and BSWL bits are cleared. In addition, the channel buffer registers are reset, the buffer pointers are reset, and the EN bit is cleared. The remainder of the channel registers are not changed. Any DBUS transfer that was in progress is stopped. The ISDD bit is cleared when the MCU writes a zero to this bit. BSWH - Bus Switch High Enable
- 0 = Channel 0 Bus High Switch Open
- 1 = Channel 0 Bus High Switch Close Channel 0 of the 33781 has a switch on both the high side and the low side of the bus output driver to allow the channel to drive two separate sets of bus wires. Through this bus switch the bus receiver can also receive data from slaves on both of these buses. When the BSWH bit is written as zero, the high side bus switch will be open. When the bit is written as a 1, the high side bus switch will be closed. Reads of this bit show the current state of the high side bus switch. The BSWH bit is cleared and the bus switch opened if a channel zero thermal shutdown occurs, if the channel zero EN bit is cleared or ISDD bit is set, or if the high side or low side pseudo bus thermal limit is exceeded. It is necessary to write a one to the BSWH bit to close the switch again. BSWL - Bus Switch Low Enable
- 0 = Channel 0 Bus Low Switch Open
- 1 = Channel 0 Bus Low Switch Close When the BSWL bit is written as zero, the low side bus switch will be open. When the bit is written as a 1, the low side bus switch will be closed. Reads of this bit show the current state of the low side bus switch. The BSWL bit is cleared and the bus switch opened, if a channel 0 thermal shutdown occurs, if the channel zero EN 10 6 11 8
Table 10. DLY[B:A] Frame Spacing (continued)
36 Freescale Semiconductor
command that will be sent onto the specified DBUS channel. the value 8 (1000) is automatically written into this register. register. The bit assignments are shown in Figure 33. Figure 33. Dn Spread Spectrum Control Register Bit Assignment DEV[2:0] = 000 - No Deviation. fine control of the bit rate without frequency spreading. Figure 34. Dn Frequency Selection Register Bit Assignments rate and minimum bit time for fCLK = 4.0MHz.
Analog Integrated Circuit Device Data
38 Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION PROTECTION AND DIAGNOSTIC FEATURES PROTECTION AND DIAGNOSTIC FEATURES OVER-CURRENT PROTECTION Current limiters on the outputs prevent damage in the case of shorts. Running in current limit results in high power dissipation of the IC. If the power dissipation becomes high enough, the die temperature will rise above its maximum rating and an over-temperature circuit on the IC will shut down the DBUS Driver/Receiver block. Each channel high and low side bus drivers have current limits for protection of both this device and slave devices connected on the DBUS. During idle mode, the DnH drivers have a high value current limit when sourcing current to allow the drivers to charge the slave power storage capacitors, and a lower value current limit when sinking current and slewing the load capacitance. Conversely, the DnL drivers have a high value current limit when they are sinking current, and a lower value current limit when they are sourcing current. In addition, the device monitors the current limit on each channel to see if the channel is in “double current limit” during every idle state. See ICL - Idle Mode Double Current Limit Bit (Idle Mode Shutdown) on page 33. If the idle current limit is detected, the ICL bit is set in the DnSTAT register for the next DBUS transaction. During signaling mode, the drivers incorporate a gross current limit and an over-current shutdown. The current shutdown is set at a low value, such that the channel high and low side bus driver will shut down if the sourcing or sinking current remains at a value larger than the response current. The over-current shutdown is delayed by a filter to allow the load capacitors to be slewed without causing a shutdown. The purpose of the gross current limit is to protect the drivers during the filter delay time. This current limit is set higher than the peak current required to slew the load capacitance. The signals from the sourcing and sinking current detection circuits are connected to a logical OR. The combined signal passes through a common filter before setting the over-current latch. During signaling mode, the over-current shutdown disables both bus drivers and sets the SDS (Signal Driver Shutdown) bit in the appropriate DnSTAT register. The drivers remain high-impedance until the end of Frame, when the bus returns to the Idle state. The end of Frame clears the over-current shutdown state, allowing the bus drivers to retry in the next Frame. However, if the signal mode over-current shutdown occurs in two sequential frames for the channel, the bus drivers are disabled and can only be re-enabled on command from the MCU. The ISDD bit is also set in the channel DEN register. If the affected channel is channel 0 this set of conditions also disables the pseudo bus switch. THERMAL PROTECTION Independent thermal protection is provided for each channel and the Pseudo bus switches. The thermal limit cell is located adjacent to the bus drivers for each channel, such that both drivers are protected. When a thermal fault is detected, the channel drivers are disabled (Hi-Z) until they are re-enabled via the SPI. The thermal protection incorporates hysteresis, preventing the channel bus drivers from being re-enabled until the temperature has decreased. Thermal fault information is reported via the DEN register. See DnEN Register section for a description of the fault reporting and clearing of the EN bits. LOAD DUMP OPERATION During an over-voltage condition (e.g., when load dump is applied at the VSUPn pins), the DBUS voltage waveform is modified to ensure that power dissipation is minimized, DBUS timing is not violated, and internal components are protected. The midpoint of the signalling voltage is clamped at about 13V, such that for V SUPn greater than 26V, the signalling voltage levels do not increase. An over-voltage detection circuit connected to DnH, having a threshold at about 26V, causes the slew rates and driver conditions to be modified. For a Signal-to-Idle transition, this causes the DnH voltage to rise rapidly to the Idle state, and the DnL voltage is maintained close to zero. For an Idle-to-Signal transition, the DnH voltage will decrease rapidly until the over-voltage threshold is reached, when normal operation resumes. During this rapid fall of DnH, the DnL voltage is maintained close to zero by forcing that driver on. See Figure 6 RESET FUNCTION A low level on RST forces all internal registers to a known (reset) state and the receive and transmit queue pointers are reset. Because the DBUS channels are now disabled (ENn = 0), the DBUS lines are tri-stated. ABORT FUNCTION An abort is generated on a channel whenever a control register (DnCTRL, DnPOLY, DnSEED, DnLENGTH, DnSSCTRL or DnFSEL) is addressed while writing, even if the data is unchanged. No other register writes cause an abort, and reads of any register do not cause an abort. The abort is only taken for the channel where the write occurs - all other channels are not effected. The DEN register is not affected by an abort. The abort occurs as soon as the address of the control register is received on the SPI. Any DBUS transfer that was in progress is stopped, and DBUS lines return to their Idle states. The abort condition remains true throughout the SPI0 write to the DBUS control registers. After the last bit of the DBUS control register is written, the channel addressed buffer data bits and the SPI1 registers are cleared, the status register bits are reset, and the transmit and receive queue pointers are reset for both SPI0 and SPI1. The programmed inter-frame delay is then enforced (using the new values of the delay control bits) to allow reservoir capacitors in remote
Analog Integrated Circuit Device Data Freescale Semiconductor 39 33781 FUNCTIONAL DEVICE OPERATION PROTECTION AND DIAGNOSTIC FEATURES nodes to charge. In the case of DLY changing, any partial inter-frame delay based on old control settings is lost. ENABLE (DISABLE) FUNCTION When a DBUS channel is disabled, the 33781 device forces its bus output to tri-state. When the channel is disabled the channel addressed buffer data bits are cleared, the status register bits are reset, and the transmit and receive queue reset. Any DBUS transfer that was in progress is stopped. CHANNEL LOOP FUNCTION When loop mode is enabled the transmitter and receiver circuits are connected within the IC. This allows data to be passed directly through the transmit and receive circuits without going out on the DBUS channel. When LOOP mode is enabled the DBUS channel is disconnected from the transmitter and receiver circuits so that any bus fault conditions do not interfere with this test. When the loop function is enabled, the EN bit in the DnEN register is cleared, the buffer data bits are cleared, the status register bits are reset, and the transmit and receive queue reset the by the state machine. When the loop mode is exited the state machine sets the registers to their reset state and resets the transmit and receive queue. This allows proper start up of bus transactions. The channel queue pointers work the same as in non-loop mode.
Analog Integrated Circuit Device Data
40 Freescale Semiconductor
For the most current package revision, visit www.freescale.com and perform a keyword search using the “98A” listed below. EK SUFFIX (PB-FREE) 32-PIN 98ASA10556D ISSUE B
Analog Integrated Circuit Device Data Freescale Semiconductor 41 33781 PACKAGE DIMENSIONS EK SUFFIX (PB-FREE) 32-PIN 98ASA10556D ISSUE B
Analog Integrated Circuit Device Data
42 Freescale Semiconductor
EK SUFFIX (PB-FREE) 32-PIN 98ASA10556D ISSUE B
Analog Integrated Circuit Device Data Freescale Semiconductor 43 33781
REVISION HISTORY
REVISION DATE DESCRIPTION OF CHANGES 1 3/2008 • Initial Release 2 5/2008 • Deleted rows from Figure 7, Receiver Decision Logic
- Corrected several parameter adjustments 3 7/2008 • Numerous minor label and limit changes to Electrical Characteristics
- Text corresponding to the changes in the El ectrical Characteristics were also made. 4 7/2008 • Changed line to read: In addition, the device monitors the current limit on each channel to see if the channel is in “double current limit” during every idle state. In the OVER- CURRENT Protection
Rev. 4.0 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”, must be validated for each customer application by customer’s technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc., 2007-2008. All rights reserved. How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. Technical Information Center, EL516
2100 East Elliot Road
Tempe, Arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.com/support Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7
81829 Muenchen, Germany
+44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) www.freescale.com/support Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo 153-0064 Japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com Asia/Pacific: Freescale Semiconductor Hong Kong Ltd. Technical Information Center
2 Dai King Street
Tai Po, N.T., Hong Kong +800 2666 8080 support.asia@freescale.com For Literature Requests Only: Freescale Semiconductor Literature Distribution Center P .O. Box 5405 Denver, Colorado 80217 1-800-441-2447 or 303-675-2140 Fax: 303-675-2150 LDCForFreescaleSemiconductor@hibbertgroup.com