MC33742 MOTOROLA | Alldatasheet

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Technical content

Features

• High-Speed 1.0 Mbps CAN Interface with Bus Diagnostic Capability (Detection of CANH and CANL Short to Ground, to VDD, and to VSUP) • Low-Drop Voltage 5.0 V, 200 mA V DD Regulator with Current-Limiting, Overtemperature Pre-Warning, and Output Monitoring with Reset • Additional 5.0 V Regulator with External Series Pass Transistor • Normal, Standby, Stop, and Sleep Modes with Low Sleep and Stop Mode Current • 150 mA High-Side Switch Output for Control of External Circuitry • Four External Wake-Up Inputs • Software-Programmable Watchdog Window, Interrupt, and Reset SYSTEM BASIS CHIP WITH ENHANCED HIGH-SPEED CAN

ORDERING INFORMATION

Range (TA) Package MC33742DW/R2 -40°C to 125°C 28 SOICW MC33742SDW/R2 DW SUFFIX CASE 751F-05 28-TERMINAL SOICW Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

33742 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

Figure 1. 33742 Simplified Internal Block Diagram Table 1. Significance Device Differences condition occurred and if the watchdog register is not properly triggered. condition occurred and if the watchdog register is not properly triggered.

5.0 V/200 mA

Freescale Semiconductor, Inc.

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33742 TERMINAL DEFINITIONS A functional description of each terminal can be found in the System/Application Information section beginning on page 18. Terminal Terminal Name Formal Name Definition 1R X D Receive Data CAN bus receive data output 2T X D Transmit Data CAN bus transmit data input 3V DD Voltage Digital Drain 5.0 V regulator output terminal.

4 RST Reset Output

(Active LOW) This is the device reset output whose main function is to reset the MCU. This terminal has an internal pull-up current source to VDD

5 INT Interrupt Output

(Active LOW) This output is asserted LOW when an enabled interrupt condition occurs. The output is a push-pull structure. 6–9 20–23 GND Ground Ground of the IC. These terminals are co nnected to the package lead frame in order to provide a thermal path. 10 V2 Voltage Source 2 Sense input for V2 regulator using exter nal ballast. V2 is also the internal supply for the CAN cell. 11 V2CTRL Voltage Source 2 Control Output driver for the external ballast transistor. 12 V SUP Voltage Supply Supply input for the complete device. 13 HS High-Side Output Output of internal high-side switch. Current capability is internally limited to 150 mA. 14–17 L0–L3 Level 0 –3 Inputs Input interfaces to external circuitr y (switched or ICs). Levels at these terminals can be read by SPI and input can be used as programmable wake-up input in Sleep or Stop mode. 18 CANH CAN High CAN high output. 19 CANL CAN Low CAN low output. 24 SCLK Serial Data Clock Clock input for the Seri al Peripheral Interface (SPI) of the device. 25 MISO Master In/Slave Out SPI data sent to MCU. When CS is HIGH, terminal is high impedance. 26 MOSI Master Out/Slave In SPI data received by the 33742.

27 CS Chip Select

(Active LOW) Chip select terminal for SPI. When CS is LOW, device is selected.

28 WDOG Watchdog Output

(Active LOW) Output of watchdog circuitry. Terminal is asserted LOW if software watchdog is not correctly triggered. WDOG MISO SCLK GND GND GND GND CANL CANH CS MOSI RXD RST INT GND GND GND GND V2CTRL V SUP HS TXD VDD Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

All voltages are with respect to ground unless otherwise noted.

  1. ESD1 testing is performed in accordance with the Human Body Model (C ZAP=100 pF, RZAP=1500 Ω).
  2. ESD2 testing is performed in ac cordance with the Machine Model (CZAP=200 pF, RZAP=0 Ω).
  3. Testing in accordance with ISO 7637-1. See also Figure 2.
  4. Maximum power dissipation at 85°C ambient temperature in free air with no heatsink, according to JEDEC JESD51-2 and JESD51-3
  5. Load dump test in accordance with ISO 7637-1.
  6. Transient test in accordance with ISO 7637-1. See also Figure 3.

Figure 2. ISO 7637 Test Setup for L0:L3 Inputs Figure 3. ISO 7637 Test Setup for CANH/CANL Note Waveform per ISO 7637-1. Test Pulses 1, 2, 3a, and 3b. Note Waveform per ISO 7637-1. Test Pulses 1, 2, 3a, and 3b. Freescale Semiconductor, Inc.

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33742 THERMAL RATINGS Operating Temperature Ambient Junction TA TJ -40 to 125 -40 to 150 Storage Temperature TSTG -55 to 165 °C Thermal Resistance Junction to GND Terminals RθJG 20 °C/W Peak Package Reflow Temperature During Solder Mounting (Note 7) TSOLDER 240 °C Notes 7. Terminal soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. MAXIMUM RATINGS (continued) All voltages are with respect to ground unless otherwise noted. Rating Symbol Value Unit Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

STATIC ELECTRICAL CHARACTERISTICS Characteristics noted under conditions 4.75 V ≤ V2 ≤ 5.25 V, 5.5 V ≤ VSUP ≤ 18 V, and -40°C ≤ TA ≤ 125°C. Typical values noted reflect the approximate parameter mean at TA =2 5°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit VSUP TERMINAL Nominal DC Supply Voltage VSUP 5.5 – 18 V Extended DC Voltage Full Functionality (Note 8) Reduced Functionality (Note 9) VSUP-EX 4.5 5.5 V Input Voltage During Load Dump VSUP-LD –– 4 0 V Input Voltage During Jump Start VSUP-JS –– 2 7 V Supply Current in Standby Mode (Note 10) (IOUT at VDD = 10 mA, CAN Recessive or Sleep Mode) TA ≥ 25°C TA =- 40°Ct o2 5°C ISUP(STDBY) 14.5 mA Supply Current in Normal Mode (Note 10) (IOUT at VDD = 10 mA, CAN Recessive or Sleep Mode) TA ≥ 25°C TA =- 40°Ct o2 5°C ISUP(NORM) 12.4 mA Supply Current in Sleep Mode (Note 10) [VDD and V2 OFF, CAN in Sleep Mode with CAN Wake-Up Disabled (Note 11)] VSUP < 13.5 V, Oscillator Running (Note 12) VSUP < 13.5 V, Oscillator Not Running (Note 13) VSUP = 18 V, Oscillator Running (Note 12) ISUP(SLP-WD) 110 105 140 µA Supply Current in Sleep Mode (Note 10) [V DD and V2 OFF, VSUP < 13.5 V, Oscillator Not Running (Note 13), CAN in Sleep Mode with Wake-Up Enabled] TA =- 4 0°C TA =2 5°C TA = 125°C ISUP(SLP-WE) µA Supply Current in Stop Mode (Note 10) [I OUT at VDD < 2.0 mA, VDD ON, CAN in Sleep Mode with Wake-Up Disabled (Note 11) VSUP < 13.5 V, Oscillator Running (Note 12) VSUP < 13.5 V, Oscillator Not Running (Note 13) VSUP = 18 V, Oscillator Running (Note 12) ISUP(STOP-WD) 100 160 160 210 µA Notes 8. All functions and modes av ailable and operating. Watchdog, HS turn ON/turn OF F, CAN cell operating, L0:L3 inputs operating, S PI read/ write operation. Overtemperature may occur. 9. V DD > 4.0 V, RST HIGH if reset 2 selected by SPI, logic terminal high level reduced, device is functional. 10. Current measured at V SUP terminal. 11. If CAN cell is Sleep-Enabled for wake-up, an additional current (ICAN-SLEEP) must be added to specified value. 12. Oscillator running means one of the foll owing function is active: Forced Wake-Up or Cyclic Sense or Software Watchdog in Stop mode. 13. Oscillator not running means none of the follo wing functions are active: Forced Wake-Up and Cyclic Sense and Software Watchdog in Stop mode. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33742 STATIC ELECTRICAL CHARACTERISTICS (continued) Characteristics noted under conditions 4.75 V ≤ V2 ≤ 5.25 V, 5.5 V ≤ VSUP ≤ 18 V, and -40°C ≤ TA ≤ 125°C. Typical values noted reflect the approximate parameter mean at TA =2 5°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit VSUP TERMINAL (continued) Supply Current in Stop Mode (Note 14) [IOUT at VDD < 2.0 mA, VDD ON, VSUP < 13.5 V, Oscillator Not Running (Note 15), CAN in Sleep Mode with Wake-Up Enabled] TA =- 4 0°C TA =2 5°C TA = 125°C ISUP(STOP-WE) 100 µA BATFAIL Flag Internal Threshold V BF 1.5 3.0 4.0 V BATFAIL Flag Hysteresis (Note 16) VBF(HYS) –1 . 0– V Battery Fall Early Warning Threshold In Normal and Standby Modes VBF(EW) 5.3 5.8 6.3 V Battery Fall Early Warning Hysteresis In Normal and Standby Modes (Note 16) VBF(EW-HYST) 0.1 0.2 0.3 V VDD TERMINAL (Note 17) VDD Output Voltage (2.0 mA < IDD < 200 mA)

5.5 V < VSUP < 27 V

4.5 V < VSUP < 5.5 V VDDOUT 4.9 4.0 5.0 5.1 V Dropout Voltage IDD = 200 mA VDDDRP1 – 0.2 0.5 V Dropout Voltage, Limited Output Current and Low VSUP IDD = 50 mA, 4.5 V < VSUP VDDDRP2 –0 . 1 0 . 2 5 V VDD Output Current Internally Limited IDD 200 285 350 mA Thermal Shutdown (Junction) Normal or Standby Mode TSD 160 – 200 Overtemperature Pre-Warning (Junction) VDDTEMP Bit Set TPW 125 – 160 Temperature Threshold Difference TSD - TPW 20 – 40 °C RST Threshold, Selectable by RSTTH Bit in SPI Register RCR Threshold 1, Default Value after Reset, RSTTH Bit set to 0 Threshold 2, RSTTH bit Set to 1 VRSTTH 4.5 4.0 4.6 4.2 4.7 4.3 V VDD for Reset Active V DDR 1.0 – VRSTTH V Notes 14. Current measured at V SUP terminal. 15. Oscillator not running means none of the follo wing functions are active: Forced Wake-Up and Cyclic Sense and Software Watchdog in Stop mode. 16. Guaranteed by design; however, it is not production tested. 17. I DD is the total regulator output current. VDD specification with external capacitor. Stability requirement: Capacitance > 47 µF, ESR < 1.3 Ω (tantalum capacitor). In Reset, Normal Request, Normal and Standby modes. Measures with capacitance = 47 µF tantalum. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

STATIC ELECTRICAL CHARACTERISTICS (continued) Characteristics noted under conditions 4.75 V ≤ V2 ≤ 5.25 V, 5.5 V ≤ VSUP ≤ 18 V, and -40°C ≤ TA ≤ 125°C. Typical values noted reflect the approximate parameter mean at TA =2 5°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit VDD TERMINAL (continued) (Note 18) Line Regulation (IDD = 10 mA, Capacitance = 47 µF Tantalum at VDD)

9.0 V < VSUP < 18 V

5.0 mV Load Regulation (Capacitance = 47 µF Tantalum at VDD) 1.0 mA < IDD < 200 mA VLD – 25 75 mV Thermal Stability VSUP = 13.5 V, IDD = 100 mA (Note 19) VTHERM-S –3 0 5 0 mV VDD TERMINAL IN STOP MODE (Note 18) VDD Output Voltage IDD ≤ 2.0 mA IDD ≤ 10 mA VDDSTOP 4.75 4.75 5.0 5.0 5.25 5.25 V IDD Output Current to Wake-Up IDDS-WU 10 17 25 mA Reset Threshold Selectable by SPI, Default Value after Reset, Bit Value 0 Selectable by SPI, Bit Value 1 VRST-STOP 4.5 4.1 4.6 4.2 4.7 4.3 V Line Regulation (Capacitance = 47 µF Tantalum at VDD) 5.5 V < VSUP < 27 V, IDD = 2.0 mA VLR-STOP –5 . 0 2 5 mV Load Regulation (Capacitance = 47 µF Tantalum at VDD) 1.0 mA < IDD < 10 mA VLD-STOP –1 5 7 5 mV V2 TRACKING VOLTAGE REGULATOR (Note 20) V2 Output Voltage (Capacitance = 10 µF Tantalum at V2) 2.0 mA ≤ I2 ≤ 200 mA, 5.5 V < VSUP < 27 V 0.99 1.0 1.01 VDD I2 Output Current (for Information Only) Depending on External Ballast Transistor 200 – – mA V2 Control Drive Current Capability (Note 21) Worst Case at TJ = 125°C I2CTRL 0– 1 0 mA V2LOW Flag Threshold V2LTH 3.75 4.0 4.25 V Notes 18. I DD is the total regulator output current. VDD specification with external capacitor. Stability requirement: capacitance > 47 µF, ESR < 1.3 Ω (tantalum capacitor). In Reset, Normal Request, Normal and Standby modes, measures with capacitance = 47 µF tantalum. 19. Guaranteed by characterization and design; however, it is not production tested. 20. V2 specification with external capac itor. Stability requirement: capacitance > 42 µF and ESR < 1.3 Ω (tantalum capacitor), external resistor between base and emitter required. Measurement conditions: ballast transistor MJD32C, capacitance > 10 µF tantalum, 2.2 kΩ resistor between base and emitter of ballast transistor. 21. Guaranteed current capability of the V2CTRL terminal is 10 mA . Current may be higher. No active limitation is provided. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33742 STATIC ELECTRICAL CHARACTERISTICS (continued) Characteristics noted under conditions 4.75 V ≤ V2 ≤ 5.25 V, 5.5 V ≤ VSUP ≤ 18 V, and -40°C ≤ TA ≤ 125°C. Typical values noted reflect the approximate parameter mean at TA =2 5°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit LOGIC OUTPUT TERMINAL (MISO) (Note 22) Low-Level Output Voltage IOUT = 1.5 mA VOL 0– 1 . 0 V High-Level Output Voltage IOUT = -250 µA VOH VDD-0 . 9 – V DD V Tri-Stated MISO Leakage Current 0V < VMISO < VDD IHZ -2.0 – 2.0 µA LOGIC INPUT TERMINALS (MOSI, SCLK, CS) High-Level Input Voltage VIH 0.7 VDD –V DD + 0.3 V Low-Level Input Voltage VIL -0.3 – 0.3 V DD V High-Level Input Current on CS VI = 4.0 V IIH -100 – -20 µA Low-Level Input Current on CS VI = 1.0 V IIL -100 – -20 µA MOSI and SCLK Input Current 0V < VIN < VDD IIN -10 – 10 µA RST OUTPUT TERMINAL (Note 23) High-Level Output Current 0V < VOUT < 0.7 VDD IOH -300 -250 -150 µA Low-Level Output Voltage IO = 1.5 mA, 5.5 V < VSUP < 27 V IO = 0 mA, 1.0 V <VSUP < 5.5 V VOL 0.9 0.9 V RST Pulldown Current V > 0.9 V IPDW 2 . 3–5 . 0 mA WDOG OUTPUT TERMINAL (Note 24) Low-Level Output Voltage IO = 1 . 5m A , 1 . 0V < VSUP < 27 V VOL 0– 0 . 9 V High-Level Output Voltage IO = -250 µA VOH VDD-0.9 – V DD V INT OUTPUT TERMINAL (Note 24) Low-Level Output Voltage IO = 1.5 mA VOL 0– 0 . 9 V High-Level Output Voltage IO = -250 µA VOH VDD-0.9 – V DD V Notes 22. Push-pull structure with tri-state condition ( CS HIGH). 23. Output terminal only. Supply from V DD. Structure switch to ground with pullup current source. 24. Push-pull structure. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

STATIC ELECTRICAL CHARACTERISTICS (continued) Characteristics noted under conditions 4.75 V ≤ V2 ≤ 5.25 V, 5.5 V ≤ VSUP ≤ 18 V, and -40°C ≤ TA ≤ 125°C. Typical values noted reflect the approximate parameter mean at TA =2 5°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit HS OUTPUT TERMINAL Driver Output ON Resistance TJ = 25°C, IOUT - 150 mA, VSUP > 9.0 V TA = 125°C, IOUT - 150 mA, VSUP > 9.0 V TA = 125°C, IOUT - 120 mA, 5.5 V < VSUP < 9.0 V RDS(ON) 2.0 3.5 2.5 4.5 5.5 Ω Output Current Limitation V SUP - VHS > 1.0 V ILIM 160 – 500 mA HS Thermal Shutdown TSD 155 – 190 °C HS Leakage Current ILEAK –– 1 0 µA Output Clamp Voltage IOUT = -10 mA, No Inductive Load Drive Capability VCL -1.5 – -0.3 V L0, L2, L2, AND L3 INPUT TERMINALS Negative Switching Threshold 5.5 V < VSUP < 6.0 V

6.0 V < VSUP < 18 V

18 V < VSUP < 27 V

2.0 2.5 2.7 2.5 3.0 3.2 3.0 3.6 3.7 V Positive Switching Threshold

5.5 V < V

SUP < 6.0 V 2.7 3.0 3.5 3.3 4.0 4.2 3.8 4.6 4.7 V Hysteresis SUP < 27 V VHYST 0.6 – 1.3 V Input Current -0.2 V < VIN < 40 V IIN -10 – 10 µA CAN SUPPLY Supply Current of CAN Cell CAN in Normal Mode, Bus Recessive State CAN in Normal Mode, Bus Dominant State without Bus Load CAN in Sleep State, Wake-Up Enabled, V2 Regulator OFF CAN in Sleep State, Wake-Up Disabled, V2 Regulator OFF (Note 25) IRES IDOM ICAN-SLEEP IDIS 1.3 1.5 3.0 3.5 1.0 mA mA µA µA Notes 25. Guaranteed by design; however, it is not production tested. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33742 STATIC ELECTRICAL CHARACTERISTICS (continued) Characteristics noted under conditions 4.75 V ≤ V2 ≤ 5.25 V, 5.5 V ≤ VSUP ≤ 18 V, and -40°C ≤ TA ≤ 125°C. Typical values noted reflect the approximate parameter mean at TA =2 5°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit CANH AND CANL TERMINALS Bus Terminals Common Mode Voltage VCM -27 – 40 V Differential Input Voltage (Common Mode Between -3.0 V and 7.0 V) Recessive State at RXD Dominant State at RXD VCANH - VCANL 900 500 mV Differential Input Hysteresis (RXD) VHYST 100 – – mV Input Resistance RIN 5.0 – 100 k Ω Differential Input Resistance RIND 10 – 100 k Ω CANH Output Voltage TXD Dominant State TXD Recessive State VCANH 2.75 4.5 3.0 V CANL Output Voltage TXD Dominant State TXD Recessive State VCANL 0.5 2.0 2.25 V Differential Output Voltage TXD Dominant State TXD Recessive State VoH-VoL 1.5 3.0 100 V mV Output Current Capability (Dominant State) CANH CANL ICANH ICANL -35 mA Overtemperature Shutdown TSD 160 180 – °C CANL Overcurrent Detection (Note 26) CANL CANH ICANL/OC ICANH/OC -200 200 -60 mA CANH and CANL Input Current, Device Supplied (CAN Sleep Mode with CAN Wake-Up Enabled or Disabled) VCANH, VCANL from 0 V to 5.0 V VCANH, VCANL =- 2 . 0 V VCANH, VCANL =7 . 0V ICAN1 -60 3.0 -50 µA CANH and CANL Input Current, Device Unsupplied VCANH, VCANL = 2.5 V VCANH, VCANL = -2.0 V VCANH, VCANL =7 . 0 V ICAN2 -60 -50 190 100 240 µA Notes 26. Reported in CAN register. For a description of the contents of the CAN register, refer to CAN Register (CAN) on page 40. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

STATIC ELECTRICAL CHARACTERISTICS (continued) Characteristics noted under conditions 4.75 V ≤ V2 ≤ 5.25 V, 5.5 V ≤ VSUP ≤ 18 V, and -40°C ≤ TA ≤ 125°C. Typical values noted reflect the approximate parameter mean at TA =2 5°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit CANH AND CANL DIAGNOSTIC INFORMATION CANL to GND Threshold VLG –1 . 7 5– V CANH to GND Threshold VHG –1 . 7 5– V CANL to VSUP Threshold VLVB –V SUP -2 . 0 – V CANH to VSUP Threshold VHVB –V SUP -2 . 0 – V CANL to VDD Threshold VL5 –V DD-0 . 4 3 – V CANH to VDD Threshold VH5 –V DD-0 . 4 3 – V RXD Weak Pulldown Current Source (Note 27) RXD Permanent Dominant Failure Condition IRXDW – 100 – µA TXD AND RXD TERMINALS TXD Input High Voltage VIH 0.7 VDD – VDD +0 . 4 V TXD Input Low Voltage VIL -0.4 – 0.3 V DD V TXD High-Level Input Current VTXD = V2 IIH -10 – 10 µA TXD Low-Level Input Current VTXD = 0 V IIL -150 -100 -50 µA RXD Output High Voltage IRXD = 250 µA VOH VDD - 1.0 –– V RXD Output Low Voltage IRXD = 1.0 mA VOL –– 0 . 5 V Notes 27. Guaranteed by design; however, it is not production tested. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33742 DYNAMIC ELECTRICAL CHARACTERISTICS Characteristics noted under conditions 4.75 V ≤ V2 ≤ 5.25 V, 5.5 V ≤ VSUP ≤ 18 V, and -40°C ≤ TA ≤ 125°C. Typical values noted reflect the approximate parameter mean at TA =2 5°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit DIGITAL INTERFACE TIMING (Note 28) SPI Operation Frequency fREQ 0.25 – 4.0 MHz SCLK Clock Period tPCLK 250 – N/A ns SCLK Clock High Time tWSCLKH 125 – N/A ns SCLK Clock Low Time tWSCLKL 125 – N/A ns Falling Edge of CS to Rising Edge of SCLK tLEAD 100 – N/A ns Falling Edge of SCLK to Rising Edge of CS tLAG 100 – N/A ns MOSI to Falling Edge of SCLK tSISU 40 – N/A ns Falling Edge of SCLK to MOSI tSIH 40 – N/A ns MISO Rise Time (Note 29) CL = 220 pF tRSO –2 5 5 0 ns MISO Fall Time (Note 29) CL = 220 pF tFSO –2 5 5 0 ns Time from Falling or Rising Edges of CS MISO Low Impedance MISO High Impedance tSOEN tSODIS ns Time from Rising Edge of SCLK to MISO Data Valid 0.2 VDD ≤ MISO ≥ 0.8 VDD, CL = 200 pF tVALID –– 5 0 ns STATE MACHINE TIMING Delay Between CS LOW-to-HIGH Transition (at End of SPI Stop Command) and Stop Mode Activation (Note 30) tCS-STOP 1 8–3 4 µs Interrupt Low-Level Duration Stop Mode tINT 7.0 10 13 µs Internal Oscillator Frequency (Note 31) fOSC – 100 – kHz Watchdog Period Normal and Standby Modes Period 1 Period 2 Period 3 Period 4 tWD 8.58 39.6 308 9.75 100 350 10.92 50.4 112 392 ms Notes 28. See Figure 4, SPI Timing Diagram, page 17. 29. Not production tested. Guaranteed by design. 30. Not production tested. Guaranteed by design. Detected by V2 OFF. 31. fOSC is indirectly measured (1.0 ms reset) and trimmed. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

DYNAMIC ELECTRICAL CHARACTERISTICS (continued) Characteristics noted under conditions 4.75 V ≤ V2 ≤ 5.25 V, 5.5 V ≤ VSUP ≤ 18 V, and -40°C ≤ TA ≤ 125°C. Typical values noted reflect the approximate parameter mean at TA =2 5°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit STATE MACHINE TIMING (continued) Normal Request Mode Timeout Normal Request Mode tNRTOUT 308 350 392 ms Watchdog Period Stop Mode Period 1 Period 2 Period 3 Period 4 tWD-STOP 6.82 31.5 245 9.75 100 350 12.7 58.5 130 455 ms Watchdog Period Accuracy Normal and Standby Modes Stop Mode fACC -12 -30 Cyclic Sense/FWU Timing Sleep and Stop Modes Timing 1 Timing 2 Timing 3 Timing 4 Timing 5 Timing 6 Timing 7 Timing 8 tCSFWU 3.22 6.47 12.9 25.9 51.8 66.8 134 271 4.6 9.25 18.5 95.5 191 388 5.98 48.1 96.2 124 248 504 ms Cyclic Sense ON Time Sleep and Stop Modes. tON 200 350 500 µs Cyclic Sense/FWU Timing Accuracy Sleep and Stop Modes tACC -30 – 30 Delay Between SPI Command and HS Turn ON (Note 32) Normal or Standby Mode, VSUP > 9.0 V tS-HSON –– 22 µs Delay Between SPI Command and HS Turn OFF (Note 32) Normal or Standby Mode, VSUP > 9.0 V tS-HSOFF –– 22 µs Delay Between SPI and V2 Turn ON (Note 32) Standby Mode tS-V2ON 9.0 – 22 µs Delay Between SPI and V2 Turn OFF (Note 32) Normal Mode tS-V2OFF 9.0 – 22 µs Delay Between Normal Request and Normal Mode After Watchdog Trigger Command (Note 32) Normal Request Mode tS-NR2N 15 35 70 µs Delay Between SPI and CAN Normal Mode (Note 32) Normal Mode (Note 33) tS-CAN_N –– 1 0 µs Delay Between SPI and CAN Sleep Mode (Note 32) Normal Mode (Note 33) tS-CAN_S –– 1 0 µs Notes 32. Delay starts at falling edge of clock cycle #8 of the SPI command and start of “Turn ON” or “Turn OFF” of HS or V2. 33. Guaranteed by design; however, it is not production tested. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33742 DYNAMIC ELECTRICAL CHARACTERISTICS (continued) Characteristics noted under conditions 4.75 V ≤ V2 ≤ 5.25 V, 5.5 V ≤ VSUP ≤ 18 V, and -40°C ≤ TA ≤ 125°C. Typical values noted reflect the approximate parameter mean at TA =2 5°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit STATE MACHINE TIMING (continued) Delay Between CS Wake-Up (CS LOW to HIGH) and Device in Normal Request Mode (VDD ON and RST HIGH) Stop Mode tW-CS 15 40 90 µs Delay Between CS Wake-Up (CS LOW to HIGH) and First Accepted SPI Command Device in Stop Mode After Wake-Up tW-SPI 90 – N/A µs Delay Between INT Pulse and First SPI Command Accepted Device in Stop Mode After Wake-Up tS-1STSPI 20 – N/A µs Delay Between Two SPI Messages Addressing the Same Register t2SPI 25 – – µs VDD TERMINAL Reset Delay Time Measured at 50% of Reset Signal tD 4.0 – 30 µs IDD Overcurrent to Wake-Up Deglitcher Time (Note 34) tIDD-DGLT 40 55 75 µs RST TERMINAL Reset Duration After VDD HIGH 33742 33742S tRSTDUR tRSTDURS 3.0 3.5 4.0 ms L0, L2, L2, AND L3 INPUT TERMINALS Wake-Up Filter Time tWUF 8.0 20 38 µs Notes 34. Guaranteed by design; however, it is not production tested. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

DYNAMIC ELECTRICAL CHARACTERISTICS (continued) Characteristics noted under conditions 4.75 V ≤ V2 ≤ 5.25 V, 5.5 V ≤ VSUP ≤ 18 V, and -40°C ≤ TA ≤ 125°C. Typical values noted reflect the approximate parameter mean at TA =2 5°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit CAN MODULE TIMING Dominant State Timeout tDOUT 200 360 520 µs Propagation Loop Delay TXD to RXD (Recessive to Dominant) (Note 35) Slew Rate 3 Slew Rate 2 Slew Rate 1 Slew Rate 0 tLRD 110 100 110 130 200 210 225 255 310 ns Propagation Delay TXD to CAN (Recessive to Dominant) (Note 36) Slew Rate 3 Slew Rate 2 Slew Rate 1 Slew Rate 0 tTRD 100 160 110 150 200 300 ns Propagation Delay CAN to RXD (Recessive to Dominant) (Note 37) tRRD 10 50 140 ns Propagation Loop Delay TXD to RXD (Dominant to Recessive) (Note 35) Slew Rate 3 Slew Rate 2 Slew Rate 1 Slew Rate 0 tLDR 100 120 140 250 150 165 200 340 200 220 250 410 ns Propagation Delay TXD to CAN (Dominant to Recessive) (Note 36) Slew Rate 3 Slew Rate 2 Slew Rate 1 Slew Rate 0 tTDR 200 125 150 180 310 150 190 250 460 ns Propagation Delay CAN to RXD (Dominant to Recessive) (Note 37) tRDR 20 30 60 ns Non-Differential Slew Rate (CANL or CANH) Slew Rate 3 Slew Rate 2 Slew Rate 1 Slew Rate 0 tSL3 tSL2 tSL1 tSL0 4.0 3.0 2.0 1.0 13.5 8.0 5.0 V/µs Notes 35. See Figure 5 , page 17. 36. See Figure 6, page 17. 37. See Figure 7, page 17. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Figure 4. SPI Timing Diagram Figure 5. Propagation Loop Delay TXD to RXD Figure 6. Propagation Delay TXD to CAN Figure 7. Propagation Delay CAN to RXD is set by the 33742 at SCLK rising edge (after tVALID delay time).

0.9 VVDIFF

Freescale Semiconductor, Inc.

SYSTEM/APPLICATION INFORMATION INTRODUCTION The 33742 and the 33742S are integrated circuits dedicated to automotive applications. Their functions include the following: • One fully protected voltage regulator with 200 mA total output current capability available at the VDD terminal. • Driver for external pass transistor for V2 regulator function. •V DD regulator undervoltage reset function, programmable window or timeout software watchdog function. • Two running modes: Normal and Standby modes when the microcontroller is running. • Sleep and Stop modes for operation in low power mode to reduce the application current consumption, while offering wake-up capability from CAN interface, L3:L0 wake-up input, and automatic timer wake-up. • Programmable wake-up input and cyclic sense wake-up. • CAN high-speed physical interface with bus failure diagnostic and enhanced protection feature for TXD and RXD failure. • Interface with micro through SPI . Interrupt output to report device status, diagnostic, and wake-up event. FUNCTIONAL TERMINAL DESCRIPTION RXD and TXD The RXD and TXD terminals (receive data terminal and transmit data terminal, respectively) are connected to the microcontroller CAN protocol handler. TXD is an input and controls the CANH and CANL line state (dominant when TXD is LOW, recessive when TXD is HIGH). RXD is an output and reports the bus state (RXD LOW when CAN bus is dominant, HIGH when CAN bus is recessive). VDD The VDD terminal is the output terminal of the 5.0 V internal regulator. It can deliver up to 200 mA. This output is protected against overcurrent and overtemperature. It includes an overtemperature pre-warning flag, which is set when the internal regulator temperature exceeds 130°C typical. When the temperature exceeds the overtemperature shutdown (170°C typical), the regulator is turned off. VDD includes an undervoltage reset circuitry, which sets the RST terminal LOW when VDD is below the undervoltage reset threshold. RST The Reset terminal RST is an output that is set LOW when the device is in reset mode. The RST terminal is set HIGH when the device is not in reset mode. RST includes an internal pullup current source. When RST is LOW, the sink current capability is limited, allowing RST to be shorted to 5.0 V for software debug or software download purposes. INT The Interrupt terminal INT is an output that is set LOW when an interrupt occurs. INT is enabled using the Interrupt Register (INTR). When INT occurs, INT stays LOW until the INT source is cleared. INT output also reports a wake-up event by a 10 µs typical pulse when the device is in stop mode. The V2 terminal is the input sense of the V2 regulator. It is connected to the external ballast transistor. V2 is also the 5.0 V supply of the internal CAN interface. It is possible to connect V2 to an external 5.0 V regulator or to the VDD output when no external ballast transistor is used. In this case, the V2CTRL terminal must be left open. Refer to Figure 28, 33742 Typical Application Schematic, page 46. V2CTRL The V2CTRL terminal is the output drive of the V2 regulator connected to the external ballast transistor. VSUP The VSUP terminal is the battery supply input of the device. HS The HS terminal is the internal high-side driver output. It is internally protected against overcurrent and overtemperature. L0, L1, L2, and L3 The L0:L3 input terminals can be connected to external switches or any IC’s output. The state of the inputs can be read by SPI. Theses inputs can be used as wake-up events when the device is set in Sleep or Stop mode. CANH and CANL The CAN High and CAN Low terminals are the interfaces to the CAN bus lines. They are controlled by TXD input level, and the state of CANH and CANL is reported through RXD output. A 60 Ω impedance termination is connected between CANH and CANL. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33742 SCLK This is the Serial Data Clock terminal of the serial peripheral interface. MISO This is the Master In/Slave Out terminal of the serial peripheral interface. Data are send from the device to the microcontroller through MISO terminal. MOSI This is the Master Out/Slave In terminal of the serial peripheral interface. Control data from the microcontroller are received through this terminal. CS This is the device Chip Select terminal of the serial peripheral interface. When this terminal is LOW, the internal serial peripheral interface of the device is selected. WDOG The Watchdog terminal is used to signal that a software watchdog has not been properly triggered. DEVICE OPERATION Power Supply The 33742 is supplied from the battery line through the VSUP terminal. An external diode is required to protect against negative transients and reverse battery. The 33742 can operate from 4.5 VDC and under jump-start conditions at 27 VDC. The VSUP terminal sustains standard automotive voltage conditions such as load dump at 40 V. When VSUP falls below

3.0 V typical, the 33742 detects it and stores the information in

the Mode Control Register (MCR) bit BATFAIL. Detection is available in all operation modes. Note For a detailed description of all the registers mentioned in this section, refer to the section titled SPI INTERFACE AND REGISTER DESCRIPTION beginning on page 38. The 33742 incorporates a battery early warning function, which provides a maskable interrupt when the VSUP voltage is below 6.0 V typical. A hysteresis is included. Operation is only in Normal and Standby modes. VSUP LOW is reported in the Input/Output Register (IOR). VDD Regulator The VDD regulator is a 5.0 V output with output current capability up to 200 mA. It includes a voltage monitoring circuitry associated with an undervoltage reset function. The VDD regulator is fully protected against overcurrent and short circuit. It has overtemperature detection warning flags (bit VDDTEMP in the MCR and INTR registers) and overtemperature shutdown with hysteresis. V2 Regulator V2 regulator circuitry is designed to drive an external pass transistor increasing output current flexibility. Two terminals, V2 and V2CTRL, are used to achieve the flexibility. Output voltage is 5.0 V and is realized by a tracking function of the VDD regulator. The recommended ballast transistor is MJD32C. Other transistors can be used, however. Depending on the PNP transistor gain, an external resistor-capacitor network might be connected. V2 is the supply input for the CAN cell. The state of V2 is reported in the IOR register (bit V2LOW set to logic [1] if V2 is below 4.0 V typical). HS VSUP Switch Output HS output is a 2.0 Ω typical switch from VSUP terminal. It allows the supply of external switches and their associated pullup or pulldown circuitry, in conjunction, for example, with the wake-up input terminals L0:L3. Output current is limited to 200 mA and HS is protected against short circuit and has an overtemperature shutdown (bit HSOT in the IOR register and bit HSOT-V2LOW in the INTR register). HS output is controlled by the bit HSON in the IOR register. Thanks to an internal timer, HS can be activated at regular intervals in Sleep and Stop modes. It can also be permanently turned on in Normal or Standby modes to drive loads or supply peripheral components. No internal clamping protection circuit is implemented; thus dedicated external protection circuitry is required in case of inductive load drive. HS negative voltage should not go below -0.3 V. Battery Fail Early Warning Refer to the discussion under the heading Power Supply, above. Internal Clock The 33742 has an internal clock used to generate all timings (reset, watchdog, cyclic wake-up, filtering time, etc.). Two oscillators are implemented. A high-accuracy (±12 percent) oscillator used in Normal Request, Normal, and Standby modes, and a low-accuracy (±30 percent) oscillator used in Sleep and Stop modes. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

microcontroller flash memory. Table 2 below offers a summary of the functional modes. trigger in a closed window). Table 2. Table of Operation

  1. Mode entered via special s equence described under the heading Debug Mode: Hardware and Software Debug with the 33742 beginning on
  2. I DD overcurrent always enabled.

Freescale Semiconductor, Inc.

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33742 In Normal Request mode, the VDD regulator is ON, the V2 regulator is OFF, and the RST terminal is HIGH. As soon as the 33742 enters the Normal Request mode, an internal 350 ms timer is started (parameter tNRTOUT). During these 350 ms, the MCU of the application must address the 33742 via SPI and configure the TIM1 subregister to select the watchdog period. This is the condition for the 33742 to stop the 350 ms timer and go into the Normal or Standby mode and set the watchdog timer according to the configuration. Normal Request Entered and No Watchdog Configuration Occurs If the Normal Request mode is entered after the 33742 powers up or after a wake-up from Stop mode, and if no watchdog configuration occurs while the 33742 is in Normal Request mode, the 33742 goes into Reset mode after the 350 ms time period has expired before again going into Normal Request mode. If no watchdog configuration is achieved, the 33742 alternatively goes from Normal Request mode, to Reset mode, to Normal Request mode, and so on. If the Normal Request mode is entered after a wake-up from Sleep mode, and if no watchdog configuration occurs while the 33742 is in Normal Request mode, the 33742 goes back to Sleep mode. Normal Mode In Normal mode, both the VDD and V2 regulators are ON. This corresponds to the normal application operation. All functions are available in this mode (watchdog, wake-up input reading through SPI, HS activation, and CAN communication). Watchdog software is running and must be periodically cleared through SPI. Standby Mode In Standby mode, only the VDDregulator is ON. The V2 regulator is turned OFF by disabling the V2CTRL terminal. The CAN interface is not able to send messages. If a CAN message is received, the CANWU bit is set. Other functions available are L0:L3 input reading through SPI and HS activation. Watchdog is running. Sleep Mode In Sleep mode, the VDD and V2 regulators are OFF. Current from the VSUP terminal is reduced. In Sleep mode, the 33742 can be awakened by L0:L3 inputs, by cyclic sense of the L0:L3 inputs, by the automatic forced wake-up timer, and from the CAN physical interface receiving an incoming CAN message. When a wake-up occurs, the 33742 goes first into the Reset mode before entering Normal Request mode. Stop Mode The V2 regulator is turned OFF by disabling the V2CTRL terminal. The VDD regulator is activated in a special low power mode, allowing the delivery of a few mA. The objective is to maintain power on the MCU of the application while the MCU is turned into power-saving condition (i.e, Stop or Wait modes). In Stop mode, the device supply current from VPWR is very low. When the application is in Stop mode (both MCU and 33742), the application can wake up from either the 33742 side (for example, cyclic sense, forced wake-up, CAN message, wake-up inputs, and overcurrent on VDD) or the MCU side (key wake-up, etc.). Stop mode is always selected by SPI. In Stop mode, the watchdog software may be either running or not running depending upon selection by SPI (Reset Control Register [RCR], bit WDSTOP). To clear the watchdog if it is running, the 33742 must be awakened by the CS terminal (SPI wake-up). In Stop mode, the 33742 wake-up capability is identical to that in Sleep mode, with the addition of CS and VDD overcurrent wake- up. Refer to Table 2, page 20. Application Wake-Up from 33742 Side When the application is in Stop mode, it can wake up from the 33742 side. When a wake-up is detected by the 33742 (for example, CAN, wake-up input), the 33742 turns itself into Normal Request mode and generates an interrupt pulse at the INT terminal. Application Wake-Up from MCU Side When the application is in Stop mode, the wake-up event may come from the MCU side. In this case the MCU signals to the 33742 by a LOW-to-HIGH transition on the CS terminal. Then the 33742 goes into Normal Request mode and generates an interrupt pulse at the INT terminal. Stop Mode Current Monitor If the VDD output current exceeds an internal threshold (IDDS-WU), the 33742 goes automatically into Normal Request mode and generates an interrupt at the INT terminal. The interrupt is not maskable and the INTR register will have no flag set. Interrupt Generation When Wake-Up from Stop Mode When the 33742 wakes up from Stop mode, it first enters the Normal Request mode before generating a pulse (10µs typical) on the INT terminal. These interrupts are not maskable, and the wake-up event can be read through the SPI registers, CANWU bit in the CAN Register (CANR), and LCTRx bit in the Wake-Up Register (WUR). In case of wake-up from Stop mode overcurrent or from forced wake-up, no bit is set. After the INT pulse, the 33742 accepts SPI command after a time delay (tS-1STSPI). Watchdog Software in Stop Mode If watchdog is enabled, the MCU has to wake up independently of the 33742 before the end of the 33742 watchdog time. In order to do this, the MCU must signal the wake-up to the 33742 through the SPI wake-up (CS activation). The 33742 then wakes up and jumps into the Normal Request mode. The MCU has to configure the 33742 to go to either Normal or Standby mode. The MCU can then decide to go back to the Stop mode. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Request mode. The MCU can then be initialized. Figure 8. Entering Stop Mode SPI (TIM1 subregister, bit WDW). Default is watchdog window. Watchdog can only be cleared within the open window time. addressing the TIM1 subregister. VDD returns to the normal voltage. VDD is within its operation range. Freescale Semiconductor, Inc.

set to 1 in the LPC register), Cyclic Sense cannot be enabled.

33742 Power-Up and 33742 Wake-Up from Sleep Mode

prior to moving into Normal Request mode. page 25, shows device behavior after power-up sequence. Figure 10. 33742 State Diagram (Not Valid in Debug Modes)

33742 Power-Up

  1. These two SPI commands must be se nt consecutively in this sequence.

Freescale Semiconductor, Inc.

Figure 12. Entering Debug Mode within the 350 ms time period of the Normal Request mode. Figure 13. Transitions to Enter Debug Modes 33742/33742S not in Debug mode. Freescale Semiconductor, Inc.

Figure 14. Simplified 33742 State Diagram in Debug Modes (1) If Stop mode is entered, it is entered without watchdog, no matter the WDSTOP bit. (E) Debug mode entry point (Step 5 of the Debug mode entering sequence). (R) Represents transitions to Reset mode due to VDD low. Freescale Semiconductor, Inc.

forced to a value equal to or above VDD. is LOW, the RST terminal sinks 5.0 mA maximum (IPDW). Figure 15. Simplified Schematic for Microcontroller Flash Programming

33742 MCU with

Note External supply and sources applied to VDD, RST, and WDOG test points on application circuit board.

5.0 V Programming Tool

Freescale Semiconductor, Inc.

Figure 16. Simplified Block Diagram of CAN Interface mode to allow wake-up detection. the CAN interface current is sourced from the V2 terminal. disabling the remote CAN wake-up capability. divided by 2, or approximately. 2.5 V. CANH is pulled HIGH toward 5.0 V (voltage at V2). RXD is set LOW. This is illustrated in Figure 16, page 29. Freescale Semiconductor, Inc.

Figure 17. CAN Interface Levels page 20, Table 4, below, and Table 5, page 31. is affected by the slew rate selection. Table 4. CAN Interface/33742 Modes and Terminal Status—Operation with Ballast on V2 (Note 44)

5.0 V Internal Pullup

Sleep Sleep 0 V LOW LOW Floating to GND NO. Stop Sleep 0 V LOW LOW Floating to GND NO.

  1. See also Figure 28, page 46.

Freescale Semiconductor, Inc.

incoming CAN message and SBC wake-up. The CAN Sleep mode is done via the CAN SPI register. are high ohmic termination to ground. SPI command, CAN H and CANL are set in recessive level. This is illustrated in Figure 18. Figure 18. CAN Signals in TXRX and Sleep Modes Table 5. CAN Interface/33742 Modes and Terminal Status—Operation without Ballast on V2 (Note 45) Sleep Sleep 0 V LOW LOW Floating to GND NO. Stop Sleep 0 V LOW LOW Floating to GND NO.

  1. See also Figure 29, page 47.

Freescale Semiconductor, Inc.

• The three pulses must occur within a time frame of 1.0 ms. bus Sleep state and wake-up sequence. Figure 19. CAN Bus Signal During Can Sleep State and Wake-Up Sequence Freescale Semiconductor, Inc.

short to VSUP, and short to VDD. Figure 21. CAN Bus Simplified Structure Table 6. Short to GND, Short to VSUP, and Short to 5.0 V Detection Truth Table Freescale Semiconductor, Inc.

by the Hg comparator, is also close to zero. example, CANH short to VSUP) is reported in the LPC register. indicate that a CAN bus failure has been detected. MCU that the device has started to detect a bus failure. D1 is set to 1 if the error is not identified). the bit “non-identified failure” (CAN-UF) will be set. module within the MCU cannot receive any incoming message. and explained below, is necessary. Figure 22. RXD Path and RXD Permanent Recessive Detection Principle correct low level at TXD, as illustrated in Figure 23, page 36.

2.0 V Sampling Sampling

Note RXD Flag is neither the RXPR bit in the LPC register nor the CAN-F bit in the INTR register. Freescale Semiconductor, Inc.

Figure 23. RXD Recovery Conditions possible. The 33742 has a TXD permanent timeout detector. reported in the TIM1 register. done by an SPI command and controlled by the MCU. reported in the CAN register. nor the CAN-F bit in INTR register. Freescale Semiconductor, Inc.

Table 7. Fault/Warning Battery Fail Turn OFF Turn OFF Turn OFF due to V2. VDD Overtemperature Turn OFF Turn OFF Turn OFF due to V2. Turn OFF Turn OFF due to V2. Watchdog Reset ON Turn OFF Turn OFF due to V2.

  1. Refer to descriptions of CA NH and CANL short to GND, VDD, and VSUP elsewhere in table.
  2. Peak current 150 mA during TXD dominant only. Due to loss of co mmunication, CAN controller reaches bus OFF state. Average current
  3. Overcurrent might be detected. Bit THERM-CUR set in CAN register.

Freescale Semiconductor, Inc.

bits are used to identify the internal 33742 register address. MCU to the 33742 or read back from the 33742 to the MCU. Figure 24. Data Format Description Table 8 lists the possible reset conditions. Table 8. Possible Reset Conditions condition causing the bit to be set at the reset value. Note Read operation: R/W bit = 0; Write operation: R/W = 1.

33742 Reset POR Power-ON Reset

33742 Mode

33742 Mode RESET 33742 in Reset Mode

Table 9. List of Registers Freescale Semiconductor, Inc.

Table 10. Mode Control Register

  1. BATFAIL bit cannot be set by SPI. BATFAIL is set when V SUP
  2. See Table 8, page 38, for definitions of reset conditions.

Table 11. Mode Control Register Control Bits

33742 Mode Description

001 N o r m a l –

1 0 1 Normal No Watchdog running.

111 S t o p

  1. Watchdog ON or OFF depends on RCR bit D3.
  2. Before entering Sleep mode, bit BATFAIL in MCR must be

RCR must be previously set to 1. Table 12. Mode Control Register Status Bits 0 No overtemperature pre-warning.

1 Temperature pre-warning on V DD

1 CAN Failure or HS overtemperature or

0 No watchdog reset occurred. Freescale Semiconductor, Inc.

module, mode, slew rate, and wake-up. Table 13. Reset Control Register

  1. See Table 8, page 38, for definitions of reset conditions.

Table 14. Reset Control Register Control Bits 1 Watchdog runs in Stop Mode. 0 Device cannot enter Sleep Mode.

0 CAN Sleep Mode disable (despite D0 bit

1 CAN Sleep Mode enabled (in addition to

0 Reset Threshold 1 selected (typ 4.6 V). 1 Reset Threshold 2 selected (typ 4.2 V). Table 15. CAN Register

  1. See Table 8, page 38, for definitions of reset conditions.

Table 16. CANCLR Control Bits

1 Re-enables CAN driver after TXD permanent

Table 17. CAN High-Speed Transceiver Modes Freescale Semiconductor, Inc.

Table 18. CAN Register Status Bits 0 Identified CAN failure (Note 55). 1N o n-identified CAN failure.

0 No overtemperature or overcurrent on

1 Overtemperature or overcurrent on

  1. Error bits are latched in the CAN register.

Table 19. Input/Output Register

  1. See Table 8, page 38, for definitions of reset conditions.

Table 20. HSON Control Bits 0 HS OFF, in Normal and Standby modes. 1 HS ON, in Normal and Standby modes (Note 57).

  1. When HS is turned OFF due to an overtemperature condition,

to 1. Error bits are latched in the IOR register. Table 21. Input/Output Register Status Bits Freescale Semiconductor, Inc.

waking up the 33742 from Sleep or Stop modes (Table 22). Table 22. Wake-Up Register

  1. See Table 8, page 38, for definitions of reset conditions.

Table 23. Wake-Up Register Control Bits Table 24. Wake-Up Register Status Bits (Note 59)

  1. WUR status bits have two functions. After 33742 wake-up,

Freescale Semiconductor, Inc.

  1. TIM1—Controls the watchdog timing selection as well as

characteristics are described in Table 26.

  1. TIM2—Selects an appropriate timing for sensing the

timing characteristics are described in Table 29, page 44. Both subregisters also report the CANL and TXD diagnostic. Figure 25. Window Watchdog Figure 26. Timeout Watchdog Table 25. TIM1 Timing and

  1. See Table 8, page 38, for definitions of reset conditions.

Table 26. TIM1 Control Bits Table 27. Timing Register Status Bits

0 No TXD dominant

Table 28. TIM2 Timing and

  1. See Table 8, page 38, for definitions of reset conditions.

Freescale Semiconductor, Inc.

Figure 27. HS Operation When Cyclic Sense Is Selected permanently OFF or HS cyclic). modes; time is defined by the TIM2 subregister). the sampling point of the Cyclic Sense period (LX2HS bit). sense or direct wake-up operation. Table 29. TIM2 Control Bits Table 30. Low Power Control Register

  1. See Table 8, page 38, for definitions of reset conditions.

Table 31. LX2HS Control Bits 1 Yes. Lx inputs sensed at sampling point. Table 32. HSAUTO Control Bits 1 ON, HS Cyclic, period defin ed in TIM2 subregister. Table 33. CAN-INT Control Bits

Description

0 Interrupt as soon as CAN bus failure detected.

1 Interrupt when CAN bus failure detected and fully

identified. Notes 63. If CAN-INT is at 0, any undetermined CAN failure will be latched in the CAN register (bit D1: CAN-UF) and can be accessed by SPI (refer to CAN Register (CAN) on page 40). After reading the CAN register or setting CAN-INT to 1, it will be cleared automatically. The existence of CAN-UF always has priority over clearing, meaning that a further undetermined CAN failure does not allow clearing the CAN-UF bit. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

cleared (read register) and the recovery condition must occur. Errors bits are latched in the CAN register and the IOR register. remains at 0000 (not bit set into the INTR register). Table 34. LPC Status Bits 0 No RXD permanent recessive. Table 35. Interrupt Register

  1. If only HSOT- V2LOW interrupt is selected (only bit D2 set in
  2. Bit D2 = 1: Interrupt source is HSOT.
  3. Bit D2 = 0: Interrupt source is V2LOW.

HSOT and V2LOW bits status are available in the IOR register. , page 38, for definitions of reset conditions. Table 36. Interrupt Register Control Bits CANF Mask bit for CAN failures. VSUPLOW Mask bit for VSUP < 6.1 V. Table 37. Interrupt Register Status Bits Freescale Semiconductor, Inc.

PACKAGE AND THERMAL CONSIDERATIONS The 33742 is a standard surface mount SOIC 28 package. In order to improve the thermal performances of the SOIC 28 package, eight terminals are internally connected to the lead frame and are used for heat transfer to the printed circuit board.

APPLICATIONS

Figure 28 shows a typical 33742 application. Figure 28. 33742 Typical Application Schematic

1.0 Mbps CAN

Rp, Rd: Example: 1.0 kΩ depending on switch type. Freescale Semiconductor, Inc.

Figure 29. 33742 Application Without External Ballast Transistor on V2 Regulator Figure 30. CAN Bus Standard Termination Figure 31. CAN Bus Split Termination

33742 Partial Block Diagram MCU

Freescale Semiconductor, Inc.

B SAM0.025 B SC M0.25 B M SEATING PLANE A NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSIONS. 4. MAXIMUM MOLD PROTRUSION 0.015 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM MIN MAX MILLIMETERS A 2.35 2.65 A1 0.13 0.29 B 0.35 0.49 C 0.23 0.32 D 17.80 18.05 E 7.40 7.60 e 1.27 BSC H 10.05 10.55 L 0.41 0.90 θ 0 8 °° L θ C PIN 1 IDENT A B D E H e 0.10 C DW SUFFIX 28-LEAD SOICW PLASTIC PACKAGE CASE 751F-05 ISSUE F Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33742 NOTES Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33742 NOTES Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

HOW TO REACH US: USA/EUROPE/LOCATIONS NOT LISTED: JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center Motorola Literature Distribution 3-20-1 Minami-Azabu. Minato-ku, Tokyo 106-8573, Japan P.O. Box 5405, Denver, Colorado 80217 81-3-3440-3569 1-800-521-6274 or 480-768-2130 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong 852-26668334 HOME PAGE: http://motorola.com/semiconductors MC33742 Information in this document is provided solely to enable system and software implem enters to use Motorola products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Motorola reserves the right to make changes without further noti ce to any products herein. Motorola makes no warranty, represen tation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola data sheets and/or s pecifications can and do vary in different applications and actual performance may var y over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola pro ducts are not designed, intended, or authorized for use as compon ents in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and di stributors harmless against all claims, costs, damages, and expenses , and reasonable attorney fees arising out of, directly or indirectly, any claim of persona l injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. MOTOROLA and the Stylized M Logo are registered in the US Patent and Trademark Office. All other product or service names are t he property of their respective owners. © Motorola, Inc. 2004 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...