33742_08 FREESCALE | Alldatasheet

Document overview

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Technical content

Features

  • 1.0Mbps CAN transceiver bus inte rface with bus diagnostic capability
  • SPI control at frequencies up to 4.0Mhz
  • 5.0V low dropout voltage regulato r with current limiting, over- temperature prewarning, and output monitoring and reset
  • a Second 5.0V regulator capability using an external series pass transistor
  • Normal, Standby, Stop, and Sleep m odes of operation with Low sleep and Stop mode current
  • A high side (HS) switch output driv er for controlling external circuitry.
  • Pb-free packaging designated by suffix code EG and EP

Figure 1. 33742 Simplified Application Diagram

ORDERING INFORMATION

Range (TA) Package MC33742DW/R2 - 40°C to 125°C

28 SOICW

EG SUFFIX (PB-FREE) 98ASB42345B 28-PIN SOICW EP SUFFIX (PB-FREE) 98ASA10825D 48-PIN QFN 33742 VPWR 5.0V VSUPVDD MCU CS SCLK MOSI MISO GND SPI CS SCLK MOSI MISO RST INT TXD RXDGND CANL CANH HS WDOG V2CTRL Twisted Pair CAN Bus VPWR Safe Circuitry ECU Local Circuitry

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Table 1. Device Differences During a Reset Condition watchdog register is not properly triggered. watchdog register is not properly triggered.

Figure 2. 33742 Simplified Internal Block Diagram

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Figure 3. 33742 28-Pin Connections Table 2. 33742 28-Pin Definitions A functional description of each pin can be found in the Functional Pin description section beginning on page 23. 1 RXD Receive Data CAN bus receive data output pin. 2 TXD Transmit Data CAN bus transmit data input pin. 3 VDD Voltage Digital Drain 5.0V regulator output pin. Supply pin for the MCU.

4 RST Reset Output

an internal pullup current source to VDD.

5 INT Interrupt Output

a 33742-to-PCB thermal path. internal supply for the CAN transceiver. 11 V2CTRL Voltage Source 2 Control Output drive source for the V2 regulator connected to the external series pass transistor. 12 VSUP Voltage Supply Supply input pin for the 33742. 13 HS High Side Output Output of the internal high side switch. The output current is internally limited to 150mA. 14 –17 L0- L3 Level 0 - 3 Inputs Inputs from external switches or from logic circuitry. 18 CANH CAN High Output CAN high output pin. 19 CANL CAN Low Output CAN low output pin. 24 SCLK Serial Data Clock Clock input pin for the Serial Peripheral Interface (SPI). 26 MOSI Master Out Slave In SPI data received by the 33742.

27 CS Chip Select

LOW, the 33742 is the selected device of the SPI bus.

28 WDOG Watchdog Output

Figure 4. 33742 48-Pin Connections Table 3. 33742 48-Pin Definitions A functional description of each pin can be found in the Functional Pin description section beginning on page 23. NC No Connect No connection. 2 SCLK Serial Data Clock Clock input pin for the Serial Peripheral Interface (SPI). 4 MOSI Master Out Slave In SPI data received by the 33742.

5 CS Chip Select

LOW, the 33742 is the selected device of the SPI bus.

6 WDOG Watchdog Output

7 RXD Receive Data CAN bus receive data output pin. 8 TXD Transmit Data CAN bus transmit data input pin. 9 VDD Voltage Digital Drain 5.0V regulator output pin. Supply pin for the MCU.

10 RST Reset Output

an internal pullup current source to VDD.

11 INT Interrupt Output

a 33742-to-PCB thermal path.

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internal supply for the CAN transceiver. 28 VSUP Voltage Supply Supply input pin for the 33742. 29 HS High Side Output Output of the internal high side switch. The output current is internally limited to 150mA. 30-33 L0- L3 Level 0 - 3 Inputs Inputs from external switches or from logic circuitry. 34 CANH CAN High Output CAN high output pin. 35 CANL CAN Low Output CAN low output pin. Table 3. 33742 48-Pin Definitions (continued) A functional description of each pin can be found in the Functional Pin description section beginning on page 23.

Analog Integrated Circuit Device Data Freescale Semiconductor 7 33742

ELECTRICAL CHARACTERISTICS

Table 4. Maximum Ratings permanent damage to the device.

  1. Testing done in accordance with the Human Body Model (C ZAP = 100pF, RZAP = 1500Ω), Machine Model (CZAP = 200pF, RZAP = 0Ω).
  2. Testing done in accordance with ISO 7637-1. See Figure 5.
  3. Load dump testing done in accordance with ISO 7637-1, Transient test done in accordance with ISO 7637-1. See Figure 6.

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Figure 5. Transient Test Setup for L0 : L3 Inputs Figure 6. Transient Test Setup for CANH / CANL

  1. Maximum power dissipation is at 85°C am bient temperature in free aIr and with no heatsink, according to JEDEC JESD51-2 and
  2. The package is not designed for immers ion soldering. The maximum soldering time is 10 seconds at 240°C on any pin. Exceeding the

maximum temperature and time limits may cause permanent damage to the device.

  1. Pin soldering temperature limit is for 10 seconds maximum dur ation. Not designed for immersion soldering. Exceeding these limits may

cause malfunction or permanent damage to the device.

  1. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow

and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics. Table 4. Maximum Ratings (continued) permanent damage to the device. Note Waveform per ISO 7637-1. Test Pulses 1, 2, 3a, and 3b. Note Waveform per ISO 7637-1. Test Pulses 1, 2, 3a, and 3b.

Analog Integrated Circuit Device Data Freescale Semiconductor 9 33742 STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 5. Static Electrical Characteristics reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted.

  1. All functions and modes available and operating: Watchdog, HS turn ON / turn OFF, CAN transceiver operating, L0 : L3 inputs operating,

normal SPI operation. The 33742 may experience an over-temperature fault.

  1. At VDD > 4.0V, RST HIGH if reset 2 selected via SPI. The logic HIGH level will be degraded but the 33742 is functional.
  2. Current measured at the VSUP pin.
  3. If CAN Module is Sleep-enabled for wake-up, an additional current (I CAN-SLEEP) must be added to specified value.
  4. Oscillator running means one of the foll owing function is active: Forced Wake-up or Cyclic Sense or Software Watchdog in Stop mode.
  5. Oscillator not running means none of the foll owing functions are active: Forced Wake-up and Cyclic Sense and Software Watchdog in

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STATIC ELECTRICAL CHARACTERISTICS INPUT PIN (VSUP) (CONTINUED) Supply Current in Stop Mode(14) ( IOUT at VDD < 2.0mA, VDD ON, VSUP < 13.5V, Oscillator Not Running, CAN in Sleep Mode with Wake-up Enabled)(15) TA = - 40°C TA = 25°C TA = 125°C ISUP(STOP-WE) 100 μA BATFAIL Flag Internal Threshold VBF 1.5 3.0 4.0 V BATFAIL Flag Hysteresis(16) VBF(HYS) — 1.0 — V Battery Fall Early Warning Threshold In Normal and Standby Modes VBF(EW) 5.3 5.8 6.3 V Battery Fall Early Warning Hysteresis In Normal and Standby Modes(16) VBF(EW-HYST) 0.1 0.2 0.3 V OUTPUT PIN (VDD)(17) VDD Output Voltage (2.0mA < IV1 < 200mA) 5.5V < VSUP < 27V 4.5V < VSUP < 5.5V VDDOUT 4.9 4.0 5.0 5.1 V Dropout Voltage IDD = 200mA VDDDRP1 — 0.2 0.5 V Dropout Voltage, Limited Output Current and Low VSUP IDD = 50 mA, 4.5 V < VSUP VDDDRP2 — 0.1 0.25 V Output Current Internally Limited IDD 200 285 350 mA Thermal Shutdown (Junction) Normal or Standby Mode TSD 160 — 200 Over-temperature Pre-warning (Junction) VDDTEMP Bit Set TPW 125 — 160 Notes 14. Current measured at the VSUP pin. 15. Oscillator not running means none of the foll owing functions are active: Forced Wake-up and Cyclic Sense and Software Watchdog in Stop mode. 16. Guaranteed by design; it is not production tested. 17. I DD is the total regulator output current. V1 specification with external capacitor. Stability requirement: Capacitance > 47μF, ESR < 1.3Ω (tantalum capacitor). In Reset, Normal Request, Normal and Standby modes. Measures with capacitance = 47μF tantalum. Table 5. Static Electrical Characteristics (continued) reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted.

Analog Integrated Circuit Device Data Freescale Semiconductor 11 33742 STATIC ELECTRICAL CHARACTERISTICS OUTPUT PIN (VDD) (CONTINUED)(18) Temperature Threshold Difference TSD - TPW 20 — 40 °C Reset Threshold Threshold 1, Default Value after Reset, RSTTH Bit Set to Logic [0] Threshold 2, RSTTH Bit Set to Logic [1] VRSTTH 4.5 4.0 4.6 4.2 4.7 4.3 V VDD for Reset Active VDDR 1.0 — VRSTTH V Line Regulation (IDD = 10mA, Capacitance = 47μF Tantalum at VDD) 9.0V < VSUP < 18V 5.5V < VSUP < 27V VDDR 5.0 mV Load Regulation (Capacitance = 47μF Tantalum at V1) 1.0mA < IDD < 200mA VLD — 25 75 mV Thermal Stability VSUP = 13.5V, IDD = 100mA(19) VTHERM-S — 30 50 mV OUTPUT PIN IN STOP MODE (VDD)(18) VDD Output Voltage IDD ≤ 2.0mA IDD ≤ 10mA VDDSTOP 4.75 4.75 5.0 5.0 5.25 5.25 V IDD Output Current to Wake-up IDDS-WU 10 17 25 mA Reset Threshold(18) Threshold 1, Default Value after Reset, RSTTH Bit Set to Logic [0] Threshold 2, RSTTH Bit Set to Logic [1] VRST-STOP 4.5 4.1 4.6 4.2 4.7 4.3 V Line Regulation (Capacitance = 47μF Tantalum at VDD) 5.5V < VSUP < 27V, IDD = 2.0mA VLR-STOP — 5.0 25 mV Load Regulation (Capacitance = 47μF Tantalum at V1) 1.0mA < IDD < 10mA VLD-STOP — 15 75 mV Notes 18. I DD is the total regulator output current. VDD specification with external capacitor. Stability requirement: capacitance > 47μF, ESR < 1.3Ω (tantalum capacitor). In Reset, Normal Request, Normal and Standby modes, measures with capacitance = 47μF tantalum.Selectable by RSTTH bit in SPI Register Reset Control Register (RCR). 19. Guaranteed by characterization and des ign; it is not production tested. reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted.

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STATIC ELECTRICAL CHARACTERISTICS TRACKING VOLTAGE REGULATOR (V2)(20) V2 Output Voltage (Capacitance = 10μF Tantalum at V2) 2.0mA ≤ IV2 ≤ 200mA, 5.5V < VSUP < 27V 0.99 1.0 1.01 VDD IV2 Output Current (for Information Only) Depending on External Ballast Transistor IV2 200 — — mA V2 Control Drive Current Capability(21) Worst Case at TJ = 125°C IV2CTRL 0.0 — 10 mA V2LOW Flag Threshold V2LTH 3.75 4.0 4.25 V LOGIC OUTPUT PIN (MISO)(22) Low-level Output Voltage IOUT = 1.5mA VOL 0.0 — 1.0 V High-level Output Voltage IOUT = -250μA VOH VDD - 0.9 — VDD V Tri-stated MISO Leakage Current 0V < VMISO < VDD IHZ - 2.0 — 2.0 μA Notes 20. V2 specification with external capacit or. Stability requirement: capacitance > 42μF and ESR < 1.3Ω (tantalum capacitor), external resistor between base and emitter required. Measurement conditions: ballast transistor MJD32C, capacitance > 10μF tantalum, 2.2kΩ resistor between base and emitter of ballast transistor. 21. The guaranteed V2CTRL current capability is 10mA. No active current limiting is used so the actual available current may be higher. 22. Push-pull structure with tri-state condition ( CS HIGH). reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted.

Analog Integrated Circuit Device Data Freescale Semiconductor 13 33742 STATIC ELECTRICAL CHARACTERISTICS LOGIC INPUT PINS (MOSI, SCLK, CS) High-level Input Voltage VIH 0.7 VDD — VDD + 0.3 V Low-level Input Voltage VIL - 0.3 — 0.3 VDD V High-level Input Current on CS VIN = 4.0V I IH -100 — - 20 μA Low-level Input Current on CS VIN = 1.0V I IL -100 — - 20 μA MOSI and SCLK Input Current 0V < VIN < VDD I IN -10 — 10 μA OUTPUT PIN (RST)(23) High-level Output Current 0V < VOUT < 0.7 VDD IOH - 300 - 250 -150 μA Low-level Output Voltage IO = 1.5mA, 5.5V < VSUP < 27V IO = 0mA, 1.0V <VSUP < 5.5V VOL 0.0 0.0 0.9 0.9 V RST Pulldown Current V > 0.9V IPDW 2.3 — 5.0 mA OUTPUT PIN (WDOG)(24) Low-level Output Voltage IO = 1.5mA, 1.0V < VSUP < 27V VOL 0.0 — 0.9 V High-level Output Voltage IO = -250μA VOH VDD - 0.9 — VDD V OUTPUT PIN (INT)(24) Low-level Output Voltage IO = 1.5 mA VOL 0.0 — 0.9 V High-level Output Voltage IO = -250μA VOH VDD - 0.9 — VDD V Notes 23. Output pin only. Supply from VDD. Structur e switch to ground with pullup current source. 24. Push-pull structure. reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted.

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STATIC ELECTRICAL CHARACTERISTICS OUTPUT PIN (HS) Driver Output ON Resistance TA = 25°C, IOUT - 150mA, VSUP > 9.0V TA = 125°C, IOUT - 150mA, VSUP > 9.0V TA = 125°C, IOUT - 120mA, 5.5V < VSUP < 9.0V RDS(ON) 2.0 3.5 2.5 4.5 5.5 Ω Output Current Limitation VSUP - VHS > 1.0V ILIM 160 — 500 mA HS Thermal Shutdown TSD 155 — 190 °C HS Leakage Current ILEAK — — 10 μA Output Clamp Voltage IOUT = -10mA, No Inductive Load Drive Capability VCL -1.5 — - 0.3 V INPUT PINS (L0, L1, L2, AND L3) Low-voltage Detection Threshold 5.5V < VSUP < 6.0V 6.0V < VSUP < 18V 18V < VSUP < 27V VTHL 2.0 2.5 2.7 2.5 3.0 3.2 3.0 3.6 3.7 V High-voltage Detection Threshold 5.5V < VSUP < 6.0V 6.0V < VSUP < 18V 18V < VSUP < 27V VTHH 2.7 3.0 3.5 3.3 4.0 4.2 3.8 4.6 4.7 V Hysteresis 5.5V < VSUP < 27V VHYS 0.6 — 1.3 V Input Current - 0.2V < VIN < 40V I IN -10 — 10 μA CAN TRANSCEIVER CURRENT Supply Current of CAN Module CAN in Normal mode, Bus Recessive State CAN in Normal mode, Bus Dominant State without Bus Load CAN in Sleep State, Wake-up Enabled, V2 Regulator OFF CAN in Sleep State, Wake-up Disabled, V2 Regulator OFF(25) IRES IDOM ICAN-SLEEP IDIS 1.3 1.5 3.0 3.5 1.0 mA mA μA μA Notes 25. Guaranteed by design; it is not production tested. reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted.

Analog Integrated Circuit Device Data Freescale Semiconductor 15 33742 STATIC ELECTRICAL CHARACTERISTICS PINS (CANH AND CANL) Bus Pin Common Mode Voltage VCM - 27 — 40 V Differential Input Voltage (Common Mode Between - 3.0V and 7.0V) Recessive State at RXD Dominant State at RXD VCANH - VCANL 900 500 mV Differential Input Hysteresis (RXD) VHYS 100 — — mV Input Resistance 28-pin SOIC 48-pin QFN RIN 5.0 5.0 100 kΩ Differential Input Resistance RIND 10 — 100 kΩ CANH Output Voltage TXD Dominant State TXD Recessive State VCANH 2.75 4.5 3.0 V CANL Output Voltage TXD Dominant State TXD Recessive State VCANL 0.5 2.0 2.25 V Differential Output Voltage TXD Dominant State TXD Recessive State VoH - VoL 1.5 3.0 100 V mV Output Current Capability (Dominant State) CANH CANL ICANH ICANL - 35 mA Over-temperature Shutdown TSD 160 180 — °C CANL Over-current Detection(26) CANL CANH ICANL /OC ICANH /OC - 200 200 - 60 mA CANH and CANL Input Current, Device Supplied (CAN Sleep mode with CAN Wake-up Enabled or Disabled) VCANH, VCANL from 0V to 5.0V VCANH, VCANL = - 2.0V VCANH, VCANL = 7.0V ICAN1 - 60 3.0 - 50 μA CANH and CANL Input Current, Device Unsupplied VCANH, VCANL = 2.5V VCANH, VCANL = - 2.0V VCANH, VCANL = 7.0V ICAN2 - 60 - 50 190 100 240 μA Notes 26. Reported in CAN register. For a description of the contents of the CAN register, refer to CAN Register (CAN) on page 49 reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted.

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STATIC ELECTRICAL CHARACTERISTICS DIAGNOSTIC INFORMATION (CANH AND CANL) CANL to GND Threshold VLG — 1.75 — V CANH to GND Threshold VHG — 1.75 — V CANL to VSUP Threshold VLVB — VSUP - 2.0 — V CANH to VSUP Threshold VHVB — VSUP - 2.0 — V CANL to VDD Threshold VL5 — VDD - 0.43 — V CANH to VDD Threshold VH5 — VDD - 0.43 — V RXD Weak Pull-down Current Source(27) RXD Permanent Dominant Failure Condition IRXDW — 100 — μA PINS (TXD AND RXD) TXD Input High-voltage VIH 0.7 VDD — VDD + 0.4 V TXD Input Low-voltage VIL - 0.4 — 0.3 VDD V TXD High-level Input Current VTXD = V2 IIH -10 — 10 μA TXD Low-level Input Current VTXD = 0V IIL -150 - 100 - 50 μA RXD Output High Voltage(28) IRXD = 250μA VOH VDD - 1.0 — — V RXD Output Low-voltage IRXD = 1.0mA VOL — — 0.5 V Notes 27. Guaranteed by design; it is not production tested. 28. RXD is a push-pull structure between the V2 pin and GND. reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted.

Analog Integrated Circuit Device Data Freescale Semiconductor 17 33742 DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 6. Dynamic Electrical Characteristics reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted.

  1. See Figure 7, SPI Timing Diagram, page 22.
  2. Not production tested. Guaranteed by design.
  3. Not production tested. Guaranteed by design. Detected by V2 OFF.
  4. f OSC is indirectly measured (1.0ms reset) and trimmed.

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DYNAMIC ELECTRICAL CHARACTERISTICS STATE MACHINE TIMING (CS, SCLK, MOSI, MISO, WDOG, INT) (CONTINUED) Watchdog Period Normal and Standby Modes 28-pin SOIC Period 1 Period 2 Period 3 Period 4 48-pin QFN Period 1 Period 2 Period 3 Period 4 t WDOG 8.58 39.6 308 8.3 38.5 300 9.75 100 350 9.75 100 350 10.92 50.4 112 392 10.92 50.4 112 392 ms Normal Request Mode Timeout 28-pin SOIC 48-pin QFN t NRTOUT 308 300 350 350 392 392 ms Watchdog Period Stop Mode Period 1 Period 2 Period 3 Period 4 t WD-STOP 6.82 31.5 245 9.75 100 350 12.7 58.5 130 455 ms Watchdog Period Accuracy Normal and Standby Modes Stop Mode t ACC -12 - 30 Cyclic Sense / FWU Timing Sleep and Stop Modes Timing 1 Timing 2 Timing 3 Timing 4 Timing 5 Timing 6 Timing 7 Timing 8 t CSFWU 3.22 6.47 12.9 25.9 51.8 66.8 134 271 4.6 9.25 18.5 95.5 191 388 5.98 48.1 96.2 124 248 504 ms Cyclic Sense ON Time Sleep and Stop modes. t ON 200 350 500 μs Cyclic Sense / FWU Timing Accuracy Sleep and Stop modes t ACC - 30 — 30 Table 6. Dynamic Electrical Characteristics (continued) reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted.

Analog Integrated Circuit Device Data Freescale Semiconductor 19 33742 DYNAMIC ELECTRICAL CHARACTERISTICS STATE MACHINE TIMING (CS, SCLK, MOSI, MISO, WDOG, INT) (CONTINUED) Delay Between SPI Command and HS Turn ON(33) Normal or Standby mode, VSUP > 9.0V t S-HSON — — μs Delay Between SPI Command and HS Turn OFF(33) Normal or Standby mode, VSUP > 9.0V t S-HSOFF — — μs Delay Between SPI and V2 Turn ON(33) Standby mode t S-V2ON 9.0 — 22 μs Delay Between SPI and V2 Turn OFF(33) Normal mode t S-V2OFF 9.0 — 22 μs Delay Between Normal Request and Normal mode After Watchdog Trigger Command(33) Normal Request mode t S-NR2N 15 35 70 μs Notes 33. Delay starts at falling edge of clock cycle #8 of the SPI command and start of “Turn ON” or “Turn OFF” of HS or V2. reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted.

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DYNAMIC ELECTRICAL CHARACTERISTICS STATE MACHINE TIMING (CS, SCLK, MOSI, MISO, WDOG, INT) (CONTINUED) Delay Between SPI and CAN Normal mode(34) Normal mode(35) t S-CAN_N — — 10 μs Delay Between SPI and CAN Sleep Mode(34) Normal mode (35) t S-CAN_S — — 10 μs Delay Between CS Wake-up (CS LOW to HIGH) and Device in Normal Request mode (VDD ON and RST HIGH) Stop mode t W-CS 15 40 90 μs Delay Between CS Wake-up (CS LOW to HIGH) and First Accepted SPI Command Device in Stop mode After Wake-up t W-SPI 90 — N/A μs Delay Between INT Pulse and First SPI Command Accepted Device in Stop mode After Wake-up t S-1STSPI 20 — N/A μs Delay Between Two SPI Messages Addressing the Same Register t 2SPI 25 — — μs OUTPUT PIN (VDD) Reset Delay Time Measured at 50% of Reset Signal t D 4.0 — 30 μs IDD Over-current to Wake-up Deglitcher Time(35) tIDD-DGLT 40 55 75 μs OUTPUT PIN (RST) Reset Duration After VDD HIGH 33742 33742S t RSTDUR t RSTDURS 3.0 3.5 4.0 ms INPUT PINS (L0, L1, L2, AND L3) Wake-up Filter Time t WUF 8.0 20 38 μs Notes 34. Delay starts at falling edge of clock cycle #8 of the SPI command and start of “Turn ON” or “Turn OFF” of HS or V2. 35. Guaranteed by design; it is not production tested. reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted.

Analog Integrated Circuit Device Data Freescale Semiconductor 21 33742 DYNAMIC ELECTRICAL CHARACTERISTICS CAN MODULE – SIGNAL EDGE RISE AND FALL TIMES (CANH, CANL) Dominant State Timeout t DOUT 200 360 520 μs Propagation Loop Delay TXD to RXD (Recessive to Dominant)(36) Slew Rate 3 Slew Rate 2 Slew Rate 1 Slew Rate 0 t LRD 110 100 110 130 200 210 225 255 310 ns Propagation Delay TXD to CAN (Recessive to Dominant)(37) Slew Rate 3 Slew Rate 2 Slew Rate 1 Slew Rate 0 t TRD 100 160 110 150 200 300 ns Propagation Delay CAN to RXD (Recessive to Dominant)(38) t RRD 10 50 140 ns Propagation Loop Delay TXD to RXD (Dominant to Recessive)(36) Slew Rate 3 Slew Rate 2 Slew Rate 1 Slew Rate 0 t LDR 100 120 140 250 150 165 200 340 200 220 250 410 ns Propagation Delay TXD to CAN (Dominant to Recessive)(37) Slew Rate 3 Slew Rate 2 Slew Rate 1 Slew Rate 0 t TDR 200 125 150 180 310 150 190 250 460 ns Propagation Delay CAN to RXD (Dominant to Recessive)(38) t RDR 20 30 60 ns Non-Differential Slew Rate (CANL or CANH) Slew Rate 3 Slew Rate 2 Slew Rate 1 Slew Rate 0 t SL3 t SL2 t SL1 t SL0 4.0 3.0 2.0 1.0 13.5 8.0 5.0 V/μs Bus Communication Rate tBUS 60k — 1.0M bps Νοτεσ 36. See Figure 8, page 22. 37. See Figure 9, page 22. 38. See Figure 10, page 22. reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted.

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Figure 7. SPI Timing Diagram Figure 8. Propagation Loop Delay TXD to RXD Figure 9. Propagation Delay TXD to CAN Figure 10. Propagation Delay CAN to RXD is set by the 33742 at SCLK rising edge (after tVALID delay time).

0.9 VVDIFF

Analog Integrated Circuit Device Data Freescale Semiconductor 23 33742 FUNCTIONAL DESCRIPTION INTRODUCTION FUNCTIONAL DESCRIPTION INTRODUCTION The 33742 and the 33742S are system basis chips (SBCs) dedicated to automotive applications. Their functions include the following:

  • One fully protected 5.0V voltage regulator with 200mA total output current capability available at the VDD pin.
  • VDD regulator under-voltage reset function, programmable window or time-out software watchdog function.
  • Internal driver (V2) for an external series pass transistor to implement a second 5.0V voltage regulator.
  • Two running modes: Normal and Standby modes set by the system microcontroller.
  • Sleep and Stop modes low power operating modes to reduce an application’s current consumption while providing a wake-up capability from the CAN interface, L3 : L0 wake-up inputs, or from a timer wake-up.
  • Programmable wake-up input and cyclic sense wake- ups.
  • CAN high-speed physical bus interface with TXD and RXD fault diagnostic capability and enhanced protection features.
  • An SPI interface for use in communicating with a MCU and Interrupt outputs to report SBC status, perform diagnostics, and report wake-up events. FUNCTIONAL PIN DESCRIPTION RECEIVE AND TRANSMIT DATA (RXD AND TXD) The RXD and TXD pins (receive data and transmit data pins, respectively) are connected to a microcontroller’s CAN protocol handler. TXD is an input and controls the CANH and CANL line state (dominant when TXD is LOW, recessive when TXD is HIGH). RXD is an output and reports the bus state (RXD LOW when CAN bus is dominant, HIGH when CAN bus is recessive). The RXD terminal is a push-pull structure between the V2 pin and GND. Voltage Digital Drain (VDD) The VDD pin is the output pin of the 5.0V internal regulator. It can deliver up to 200mA. This output is protected against over-current and over-temperature. It includes an over- temperature pre-warning flag, which is set when the internal regulator temperature exceeds 130°C typical. When the temperature exceeds the over-temperature shutdown (170°C typical), the regulator is turned off. VDD includes an under-voltage reset circuitry, which sets the RST pin LOW when VDD is below the under-voltage reset threshold. RESET OUTPUT (RST) The Reset pin RST, is an output that is set LOW when the device is in reset mode. The RST pin is set HIGH when the device is not in reset mode. RST includes an internal pullup current source. When RST is LOW, the sink current capability is limited, allowing RST to be shorted to 5.0V for software debug or software download purposes. INTERRUPT OUTPUT (INT) The Interrupt pin INT, is an output that is set LOW when an interrupt occurs. INT is enabled using the Interrupt Register (INTR). When an interrupt occurs, INT stays LOW until the interrupt source is cleared. INT output also reports a wake-up event by a 10μs typical pulse when the device is in Stop mode. VOLTAGE SOURCE 2 (V2) The V2 pin is the input sense for the V2 regulator. It is connected to the external series pass transistor. V2 is also the 5.0V supply of the internal CAN interface. It is possible to connect V2 to an external 5.0V regulator or to the VDD output when no external series pass transistor is used. In this case, the V2CTRL pin must be left open. Refer to Figure 31, SBC Typical Application Schematic, page 57. VOLTAGE SOURCE 2 CONTROL (V2CTRL) The V2CTRL pin is the output drive pin for the V2 regulator connected to the external series pass transistor. VOLTAGE SUPPLY (VSUP) The VSUP pin is the battery supply input of the device. HIGH-SIDE OUTPUT (HS) The HS pin is the internal high side driver output. It is internally protected against over-current and over- temperature. LEVEL 0-3 INPUTS (L0: L3) The L0 : L3 pins can be connected to contact switches or the output of other ICs for external inputs. The input states can be read by SPI. These inputs can be used as wake-up events for the SBC when operating in the Sleep or Stop mode. CAN HIGH AND CAN LOW OUTPUTS (CANH AND CANL) The CAN High and CAN Low pins are the interfaces to the CAN bus lines. They are controlled by TXD input level, and

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FUNCTIONAL PIN DESCRIPTION the state of CANH and CANL is reported through RXD output. A 60Ω termination resistor is connected between CANH and CANL pins. SERIAL DATA CLOCK (SCLK) SCLK is the Serial Data Clock input pin of the serial peripheral interface. MASTER IN SLAVE OUT (MISO) MISO is the Master In Slave Out pin of the serial peripheral interface. Data is sent from the SBC to the microcontroller through the MISO pin. MASTER OUT SLAVE IN (MOSI) MOSI is the Master Out Slave In pin of the serial peripheral interface. Control data from a microcontroller is received through this pin. CHIP SELECT (CS) CS is the Chip Select pin of the serial peripheral interface. When this pin is LOW, the SPI port of the device is selected. WATCHDOG OUTPUT (WDOG) The Watchdog output pin is asserted LOW to flag that the software watchdog has not been properly triggered.

Analog Integrated Circuit Device Data Freescale Semiconductor 25 33742 FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION OUTPUTS 5.0V LINEAR REGULATOR (LDO) This low dropout linear regulator (V1) outputs a regulated 5.0V at 200mA. The associated monitoring circuit provides detection of under-voltage, over-current, and short-circuit conditions, as well as over-temperature and a reset function. 5.0V REGULATOR BASE PNP DRIVE The V2 linear regulator control circuitry provides drive for an external series pass transistor (PNP type). The 5.0V output tracks the V1 regulator HIGH SIDE SWITCH The high switch provides a 2.0 Ohm (typ.) RDSON MOSFET driver connected to the VSUP pin. The output is protected against short-circuit conditions and provides over- temperature shutdown. CAN PHYSICAL LAYER INTERFACE This circuitry provides communication between the TXD & RXD pins, from/to the MCU, and the CANL & CANH pins of the CAN physical interface. The various modes of the CAN interface are controlled through the SPI control registers. INTEGRATED SUPPLY VSUP CONTROL & MONITOR This circuitry protects the IC from transient conditions such as vehicle jump-start (27V) and load dump (40V). If the VSUP voltage falls below 3.0V (or a 6.0V warning interrupt), an under-voltage detection is reported. ANALOG CIRCUITRY OSCILLATOR This circuit is used to generate the internal timings for reset, watchdog, cyclic wake-up, filtering time, etc. MODE CONTROL The 4 operating modes of the IC are controlled through the SPI control registers. There are also several special modes possible. PROGRAMMABLE WAKE-UP The 4 inputs are used in conjunction with various SPI control register bits to determine the wake-up conditions and the reaction of the IC. They can be connected to contact switches or other ICs. MC33742 - Functional Block Diagram Analog Circuitry MCU Interface Outputs Integrated Supply Integrated Supply VSUP Control & Monitor Analog Circuitry Mode Control MCU Interface SPI Interface CAN Interface / Control Reset & INT Outputs CAN Physical Layer Interface 5.0V Linear Regulator (LDO) High-side Switch 5.0V Regulator Base PNP DriveOscillator Watchdog Timer Programmable Wake-up

Analog Integrated Circuit Device Data

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FUNCTIONAL INTERNAL BLOCK DESCRIPTION MCU INTERFACE SPI INTERFACE The IC and the MCU communicate using the SPI control and status reporting registers. The clock speed (SCLK) can be as high as 4.0MHz. RESET & INT These 2 outputs notify the MCU when the IC is in reset mode, or when an enabled interrupt condition has occurred. WATCHDOG TIMER The timer can be used as a watchdog window or watchdog timeout function. The SPI control register provide the choice as well as the timeout value. When the watchdog timer is not properly serviced by the MCU, an error signal (WDOGN low) and a reset signal (RSTN low) are output. CAN INTERFACE/CONTROL The operation of the CAN interface is controlled by the MCU through the use of SPI control register bits.

Analog Integrated Circuit Device Data Freescale Semiconductor 27 33742 FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES FUNCTIONAL DEVICE OPERATION SUPPLY VOLTAGE AT VSUP The 33742 receives its operating voltage via the VSUP pin. An external diode is needed in series with the VSUP pin and the supply voltage to protect the SBC against negative transients or from a reverse battery situation that can occur in a vehicle application. The 33742 will operate from a supply voltage input as low as 4.5VDC to as high as 27VDC. The later voltage is often encountered during a vehicle jump-start. The VSUP pin can tolerate automotive transient conditions such as load dump to 40V. The SBC is able to detect when V SUP falls below 3.0V typical. This under-voltage state is detected and retained in the parts Mode Control Register (MCR) as the BATFAIL bit. This detection capability is available across all operating modes. Note For a detailed description of all the registers mentioned in this section, refer to the section titled SPI Interface And Register Description beginning on page 47. The SBC incorporates a VSUP level early warning function, which provides a maskable interrupt if the VSUP voltage level falls below 6.0V typical. Hysteresis is used to reduce false detections. The early warning function works only in Normal and Standby operation modes. An under-voltage at the VSUP pin is reported in the Input / Output Register (IOR). VDD REGULATOR The VDD regulator provides a 5.0V low dropout voltage capable of supplying up to 200mA with monitoring circuitry for under-voltage detection and a reset function. The VDD regulator is protected against over-current and short-circuit conditions. It has over-temperature detection and will set warning flags (bit VDDTEMP in the MCR and INTR registers) and has over-temperature shutdown with hysteresis. V2 REGULATOR The V2 regulator feature provides for a second 5.0VDC voltage source The internal V2 circuitry will drive an external series pass transistor, substantially increasing the available supply current. Two pins, the V2 and the V2CTRL, are used to sense and drive the series pass transistor. The output voltage is 5.0V and tracks the VDD regulator. The MJD32C transistor is recommended for use as the external pass device. Other PNP transistors can be used but depending on the device’s gain, an external resistor-capacitor network might be needed. V2 is also the supply voltage for the on- board CAN module. An under-voltage condition for the V2 voltage is reported in the IOR Register (bit V2LOW set to logic [1] if V2 falls below 4.0V typical). HS VSUP SWITCH OUTPUT The HS output is a 2.0Ω typical switch tied to the VSUP pin. It can power or bias external switches and their associated pullup or put-downs or other circuitry. An example is biasing a set of switches connected to the L0 : L3 wake-up input pins. The HS VSUP output current is limited to 200mA and is protected against short circuits conditions and will report an over-temperature shutdown condition (bit HSOT in the IOR register and bit HSOT - V2LOW in the INTR register). The HS output “on” state is set by the HSON bit in the IOR register. A cyclic mode of operation can be implemented using an internal timer in the Sleep and Stop operating modes. It can also be turned on in Normal or Standby modes to drive loads or supply peripheral components. No internal protection circuitry is provided, however. Dedicated chip protection circuitry is required for inductive load applications. The HS output pin should not go below - 0.3V. BATTERY FAIL EARLY WARNING Refer to the previous discussion under the heading, Supply Voltage at VSUP. INTERNAL CLOCK The 33742 has an internal clock used to generate all timings (reset, watchdog, cyclic wake-up, filtering time, etc.). There are two on-board oscillators: a higher accuracy (±12 percent) oscillator used in Normal Request, Normal, and Standby modes, and a lower accuracy (±30 percent) oscillator used during Sleep and Stop modes. OPERATIONAL MODES INTRODUCTION The 33742 has four modes of operation, all controllable via the SPI. The modes are Standby, Normal, Stop, and Sleep. An additional temporary mode called Normal Request mode is automatically accessed by the device after reset or wake- up from Stop mode. A Reset mode is also implemented. Special modes and configurations are possible for debug and program microcontroller flash memory. Table 7, page 29, offers a summary of the functional modes. STANDBY MODE In Standby mode only the VDD regulator is ON. The V2 regulator is turned OFF by disabling the V2CTRL pin. Other functions available are the L0 : L3 inputs read through via the SPI and HS output activation. The CAN interface is not able to send messages. If a CAN message is received, the CANWU bit is set. The watchdog timer is running.

Analog Integrated Circuit Device Data

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FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES NORMAL MODE In Normal mode, both the VDD and V2 regulators are in the ON state. All functions are available in this operating mode (watchdog, wake-up input reading through SPI, HS activation, and CAN communication). The watchdog timer is running and must be periodically cleared through SPI. STOP MODE The V2 regulator is turned OFF by disabling the V2CTRL pin. The VDD regulator is activated in a special low power mode supplying only a few mA of current. This maintains “keep alive” power for the application’s MCU while the MCU is in a power-saving state (i.e., a MCU’s version of Stop or Wait). In the Stop mode, the supply current available from VSUP pin is very low. Both parts (the SBC or the MCU) can be awakened from either the 33742 side (for example, cyclic sense, forced wake-up, CAN message, wake-up inputs, and over-current on VDD) or from the MCU side (key wake-up, etc.). Stop mode is always selected via SPI. In Stop mode, the watchdog software may be either running or not running depending upon selection by SPI (Reset Control Register [RCR], bit WDSTOP). To clear a running watchdog timer, the SBC must be awakened using the CS pin (SPI wake-up). In Stop mode, wake-up is identical to that in Sleep mode, with the addition of CS and VDD over-current wake-up. Refer to Table 7, page 29. SLEEP MODE In Sleep mode, the VDD and V2 regulators are OFF. Current consumption from the VSUP pin is cut. In Sleep mode, the SBC can be awakened by sensing individual level individual level changes in the L0 : L3 inputs, by cyclic checking of the L0 : L3 inputs, by the forced wake-up timer, or from the CAN physical interface upon receiving a CAN message. When a wake-up occurs, the SBC goes first into the Reset mode before entering Normal Request mode. RESET MODE In the Reset mode, the RST pin is LOW and a timer runs for t RSTDUR time. After t RSTDUR has elapsed, the 33742 enters the Normal Request operating mode. The Reset mode is entered if a reset condition occurs (VDD LOW, watchdog time-out, or watchdog trigger in a closed window). NORMAL REQUEST MODE The Normal Request mode is a temporary operating mode automatically entered by the SBC after the Reset mode or after the 33742 wakes up from the Stop mode. After a wake-up from the Sleep mode or after a device power-up, the SBC enters the Reset mode prior to entering the Normal Request mode. After a wake-up from the Stop mode, the 33742 enters the Normal Request mode directly. In Normal Request mode, the VDD regulator is ON, the V2 regulator is OFF, and the RST pin is HIGH. As soon as the SBC enters the Normal Request mode, an internal 350ms timer is started (parameter tNRTOUT). During this time, the application’s MCU must address the 33742 via SPI and configure the TIM1 sub register to select the watchdog period. This is required of the SBC to stop the 350ms watchdog timer and enter the Normal or Standby mode and to set the watchdog timer configuration. NORMAL REQUEST ENTERED AND NO WATCHDOG CONFIGURATION OCCURS If the Normal Request mode is entered after the SBC powers up or after a wake-up from Stop mode and no watchdog configuration occurs before the 350ms time period has expired, the device enters the Reset mode. If no watchdog configuration is performed, the 33742 will cycle from the Normal Request mode to Reset mode to Normal Request mode. If the Normal Request mode is entered after a wake-up from Sleep mode, and no watchdog configuration occurs while the 33742S is in Normal Request mode, the SBC returns to the Sleep mode.

Table 7. Table of Operations mode and generates an interrupt pulse at the INT pin. is a non-maskable and the INTR register will have no flag set. LOW Not Active Not running Low power. Same as Normal – Normally HIGH. Same as Standby – Normally HIGH. Same as Stop Same as Stop Normally HIGH.

  1. Mode entered via special s equence described under the heading Debug Mode: Hardware and Software Debug with the 33742,
  2. I DD over-current always enabled.

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after a time delay (t S-1STSPI). mode. The MCU can then decide to return to the Stop mode. Normal Request mode. The MCU can then be re-initialized. Figure 11. Entering the Stop Mode WDW). Default operation is a watchdog window. A 33742 output is available to perform a reset of the MCU.

  • V DD Falling Out of Range — If VDD falls below the reset threshold (V RSTTH), the RST pin is pulled LOW until VDD returns to the normal voltage.
  • Power-ON Reset — At 33742 power-on or wake-up from Sleep mode, the RST pin is maintained LOW until VDD is within its operation range.
  • Watchdog Timeout — If watchdog is not cleared, the 33742 will pull the RST pin LOW for the duration of the reset time (t RSTDUR). RST AND WDOG OPERATION Table 8 describes watchdog and reset output modes of operation. RST is activated in the event VDD fall or watchdog is not triggered. WDOG output is active LOW as soon as RST goes LOW and stays LOW as long as the watchdog is not properly reset via SPI. The WDOG output pin is designed as a push-pull structure that can drive off chip components signaling, for instance, errant MCU operation. Figure 12 illustrates the device behavior in the event the TIM1 register in not properly accessed. In this case, a software reset occurs and the WDOG pin is set LOW until the TIM1 register is properly accessed. SPI CS SPI Stop/Sleep Command 33742 in Normal or Standby mode 33742 in Stop mode. No IDD over IDD-DGLT 33742 in Stop mode. IDD over IDD-DGLT tCS-STOP tIDD-DGLT

Figure 12. RST and WDOG Output Operation a wake-up occurs from Stop mode. Table 8. Watchdog and Reset Output Operation

  1. WDOG stays LOW until the TIM1 register is properly addressed through SPI.

Analog Integrated Circuit Device Data

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FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES expander. The wake-up input states are read through SPI (WUR register). In order to select and activate direct wake-up from the L0 : L3 inputs, the WUR register must be configured with the appropriate level sensitivity. Additionally, the Low Power Control (LPC) Register must be configured with 0xx0 data (bits LX2HS and HSAUTO are set to 0). The sensitivity of the L0 : L3 inputs is selected by the WUR register. Level sensitivity is configured by L0 : L3 input pairs: L0 and L1 level sensitivity are configured together, while L2 and L3 are configured together. CYCLIC SENSE WAKE-UP (CYCLIC SENSE TIMER AND WAKE-UP INPUTS L0 : L3) The 33742 can wake up upon state change of one of the four wake-up input lines (L0 : L3). The external pullup or pulldown resistor of the switches associated with the wake-up input lines can be biased from the HS VSUP switch. The HS switch is activated in Sleep or Stop modes from an internal timer. Cyclic Sense and Forced Wake-up are exclusive states. If Cyclic Sense is enabled, Forced Wake-up cannot be enabled. In order to select and activate the cyclic sense wake-up from the L0 : L3 inputs, the WUR register must be configured with the appropriate level sensitivity and the LPC register must be configured with 1xx1 data (bit LX2HS set at 1 and bit HSAUTO set at 1). The wake-up mode selection (direct or cyclic sense) is valid for all four wake-up inputs. FORCED WAKE-UP The SBC can wake up automatically after a predetermined time spent in Sleep or Stop mode. Cyclic Sense and Forced Wake-up are exclusive. If Forced Wake-up is enabled (FWU bit set to 1 in the LPC register), Cyclic Sense cannot be enabled. CAN INTERFACE WAKE-UP The SBC incorporates a high-speed 1.0 Mbps CAN physical interface. It is compatible with ISO 11898-2 standard. The operation of the CAN physical interface is controlled through the SPI. The CAN operating modes are independent of the 33742 operational modes. The SBC can wake up from a CAN message if the CAN wake-up feature is enabled. Refer to the section titled LOGIC COMMANDS AND REGISTERS beginning on page 47 for details of the wake-up detection. SPI WAKE-UP The 33742 can be awakened by changes on the CS pin in Sleep or Stop modes. Wake-up is detected as a LOW-to- HIGH level transition on the CS pin. In the Stop mode, this corresponds to a condition where an MCU and the SBC are both in the Stop mode and when the application wake-up event comes through the MCU.

33742 POWER-UP AND WAKE-UP FROM SLEEP

After device or system power-up, or after the SBC awakens from Sleep mode, the 33742S enters into the Reset mode prior to moving into Normal Request mode. Figure 13, shows the device state diagram. Figure 14, shows device operation after power-up.

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of the SBC internal software watchdog timer. will generate a reset every 350ms until the part is configured.

  • Step 1– Power down the SBC.
  • Step 2 – Power up the SBC. This sets the BATFAIL bit, allowing the 33742 to enter Normal Request mode.
  • Step 3 – Write to the TIM1 sub register to allow the SBC to enter Normal mode.
  • Step 4 – Write to the MCR register with data 0000. This enables the debug mode. Complete SPI byte is 0001 0000.
  • Step 5 – Write to the MCR register normal debug. SPI byte is 0001 x101. Important While in debug mode, the SBC can be used without having to clear the watchdog on a regular basis to facilitate software and hardware debug.
  • Step 6 – To leave the debug mode, write 0000 to the MCR register. At Step 2, the SBC is in Normal Request. Steps 3, 4, and 5 should be completed consecutively and within the 350ms time period of the Normal Request mode. If not, the 33742 will go into Reset mode and enter Normal Request again. Figure 15, page 34, illustrates debug mode selection.

Figure 15. Entering Debug Mode window of the Normal Request mode. of the SBC once the debug mode has been selected.

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Figure 18. Simplified Schematic for Microcontroller Flash Programming

33742 MCU with

Note External supply and sources applied to VDD, RST, and WDOG test points on application circuit board.

5.0 V Programming Tool

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Figure 20. CAN Interface Levels page 29, Table 9, below, and Table 10, page 39. current will flow into the diode. an external resistor (i.e. the MCU RXD pin internal pullup). RXD loop time is affected by the slew rate selection.

Table 9. CAN Interface / 33742S Modes and Pin Status—Ope ration with Ballast on V2(45) Sleep Sleep 0.0V LOW LOW Floating to GND NO. Stop Sleep 0.0V LOW LOW Floating to GND NO.

  1. See also Figure 31, page 57.
  2. The state of the RXD pin is dependant upon: 1) the V2 voltage, 2) the external circuitry connected to RXD, (i.e. the MCU RXD pin), and

3) any external pull-up between RXD and the 5V supply. Table 10. CAN Interface / 33742 Modes and Pin Status — Operation without Ballast on V2 (47) Sleep Sleep 0.0V LOW LOW Floating to GND NO. Stop Sleep 5.0V LOW LOW Floating to GND NO.

  1. See also Figure 36, page 60.
  2. The state of the RXD pin is dependant upon: 1) the V2 voltage, 2) the external circuitry connected to RXD, (i.e. the MCU RXD pin), and

3) any external pull-up between RXD and the 5V supply.

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  • Sleep mode with CAN wake-up enable: detection of incoming CAN message and SBC wake-up.
  • Sleep mode with CAN wake-up disable: no detection of incoming CAN message. The CAN Sleep modes are set via the CAN SPI register. In CAN Sleep mode (with wake-up enable or disable), the CAN interface is internally supplied from the VSUP pin. The voltage at V2 pin can be either 5.0V or turned off. When the CAN is in Sleep mode, the current sourced from V2 is extremely low. In most cases the V2 voltage is off; however, the CAN can be placed into Sleep mode even with 5.0V applied on V2. In CAN Sleep mode, the CANH and CANL drivers are disabled, and the receiver is also disabled. CANH and CANL are high-impedance mode to ground. CAN SIGNALS IN TXRX AND SLEEP MODES When the CAN interface is set back into TXRX mode by an SPI command, CAN H and CANL are set in recessive level. This is illustrated in Figure 21.

Figure 21. CAN Signals in TXRX and Sleep Modes

  • The CAN interface wake-up receiver must receive a series of three consecutive valid dominant pulses, each of which must be longer than 500ns and shorter than 500μs.
  • The distance between 2 pulses must be lower than 500μs.
  • The three pulses must occur wi thin a time frame of 1.0ms. The pattern wake-up of the 33742 CAN interface allow wake-up by any CAN message content. Figure 22 below illustrates the CAN signals during a CAN bus Sleep state and wake-up sequence. CANL CANH TXD RXD Ground 2.5V CANL Dominant CANH Dominant CANL/CANH Recessive CAN in TXRX Mode CAN in Sleep Mode (Wake-up Enable or Disable) CAN in TXRX Mode (Controlled by SPI Command)

Figure 22. CAN Bus Signal During Can Sleep State and Wake-up Sequence

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Figure 23 illustrates how the wake-up signal is generated. three pulses, the internal wake-up signal is asserted. Figure 23. Wake-Up Functional Block Diagram wake-up is reported by the CANWU bit in the CAN register. interface was in Sleep mode. drivers; that is, whether they are recessive or dominant.

Figure 24. CAN Bus Simplified Structure Table 11. Short to GND, Short to VSUP , and Short to 5.0V (VDD) Detection Truth Table

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measured by the Hg comparator, is also close to zero. which bus line, CANL or CANH, is shorted to GND or VSUP. once the driver is turned on. indicate that a CAN bus failure has been detected. however, is it not possible to fully identify the specific error. [1} if the error is not identified). registers and bit D1 will be reset to logic [0]. Figure 25 and explained below, is necessary. Figure 25. RXD Path and RXD Permanent Recessive Detection Principle Note The RXD Flag is neither the RXPR bit in the LPC register, nor the CANF bit in the INTR register.

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Table 12 describes the relationship between device fault or warning and the operation of the VDD, V2, CAN, and HS interface. Table 12. Fault / Warning Battery Fail Turn OFF Turn OFF Turn OFF due to V2. VDD Over-temperature Turn OFF Turn OFF Turn OFF due to V2. Turn OFF Turn OFF due to V2. Watchdog Reset ON Turn OFF Turn OFF due to V2.

  1. Refer to descriptions of CANH and CANL shor t to GND, VDD, and VSUP elsewhere in table.
  2. Peak current 150mA during TXD dominant only. Due to loss of co mmunication, CAN controller reaches bus OFF state. Average current
  3. Over-current might be detected. THERM-CUR bit set in CAN register.

the internal SBC register address. Bit 4 is a read/write bit. read back from the 33742 to the MCU. Figure 27. Data Format Description. Table 13. Possible Reset Conditions

33742 Reset POR Power-ON Reset

33742 Mode

33742 Mode RESET 33742S in Reset mode

Table 14. List of Registers

  • TIM1: Watchdog timing control, Watch - dog Window (WDW) or Watchdog Tim- eout (WTO) mode
  • TIM2: Cyclic Sense and Forced Wake- up timing selection CANL and TXD failure reporting LPC $110 Low Power Control Register (LPC) on page 54 Control HS periodic activation in Sleep and Stop modes, Forced Wake-up mode activation, CAN-INT mode selection CANH and RXD failure reporting INTR $111 Interrupt Register (INTR) on page 56 Enable or Disable of Interrupts Interrupt source

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Tables 15 through 17 describes the various Mode Control Registers. Table 15. Mode Control Register

  1. BATFAIL bit cannot be set by SPI. BATFAIL is set when VSUP falls below 3.0V.
  2. See Table 13 page 47, for definitions of reset conditions

Table 16. Mode Control Register Control Bits Software Debug with the 33742, page 34. 1 0 1 Normal No Watchdog running. Debug mode.

  1. Watchdog ON or OFF depends on RCR bit D3.
  2. Before entering Sleep mode, BATFAIL bit in MCR must be previ ously cleared (MCR read operation), and NOSTOP bit in RCR must be

previously set to logic [1]. Table 17. Mode Control Register Status Bits 0 No over-temperature pre-warning. 1 Temperature pre-warning on VDD regulator (bit latched). 1 CAN Failure or HS over-temperature or V2 low. 0 No watchdog reset occurred.

Tables 18 and 19 contain various Reset Control Register information. mode, slew rate, and wake-up. Table 18. Reset Control Register

  1. See Table 13 page 47, for definitions of reset conditions.

Table 19. Reset Control Register Control Bits 1 Watchdog runs in Stop mode. 0 Device cannot enter Sleep mode. 1 Sleep mode allowed. Device can enter Sleep mode. 0 CAN Sleep mode disable (despite D0 bit in CAN register). 1 CAN Sleep mode enabled (in addition to D0 in CAN register). 0 Reset Threshold 1 selected (typ 4.6V). 1 Reset Threshold 2 selected (typ 4.2V). Table 20. CAN Register

  1. See Table 13, page 47, for definitions of reset conditions.

Table 21. CANCLR Control Bits recovery conditions must occur to re-enable.

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in Normal and Standby modes, while Table 26 provides status bit information. Table 22. CAN High-Speed Transceiver Modes Table 23. CAN Register Status Bits 0 Identified CAN failure(58). 1 Non-identified CAN failure. 0 No over-temperature or over-current on CANH or CANL drivers. 1 Over-temperature or over-current on CANH or CANL drivers.

  1. Error bits are latched in the CAN register.

Table 24. Input / Output Register

  1. See Table 13, page 47, for definitions of reset conditions.

Standby modes as port expander, as well as for waking up the SBC from Sleep or Stop modes (Table 27). configured together (Table 28). Table 25. HSON Control Bits 0 HS OFF, in Normal and Standby modes.

  1. When HS is turned OFF due to an over-temperature condition, it can be turned ON again by setting the appropriate control bit to 1. Error

bits are latched in the IOR register. Table 26. Input / Output Register Status Bits 1 SBC accepts command to go to Debug modes (no Watchdog). Table 27. Wake-Up Register

  1. See Table 13, page 47, for definitions of reset conditions.

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  • T I M 1 — Controls the watchdog timing selection as well as either the watchdog window or the watchdog timeout option (Figure 28 and Figure 29, respectively). TIM1 is selected when bit D3 is 0 (Table 30). Watchdog timing characteristics are described in Table 31.
  • T I M 2 — Selects an appropriate timing for sensing the wake-up circuitry or cyclically supplying devices by switching the HS on or off. TIM2 is selected when bit D3 is 1 (Table 32). Figure 30, page 54, describes HS operation when cyclic sense is selected Cyclic sense timing characteristics are described in Table 34, page 54. Both subregisters also report the CANL and TXD diagnostics.

Table 28. Wake-up Register Control Bits Table 29. Wake-up Register Status Bits (62)

  1. WUR status bits have two functions. After SBC wake-up, they indicate the wake-up source; for example, L2WU set at logic [1] if wake-

first reading of the WUR register, the LxWU bits are reset. This can occur only if the SBC was in Stop mode. Table 30. TIM1 Timing and CANL Failure Diagnostic Register

  1. See Table 13, page 47, for definitions of reset conditions.

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Figure 30. HS Operation When Cyclic Sense Is Selected

  • The state of HS in Stop and Sleep mo des (HS permanently OFF or HS cyclic).
  • Enable or disable of the forced wake-up function (SBC automatic wake-up after time spent in Sleep or Stop modes; time is defined by the TIM2 sub register).
  • Enable or disable the sense of the wake-up inputs (Lx) at the sampling point of the Cyclic Sense period (LX2HS bit). (Refer to Reset Control Register (RCR) on page 49 for details of the LPC register setup required for proper cyclic sense or direct wake- up operation. The LPC register also reports the CANH and RXD diagnostic. Cyclic Sense Timing, OFF Time time HS Sample 10μs HS OFF HS ON Lx Sampling Point Cyclic Sense Timing, ON Time

Table 34. TIM2 Control Bits Table 35. Low Power Control Register

  1. See Table 13, page 47, for definitions of reset conditions.

Table 36. LX2HS Control Bits 1 Yes. Lx inputs sensed at sampling point. Table 37. HSAUTO Control Bits 1 ON, HS Cyclic, period defined in TIM2 subregister. Table 38. CAN-INT Control Bits 0 Interrupt as soon as CAN bus failure detected. 1 Interrupt when CAN bus failure detected and fully identified.

  1. If CAN-INT is at logic [0], any undetermined CAN failure will be latched in the CAN register (bit D1: CAN-UF) and can be accessed by

allow clearing the CAN-UF bit. Table 39. LPC Status Bits 0 No RXD permanent recessive.

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in the CAN register and the IOR register. (not bit set into the INTR register). Table 40. Interrupt Register

  1. If only HSOT - V2LOW interrupt is selected (only bit D2 set in INTR register), reading INTR register bit D2 leads to two possibilities:
  2. Bit D2 = 1: Interrupt source is HSOT.
  3. Bit D2 = 0: Interrupt source is V2LOW.

HSOT and V2LOW bits status are available in the IOR register.

  1. See Table 13, page 47, for definitions of reset conditions.

Table 41. Interrupt Register Control Bits CANF Mask bit for CAN failures. HSOT - V2LOW Mask bit for HS over-temperature AND V2LTH < 4.0V. VSUPLOW Mask bit for VBF(EW) < 5.8V. Table 42. Interrupt Register Status Bits 0 No VDD medium temperature (pre-warning). 1 VDD medium temperature (pre-warning).

and from reverse battery. This is illustrated in Figure 31. Figure 31. SBC Typical Application Schematic

1.0 Mbps CAN

Rp, Rd: Example: 1.0kΩ depending on switch type.

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operates with an external ballast transistor.

  • C4: 100nF
  • C3: 10 μF < C3 <22μF, ESR < 1.0Ω or
  • C3: 22 μF < C3 <47μF, ESR < 5.0Ω or
  • C 3 : ≥ 47μF, ESR < 10Ω V2 REGULATOR: OPERATING WITH EXTERNAL BALLAST TRANSISTOR The V2 regulator is a tracking regulator of the VDD output. Its accuracy relative to VDD is ±1.0%. It requires external decoupling and stabilizing capacitors. The recommended value are as follows:
  • 2 2 μF, ESR < 5.0Ω
  • 4 7 μF, ESR < 10Ω The V2 pin has two functions: it is a sense input for the V2 regulator and is a 5.0V power supply input to the CAN interface. With respect to ballast transistor selection, either PNP or PMOS transistors may be used. A resistor between base and emitter (or source and drain) is necessary to ensure proper operation and optimized performances. Recommended bipolar transistor is MJD32C. V2 REGULATOR: OPERATION WITHOUT BALLAST TRANSISTOR The external ballast transistor is optional. If the application does not requires more than the maximum output current capability of the VDD regulator, then the ballast transistor can be omitted. The thermal aspects must be analyzed as well. The electrical connection is illustrated in Figure 32.

Figure 32. V2 Regulator Electrical Connection failure of the VDD regulator. (CAN interface is in TXRX mode): VDD is on and V2 is off. Figure 33, page 59, illustrates the operation.

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Figure 35 shows an example wherein VDD is shorted to 4.0V, and after 100ms the 33742 enters Sleep mode. Figure 35. Under-voltage at VDD. Sleep mode selected. Figure 36. CAN Bus Standard Termination Figure 37. CAN Bus Split Termination

Analog Integrated Circuit Device Data Freescale Semiconductor 61 33742 PACKAGING PACKAGE AND THERMAL CONSIDERATIONS PACKAGING PACKAGE AND THERMAL CONSIDERATIONS The 33742 SBC is a standard surface mount 28-pin SOIC wide body. In order to improve the thermal performances of the SOIC package, eight of the 28 pins are internally connected to the package lead frame for heat transfer to the printed circuit board. PACKAGING DIMENSIONS Important For the most current revision of the package, visit www.freescale.com and perform a keyword search on the 98A drawing number below. DW SUFFIX EG SUFFIX (PB-FREE) 28-LEAD SOICW 98ASB42345B ISSUE G

Analog Integrated Circuit Device Data

62 Freescale Semiconductor

EG SUFFIX (PB-FREE) 28-LEAD SOICW 98ASB42345B ISSUE G

Analog Integrated Circuit Device Data Freescale Semiconductor 63 33742 PACKAGING PACKAGING DIMENSIONS EP SUFFIX (PB-FREE) 48-LEAD QFN 98ASA10825D ISSUE 0

Analog Integrated Circuit Device Data

64 Freescale Semiconductor

EP SUFFIX (PB-FREE) 48-LEAD QFN 98ASA10825D ISSUE 0

Analog Integrated Circuit Device Data Freescale Semiconductor 65 33742 PACKAGING PACKAGING DIMENSIONS EP SUFFIX (PB-FREE) 48-LEAD QFN 98ASA10825D ISSUE 0

66 Freescale Semiconductor

J), and thermal resistance (RθJA). measurement and simulation according to the standards listed below. Figure 38. Surface Mount for SOIC Wide Body Table 43. Thermal Performance Comparison

  1. Per JEDEC JESD51-2 at natural convection, still air
  2. 2s2p thermal test board per JEDEC JESD51-7.
  3. Per JEDEC JESD51-8, with the board temperature on the

center trace near the center lead.

  1. Single layer thermal test board per JEDEC JESD51-3.
  2. Thermal resistance between the die junction and the

surface and remaining surfaces insulated.

28 Pin SOICW

Figure 39. Thermal Test Board Table 44. Thermal Resistance Performance

33742 Pin Connections

68 Freescale Semiconductor

Figure 40. Device on Thermal Test Board RθJA Figure 41. Transient Thermal Resistance RθJA,

1 W Step response, Device on Thermal Test Board Area A = 600 (mm2)

Analog Integrated Circuit Device Data Freescale Semiconductor 69 33742

REVISION HISTORY

REVISION DATE DESCRIPTION OF CHANGES 3 2/2006 • Converted to Freescale format

  • Implemented Revision History page 4 6/2006 • Added Thermal Addendum (Rev. 1.0)
  • Changed Data Sheet from “Advanced” to “Final” 5 8/2006 • Added MCZ33742EG/R2 and MCZ33742SEG/R2 to the Ordering Information block 6 8/2006 • Replaced label for Logic Inputs to Logic Signals (RXD, TXD, MOSI, MISO, CS, SCLK, RST, WDOG, and INT) on page 7 7 10/2006 • Removed all references to the 54 pin package.
  • Removed Peak Package Reflow Temperature Duri ng Reflow (solder reflow) parameter from Maximum Ratings on page 7. Added note with instructions from www.freescale.com. 8 2/2007 • Revised () and (),
  • Restated notes in Maximum Ratings on page 7 9 3/2007 • Text corrections to the included thermal addendum 10 5/2007 • Added EP 48 pin QFN package
  • Added 98ARH99048A Package drawing
  • Added PCZ33742EP/R2 to the ordering information 11 6/2008 • Made changes defining RXD as a push-pull structure on page 16, 23, 38, and 39
  • Updated figures Figure 12 and Figure 25
  • Added provisions of differentiation for 28-pin SOIC and 48-pin QFN for ESD Capability, Human Body Model(1) on page 7, Watchdog Period Normal and Standby Modes on page 18, and Normal Request Mode Timeout on page 18
  • Update the Freescale format and style to the current standards
  • Added the Functional Internal Block Description section
  • Changed PCZ33742EP/R2 to MC33742EP/R2 in the ordering information

Rev. 11 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”, must be validated for each customer application by customer’s technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc., 2007-2008. All rights reserved. How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. Technical Information Center, EL516

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